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m pd703000, 703001 mos integrated circuit description the m pd703000 is a product in the v850 family tm of 32-bit single-chip microcontrollers for real-time control applications. it integrates a 32-bit cpu, rom, ram, interrupt controller, real-time pulse unit, and serial interface on a single chip. the m pd703001 is a rom-less model of the m pd703000. the functions are described in detail in the following manuals. be sure to read these manuals when designing your system. v851 users manual - hardware : u10935e v850 family users manual - architecture : u10243e features ? number of instructions: 74 ? minimum instruction execution time: 30 ns (at 33 mhz) ? general-purpose register: 32 bits x 32 ? instruction set ideal for control application ? internal memory rom : 32k bytes ( m pd703000) ram : 1k bytes ( m pd703000, 703001) ? high-performance interrupt controller ? real-time pulse unit ideal for control ? powerful serial interface (dedicated baud rate generator) ? clock generator ? power save function application field ? system control fields using servo motor (ppcs, printers, and nc machine tools) ? other control fields requiring high response speed (engine control, etc.) the m pd703000 is treated as the representative model in this document. v851 tm 32-/16-bit single-chip microcontroller the information in this document is subject to change without notice. the mark shows major revised points. document no. u10987ej3v0ds00 (3rd edition) date published september 1997 n printed in japan 1996 data sheet
2 m pd703000, 703001 ordering information part number package maximum operating internal rom frequency (mhz) m pd703000gc-25-xxx-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 25 32k bytes m pd703000gc-33-xxx-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 33 32k bytes m pd703001gc-25-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 25 none m pd703001gc-33-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) 33 none remark xxx indicates a rom code suffix. pin configuration 100-pin plastic qfp (fine pitch) (14 14 mm) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 v dd v ss p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p07/intp13 p06/intp12 p05/intp11 p04/intp10 p03/ti1 p02/tclr1 p01/to11 p00/to10 v dd v ss p17 p16 p15 p14 p13 p12 p11 p10 v ss v dd mode0 mode1 ic0 (g) ic1 (v) reset v ss v dd p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/st0 p96/st1 p97 wait v dd v ss x2 x1 cksel cv dd cv ss clkout v ss v dd p103 p102 p101/hldrq p100/hldak p65/a21 p66/a22 p67/a23 v ss v dd p30/so p31/si p32/sck p33/txd p34/rxd p35 p36 p37 v dd v ss p20/nmi p21/intp00 p22/intp01 p23/intp02 p24/intp03 p25 p26 p27 v ss v dd caution ( ) indicates the processing of the pins not used in the normal operation mode. g : directly connect this pin to v ss . v : directly connect this pin to v dd .
3 m pd703000, 703001 p00-p07 : port0 a16-a23 : address bus p10-p17 : port1 lben : lower byte enable p20-p27 : port2 uben : upper byte enable p30-p37 : port3 r/w : read/write status p40-p47 : port4 dstb : data strobe p50-p57 : port5 astb : address strobe p60-p67 : port6 st0, st1 : status p90-p97 : port9 hldak : hold acknowledge p100-p103 : port10 hldrq : hold request to10, to11 : timer output clkout : clock output tclr1 : timer clear cksel : clock select ti1 : timer input wait : wait intp00-intp03, mode0, mode1 : mode intp10-intp13 : interrupt request from peripherals reset : reset nmi : non-maskable interrupt request x1, x2 : crystal so : serial output cv dd : power supply for clock generator si : serial input cv ss : ground for clock generator sck : serial clock v dd : power supply txd : transmit data v ss : ground rxd : receive data ic0, ic1 : internally connected ad0-ad15 : address/data bus
4 m pd703000, 703001 function block diagram intp00-intp03 nmi to10, to11 intp10-intp13 tclr1 ti1 txd rxd so si sck intc rpu uart sio brg csi rom note 32 k bytes ram 1 k bytes cpu pc 32-bit barrel shifter system registers general registers (32 bits 32) alu multiplier 16 16 32 port cg instruction queue bcu astb dstb r/w uben lben wait a16-a23 ad0-ad15 st0,st1 hldrq hldak cksel clkout x1 x2 mode0,mode1 reset p100-p103 p90-p97 p60-p67 p50-p57 p40-p47 p30-p37 p21-p27 p20 p10-p17 p00-p07 note not provided to pd703001 m
5 m pd703000, 703001 table of contents 1. list of pin functions ...................................................................................................... ............ 7 1.1 port pins ................................................................................................................. ...................... 7 1.2 pins other than port pins ................................................................................................. ......... 9 1.3 i/o circuits of pins and recommended connections of unused pins .................................. 11 2. function blocks ............................................................................................................ .............. 13 2.1 internal units ............................................................................................................ .................... 13 2.1.1 cpu ..................................................................................................................... ............................... 13 2.1.2 bus control unit (bcu) .................................................................................................. ...................... 13 2.1.3 rom ..................................................................................................................... .............................. 13 2.1.4 ram ..................................................................................................................... ............................... 13 2.1.5 port .................................................................................................................... ................................. 13 2.1.6 interrupt controller .................................................................................................... ........................... 13 2.1.7 clock generator ......................................................................................................... ......................... 13 2.1.8 realtime pulse unit (rpu) ............................................................................................... ................... 13 2.1.9 serial interface ........................................................................................................ ............................ 14 3. cpu function ............................................................................................................... ................... 15 3.1 features .................................................................................................................. ...................... 15 4. bus control function ....................................................................................................... ........ 16 4.1 features .................................................................................................................. ...................... 16 5. interrupt/exception handling ............................................................................................... 17 5.1 features .................................................................................................................. ...................... 17 5.2 configuration ............................................................................................................. .................. 17 6. clock generator ............................................................................................................ ............ 19 6.1 features .................................................................................................................. ...................... 19 6.2 configuration ............................................................................................................. .................. 19 7. timer/counter function (real time pulse unit) ..................................................................... 20 7.1 features .................................................................................................................. ...................... 20 7.2 configuration ............................................................................................................. .................. 21 8. serial interface function (sio) ............................................................................................ .22 8.1 features .................................................................................................................. ...................... 22 8.2 asynchronous serial interface (uart) ..................................................................................... 2 2 8.2.1 features ................................................................................................................ .............................. 22 8.2.2 configuration ........................................................................................................... ........................... 23 8.3 clocked serial interface (csi) ............................................................................................ ......... 24 8.3.1 features ................................................................................................................ .............................. 24 8.3.2 configuration ........................................................................................................... ........................... 24 8.4 baud rate generator (brg) ................................................................................................. ...... 25 8.4.1 features ................................................................................................................ .............................. 25 8.4.2 configuration ........................................................................................................... ........................... 25 9. port function .............................................................................................................. .................. 26 9.1 features .................................................................................................................. ...................... 26 9.2 configuration ............................................................................................................. .................. 26 10. reset function ............................................................................................................ ................ 38 10.1 features ................................................................................................................. ..................... 38
6 m pd703000, 703001 11. instruction set ........................................................................................................... ................ 39 11.1 instruction set list ..................................................................................................... ............... 39 12. electrical specifications ................................................................................................. .... 46 12.1 when v dd = 5.0 10% ................................................................................................................ 46 12.2 when v dd = 3.0 to 3.6 v ............................................................................................................. 65 13. characteristic curve (reference) .......................................................................................... 83 14. package drawings .......................................................................................................... .......... 84 15. recommended soldering conditions ................................................................................ 85
7 m pd703000, 703001 1. list of pin functions 1.1 port pins (1/2) pin name i/o function shared pin p00 i/o port 0 to10 p01 8-bit input/output port to11 p02 input/output specifiable bit-wise tclr1 p03 ti1 p04 intp10 p05 intp11 p06 intp12 p07 intp13 p10-p17 i/o port 1 8-bit input/output port input/output specifiable bit-wise p20 input port 2 nmi p21 i/o p20 is a dedicated input port. intp00 p22 when a valid edge is input, this pin operates as an nmi input. intp01 p23 bit 0 of p2 register indicates the nmi input status. intp02 p24 p21 to p27 are 7-bit input/output ports. intp03 p25-27 input/output specifiable bit-wise p30 i/o port 3 so p31 8-bit input/output port si p32 input/output specifiable bit-wise sck p33 txd p34 rxd p35-37 p40-p47 i/o port 4 ad0-ad7 8-bit input/output port input/output specifiable bit-wise p50-p57 i/o port 5 ad8-ad15 8-bit input/output port input/output specifiable bit-wise p60-p67 i/o port 6 a16-a23 8-bit input/output port input/output specifiable bit-wise
8 m pd703000, 703001 (2/2) pin name i/o function shared pin p90 i/o port 9 lben p91 8-bit input/output port uben p92 input/output specifiable bit-wise r/w p93 dstb p94 astb p95 st0 p96 st1 p97 p100 i/o port 10 hldak p101 4-bit input/output port hldrq p102 input/output specifiable bit-wise p103
9 m pd703000, 703001 1.2 pins other than port pins (1/2) pin name i/o function shared pin to10 output pulse signal of timer 1 p00 to11 p01 tclr1 input timer 1 external clear signal p02 ti1 timer 1 external count clock p03 intp10 input external maskable interrupt request, or timer 1 external capture trigger p04 intp11 p05 intp12 p06 intp13 p07 nmi input non-maskable interrupt request p20 intp00 input external maskable interrupt request p21 intp01 p22 intp02 p23 intp03 p24 so output csi serial data transmission p30 si input csi serial data reception p31 sck i/o csi serial clock p32 txd output uart serial data transmission p33 rxd input uart serial data reception p34 ad0-ad7 i/o 16-bit multiplexed address/data bus to extend external memory p40-p47 ad8-ad15 p50-p57 a16-a23 output higher address bus to extend external memory p60-p67 lben output external data bus lower byte enable signal p90 uben external data bus higher byte enable signal p91 r/w external read/write status p92 dstb external data strobe signal p93 astb external address strobe signal p94 st0 external bus cycle status p95 st1 p96 hldak output bus hold acknowledge p100 hldrq input bus hold request p101 clkout output system clock cksel input clock generator operation mode specification wait input bus cycle wait insertion control signal mode0,mode1 input operation mode specification reset input system reset x1 input connect resonator for system clock. input external clock to x1. x2 cv dd positive power for internal clock generator cv ss ground potential for internal clock generator
10 m pd703000, 703001 (2/2) pin name i/o function shared pin v dd positive power supply v ss ground potential ic0, ic1 internally connected
11 m pd703000, 703001 1.3 i/o circuits of pins and recommended connections of unused pins table 1-1 shows the i/o circuit types of the respective pins in the normal operation mode and recommended connections of unused pins. figure 1-1 shows the respective circuit types partially simplified. when connecting a pin to v dd or v ss via resistor, use of a resistor of 3 to 10 k w is recommended. table 1-1. i/o circuit types of respective pins and recommended connections of unused pins pin name i/o circuit type recommended connections p00/to10,p01/to11 5 input: individually connect to v dd or v ss via resistor p02/tclr1,p03/ti1, 8 output: open p04/intp10-p07/intp13 p10-p17 5 p20/nmi 2 directly connect to v ss p21/intp00-p24/intp03 8 input: individually connect to v dd or v ss via resistor p25 5 output: open p26,p27 8 p30/so 5 p31/si,p32/sck 8 p33/txd,p34/rxd,p35 5 p36,p37 8 p40/ad0-p47/ad7 5 p50/ad8-p57/ad15 p60/a16-p67/a23 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/st0,p96/st1 p97 p100/hldak p101/hldrq p102 p103 clkout 3 open cksel 2 C wait 1 directly connect to v dd mode0,mode1 2 C reset ic0 C directly connect to v ss ic1 C directly connect to v dd
12 m pd703000, 703001 figure 1-1. i/o circuits of pins type 1 type 5 type 2 type 8 type 3 p-ch n-ch in v dd in schmitt trigger input with hysteresis characteristics p-ch n-ch v dd out p-ch n-ch v dd in/out data output disable input enable p-ch n-ch v dd in/out data output disable
13 m pd703000, 703001 2. function blocks 2.1 internal units 2.1.1 cpu most instructions, such as address calculation, arithmetic and logic operation, and data transfer, are executed in one clock cycle under control of 5-stage pipeline. the cpu also includes dedicated hardware such as a multiplier (16 by 16) and a 32-bit barrel shifter, aiming at processing complex instructions at high speeds. in addition, the cpu can access internal rom (32 kb) and ram (1 kb) in one clock cycle. 2.1.2 bus control unit (bcu) the bcu initiates necessary external bus cycles based on the physical address given by the cpu. when an instruction fetch is executed from external memory area, if no bus cycle initiation is requested by the cpu, the bcu creates a prefetch address to prefetch an instruction code. the prefetched instruction code is taken into the internal instruction queue. 2.1.3 rom the rom has a capacity of 32 kb and is mapped from the address 00000000h. access to the rom is enabled/ disabled by setting the mode0 and mode1 pins. the cpu can access any address of the rom in one clock cycle (to fetch an instruction). 2.1.4 ram this ram has a capacity of 1 kb and is mapped from address ffffe000h. the cpu can access any address of the ram in one clock cycle (to access data). 2.1.5 port the m pd703000 is provided with a total of 68 input/output port pins (of which one is an input port pin), or ports 0 through 10. these port pins can be used as the control pins. 2.1.6 interrupt controller the interrupt controller controls various interrupt requests (nmi, intp00-intp03, and intp10-intp13) issued by peripheral hardware or external devices. up to eight levels of interrupt priority can be individually specified for each interrupt request. in addition, multiplexed processing control can be performed. 2.1.7 clock generator the clock generator generates a cpu operating clock whose frequency is 5 times as high as (with the internal pll) or half (without the internal pll) the frequency of the resonator connected across the x1 and x2 pins. instead of connecting a resonator, a clock signal can be input from off-chip. 2.1.8 realtime pulse unit (rpu) the rpu which includes a 16-bit timer/event counter and a 16-bit interval timer, measures pulse intervals and pulse frequency, and outputs programmable pulses.
14 m pd703000, 703001 2.1.9 serial interface the serial interface includes one channel of uart (asynchronous serial interface) and one channel of csi (clocked serial interface). the uart transfers data with the txd and rxd pins. the baud rate is generated by an on-chip dedicated baud rate generator. the csi transfers data with the so, si, and sck pins. the baud rate can be generated from an on-chip dedicated baud rate generator, or supplied from off-chip.
15 m pd703000, 703001 3. cpu function the cpu of the m pd703000 is based on the risc architecture and executes almost all the instructions in one clock cycle, using a 5-stage pipeline. 3.1 features ? minimum instruction execution time: 30 ns (internal 33 mhz) ? address space: 16-mb linear ? general registers: 32 bits x 32 ? internal 32-bit architecture ? five-stage pipeline control ? multiplication/division instruction ? saturated operation instruction ? 32-bit shift instruction: 1 clock ? long/short format ? internal memory ? rom: 32k bytes ? ram: 1k bytes ? bit manipulation instructions: 4 types ? set ? clear ? not ? test
16 m pd703000, 703001 4. bus control function 4.1 features ? external device connectable with port pins ? wait function ? programmable wait function inserting up to 3 states per 2 blocks ? external wait function effected by wait pin ? idle state inserting function ? bus arbitration function ? bus hold function
17 m pd703000, 703001 5. interrupt/exception handling 5.1 features ? interrupt ? non-maskable : 1 source ? maskable : 14 sources ? 8-level programmable priority control ? multiplexed processing control according to priority ? masking each maskable interrupt request ? valid edge specification for external interrupt request ? exception ? software exception : 32 sources ? exception trap : 1 source (illegal instruction code exception) 5.2 configuration internal bus rpu sio intp10 intp11 intp12 intp13 intm2 intcsi0 intser0 intsr0 intst0 intp00 intp01 intp02 intp03 intm1 edge detection 32103210 3210 intov1 intp10/intcc10 intp11/intcc11 intp12/intcc12 intp13/intcc13 intcm4 ovif1 p1if0 p1if1 p1if2 p1if3 cmif4 csif0 seif0 srif0 stif0 p0if0 p0if2 p0if3 p0if1 mkn (interrupt mask flag) priority controller prn handler address generator ispr 70 interrupt request id psw cpu halt mode release signal selector edge detection interrupt request acknowledge
18 m pd703000, 703001 default handler restore priority address pc control gener- register ating unit excep- tion code table 5-1. interrupts interrupt/exception sources type class reset interrupt reset reset input 0000h 00000000h undefined non-maskable interrupt nmi nmi input 0010h 00000010h next pc software exception exception trap0n note trap instruction 004n note h 00000040h next pc exception trap1n note trap instruction 005n note h 00000050h next pc exception trap exception ilgop illegal instruction code 0060h 00000060h next pc maskable interrupt intov1 ovic1 timer 1 overflow rpu 0 0080h 00000080h next pc interrupt intp10/intcc10 p1ic0 match of intp10 & cc10 pin/rpu 1 0090h 00000090h next pc interrupt intp11/intcc11 p1ic1 match of intp11 & cc11 pin/rpu 2 00a0h 000000a0h next pc interrupt intp12/intcc12 p1ic2 match of intp12 & cc12 pin/rpu 3 00b0h 000000b0h next pc interrupt intp13/intcc13 p1ic3 match of intp13 & cc13 pin/rpu 4 00c0h 000000c0h next pc interrupt intcm4 cmic4 match of cm4 rpu 5 00d0h 000000d0h next pc interrupt intcsi0 csic0 csi0 transmit/receive sio 6 00e0h 000000e0h next pc completion interrupt intser0 seic0 uart0 receive error sio 7 00f0h 000000f0h next pc interrupt intsr0 sric0 uart0 receive completion sio 8 0100h 00000100h next pc interrupt intst0 stic0 uart0 transmit completion sio 9 0110h 00000110h next pc interrupt intp00 p0ic0 intp00 pin pin 10 0120h 00000120h next pc interrupt intp01 p0ic1 intp01 pin pin 11 0130h 00000130h next pc interrupt intp02 p0ic2 intp02 pin pin 12 0140h 00000140h next pc interrupt intp03 p0ic3 intp03 pin pin 13 0150h 00000150h next pc note the "n" in the "software exception " rows is a value from 0 to fh. remarks 1. default priority: priority used when two or maskable interrupt requests are simultaneously generated. 0 indicates the highest priority. restore pc: pc value saved to eipc or fepc when interrupt/exception processing is started. however, the restore pc value saved if an interrupt is accepted while the divh (division) instruction is being executed is the pc value of the current instruction (divh). 2. the execution address of an illegal instruction when an illegal instruction code exception occurs can be calculated as (restore pc C 4). name generation sources
19 m pd703000, 703001 6. clock generator 6.1 features ? multiply function by pll clock synthesizer (f xx = 1 5 f ) ? direct mode directly to input external clock ? power save mode ? halt mode ? idle mode ? software stop mode ? clock output inhibit function 6.2 configuration cksel x1 (f xx ) x2 osc pfc 2 1 scf vco 1/20 divider circuit pll synthesizer in pll mode (f vco ) 2 1 (f xx ) in direct mode f f vco : : osc : pfc : scf : vco : f vco oscillation frequency (=10f ) internal system clock frequency (=1/2f vco : in pll mode) internal system clock frequency (=1/2f : in direct mode) oscillator (supported in pll mode only) phase frequency comparator switched capacitor filter voltage controlled oscillator
20 m pd703000, 703001 7. timer/counter function (real time pulse unit) 7.1 features ? pulse interval and frequency measurement and output of programmable pulse ? 16-bit measurement possible ? pulse can be generated in various shapes (interval pulse, one-shot pulse) ? timer 1 ? 16-bit timer/event counter ? sources of count clock: 2 types (divided system clock or external pulse input) ? capture/compare registers: 4 ? count clear pin: tclr1 ? interrupt sources: 5 ? external pulse output: 2 ? timer 4 ? 16-bit interval timer ? count clock selected from divided system clock ? compare register: 1 ? interrupt source: 1
21 m pd703000, 703001 7.2 configuration (1) timer 1 (16-bit timer/event counter) (2) timer 4 (16-bit interval timer) tm4 (16 bits) cm4 clear & start intcm4 note m/16 m/32 f f m f /2 /4 /8 f f f note internal count clock remark indicates the system clock. f m m/4 m/8 m/16 f f f f /2 /4 f f m f tclr1 ti1 intp10 intp11 intp12 intp13 note2 note1 clear and start tm1 (16 bits) cc10 cc11 cc12 cc13 intov1 intcc10 intcc11 s r note3 q q s q q r note3 intcc12 intcc13 to10 to11 notes 1. internal count clock remark indicates the system clock. f 2. external count clock 3. gives priority to reset edge detection edge detection clear & start edge detection edge detection edge detection edge detection
22 m pd703000, 703001 8. serial interface function (sio) 8.1 features the m pd703000 is provided with the following two types of interface methods as serial interface functions, each of which has one channel: (1) asynchronous serial interface (uart) (2) clocked serial interface (csi) 8.2 asynchronous serial interface (uart) 8.2.1 features ? transfer rate: 150 bps to 76800 bps (system clock: 33 mhz) ? full-duplex communication ? 2-pin configuration txd: transmit data output pin rxd: receive data input pin ? receive error detection function ? parity error ? framing error ? overrun error ? three interrupt sources ? receive error interrupt (intser0) ? reception completion interrupt (intsr0) ? transmission interrupt (intst0) ? character length of transmission/reception data is specified by asim0 and asim1 registers. ? character length : 7, 8 bits 9 bits (with extended bit appended) ? parity function : odd, even, 0, none ? transmission stop bit: 1, 2 bits ? baud rate generator
23 m pd703000, 703001 8.2.2 configuration internal bus 16/8 receive buffer 8 rxb0 rxb0l receive shift register rxd txd receive control parity check 1 16 intsr0 intser0 pe0 fe0 ove0 sot0 asis 16/8 transmit shift register txs0 txs0l transmit control parity append intst0 1 16 1 2 selector baud rate generator 88 asim00 asim01 ebs0 rxe0 ps01 ps00 cl0 sl0 scls0 f
24 m pd703000, 703001 8.3 clocked serial interface (csi) 8.3.1 features ? high-speed transfer rate 8.25 mbps max. (system clock: 33 mhz) ? half-duplex communication ? data length of 8 bits ? selection of external or internal clock ? three pins used so : serial data output pin si : serial data input pin sck : serial clock i/o pin ? one interrupt source ? interrupt request signal (intcsi0) 8.3.2 configuration internal bus ctxe0 crxe0 csot0 mod0 cls01 cls00 csim0 si so sck shift register sio0 so latch dq 2 1 selector serial clock controller serial clock counter interrupt controller intcsi0 baud rate generator /2 f f selector
25 m pd703000, 703001 8.4 baud rate generator (brg) 8.4.1 features ? serial clock selectable from baud rate generator output and f (system clock) ? same baud rate for transmission/reception 8.4.2 configuration internal bus 7 0 bprm0 brg0 match clear tmbrg0 uart csi /2 prescaler 2 1 brce0 bpr02 bpr01 bpr00 f f
26 m pd703000, 703001 9. port function 9.1 features the ports of the m pd703000 have the following features: ? number of port pins input port : 1 i/o port : 67 ? shared with i/o pins of other peripheral functions ? input/output specifiable bitwise ? noise elimination ? edge detection 9.2 configuration figure 9-1. block diagram of p00, p01 (port 0) internal bus wr pmc wr pm wr port rd in pmc0n pm0n p0n to1n selector p0n address selector selector remark n=0, 1
27 m pd703000, 703001 figure 9-2. block diagram of p02 to p07 (port 0) wr pmc wr pm wr port rd in pmc0n pm0n p0n noise elimination edge detection p0n intp10-intp13, tclr1, ti1 address internal bus selector remark n=2-7 selector figure 9-3. block diagram of p10 to p17 (port 1) wr pm wr port rd in pm1n p1n p1n address internal bus selector remark n=0-7 selector
28 m pd703000, 703001 figure 9-4. block diagram of p20 (port 2) rd in 1 nmi p20 internal bus selector address edge detection noise elimination wr pmc wr pm wr port rd in pmc2n pm2n p2n intp00-intp03 p2n noise elimination edge detection address internal bus selector remark n=1-4 selector figure 9-5. block diagram of p21 to p24 (port 2)
29 m pd703000, 703001 figure 9-6. block diagram of p25 (port 2) wr pm wr port rd in pm25 p25 p25 address internal bus selector selector figure 9-7. block diagram of p26, p27 (port 2) wr pm wr port rd in pm2n p2n p2n address internal bus selector remark n=6, 7 selector
30 m pd703000, 703001 figure 9-8. block diagram of p30, p33 (port 3) wr pmc wr pm wr port rd in pmc3n pm3n p3n so, txd p3n address internal bus selector remark n=0, 3 selector selector figure 9-9. block diagram of p31 (port 3) wr pmc wr pm wr port rd in pmc31 pm31 p31 p31 si address internal bus selector selector
31 m pd703000, 703001 figure 9-10. block diagram of p32 (port 3) figure 9-11. block diagram of p34 (port 3) pmc34 wr pmc wr pm wr port rd in rxd p34 pm34 p34 address internal bus selector selector wr pmc wr pm wr port rd in pmc32 pm32 p32 p32 sck input sck output address internal bus selector selector selector
32 m pd703000, 703001 figure 9-12. block diagram of p35 (port 3) wr pm wr port rd in pm35 p35 p35 address internal bus selector selector figure 9-13. block diagram of p36, p37 (port 3) wr pm wr port rd in pm3n p3n p3n address internal bus selector selector remark n=6, 7
33 m pd703000, 703001 figure 9-14. block diagram of p40 to p47 (port 4) wr pm wr port rd in pm4n p4n ad0-ad7 mode0, mode1 mm0-mm2 p4n internal bus remark n=0-7 i/o control circuit
34 m pd703000, 703001 figure 9-15. block diagram of p50 to p57 (port 5) wr pm wr port rd in pm5n p5n ad8-ad15 mode0, mode1 mm0-mm2 p5n internal bus i/o control circuit remark n=0-7
35 m pd703000, 703001 figure 9-16. block diagram of p60 to p67 (port 6) wr pm wr port rd in pm6n p6n a16-a23 mode0, mode1 mm0-mm2 p6n internal bus i/o control circuit remark n=0-7
36 m pd703000, 703001 figure 9-17. block diagram of p90 to p97 (port 9) figure 9-18. block diagram of p100, p103 (port 10) wr pm wr port rd in pm9n p9n mode0, mode1 mm0-mm3 p9n lben, uben, r/w, dstb, astb, st0, st1 internal bus remark n=0-7 i/o control circuit wr pmc wr pm wr port rd in pmc10n pm10n p10n hldak, rfu note p10n internal bus remark n=0, 3 address selector selector selector note rfu is undefined value.
37 m pd703000, 703001 figure 9-19. block diagram of p101 (port 10) figure 9-20. block diagram of p102 (port 10) pmc101 wr pmc wr pm wr port rd in hldrq p101 pm101 p101 internal bus address selector selector wr pm wr port rd in pm102 p102 p102 internal bus address selector selector
38 m pd703000, 703001 10. reset function when the reset signal is made low, the system is reset, and the on-chip hardware units are initialized. the reset status is cleared when the reset signal is made high, and the cpu starts executing the program. initialize the contents of each register in the program as necessary. 10.1 features ? noise elimination circuit of analog delay ( 60 ns) provided to reset pin
39 m pd703000, 703001 11. instruction set 11.1 instruction set list ? how to read instruction set list this column indicates an instruction group. this instruction set list classifies instructions by group. this column indicates the mnemonic of the instruction. this column indicates the operand of the instruction (refer to table 11-1 ) . this column indicates the instruction code in binary number . the instruction code of a 32-bit instruction is shown in two columns (refer to table 11-2 ). this column indicates the operation of the instruction (refer to table 11-3 ) . this column indicate the operation of the flags (refer to table 11-4 ). mnemonic operand op code operation flag cy ov s z sat instruction group table 11-1. symbols shown in "operand" column symbol meaning reg1 general register (used as source register) reg2 general register (mainly used as destination register. some are also used as source registers) ep element pointer bit#3 3-bit data for bit number specification immx x-bit immediate dispx x-bit displacement regid system register number vector 5-bit data specifying trap vector (00h through 1fh) cccc 4-bit data indicating condition code
40 m pd703000, 703001 table 11-2. symbols shown in "op code" column symbol meaning r 1-bit data of code specifying reg1 or regid r 1-bit data of code specifying reg2 d 1-bit data of displacement i 1-bit data of immediate cccc 4-bit data indicating condition code bbb 3-bit data specifying bit number table 11-3. symbols shown in "operation" column symbol meaning ? assignment gr [ ] general register sr [ ] system register zero-extend (n) zero-extends "n" to word length sign-extend (n) sign-extends "n" to word length load-memory (a, b) reads data of size "b" from address "a" store-memory (a, b, c) writes data "b" of size "c" to address "a" load-memomy-bit (a, b) reads bit "b" of address "a" store-memory-bit (a, b, c) writes "c" to bit "b" of address "a" saturated (n) performs saturated processing of n (n is 2's complement) "n" indicates result of operation. if "n" 3 7fffffffh, 7fffffffh if "n" 80000000h, 80000000h result reflects result on flag byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + add C subtract || bit concatenation multiply ? divide and logical product or logical sum xor exclusive logical sum not logical negation logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift
41 m pd703000, 703001 table 11-4. symbols shown in "flag" column identifier meaning (blank) not affected 0 cleared to 0 set or cleared according to result r value once saved is restored table 11-5. condition codes condition name (cond) condition code (cccc) conditional expression meaning v 0000 ov=1 overflow nv 1000 ov=0 no overflow c/l 0001 cy=1 carry lower (less than) nc/nl 1001 cy=0 no carry not lower (greater than or equal) z/e 0010 z=1 zero equal nz/ne 1010 z=0 not zero not equal nh 0011 (cy or z)=1 not higher (less than or equal) h 1011 (cy or z)=0 higher (greater than) n 0100 s=1 negative p 1100 s=0 positive t 0101 C always (unconditional) sa 1101 sat=1 saturated lt 0110 (s xor ov)=1 less than signed ge 1110 (s xor ov)=0 greater than or equal signed le 0111 ((s xor ov) or z)=1 less than or equal signed gt 1111 ((s xor ov) or z)=0 greater than signed
42 m pd703000, 703001 instruction group mnemonic operand sld.b sld.h sld.w ld.b ld.h ld.w sst.b sst.h sst.w st.b st.h st.w mov mov movhi movea add add addi sub subr disp7[ep], reg2 disp8[ep], reg2 disp8[ep], reg2 disp16[reg1], reg2 disp16[reg1], reg2 disp16[reg1], reg2 reg2, disp7[ep] reg2, disp8[ep] reg2, disp8[ep] reg2, disp16[reg1] reg2, disp16[reg1] reg2, disp16[reg1] reg1, reg2 imm5, reg2 imm16, reg1, reg2 imm16, reg1, reg2 reg1, reg2 imm5, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 op code flag sat z s ov cy operation adr ? ep+zero-extend(disp7) gr[reg2] ? sign-extend(load-memory(adr, byte)) adr ? ep+zero-extend(disp8) gr[reg2] ? sign-extend(load-memory(adr, halfword)) adr ? ep+zero-extend(disp8) gr[reg2] ? load-memory(adr, word) adr ? gr[reg1]+sign-extend(disp16) gr[reg2] ? sign-extend(load-memory(adr, byte)) adr ? gr[reg1]+sign-extend(disp16) gr[reg2] ? sign-extend(load-memory(adr, halfword)) adr ? gr[reg1]+sign-extend(disp16) gr[reg2] ? load-memory(adr, word) adr ? ep+zero-extend(disp7) store-memory(adr, gr[reg2], byte) adr ? ep+zero-extend(disp8) store-memory(adr, gr[reg2], halfword) adr ? ep+zero-extend(disp8) store-memory(adr, gr[reg2], word) adr ? gr[reg1]+sign-extend(disp16) store-memory(adr, gr[reg2], byte) adr ? gr[reg1]+sign-extend(disp16) store-memory(adr, gr[reg2], halfword) adr ? gr[reg1]+sign-extend(disp16) store-memory(adr, gr[reg2], word) gr[reg2] ? gr[reg1] gr[reg2] ? sign-extend(imm5) gr[reg2] ? gr[reg1]+(imm16 || 0 16 ) gr[reg2] ? gr[reg1]+sign-extend(imm16) gr[reg2] ? gr[reg2]+gr[reg1] gr[reg2] ? gr[reg2]+sign-extend(imm5) gr[reg2] ? gr[reg1]+sign-extend(imm16) gr[reg2] ? gr[reg2]Cgr[reg1] gr[reg2] ? gr[reg1]Cgr[reg2] rrrrr0110ddddddd rrrrr1000ddddddd note 1 rrrrr1010dddddd0 note 2 rrrrr111000rrrrr ddddddddddddddd rrrrr111001rrrrr ddddddddddddddd0 note 3 rrrrr111001rrrrr ddddddddddddddd1 note 3 rrrrr0111ddddddd rrrrr1001ddddddd note 1 rrrrr1010dddddd1 note 2 rrrrr111010rrrrr dddddddddddddddd rrrrr111011rrrrr ddddddddddddddd0 note 3 rrrrr111011rrrrr ddddddddddddddd1 note 3 rrrrr000000rrrrr rrrrr010000iiiii rrrrr110010rrrrr iiiiiiiiiiiiiiii rrrrr110001rrrrr iiiiiiiiiiiiiiii rrrrr001110rrrrr rrrrr010010iiiii rrrrr110000rrrrr iiiiiiiiiiiiiii rrrrr001101rrrrr rrrrr001100rrrrr arithmetic operation notes 1. ddddddd = the higher 7-bit of disp8 2. dddddd = the higher 6-bit of disp8 3. ddddddddddddddd = the higher 15-bit of disp16 load/store instruction set list
43 m pd703000, 703001 instruction group mnemonic operand mulh mulh mulhi divh cmp cmp setf satadd satadd satsub satsubi satsubr tst or ori and andi xor xori not shl shl shr shr sar sar reg1, reg2 imm5, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 imm5, reg2 cccc, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm5, reg2 reg1, reg2 imm5, reg2 op code flag sat z s ov cy operation gr[reg2] ? gr[reg2] note gr[reg1] note (signed multiply) gr[reg2] ? gr[reg2] note sign-extend(imm5) (signed multiply) gr[reg2] ? gr[reg2] note imm16 (signed multiply) gr[reg2] ? gr[reg2] ? gr[reg1] note (signed divide) result ? gr[reg2]Cgr[reg1] result ? gr[reg2]Csign-extend(imm5) if conditions are satisfied then gr[reg2] ? 00000001h else gr[reg2] ? 00000000h gr[reg2] ? saturated(gr[reg2]+gr[reg1]) gr[reg2] ? saturated(gr[reg2]+sign-extend(imm5)) gr[reg2] ? saturated(gr[reg2]Cgr[reg1]) gr[reg2] ? saturated(gr[reg1]Csign-extend(imm16)) gr[reg2] ? saturated(gr[reg1]Cgr[reg2]) result ? gr[reg2]and gr[reg1] gr[reg2] ? gr[reg2]or gr[reg1] gr[reg2] ? gr[reg1]or zero-extend(imm16) gr[reg2] ? gr[reg2]and gr[reg1] gr[reg2] ? gr[reg1]and zero-extend(imm16) gr[reg2] ? gr[reg2]xor gr(reg1) gr[reg2] ? gr[reg1]xor zero-extend(imm16) gr[reg2] ? not(gr[reg1]) gr[reg2] ? gr[reg2]logically shift left by gr[reg1] gr[reg2] ? gr[reg2]logically shift left by zero-extend(imm5) gr[reg2] ? gr[reg2]logically shift right by gr[reg1] gr[reg2] ? gr[reg2]logically shift right by zero-extend(imm5) gr[reg2] ? gr[reg2]arithmetically shift right by gr[reg1] gr[reg2] ? gr[reg2]arithmetically shift right by zero-extend(imm5) rrrrr000111rrrrr rrrrr010111iiiii rrrrr110111rrrrr iiiiiiiiiiiiiii rrrrr000010rrrrr rrrrr001111rrrrr rrrrr010011iiiii rrrrr1111110cccc 0000000000000000 rrrrr000110rrrrr rrrrr010001iiiii rrrrr000101rrrrr rrrrr110011rrrrr iiiiiiiiiiiiiiii rrrrr000100rrrrr rrrrr001011rrrrr rrrrr001000rrrrr rrrrr110100rrrrr iiiiiiiiiiiiiiii rrrrr001010rrrrr rrrrr110110rrrrr iiiiiiiiiiiiiiii rrrrr001001rrrrr rrrrr110101rrrrr iiiiiiiiiiiiiiii rrrrr000001rrrrr rrrrr111111rrrrr 0000000011000000 rrrrr010110iiiii rrrrr111111rrrrr 0000000010000000 rrrrr010100iiiii rrrrr111111rrrrr 0000000010100000 rrrrr010101iiiii 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note only the lower halfword data is valid. arithmetic operation logical operation saturation operation
44 m pd703000, 703001 instruction group mnemonic operand jmp jr jarl bcond set1 clr1 not1 tst1 [reg1] disp22 disp22, reg2 disp9 bit#3, disp16[reg1] bit#3, disp16[reg1] bit#3, disp16[reg1] bit#3, disp16[reg1] op code flag sat z s ov cy operation pc ? gr[reg1] pc ? pc+sign-extend(disp22) gr[reg2] ? pc+4 pc ? pc+sign-extend(disp22) if conditions are satisfied then pc ? pc+sign-extend(disp9) adr ? gr[reg1]+sign-extend(disp16) z flag ? not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3, 1) adr ? gr[reg1]+sign-extend(disp16) z flag ? not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3, 0) adr ? gr[reg1]+sign-extend(disp16) z flag ? not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3, z flag) adr ? gr[reg1]+sign-extend(disp16) z flag ? not(load-memory-bit(adr, bit#3)) 00000000011rrrrr 0000011110dddddd ddddddddddddddd0 note 1 rrrrr11110dddddd ddddddddddddddd0 note 1 ddddd1011dddcccc note 2 00bbb111110rrrrr ddddddddddddddd 10bbb111110rrrrr ddddddddddddddd 01bbb111110rrrrr ddddddddddddddd 11bbb111110rrrrr ddddddddddddddd notes 1. ddddddddddddddddddddd = the higher 21-bit of disp22 2. dddddddd = the higher 8-bit of disp9 branch bit manipulation
45 m pd703000, 703001 instruction group mnemonic operand reg2, regid regid, reg2 vector op code flag sat z s ov cy operation sr[regid] ? gr[reg2] reg id = eipc, fepc reg id = eipsw, fepsw regid = psw gr[reg2] ? sr[regid] eipc ? pc+4 (restore pc) eipsw ? psw ecr.eicc ? interrupt code psw.ep ? 1 psw.id ? 1 pc ? 00000040h(vector=00h-0fh) 00000050h(vector=10h-1fh) if psw.ep=1 then pc ? eipc psw ? eipsw else if psw.np=1 then pc ? fepc psw ? fepsw else pc ? eipc psw ? eipsw stops psw.id ? 1 (disables maskable interrupt) psw.id ? 0 (enables maskable interrupt) dissipates 1 clock cycle without doing anything rrrrr111111rrrrr 0000000000100000 note rrrrr111111rrrrr 0000000001000000 00000111111iiiii 0000000100000000 0000011111100000 0000000101000000 0000011111100000 0000000100100000 0000011111100000 0000000101100000 1000011111100000 0000000101100000 0000000000000000 special rrr rr ldsr stsr trap reti halt di ei nop note this instruction uses reg2 as the source register, but its op code actually uses the field of reg1. therefore, the meanings of the register specification for the mnemonic and op code of this instruction are different from those of other instructions. rrrrr = regid specification, rrrrr = reg2 specification
46 m pd703000, 703001 12. electrical specifications supported electrical characteristics part number v dd = 5.0 v 10% v dd = 3.0 to 3.6 v m pd703000gc-25-xxx-7ea electrical characteristics specified outside of guaranteed operating range m pd703001gc-25-7ea electrical characteristics specified outside of guaranteed operating range m pd703000gc-33-xxx-7ea electrical characteristics specified electrical characteristics specified m pd703001gc-33-7ea electrical characteristics specified electrical characteristics specified remark xxx indicates a rom code suffix. 12.1 when v dd = 5.0 v 10% absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd v dd pin C0.5 to +7.0 v cv dd cv dd pin C0.5 to +7.0 v cv ss cv ss pin C0.5 to +0.5 v input voltage v i1 except x1 pin, v dd = 5.0 v 10% C0.5 to v dd +0.3 v clock input voltage vx x1 pin, v dd = 5.0 10% C0.5 to v dd +1.0 v output current, low i ol 1 pin 4.0 ma total of all pins 100 ma output current, high i oh 1 pin C4.0 ma total of all pins C100 ma output voltage v o v dd = 5.0 v 10% C0.5 to v dd +0.3 v operating temperature t a operating at 25 mhz C40 to +85 c operating at 33 mhz C20 to +70 c storage temperature t stg C65 to +150 c cautions 1. do not directly connect to the output (or i/o) pins of an ic product, or to the v dd , v cc , or gnd. open-drain pins and open-collector pins may be connected each other however. moreover, an external circuit that is designed so as to avoid output contention can be directly connected to a pin that goes into a high-impedance state. 2. if even one of the parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be impaired. the absolute maximum ratings specify the values exceeding which the product may be physically damaged. never exceed these ratings when using the products. the specifications and conditions shown in dc and ac characteristics below specify the range in which the product operates normally and the product quality is guaranteed. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i f c = 1 mhz 15 pf i/o capacitance c io 0 v for pins other than test pin 15 pf output capacitance c o 15 pf
47 m pd703000, 703001 operating conditions operation mode internal operating clock frequency ( f ) operating temperature (t a ) supply voltage (v dd ) direct mode 0 to 25 mhz C40 to +85 c 5.0 v 10% 0 to 33 mhz C20 to +70 c pll mode C40 to +85 c 5.0 v 10% C20 to +70 c recommended oscillation circuit (a) connecting ceramic oscillator (tdk, murata mfg.: t a = C40 to +85 c, kyocera: t a = C20 to +80 c) self-running oscillation frequency to 25 mhz self-running oscillation frequency to 33 mhz x1 x2 c1 c2 0.26 0.62 0.30 0.38 0.32 1.2 0.8 0.3 0.4 0.2 0.13 0.13 0.10 0.10 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 internal internal internal internal internal 82 68 47 33 33 30 internal 30 internal internal internal internal internal internal 82 68 47 33 33 30 internal 30 internal 2.0 3.2 5.0 5.0 6.6 2.0 2.7 3.2 5.0 6.6 5.0 5.0 6.6 6.6 fcr2.0mc3 ccr3.2mc3 fcr5.0mc5 ccr5.0mc3 ccr6.6mc3 kbr-2.0ms kbr-2.7ms kbr-3.2ms kbr-5.0msa kbr-6.6m csa5.00mg cst5.00mgw csa6.60mtz cst6.60mtw tdk corp. kyocera corp. murata mfg. co., ltd. manufacturer part number oscillation frequency f xx (mhz) recommended circuit constant oscillation stabilization time (max.) t ost (ms) oscillation voltage range c1 (pf) c2 (pf) min. (v) max. (v) cautions 1. connect the oscillation circuit as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the dotted line in the above figure. 3. thoroughly evaluate the matching between the pd703000 and oscillator. m
48 m pd703000, 703001 (b) external clock input open x1 x2 external clock caution input the voltage at the cmos level to the x1 pin.
49 m pd703000, 703001 dc characteristics (t a = C40 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) : m pd703000gc-25 ( t a = C20 to +70 c, v dd = 5.0 v 10%, v ss = 0 v) : m pd703000gc-33 parameter symbol condition min. typ. max. unit input voltage, high v ih x1 , except note 1 2.2 v dd v note 1 0.8 v dd v dd v input voltage, low v il x1 , except note 1 0 +0.8 v note 1 0 0.2 v dd v x1 clock input voltage, high v xh direct mode 0.8 v dd v dd v pll mode 0.8 v dd v dd v x1 clock input voltage, low v xl direct mode 0 0.6 v pll mode 0 0.6 v schmitt trigger input v t + note 1 rising 3.0 v threshold voltage v t C note 1 falling 2.0 v schmitt trigger input v t + Cv t C note 1 0.5 v hysteresis width output voltage, high v oh i oh = C2.5ma 0.7v dd v i oh = C100 m av dd C0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd 10 m a input leakage current, low i lil v i = 0 v C10 m a output leakage current, high i loh v o = v dd 10 m a output leakage current, low i lol v o = 0v C10 m a supply current operating i dd1 direct mode 1.5 f +5 1.8 f +10 ma pll mode 1.6 f +7 2.0 f +13 ma halt i dd2 direct mode 0.5 f +3 0.7 f +10 ma pll mode 0.6 f +5 0.9 f +13 ma idle i dd3 direct mode 8 f +300 10 f +500 m a pll mode 0.1 f +2 0.2 f +3 ma stop i dd4 note 2 150 m a note 3 200 m a notes 1. reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/ intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel 2. operating at 25 mhz: C40 c t a +50 c operating at 33 mhz: C20 c t a +50 c 3. operating at 25 mhz: 50 c < t a 85 c operating at 33 mhz: 50 c < t a 70 c remarks 1. typ. value is a value for reference at t a = 25 c, v dd = 5.0 v. 2. f : internal operating clock frequency
50 m pd703000, 703001 data retention characteristics (t a = C40 to +85 c) : m pd703000gc-25 (t a = C20 to +70 c) : m pd703000gc-33 parameter symbol condition min. typ. max. unit data hold voltage v dddr stop mode 1.5 5.5 v data hold current i dddr v dd = v dddr note 1 0.2v dddr 50 m a note 2 0.2v dddr 200 m a supply voltage rise time t rvd 200 m s supply voltage fall time t fvd 200 m s supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode releasing signal t drel 0ns input time data hold input voltage, high v ihdr note 3 0.9v dddr v dddr v data hold input voltage, low v ildr note 3 0 0.1v dddr v notes 1. operating at 25 mhz: C40 c t a +50 c operating at 33 mhz: C20 c t a +50 c 2. operating at 25 mhz: 50 c < t a 85 c operating at 33 mhz: 50 c < t a 70 c 3. reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 remark typ. value is a value for reference at t a = 25 c, v dd = 5.0 v. t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (released by falling edge) v ihdr v ildr nmi (input) (released by rising edge) stop mode set
51 m pd703000, 703001 ac characteristics (t a = C40 to +85 c, v dd = 5.0 v 10%, v ss = 0 v): m pd703000gc-25 (t a = C20 to +70 c, v dd = 5.0 v 10%, v ss = 0 v): m pd703000gc-33 ac test input waveform (a) reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 (b) other than (a) above test point 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v ac test output test point 2.2 v 0.8 v 2.2 v 0.8 v test point load condition c l = 50 pf dut (tested device) caution if the load capacitance exceeds 50 pf due to the configuration of the circuit, keep the load capacitance of this device to within 50 pf by using a buffer. 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v test point
52 m pd703000, 703001 (1) clock timing parameter symbol conditions m pd703000-25 m pd703000-33 unit min. max. min. max. x1 input cycle <1> t cyx direct mode 20 dc 15 dc ns pll mode 200 315 150 334 ns x1 input high-level width <2> t wxh direct mode 7 6 ns pll mode 80 60 ns x1 input low-level width <3> t wxl direct mode 7 6 ns pll mode 80 60 ns x1 input rise time <4> t xr direct mode 7 7 ns pll mode 15 10 ns x1 input fall time <5> t xf direct mode 7 7 ns pll mode 15 10 ns cpu operating frequency C f 0 25 0 33 mhz clkout output cycle <6> t cyk 40 dc 30 dc ns clkout high-level width <7> t wkh 0.5tC5 0.5tC5 ns clkout low-level width <8> t wkl 0.5tC5 0.5tC5 ns clkout rise time <9> t kr 55ns clkout fall time <10> t kf 55ns x1 ? clkout delay time <11> t dxk direct mode 3 17 3 17 ns remark t = t cyk parameter symbol condition m pd703000-25 m pd703000-33 unit typ. typ. self-running oscillation C f p pll mode 2.8 2.8 mhz frequency x1 (input) (pll mode) x1 (input) (direct mode) clkout (output) <1> <10 > <9> <7> <6> <8> <11 > <11 > <2> <3> <1> <2> <3> <5> <4> <4> <5>
53 m pd703000, 703001 (2) input wavefrom (a) reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. input rise time <12> t ir2 20 20 ns input fall time <13> t if2 20 20 ns 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v input signal <13> <12> (b) other than (a) above parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. input rise time <14> t ir1 10 10 ns input fall time <15> t if1 10 10 ns 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v input signal <15> <14>
54 m pd703000, 703001 (3) output waveform (other than clkout) parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. output rise time <16> t or 10 10 ns output fall time <17> t of 10 10 ns (4) reset timing parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. reset high-level width <18> t wrsh 500 500 ns reset low-level width <19> t wrsl on power application and on 500+t ost 500-t ost ns releasing stop mode except on power application 500 500 ns and on releasing stop mode remark t ost : oscillation stabilization time 0.8 v 2.2 v output signal <16> <17> 2.2 v 0.8 v reset (input) <18> <19>
55 m pd703000, 703001 [memo]
56 m pd703000, 703001 (5) read timing (1/2) parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. clkout - ? address delay time <20> t dka 320320ns clkout - ? address float delay time <21> t fka 315315ns clkout ? astb delay time <22> t dkst 315315ns clkout - ? dstb delay time <23> t dkd 315315ns clkout - ? status delay time <24> t dks 315315ns data input setup time (vs. clkout - ) <25> t sidk 55ns data input hold time (vs. clkout - ) <26> t hkid 55ns wait setup time (vs. clkout ) <27> t swtk 55ns wait hold time (vs. clkout ) <28> t hkwt 55ns address hold time (vs. clkout - ) <29> t hka 00ns address setup time (vs. astb ) <30> t sast 0.5tC10 0.5tC10 ns address hold time (vs. astb ) <31> t hsta 0.5tC10 0.5tC10 ns dstb ? address float delay time <32> t fda 00ns data input setup time (vs. address) <33> t said (2+n)tC20 (2+n)tC20 ns data input setup time (vs. dstb ) <34> t sdid (1+n)tC20 (1+n)tC20 ns astb ? dstb delay time <35> t dstd 0.5tC10 0.5tC10 ns data input hold time (vs. dstb - ) <36> t hdid 00ns dstb - ? address output delay time <37> t dda (1+i)t (1+i)t ns dstb - ? astb - delay time <38> t ddsth 0.5tC10 0.5tC10 ns dstb - ? astb delay time <39> t ddstl (1.5+i)tC10 (1.5+i)tC10 ns status setup time (vs. astb ) <40> t ssst 0.5tC10 0.5tC10 ns status hold time (vs. astb - ) <41> t hsts 0.5tC10 0.5tC10 ns dstb low-level width <42> t wdl (1+n)tC10 (1+n)tC10 ns astb high-level width <43> t wsth tC10 tC10 ns wait setup time (vs. address) <44> t sawt1 n 3 1 1.5tC20 1.5tC20 ns <45> t sawt2 (1.5+n)tC20 (1.5+n)tC20 ns wait hold time (vs. address) <46> t hawt1 n 3 1 (0.5+n)t (0.5+n)t ns <47> t hawt2 (1.5+n)t (1.5+n)t ns wait setup time (vs. astb ) <48> t sstwt1 n 3 1 tC15 tC15 ns <49> t sstwt2 (1+n)tC15 (1+n)tC15 ns wait hold time (vs. astb ) <50> t hstwt1 n 3 1ntntns <51> t hstwt2 (1+n)t (1+n)t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted. 3. i indicates the number of idle states (0 or 1) inserted in the read cycle. 4. satisfy at least one of the data input hold times t hkid (<26>) and t hdid (<36>).
57 m pd703000, 703001 (5) read timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16-a23 (output) note ad0-ad15 (i/o) astb (output) dstb (output) st0, st1 (output) wait (input) <33> <20> <29> <26> <25> <21> a0-a15 (output) d0-d15 (input) <22> <30> <31> <22> <36> <38> <37> <23> <32> <43> <34> <23> <42> <39> <24> <41> <40> <24> <27> <28> <27> <50> <49> <51> <28> <48> <44> <47> <46> <45> note r/w (output), uben (output), lben (output) remark the dotted line indicates a high-impedance state. <35>
58 m pd703000, 703001 (6) write timing (1/2) parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. clkout - ? address delay time <20> t dka 320320ns clkout ? astb delay time <22> t dkst 315315ns clkout - ? dstb delay time <23> t dkd 315315ns clkout - ? status delay time <24> t dks 315315ns wait setup time (vs. clkout ) <27> t swtk 55ns wait hold time (vs. clkout ) <28> t hkwt 55ns address hold time (vs. clkout - ) <29> t hka 00ns address setup time (vs. astb ) <30> t sast 0.5tC10 0.5tC10 ns address hold time (vs. astb ) <31> t hsta 0.5tC10 0.5tC10 ns astb ? dstb delay time <35> t dstd 0.5tC10 0.5tC10 ns dstb - ? astb - delay time <38> t ddsth 0.5tC10 0.5tC10 ns status setup time (vs. astb ) <40> t ssst 0.5tC10 0.5tC10 ns status hold time (vs. astb - ) <41> t hsts 0.5tC10 0.5tC10 ns dstb low-level width <42> t wdl (1+n)tC10 (1+n)tC10 ns astb high-level width <43> t wsth tC10 tC10 ns wait setup time (vs. address) <44> t sawt1 n 3 1 1.5tC20 1.5tC20 ns <45> t sawt2 (1.5+n)tC20 (1.5+n)tC20 ns wait hold time (vs. address) <46> t hawt1 n 3 1 (0.5+n)t (0.5+n)t ns <47> t hawt2 (1.5+n)t (1.5+n)t ns wait setup time (vs. astb ) <48> t sstwt1 n 3 1 tC15 tC15 ns <49> t sstwt2 (1+n)tC15 (1+n)tC15 ns wait hold time (vs. astb ) <50> t hstwt1 n 3 1ntntns <51> t hstwt2 (1+n)t (1+n)t ns clkout - ? data output delay time <52> t dkod 20 20 ns dstb ? data output delay time <53> t ddod 10 10 ns data output hold time (vs. clkout - ) <54> t hkod 00ns data output setup time (vs. dstb - ) <55> t sodd (1+n)tC15 (1+n)tC15 ns data output hold time (vs. dstb - ) <56> t hdod t-10 t-10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted.
59 m pd703000, 703001 (6) write timing (2/2): 1 wait t1 t2 tw t3 <20> <29> <52> <22> <30> <31> <22> <38> <56> <23> <23> <43> <55> <35> <42> <24> <41> <40> <24> <27> <28> <27> <50> <49> <51> <28> <48> <44> <47> <46> <45> <54> clkout (output) a16-a23 (output) note ad0-ad15 (i/o) astb (output) dstb (output) st0, st1 (output) wait (input) a0-a15 (output) d0-d15 (output) note r/w (output), uben (output), lben (output) remark the dotted line indicates a high-impedance state. <53>
60 m pd703000, 703001 (7) bus hold timing (1/2) parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. hldrq setup time (vs. clkout ) <57> t shqk 55ns hldrq hold time (vs. clkout ) <58> t hkhq 55ns clkout - ? hldak delay time <59> t dkha 20 20 ns hldrq high-level width <60> t whqh t+10 t+10 ns hldak low-level width <61> t whal tC10 tC10 ns clkout -? bus float delay time <62> t dkf 20 20 ns hldak - ? bus output delay time <63> t dhac C3 C3 ns hldrq ? hldak delay time <64> t dhqha1 (2n+7.5)t+20 (2n+7.5)t+20 ns hldrq - ? hldak - delay time <65> t dhqha2 0.5t 1.5t+20 0.5t 1.5t+20 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted.
61 m pd703000, 703001 (7) bus hold timing (2/2) th th th ti th clkout (output) hldak (output) dstb (output) st0, st1 (output) r/w (output) hldrq (input) astb (output) ad0-ad15 (i/o) d0-d15 (input or output) <58> <64> <65> <60> <57> <58> <57> <57> <59> <61> <59> <63> <62> a16-a23 (output) note note uben (output), lben (output) remark the dotted line indicates a high-impedance state.
62 m pd703000, 703001 (8) interrupt timing parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. nmi high-level width <66> t wnih 500 500 ns nmi low-level width <67> t wnil 500 500 ns intpn high-level width <68> t with n=00, 01, 02, 03, 10, 11, 12, 13 3t+10 3t+10 ns intpn low-level width <69> t witl n=00, 01, 02, 03, 10, 11, 12, 13 3t+10 3t+10 ns remark t = t cyk nmi (input) <66> <67> intpn (input) <68> <69> remark n = 00, 01, 02, 03, 10, 11, 12, 13
63 m pd703000, 703001 (9) csi timing (a) master mode parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. sck cycle <70> t cysk output 160 120 ns sck high-level width <71> t wskh output 0.5t cysk C20 0.5t cysk C20 ns sck low-level width <72> t wskl output 0.5t cysk C20 0.5t cysk C20 ns si setup time (vs. sck - ) <73> t ssisk 30 30 ns si hold time (vs. sck - ) <74> t hsksi 00ns so output delay time <75> t dskso 18 18 ns (vs. sck ) so output hold time <76> t hskso 0.5t cysk C5 0.5t cysk C5 ns (vs. sck - ) (b) slave mode parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. sck cycle <70> t cysk input 160 120 ns sck high-level width <71> t wskh input 50 30 ns sck low-level width <72> t wskl input 50 30 ns si setup time (vs. sck - ) <73> t ssisk 10 10 ns si hold time (vs. sck - ) <74> t hsksi 10 10 ns so output delay time <75> t dskso 30 30 ns (vs. sck ) so output hold time <76> t hskso t wskh t wskh ns (vs. sck - ) sck (i/o) si (input) so (output) <70> <72> <71> <73> <74> <75> <76> input data output data remark the dotted line indicates a high-impedance state.
64 m pd703000, 703001 (10) rpu timing parameter symbol condition m pd703000-25 m pd703000-33 unit min. max. min. max. ti1 high-level width <77> t wtih 3t+10 3t+10 ns ti1 low-level width <78> t wtil 3t+10 3t+10 ns tclr1 high-level width <79> t wtch 3t+10 3t+10 ns tclr1 low-level width <80> t wtcl 3t+10 3t+10 ns remark t = t cyk ti1 (input) <77> <78> tclr1 (input) <79> <80>
65 m pd703000, 703001 12.2 when v dd = 3.0 to 3.6 v absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd v dd pin C0.5 to +7.0 v cv dd cv dd pin C0.5 to +7.0 v cv ss cv ss pin C0.5 to +0.5 v input voltage v i1 except x1 pin, v dd = 3.0 to 3.6 v C0.5 to v dd +0.3 v clock input voltage vx x1 pin, v dd = 3.0 to 3.6 v C0.5 to v dd +1.0 v output current, low i ol 1 pin 4.0 ma total of all pins 100 ma output current, high i oh 1 pin C4.0 ma total of all pins C100 ma output voltage v o v dd = 3.0 to 3.6 v C0.5 to v dd +0.3 v operating temperature t a C20 to +70 c storage temperature t stg C65 to +150 c cautions 1. do not directly connect to the output (or i/o) pins of an ic product, or to the v dd , v cc , or gnd. open-drain pins and open-collector pins may be connected each other however. moreover, an external circuit that is designed so as to avoid output contention can be directly connected to a pin that goes into a high-impedance state. 2. if even one of the parameters exceeds the absolute maximum rating even momentarily, the quality of the product may be affected. the absolute maximum ratings specify the values exceeding which the product may be physically damaged. never exceed these ratings when using the product. the specifications and conditions shown in dc and ac characteristics below specify the range in which the product operates normally and the product quality is guaranteed. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i f c = 1 mhz 15 pf i/o capacitance c io 0 v for pins other than test pin 15 pf output capacitance c o 15 pf operating conditions operation mode internal operating clock frequency ( f ) operating temperature (t a ) supply voltage (v dd ) direct mode 0 to 12 mhz C20 to +70 c 3.0 to 3.6 v pll mode C20 to +70 c 3.0 to 3.6 v self-running oscillation frequency to 12 mhz
66 m pd703000, 703001 recommended oscillation circuit (a) connecting ceramic resonator (t a = C40 to +85 c) x1 x2 c1 c2 0.26 0.62 0.24 0.24 0.16 0.16 0.13 0.13 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 internal internal 30 internal 30 internal 30 internal internal internal 30 internal 30 internal 30 internal 2.0 3.2 2.0 2.0 2.7 2.7 3.2 3.2 fcr2.0mc3 ccr3.2mc3 csa2.00mg cst2.00mg csa2.70mg cst2.70mgw csa3.20mg cst3.20mgw tdk corp. murata mfg. co., ltd. manufacturer part number oscillation frequency f xx (mhz) recommended circuit constant oscillation stabilization time (max.) t ost (ms) oscillation voltage range c1 (pf) c2 (pf) min. (v) max. (v) cautions 1. connect the oscillation circuit as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the dotted line in the above figure. 3. thoroughly evaluate the matching between the pd703000 and oscillator. m (b) external clock input open x1 x2 external clock caution input the voltage at the cmos level to the x1 pin.
67 m pd703000, 703001 dc characteristics (t a = C20 to +70 c, v dd = 3.0 to 3.6 v, v ss = 0 v) parameter symbol condition min. typ. max. unit input voltage, high v ih except x1 and note 0.7 v dd v dd v note 0.8 v dd v dd v input voltage, low v il except x1 and note 0 0.2 v dd v note 0 0.2 v dd v x1 clock input voltage, high v xh direct mode 0.8 v dd v dd v pll mode 0.8 v dd v dd v x1 clock input voltage, low v xl direct mode 0 0.6 v pll mode 0 0.6 v schmitt trigger input v t + note , rising 3.0 v threshold voltage v t C note , falling 2.0 v schmitt trigger input v t + Cv t C note 0.5 v hysteresis width output voltage, high v oh i oh = C2.5ma 0.7v dd v i oh = C100 m av dd C0.5 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd 10 m a input leakage current, low i lil v i = 0 v C10 m a output leakage current, high i loh v o = v dd 10 m a output leakage current, low i lol v o = 0v C10 m a supply current operating i dd1 direct mode 1.0 f +3.5 1.2 f +6.5 ma pll mode 1.1 f +5 1.3 f +8.5 ma halt i dd2 direct mode 0.3 f +2 0.5 f +6.5 ma pll mode 0.4 f +3.5 0.6 f +8.5 ma idle i dd3 direct mode 5.3 f +200 6.5 f +325 m a pll mode 0.07 f +1.5 0.15 f +2 ma stop i dd4 C20 c t a +50 c140 m a 50 c < t a 70 c 200 m a note reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/ intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel remarks 1. typ. value is a value for reference at t a = 25 c, v dd = 3.3 v. 2. f : internal operating clock frequency
68 m pd703000, 703001 data retention characteristics (t a = C20 to +70 c) parameter symbol condition min. typ. max. unit data hold voltage v dddr stop mode 1.5 3.6 v data hold current i dddr v dd = v dddr C20 c t a +50 c 0.2v dddr 40 m a 50 c < t a 70 c 0.2v dddr 200 m a supply voltage rise time t rvd 200 m s supply voltage fall time t fvd 200 m s supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode releasing signal t drel 0ns input time data hold input voltage, high v ihdr note 0.9v dddr v dddr v data hold input voltage, low v ildr note 0 0.1v dddr v note reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/ intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 remark typ. value is a value for reference at t a = 25 c, v dd = 3.3 v. t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (released by falling edge) v ihdr v ildr nmi (input) (released by rising edge) stop mode set
69 m pd703000, 703001 ac characteristics (t a = C20 to +70 c, v dd = 3.0 to 3.6 v, v ss = 0 v) ac test input waveform (a) reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 (b) other than (a) above test point 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v ac test output test point 2.2 v 0.8 v 2.2 v 0.8 v test point load condition c l = 50 pf dut (tested device) caution if the load capacitance exceeds 50 pf due to the configuration of the circuit, keep the load capacitance of this device to within 50 pf by using a buffer. 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd 2.4 v 0.4 v test point
70 m pd703000, 703001 (1) clock timing parameter symbol conditions min. max. unit x1 input cycle <1> t cyx direct mode 41 dc ns pll mode 416 500 ns x1 input high-level width <2> t wxh direct mode 7 ns pll mode 170 ns x1 input low-level width <3> t wxl direct mode 7 ns pll mode 170 ns x1 input rise time <4> t xr direct mode 7 ns pll mode 15 ns x1 input fall time <5> t xf direct mode 7 ns pll mode 15 ns cpu operating frequency C f 0 12 mhz clkout output cycle <6> t cyk 82 dc ns clkout high-level width <7> t wkh 0.5tC15 ns clkout low-level width <8> t wkl 0.5tC15 ns clkout rise time <9> t kr 15 ns clkout fall time <10> t kf 15 ns x1 ? clkout delay time <11> t dxk direct mode 3 30 ns remark t = t cyk parameter symbol condition typ. unit self-running oscillation C f p pll mode 2.8 mhz frequency x1 (input) (pll mode) x1 (input) (direct mode) clkout (output) <1> <10 > <9> <7> <6> <8> <11 > <11 > <2> <3> <1> <2> <3> <5> <4> <4> <5>
71 m pd703000, 703001 (2) input waveform (a) reset, p02/tclr1, p03/ti1, p04/intp10 through p07/intp13, p20/nmi, p21/intp00 through p24/intp03, p26, p27, p31/si, p32/sck, p36, p37, mode0, mode1, cksel, x1 parameter symbol condition min. max. unit input rise time <12> t ir2 20 ns input fall time <13> t if2 20 ns 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd v dd 0 v input signal <13> <12> (b) other than (a) above parameter symbol condition min. max. unit input rise time <14> t ir1 10 ns input fall time <15> t if1 10 ns 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd 2.4 v 0.4 v input signal <15> <14>
72 m pd703000, 703001 (3) output waveform (other than clkout) parameter symbol condition min. max. unit output rise time <16> t or 20 ns output fall time <17> t of 20 ns 0.8 v 2.2 v output signal <16> <17> 2.2 v 0.8 v reset (input) <18> <19> (4) reset timing parameter symbol condition min. max. unit reset high-level width <18> t wrsh 500 ns reset low-level width <19> t wrsl on power application and on releasing 500+t ost ns stop mode except on power application and on releasing 500 ns stop mode remark t ost : oscillation stabilization time
73 m pd703000, 703001 [memo]
74 m pd703000, 703001 (5) read timing (1/2) parameter symbol condition min. max. unit clkout - ? address delay time <20> t dka 332ns clkout - ? address float delay time <21> t fka 332ns clkout ? astb delay time <22> t dkst 332ns clkout - ? dstb delay time <23> t dkd 332ns clkout - ? status delay time <24> t dks 332ns data input setup time (vs. clkout - ) <25> t sidk 5ns data input hold time (vs. clkout - ) <26> t hkid 5ns wait setup time (vs. clkout ) <27> t swtk 7ns wait hold time (vs. clkout ) <28> t hkwt 7ns address hold time (vs. clkout - ) <29> t hka 0ns address setup time (vs. astb ) <30> t sast 0.5tC25 ns address hold time (vs. astb ) <31> t hsta 0.5tC15 ns dstb ? address float delay time <32> t fda 0ns data input setup time (vs. address) <33> t said (2+n)tC45 ns data input setup time (vs. dstb ) <34> t sdid (1+n)tC35 ns astb ? dstb delay time <35> t dstd 0.5tC15 ns data input hold time (vs. dstb - ) <36> t hdid 0ns dstb - ? address output delay time <37> t dda (1+i)t ns dstb - ? astb - delay time <38> t ddsth 0.5tC15 ns dstb - ? astb delay time <39> t ddstl (1.5+i)tC15 ns status setup time (vs. astb ) <40> t ssst 0.5tC15 ns status hold time (vs. astb - ) <41> t hsts 0.5tC20 ns dstb low-level width <42> t wdl (1+n)tC15 ns astb high-level width <43> t wsth tC20 ns wait setup time (vs. address) <44> t sawt1 n 3 1 1.5tC50 ns <45> t sawt2 (1.5+n)tC50 ns wait hold time (vs. address) <46> t hawt1 n 3 1 (0.5+n)t ns <47> t hawt2 (1.5+n)t ns wait setup time (vs. astb ) <48> t sstwt1 n 3 1 tC35 ns <49> t sstwt2 (1+n)tC35 ns wait hold time (vs. astb ) <50> t hstwt1 n 3 1ntns <51> t hstwt2 (1+n)t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted. 3. i indicates the number of idle states (0 or 1) inserted in the read cycle. 4. satisfy at least one of the data input hold times t hkid (<26>) and t hdid (<36>).
75 m pd703000, 703001 (5) read timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16-a23 (output) note ad0-ad15 (i/o) astb (output) dstb (output) st0, st1 (output) wait (input) <33> <20> <29> <26> <25> <21> a0-a15 (output) d0-d15 (input) <22> <30> <31> <22> <36> <38> <37> <23> <32> <43> <34> <23> <42> <39> <24> <41> <40> <24> <27> <28> <27> <50> <49> <51> <28> <48> <44> <47> <46> <45> note r/w (output), uben (output), lben (output) remark the dotted line indicates a high-impedance state. <35>
76 m pd703000, 703001 (6) write timing (1/2) parameter symbol condition min. max. unit clkout - ? address delay time <20> t dka 332ns clkout ? astb delay time <22> t dkst 332ns clkout - ? dstb delay time <23> t dkd 332ns clkout - ? status delay time <24> t dks 332ns wait setup time (vs. clkout ) <27> t swtk 7ns wait hold time (vs. clkout ) <28> t hkwt 7ns address hold time (vs. clkout - ) <29> t hka 0ns address setup time (vs. astb ) <30> t sast 0.5tC25 ns address hold time (vs. astb ) <31> t hsta 0.5tC15 ns astb ? dstb delay time <35> t dstd 0.5tC15 ns dstb - ? astb - delay time <38> t ddsth 0.5tC15 ns status setup time (vs. astb ) <40> t ssst 0.5tC15 ns status hold time (vs. astb - ) <41> t hsts 0.5tC20 ns dstb low-level width <42> t wdl (1+n)tC15 ns astb high-level width <43> t wsth tC20 ns wait setup time (vs. address) <44> t sawt1 n 3 1 1.5tC50 ns <45> t sawt2 (1.5+n)tC50 ns wait hold time (vs. address) <46> t hawt1 n 3 1 (0.5+n)t ns <47> t hawt2 (1.5+n)t ns wait setup time (vs. astb ) <48> t sstwt1 n 3 1 tC35 ns <49> t sstwt2 (1+n)tC35 ns wait hold time (vs. astb ) <50> t hstwt1 n 3 1ntns <51> t hstwt2 (1+n)t ns clkout - ? data output delay time <52> t dkod 32 ns dstb ? data output delay time <53> t ddod 20 ns data output hold time (vs. clkout - ) <54> t hkod 0ns data output setup time (vs. dstb - ) <55> t sodd (1+n)tC30 ns data output hold time (vs. dstb - ) <56> t hdod tC15 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted.
77 m pd703000, 703001 (6) write timing (2/2): 1 wait t1 t2 tw t3 <20> <29> <52> <22> <30> <31> <22> <38> <56> <23> <23> <43> <55> <35> <42> <24> <41> <40> <24> <27> <28> <27> <50> <49> <51> <28> <48> <44> <47> <46> <45> <54> clkout (output) a16-a23 (output) note ad0-ad15 (i/o) astb (output) dstb (output) st0, st1 (output) wait (input) a0-a15 (output) d0-d15 (output) note r/w (output), uben (output), lben (output) remark the dotted line indicates a high-impedance state. <53>
78 m pd703000, 703001 (7) bus hold timing (1/2) parameter symbol condition min. max. unit hldrq setup time (vs. clkout ) <57> t shqk 7ns hldrq hold time (vs. clkout ) <58> t hkhq 7ns clkout - ? hldak delay time <59> t dkha 32 ns hldrq high-level width <60> t whqh t+15 ns hldak low-level width <61> t whal tC15 ns clkout - ? bus float delay time <62> t dkf 32 ns hldak - ? bus output delay time <63> t dhac C5 ns hldrq ? hldak delay time <64> t dhqha1 (2n+7.5)t+40 ns hldrq - ? hldak - delay time <65> t dhqha2 0.5t 1.5t+40 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in a bus cycle. the sampling timing varies when programmable wait states are inserted.
79 m pd703000, 703001 (7) bus hold timing (2/2) th th th ti th clkout (output) hldak (output) dstb (output) st0, st1 (output) r/w (output) hldrq (input) astb (output) ad0-ad15 (i/o) d0-d15 (input or output) <58> <64> <65> <60> <57> <58> <57> <57> <59> <61> <59> <63> <62> a16-a23 (output) note note uben (output), lben (output) remark the dotted line indicates a high-impedance state.
80 m pd703000, 703001 (8) interrupt timing parameter symbol condition min. max. unit nmi high-level width <66> t wnih 500 ns nmi low-level width <67> t wnil 500 ns intpn high-level width <68> t with n=00, 01, 02, 03, 10, 11, 12, 13 3t+10 ns intpn low-level width <69> t witl n=00, 01, 02, 03, 10, 11, 12, 13 3t+10 ns remark t = t cyk nmi (input) <66> <67> intpn (input) <68> <69> remark n = 00, 01, 02, 03, 10, 11, 12, 13
81 m pd703000, 703001 (9) csi timing (a) master mode parameter symbol condition min. max. unit sck cycle <70> t cysk output 330 ns sck high-level width <71> t wskh output 0.5t cysk C40 ns sck low-level width <72> t wskl output 0.5t cysk C40 ns si setup time (vs. sck - ) <73> t ssisk 60 ns si hold time (vs. sck - ) <74> t hsksi 0ns so output delay time <75> t dskso 40 ns (vs. sck ) so output hold time <76> t hskso 0.5t cysk C15 ns (vs. sck - ) (b) slave mode parameter symbol condition min. max. unit sck cycle <70> t cysk input 330 ns sck high-level width <71> t wskh input 110 ns sck low-level width <72> t wskl input 110 ns si setup time (vs. sck - ) <73> t ssisk 20 ns si hold time (vs. sck - ) <74> t hsksi 20 ns so output delay time <75> t dskso 60 ns (vs. sck ) so output hold time <76> t hskso t wskh ns (vs. sck - ) sck (i/o) si (input) so (output) <70> <72> <71> <73> <74> <75> <76> input data output data remark the dotted line indicates a high-impedance state.
82 m pd703000, 703001 (10) rpu timing parameter symbol condition min. max. unit ti1 high-level width <77> t wtih 3t+10 ns ti1 low-level width <78> t wtil 3t+10 ns tclr1 high-level width <79> t wtch 3t+10 ns tclr1 low-level width <80> t wtcl 3t+10 ns remark t = t cyk ti1 (input) <77> <78> tclr1 (input) <79> <80>
83 m pd703000, 703001 13. characteristic curve (reference) i oh vs. (v dd ? oh ) (t a = 25 c, v dd = 5.0 v, v ss = 0 v) high-level output current i oh [ma] 3.0 2.0 1.0 0 supply voltage ?high-level output voltage v dd ? oh [v] 0 0.2 0.4 0.6 i ol vs. v ol (t a = 25 c, v dd = 5.0 v, v ss = 0 v) low-level output current i ol [ma] 6.0 4.0 2.0 0 low-level output voltage v ol [v] 0 0.2 0.4 0.6
84 m pd703000, 703001 14. package drawings 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 16.0?.2 0.630?.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009?.002 p100gc-50-7ea-2 k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125?.075 0.005?.003 r s 1.7 max. 55 55 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51
85 m pd703000, 703001 15. recommended soldering conditions solder this product under the following recommended conditions. for the details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and soldering conditions other than those recommended, consult nec. table 15-1. soldering conditions of surface mount type m pd703000gc-xx-xxx-7ea : 100-pin plastic qfp (fine pitch) (14 14 mm) m pd703001gc-xx-7ea : 100-pin plastic qfp (fine pitch) (14 14 mm) soldering method soldering condition symbol of recommended condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (210 c min.), number of times: 2 max., number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-107-2 number of times: 2 max., number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) C note the number of days during which the product can be stored at 25 c, 65% rh max. after the dry pack has been opened. caution do not use two or more soldering methods in combination (except partial heating).
86 m pd703000, 703001 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
87 m pd703000, 703001 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
88 m pd703000, 703001 related documents : m pd70p3000 data sheet u10988e v850 family instruction list u10229e v851 register list u10662j (japanese version) reference : considering electric characteristics - microcomputers iei-601 (japanese version) the related documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. the v850 family and v851 are trademarks of nec corporation. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed : m pd703001gc- -7ea the customer must judge the need for lincese : m pd703000gc- - -7ea no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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