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1996, 1997 preliminary data sheet mos integrated circuit m pd30101 v r 4101? 64-bit microprocessor document no. u11846ej2v0ds00 (2nd edition) date published august 1997 n printed in japan the information in this document is subject to change without notice. description the m pd30101 (v r 4101) is one of necs v r series risc (reduced instruction set computer) microprocessors and is a high-performance 64-bit microprocessor employing the mips risc architecture. the v r 4101 is ideal for applications in battery-driven, high-performance portable information systems. this microprocessor uses the high-performance, super power-saving v r 4100? as the cpu core, and has many peripheral circuits such as dma, serial interface, keyboard interface, irda interface, touch panel interface, and real-time clock. the functions of the v r 4101 are explained in detail in the following manual. be sure to refer to this manual when designing your system. ? vr4101 users manual (u12149e) features ? employs 64-bit mips architecture 5-stage pipeline conforms to mips-iii instruction set (floating-point instructions are supported through software emulation.) ? supports high-speed sum-of-products operation instructions ? power consumption as low as 250 mw typ. (at 33 mhz and 3.3 v) ? supports three types of power control modes ? external clock: 32 khz, internal operating frequency: 33 mhz ? clock generator and pll ( 1012) ? dram interface and rom interface (flash memory is also supported.) ? dma controller (5 channels) ? peripheral circuits ideal for portable systems lcd interface, keyboard interface, and touch panel interface ? irda controller ? supports subset of isa bus ? serial interface and debug serial interface ? supply voltage: 3.0 to 3.6 v ? package: 160-pin plastic lqfp applications ? battery-driven portable information systems ? embedded controllers, etc. ordering information part number package m pd30101gm-33-8ed 160-pin plastic lqfp (fine pitch) (24 24 mm) 1997 the mark shows major revised points.

m pd30101 2 pin configuration gnd data9 add9 data8 add8 data7 add7 data6 add6 data5 add5 data4 add4 data3 add3 v dd gnd v dd gnd data2 add2 data1 add1 data0 add0 ramwe lcas ucas mras3 v dd gnd mras2 mras1 mras0 memw memr iow ior shb v dd gnd rstout irq zws pcmclk romoe romcs3 romcs2 romcs1 romcs0 gnd gnd lcdrdy lcdwe/romwe lcdoe lcdcs gnd v dd clkx2 clkx1 gnd v dd gnd v dd gnd gndp v dd p rtcrst rstsw power audiout0 audiout1 mpower gnd battint battinh rxd dcd dsr v dd 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 v dd gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 gpio10 gpio11 gnd v dd poweron pencont0 pencont1 gnd v dd pencont2 pencont3 pencont4 adeoc penchgint adcs adin adclk adsout irdout gnd v dd irdin ddin ddout rts txd dtr cts gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dd add10 data10 add11 data11 add12 data12 gnd add13 data13 add14 data14 add15 data15 gnd v dd gnd v dd add16 add17 add18 add19 add20 kport0 kport1 kport2 kport3 kport4 kport5 kport6 kport7 kscan0/evud kscan1/evinc kscan2 kscan3 kscan4 kscan5 kscan6 kscan7 gnd
m pd30101 3 pin name adclk : a/d converter clock adcs : a/d converter chip select add (0:20) : address bus adeoc : a/d converter end of change adin : a/d converter data in adsout : a/d converter serial out audiout (0:1) : audio out battinh : battery inhibit battint : battery interrupt clkx1 : clock x1 clkx2 : clock x2 cts : clear to send data (0:15) : data bus dcd : data carrier detection ddin : debug serial data in ddout : debug serial data out dsr : data set ready dtr : data terminal ready evinc : electric volume input clock evud : electric volume up/down gnd : ground gndp : quiet gnd for pll gpio (0:11) : general purpose i/o ior : i/o read iow : i/o write irdin : irda data in irdout : irda data out irq : interrupt request kport (0:7) : key scan data in kscan (0:7) : key scan data out lcas : lower column address strobe lcdcs : lcd chip select lcdoe : lcd output enable lcdrdy : lcd ready lcdwe : lcd write enable memr : memory read memw : memory write mpower : main power on mras (0:3) : dram row address strobe pcmclk : pcm clock penchgint : pen change interrupt pencont (0:4) : touch panel control power : power on switch poweron : power on state ramwe : dram write enable romcs (0:3) : rom chip select romoe : rom output enable romwe : rom write enable rstout : pcm reset rstsw : reset switch rtcrst : real time clock reset rts : request to send rxd : receive data shb : system bus hi-byte enable txd : transmit data ucas : upper column address strobe v dd : power supply voltage v dd p : quiet v dd for pll zws : zero wait state
m pd30101 4 internal block diagram and example of connection of external blocks pcmcia controller lcd controller modem rom dram clock generator pll clock driver rtc dsu icu pmu dmaau dcu cmu giu aiu kiu piu siu debug siu irda bcu a/d conv. ir driver rs-232c driver v r 4101 v r 4100 cpu core a cpu core internal block diagram v r 4100 cpu core va bus id bus control (out) control (in) address/data (i/o) bus interface data cache instruction cache tlb cp0 cpu clock generator internal clock
m pd30101 5 table of contents 1. pin functions ................................................................................................................ ......... 8 1.1 pin functions ............................................................................................................... ...................... 8 1.2 pin status in specific status ............................................................................................... ............. 12 2. internal blocks .............................................................................................................. .... 14 2.1 v r 4100 cpu core .................................................................................................................. ............ 14 2.2 bcu (bus control unit) ...................................................................................................... ............... 14 2.3 rtc (real-time clock) ....................................................................................................... ................ 14 2.4 dsu (deadmans switch unit) ................................................................................................. ......... 14 2.5 icu (interrupt control unit) ................................................................................................ .............. 14 2.6 pmu (power management unit) ................................................................................................. ...... 15 2.7 dmaau (direct memory access address unit) ............................................................................. 15 2.8 dcu (direct memory access control unit) ..................................................................................... 15 2.9 cmu (clock mask unit) ....................................................................................................... .............. 15 2.10 giu (general purpose i/o unit) ............................................................................................. ........... 15 2.11 aiu (audio interface unit) ................................................................................................. ................ 15 2.12 kiu (keyboard interface unit) .............................................................................................. ............ 15 2.13 piu (touch panel interface unit) ........................................................................................... ........... 15 2.14 debugsiu (debug serial interface unit) ..................................................................................... ..... 15 2.15 siu (serial interface unit) ................................................................................................ ................. 15 3. internal architecture ..................................................................................................... 16 3.1 pipeline .................................................................................................................... ........................... 16 3.2 cpu registers ............................................................................................................... .................... 17 3.3 outline of instruction set .................................................................................................. ............... 18 3.4 system control coprocessor (cp0) ............................................................................................ .... 20 3.4.1 cp0 registers ............................................................................................................. ............. 20 3.5 data format and addressing .................................................................................................. ......... 22 3.6 virtual storage ............................................................................................................. ...................... 23 3.6.1 virtual address space ..................................................................................................... ......... 23 3.6.2 address translation ....................................................................................................... .......... 26 3.7 cache ....................................................................................................................... ........................... 28 3.8 exception processing ........................................................................................................ ............... 29 4. initialization interface .................................................................................................... 3 2 4.1 reset function .............................................................................................................. .................... 32 4.1.1 rtc reset ................................................................................................................. ............... 32 4.1.2 rstsw ..................................................................................................................... .............. 32 4.1.3 deadmans sw .............................................................................................................. ......... 32 4.1.4 software shutdown ......................................................................................................... ......... 32 4.1.5 haltimer shutdown ......................................................................................................... ....... 32 4.2 cpu core registers at reset ................................................................................................. .......... 33 4.3 poweron sequence ............................................................................................................ ............... 36 4.4 modes of v r 4101 ........................................................................................................................... .... 38
m pd30101 6 4.4.1 power mode ................................................................................................................ ............ 38 4.4.2 privilege mode ............................................................................................................ ............ 39 4.4.3 reverse endian ............................................................................................................ ........... 39 4.4.4 bootstrap exception vector (bev) .......................................................................................... .39 4.4.5 cache error check ......................................................................................................... .......... 39 4.4.6 inhibiting parity error ................................................................................................... ............ 39 4.4.7 enabling interrupts (ie) .................................................................................................. ......... 39 5. bcu (bus control unit) ...................................................................................................... 4 0 5.1 general ..................................................................................................................... .......................... 40 6. dmaau (dma address unit) ................................................................................................ 41 6.1 general ..................................................................................................................... .......................... 41 7. dcu (dma control unit) ..................................................................................................... 42 7.1 general ..................................................................................................................... .......................... 42 8. cmu (clock mask unit) ....................................................................................................... 4 3 8.1 general ..................................................................................................................... .......................... 43 8.2 configuration ............................................................................................................... ...................... 43 9. icu (interrupt control unit) .......................................................................................... 44 9.1 general ..................................................................................................................... .......................... 44 9.2 configuration ............................................................................................................... ...................... 45 10. pmu (power management unit) ....................................................................................... 46 10.1 general .................................................................................................................... ........................... 46 10.1.1 power mode ............................................................................................................... ............ 46 11. rtc (real-time clock unit) ............................................................................................... 48 11.1 general .................................................................................................................... ........................... 48 11.2 configuration .............................................................................................................. ....................... 49 12. dsu (deadmans sw unit) ..................................................................................................... ... 50 12.1 general .................................................................................................................... ........................... 50 13. giu (general-purpose i/o unit) ....................................................................................... 51 13.1 general .................................................................................................................... ........................... 51 14. piu (touch panel interface unit) .................................................................................. 52 14.1 general .................................................................................................................... ........................... 52 14.2 example of external circuit configuration .................................................................................. ... 52 15. siu (serial interface unit) ............................................................................................... 53 15.1 general .................................................................................................................... ........................... 53 15.2 configuration .............................................................................................................. ....................... 53
m pd30101 7 16. aiu (audio interface unit) ................................................................................................ 54 16.1 general .................................................................................................................... ........................... 54 16.2 configuration .............................................................................................................. ....................... 55 17. kiu (keyboard interface unit) ....................................................................................... 56 17.1 general .................................................................................................................... ........................... 56 17.2 configuration .............................................................................................................. ....................... 57 18. debugsiu (debug serial interface unit) ...................................................................... 58 18.1 general .................................................................................................................... ........................... 58 19. instruction set ............................................................................................................. ....... 59 19.1 instruction formats ........................................................................................................ ................... 59 19.2 cpu instruction set list ................................................................................................... ................ 59 19.3 instruction execution time ................................................................................................. ............. 64 20. electrical specifications ............................................................................................... 65 21. package drawing ............................................................................................................. ... 92 22. recommended soldering conditions .......................................................................... 93
m pd30101 8 1. pin functions 1.1 pin functions (1) system bus interface signals signal name i/o functional description add (0:20) output 21-bit address bus. used to specify addresses of dram, rom, lcd, or pcmcia. data (0:15) i/o 16-bit data bus. used to transfer data from v r 4101 to dram, rom, lcd, or pcmcia, and vice versa. lcdcs output lcd chip select signal. asserted active when v r 4101 accesses lcd via add bus and data bus. lcdoe output lcd output enable signal. asserted active when v r 4101 reads data from lcd. lcdwe/romwe output multiplexed signal of lcd write enable signal and flash memory write enable signal. this signal functions as lcd write enable signal when lcdcs pin is active, and is asserted active when v r 4101 writes data to lcd. when lcdcs pin is inactive, this signal functions as rom write enable signal, and is asserted active when v r 4101 writes data to flash memory. lcdrdy input lcd ready signal. assert this signal active when lcd or pcmcia controller is ready for access by v r 4101. romcs (0:3) output rom chip select signals. used to select rom to be accessed from up to four roms connected to v r 4101. romoe output rom output enable signal. asserted active when v r 4101 reads data from rom. mras (0:3) output ras signals of dram. asserted active when valid row address of ram to be accessed is output onto add bus. up to four rams can be connected to v r 4101. ucas output cas signal of dram. asserted active when valid column address is output onto add bus when high-order byte of dram is accessed. lcas output cas signal of dram. asserted active when valid column address is output onto add bus when low-order byte of dram is accessed. ramwe output dram write enable signal. asserted active when v r 4101 writes data to dram. pcmclk output pcmcia card clock. outputs 8-mhz clock to be supplied to pcmcia controller. shb output pcmcia bus high byte enable signal. asserted active if high-order byte of data bus is valid when pcmcia is accessed. ior output pcmcia card i/o read signal. asserted active when v r 4101 reads data from i/o port of pcmcia. iow output pcmcia card i/o write signal. asserted active when v r 4101 writes data to i/o of pcmcia. memr output pcmcia card memory read signal. asserted active when v r 4101 reads data from memory of pcmcia. memw output pcmcia card memory write signal. asserted active when v r 4101 writes data to memory of pcmcia. zws input pcmcia zero wait state signal. assert this signal active when pcmcia controller is ready for access by v r 4101. irq input pcmcia card interrupt request signal. pcmcia controller asserts this pin active to inform v r 4101 of interrupt. rstout output pcmcia card reset signal. asserted active when v r 4101 resets pcmcia controller.
m pd30101 9 (2) clock interface signals signal name i/o functional description clkx1 input 32-khz clock input pin. connect one end of 32-khz crystal resonator to this pin. clkx2 input 32-khz clock input pin. connect one end of 32-khz crystal resonator to this pin. (3) battery monitor interface signals signal name i/o functional description battinh input interrupt signal indicating battery voltage level on power application. external circuit checks battery voltage on power application and, if it judges that battery voltage is sufficient for operation, asserts this pin active. battint input interrupt signal indicating battery voltage level during normal operation. external circuit checks battery voltage and, if it judges that battery voltage is not sufficient for operation, asserts this pin active. (4) initialization interface signals signal name i/o functional description mpower output signal to turn on main power. v r 4101 turns on power supply to external dc/dc converter by asserting this pin active. poweron output signal indicating that v r 4101 is to start from hibernate mode. it is asserted active when start cause is detected, and deasserted inactive after battery check has been completed. power input signal indicating that power-on switch has been pressed. when power-on switch has been pressed, external circuit asserts this pin active. rstsw input signal indicating that reset switch has been pressed. when reset switch has been pressed, external circuit asserts this pin active. rtcrst input signal resetting rtc. when power is supplied to system for first time, external circuit asserts this pin active for 230 ms. (5) rs-232c interface signals signal name i/o functional description rxd input receive data signal. used to transfer serial data from rs-232c driver/receiver to v r 4101. txd output transmit data signal. used to transfer serial data from v r 4101 to rs-232c driver/ receiver. rts output transmit request signal. v r 4101 asserts this signal active when it wishes to transmit serial data. cts input transmit enable signal. assert this signal active when rs-232c driver/receiver is ready to receive serial data. dcd input carrier detection signal. assert this signal active while valid serial data is being received. if this signal is asserted active in hibernate mode and in shutdown state, fullspeed mode can be restored. dtr output terminal equipment ready signal. v r 4101 asserts this signal active when it is ready to transmit/receive serial data. dsr input data set ready signal. assert this signal active when rs-232c driver/receiver and v r 4101 are ready to transmit/receive serial data.
m pd30101 10 (6) irda interface signals signal name i/o functional description irdin input irda serial data input signal. used to transfer serial data from v r 4101 to irda controller. irdout output irda serial data output signal. used to transfer serial data from irda controller to v r 4101. (7) debug serial interface signals signal name i/o functional description ddin input debug serial data input signal. used to transfer serial data from v r 4101 to external debug serial controller. ddout output debug serial data output signal. used to transfer serial data from external debug serial controller to v r 4101. (8) keyboard interface signals signal name i/o functional description kport (0:7) input keyboard scan data input signals. used to scan input from keyboard. kscan (2:7) output keyboard scan data output signals. assert scan line active when input from keyboard is scanned. kscan1/evinc output multiplexed signal of keyboard scan data output signal and electronic volume control clock signal. if evinc pin is enabled to output by evvolreg register, this signal functions as clock output pin to electronic volume controller. kscan0/evud output multiplexed signal of keyboard scan data output signal and electronic volume up/down signal. when evud pin is enabled to output by evvolreg register, this signal functions as volume up/down pin for electronic volume controller. (9) audio interface signals signal name i/o functional description audiout (0, 1) output audio output signals. output audio signals when wave file is reproduced. (10) touch panel interface signals signal name i/o functional description adcs output a/d converter chip select signal. this signal is asserted active when data is transferred or received to or from a/d converter. adclk output clock output signal to supply clock to a/d converter. adin input input pin to receive output data from a/d converter. adsout output a/d converter serial data output signal. used to output serial data to set a/d converter. adeoc input a/d converter data conversion end signal. assert this signal active when a/d conversion by a/d conversion has been completed. pencont (0:4) output touch panel control signals. output signals controlling voltage applied to touch panel. penchgint input touch panel interrupt. external circuit asserts this pin active when touch panel is pressed.
m pd30101 11 (11) general-purpose i/o signals signal name i/o functional description gpio (0:11) i/o general-purpose i/o pins. however, fix function of gpio9 to battery lid lock detection signal (battlock). (12) other signals signal name i/o functional description v dd positive power supply pin v dd p power supply for internal pll gnd ground pin gndp ground for internal pll
m pd30101 12 1.2 pin status in specific status (1/2) at reset by deadmans in hibernate mode or pin name at reset by rtcrst sw or rstsw in suspend mode on shutdown by haltimer add (0:20) 0 0 data (0:15) 0 0 lcdcs hi-z 1 1 hi-z lcdoe hi-z 1 1 hi-z lcdwe/romwe hi-z 1 1 hi-z lcdrdy hi-z hi-z hi-z hi-z romcs (0:3) hi-z 1 1 hi-z romoe hi-z 1 1 hi-z mras (0:3) 1 hi-z 0 0 ucas 1 hi-z 0 0 lcas 1 hi-z 0 0 ramwe 1111 pcmclk 0 0 shb 0 0 ior hi-z 1 1 hi-z iow hi-z 1 1 hi-z memr hi-z 1 1 hi-z memw hi-z 1 1 hi-z zws hi-z hi-z hi-z hi-z irq hi-z hi-z hi-z hi-z rstout hi-z 0 note hi-z clkx1 hi-z hi-z hi-z hi-z clkx2 hi-z hi-z hi-z hi-z battinh hi-z hi-z hi-z hi-z battint hi-z hi-z hi-z hi-z mpower 0110 poweron 0000 power hi-z hi-z hi-z hi-z rstsw hi-z hi-z hi-z hi-z rtcrst hi-z hi-z hi-z hi-z rxd hi-z hi-z hi-z hi-z txd 1 1 note 1 rts 1 1 note 1 cts hi-z hi-z hi-z hi-z dcd hi-z hi-z hi-z hi-z dtr 1 1 note 1 note the status in the fullspeed mode immediately before is retained. remark 0: low-level output, 1: high-level output, hi-z: high impedance, : undefined
m pd30101 13 (2/2) at reset by deadmans in hibernate mode or pin name at reset by rtcrst sw or rstsw in suspend mode on shutdown by haltimer dsr hi-z hi-z hi-z hi-z irdin hi-z hi-z hi-z hi-z irdout hi-z hi-z note hi-z ddin hi-z hi-z hi-z hi-z ddout 1 1 note 1 kport (0:7) hi-z hi-z hi-z hi-z kscan (2:7) hi-z hi-z note hi-z kscan1/evinc hi-z hi-z note hi-z kscan0/evud hi-z hi-z note hi-z audiout (0:1) 0000 adcs hi-z hi-z note hi-z adclk 0 0 note 0 adin hi-z hi-z hi-z hi-z adsout 0 0 note 0 adeoc hi-z hi-z hi-z hi-z pencont (0:4) hi-z hi-z note hi-z penchgint hi-z hi-z hi-z hi-z gpio (0:11) hi-z hi-z note hi-z note the status in the fullspeed mode immediately before is retained. remark 0: low-level output, 1: high-level output, hi-z: high impedance
m pd30101 14 2. internal blocks 2.1 v r 4100 cpu core (1) cpu the cpu processes integer instructions and consists of 64-bit register files, a 64-bit integer data bus, and a sum-of-products operation unit. (2) coprocessor 0 (cp0) the cp0 has a memory management unit (mmu) and an exception processing function. the mmu translates addresses and checks whether an access is made between different types (user, supervisor, or kernel) of memory segments. virtual addresses are translated to physical addresses by tlb (high-speed translation lookaside buffer). (3) instruction cache the instruction cache is of direct mapping, virtual index, and physical tag type. (4) data cache the data cache is of direct mapping, virtual index, physical tag, and write back type. (5) cpu bus interface the cpu bus interface controls data transfer between the v r 4100 cpu core and bcu, one of the peripheral units. as the bus interface for the v r 4100 cpu core, two 32-bit address/data multiplexed buses each for input and output, clock signals, and interrupt control signals are used. (6) clock generator a 32.768-khz crystal oscillator is oscillated by an internal oscillation circuit and multiplied by 1012 by pll (phase-locked loop) to generate a pipeline clock (pclock). the system interface clock (sclock) is generated from pclock. 2.2 bcu (bus control unit) the bcu internally transfers data with the v r 4100 cpu core via sysad bus. it also controls the lcd controller, dram, rom (flash memory or mask rom), and pcmcia controller connected to the system bus, and transfers data with the above devices via add and data buses. 2.3 rtc (real-time clock) the rtc has a precise counter that operates with a 32.768-khz clock supplied from the clock generator. it also has several counters and compare registers for various interrupts. 2.4 dsu (deadmans switch unit) the dsu is used to check whether the processor is operating normally. if the software does not clear the register of this unit at specific intervals, the system is shut down. 2.5 icu (interrupt control unit) the icu controls interrupt requests generated from the external and internal sources of the v r 4101, and reports an interrupt request, if any, to the v r 4100 cpu core.
m pd30101 15 2.6 pmu (power management unit) the pmu outputs signals necessary for controlling the power of the entire system, including the v r 4101. it also controls the pll of the v r 4100 cpu core and the internal clocks (pclock, tclock, and masterout) in the power-saving mode. 2.7 dmaau (direct memory access address unit) the dmaau controls five types of dma transfer addresses. 2.8 dcu (direct memory access control unit) the dcu controls arbitration of five types of dma transfers. 2.9 cmu (clock mask unit) the cmu controls supply of the clock (tclock or masterout) from the v r 4100 cpu core to the internal peripheral units. 2.10 giu (general purpose i/o unit) the giu controls 12 gpio pins and the dcd pin. note, however, that of the 12 gpio pins, one is reserved for a specific application at present. 2.11 aiu (audio interface unit) the aiu can be used to generate any frequency by using pwm and outputs audio signals to external devices. it also supplies a buzzer sound. 2.12 kiu (keyboard interface unit) the kiu has eight scan lines and eight detection lines to detect input of 64 keys. it can also detect roll over of 2 or 3 keys. 2.13 piu (touch panel interface unit) the piu controls detection of touching on a touch panel. the v r 4101 supports two types of a/d converter interfaces: tlc2543c and tlv1543c. 2.14 debugsiu (debug serial interface unit) the debugsiu is a serial interface for debugging and supports a transfer rate of up to 115 kbps. 2.15 siu (serial interface unit) the siu is a serial interface conforming to the rs-232c standards, and supports a transfer rate of up to 115 kbps. in addition, a irda serial interface that supports a transfer rate of 115 kbps is also included, though this irda serial interface is exclusively used with the rs-232c interface.
m pd30101 16 3. internal architecture 3.1 pipeline each instruction is executed in the following five steps: (1) if instruction fetch (2) rf register fetch (3) ex execution (4) dc data cache fetch (5) wb write back the v r 4101 has a five-stage pipeline. it takes five clocks to execute each instruction, but instructions can be executed in parallel. the pipeline clock, pclock, operates at a frequency of 33 mhz. the following figure outlines the pipeline. figure 3-1. pipeline of v r 4101 (5-stage) pclock if rf ex dc wb if rf ex dc wb if rf ex dc wb if rf ex dc wb if rf ex dc wb current cpu c y cle
m pd30101 17 3.2 cpu registers figure 3-2 shows the cpu registers of the v r 4101. the bit width of these registers is determined by the operation mode of the processor (32 bits in 32-bit mode or 64 bits in 64-bit mode). of the 32 general-purpose registers, the following two have a special meaning. ? register r0 : the contents of this register are always 0. to discard the result of an operation, describe this register as the target of an instruction. when value 0 is necessary, this register can be used as a source register. ? register r31 : this is a link register for the jal and jalr instructions. therefore, do not use this register with any other instructions. the two multiplication/division registers (hi and lo) store the result of multiplication or sum-of-products operation, or quotient (lo) and remainder (hi) resulting from division. because the v r 4101 does not support floating-point instructions, it is not provided with the 32 floating-point general- purpose registers (fgr) found in the v r 4200? and v r 4400?. remark the load link bit (ll bit) used with synchronization instructions (ll and sc) for multi-processor system supported by the v r 4200 and v r 4400 is not provided in the v r 4101 (refer to 3.3 (2) deletion of multi- processor instructions ). figure 3-2. cpu registers 63 0 63 0 r2 hi r1 r29 r30 r31 (link address) lo pc 63 0 63 0 program counter multiplication/division registers r0 = 0 general-purpose registers the v r 4101 does not have a program status word (psw). the function of psw is substituted by the status registers and cause registers incorporated to the system control coprocessor (cp0).
m pd30101 18 3.3 outline of instruction set basically, the instruction set of the v r 4101 conforms to the mips-i, -ii, and -iii instruction sets. however, it is different from those of the other processors in the v r series in the following four points. the difference between the v r 4100 and v r 4101 is that the v r 4101 can manage operations including the peripheral functions by using power mode instructions (refer to (4) ). (1) deletion of floating-point (fpu) instructions because the v r 4101 does not have a floating-point unit, it does not support fpu instructions. if an fpu instruction is encountered, therefore, a reserved instruction exception occurs. if it is necessary to use an fpu instruction, emulate the instruction in software in an exception handler. (2) deletion of multi-processor instructions the v r 4101 does not support a multiple processor operating environment. if a synchronization support instruction (ll or sc instruction) defined by mips-ii and -iii isa is encountered, a reserved instruction exception occurs. in addition, the load link bit (ll bit) is also unavailable. the v r 4101 executes all load/store instructions in the programmed sequence. therefore, the sync instruction is treated as a nop instruction. (3) addition of sum-of-products instructions the v r 4101 has a dedicated sum-of-products operation core in the cpu and additional integer sum-of- products operation instructions, in order to execute sum-of-products operation at high speeds. note that these instructions are not correctly executed with any other processors in the v r series. the operations by the sum-of-products instructions are as follows: (a) madd16 (multiply and add 16-bit integer) this instruction multiplies the contents of general-purpose register rs by the contents of general-purpose register rt. both the operands are treated as signed 16-bit integers. bits 62 through 15 of both the operands must be sign-extended. the result of the multiplication is added to a 64-bit value combining special registers hi and lo. the low-order word (64 bits) of the result is loaded to special register lo, and the high-order word is loaded to hi. an integer overflow exception does not occur. figure 3-3 outline the operation of the madd16 instruction. figure 3-3. operation of madd16 instruction rs rt 31 15 general-purpose re g ister file mul add hi lo 63 31 high-order low-order
m pd30101 19 (b) dmadd16 (doubleword multiply and add 16-bit register) this instruction multiplies the contents of general-purpose register rs by the contents of general-purpose register rt. both the operands are treated as signed 16-bit integers. bits 62 through 15 of both the operands must be sign-extended. the result of the multiplication is added to the value of special register lo. the result of the addition is treated as a signed integer. the 64-bit result is loaded to special register lo. an integer overflow exception does not occur. this operation is defined in the 64-bit mode and 32-bit kernel mode. if this instruction is encountered in the 32-bit user/supervisor mode, a reserved instruction exception occurs. (4) addition of power mode instructions the v r 4101 supports three power modes to lower the power consumption, and therefore, has dedicated instructions that set these modes. note that the power mode instructions are not correctly executed by any other processors in the v r series. the operations of the power mode instructions are as follows: (a) standby this instruction places the processor in the standby mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus has entered the idle status, the internal clock is fixed to the high level, and the pipeline operation is stopped. in the standby mode, the pll, clocks related to timers/interrupts, and interface clocks to the peripheral function blocks (tclock and masterout) operate normally. when the processor is in the standby mode it is returned to the fullspeed mode by any interrupt including an internally generated timer interrupt. (b) suspend this instruction places the processor in the suspend mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus has entered the idle status, the internal clock and tclock are fixed to the high level, and the pipeline operation and interfacing to the peripheral function blocks are stopped. in the suspend mode, the pll, clocks related to timers/interrupts, and masterout operate normally. the processor remains in the suspend mode until it accepts an interrupt. when the processor accepts an interrupt, it returns to the fullspeed mode. (c) hibernate this instruction places the processor in the hibernate mode from the fullspeed mode. when instruction execution has proceeded to the wb stage, and the sysad bus has entered the idle status, all the clocks are fixed to the high level, and the pipeline operation is stopped. the processor remains in the hibernate mode until either the power pin is asserted active or the wakeup timer interrupt occurs. the processor returns to the fullspeed mode when the power pin is asserted active, when the wakeup timer interrupt occurs, or when the dcd pin is asserted active.
m pd30101 20 3.4 system control coprocessor (cp0) cp0 supports memory management, address translation, exception processing, and privilege operations. cp0 has the registers shown in table 3-1, and a 32-entry tlb. the basic configuration of the cp0 registers of the v r 4101 is the same as that of the v r 4200 and v r 4400. however, because the number of entries of tlb, page size, cache size, physical address space, and system interface differ between the v r 4101 and v r 4200/v r 4400, the bit configuration and setting differ. for details, refer to v r 4101 users manual . 3.4.1 cp0 registers all the cp0 registers that can be used with the v r 4101 are listed below. writing to or reading from an unused register (rfu) is undefined. in the 32-bit mode, the high-order 32 bits of 64-bit registers are masked. figure 3-4. cp0 registers and tlb entry lo0 2* entry hi 10* entry lo1 3* index 0* random 1* page mask 5* wired 6* prid 15* config 16* tag hi 29* tag lo 28* lladdr 17* tlb 31 00 127/255 (?afe?entry) context 4* badvaddr 8* count 9* compare 11* cause 13* status 12* epc 14* watch lo 18* x context 20* parity error 26* watch hi 19* cache error 27* error epc 30* registers used for memory management system registers used for exception processing remark * indicates a register number.
m pd30101 21 table 3-1. cp0 registers no. register description 0 index programmable pointer to tlb array 1 random dummy random pointer to tlb array (read-only) 2 entry lo0 latter half of tlb entry for even-number vpn 3 entry lo1 latter half of tlb entry for odd-number vpn 4 context pointer to virtual pte table of kernel in 32-bit mode 5 page mask specifies page size 6 wired number of wired tlb entries 7 rfu (reserved for future use) 8 badvaddr indicates virtual address at which error occurs last 9 count timer count 10 entry hi first half of tlb entry (including asid) 11 compare timer compare value 12 status sets operation status 13 cause indicates cause of last exception 14 epc exception program counter 15 prld processor revision id 16 config sets memory system mode 17 lladdr rfu 18 watch lo low-order bits of memory reference trap address 19 watch hi high-order bits of memory reference trap address 20 x context pointer to virtual pte table of kernel in 64-bit mode 21-25 rfu 26 parity error parity bit of cache 27 cache error error and status register of cache 28 tag lo cache tag register, low 29 tag hi cache tag register, high (reserved register) 30 error epc error exception program counter 31 rfu
m pd30101 22 3.5 data format and addressing the v r 4101 uses the following four data formats: ? double word (64 bits) ? word (32 bits) ? half word (16 bits) ? byte (8 bits) the byte ordering is set by the be bit of the config register. with the current v r 4101, set little endian. figure 3-5. byte address in word: little endian 31 24 23 16 15 0 high-order address low-order address 15 14 13 12 11 10 9 8 7654 3210 word address 12 8 4 0 8 7 remarks 1. the least significant byte is the lowest address. 2. a word is addressed by the address of the least significant byte.
m pd30101 23 figure 3-6. byte address in double word: little endian high-order address low-order address double word address 16 8 0 63 32 31 0 word half word byte 23 22 15 7 14 6 21 13 5 20 12 4 19 11 3 18 10 2 17 9 1 16 8 0 16 15 8 7 remarks 1. the least significant byte is the lowest address. 2. a word is addressed by the address of the least significant byte. 3.6 virtual storage the v r 4101 has a virtual storage management mechanism using tlb. virtual addresses are used for address management by software or address calculation of the pipeline. to access memories for program fetch and data access, and internal i/o and external i/o, physical addresses translated by tlb are used. note that part of the virtual address space is not translated by tlb, but is translated to physical addresses by merely changing specific addresses. if only this part of the address space is used, the v r 4101 can be treated in the same manner as a cpu that operates with physical addresses. 3.6.1 virtual address space the v r 4101 has two operation modes, 32-bit mode and 64-bit mode, and three types of operating modes: user mode, supervisor mode, and kernel mode. the virtual address space in each mode is shown below.
m pd30101 24 figure 3-7. user mode address space 32 bits note address error 2g bytes w/tlb mapping useg 64 bits address error 1t bytes w/tlb mapping xuseg f ff f f f f f f f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x ff f f f f f f 0 x 80 0 0 0 0 0 0 0 x 7f f f f f f f 0 x 00 0 0 0 0 0 0 0 x note in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4101 users manual . figure 3-8. supervisor mode address space 64 bits address error 0.5g bytes w/tlb mapping address error 1t bytes w/tlb mapping address error 1t bytes w/tlb mapping xsseg csseg xsuseg 32 bits note address error address error 2g bytes w/tlb mapping sseg suseg 0.5g bytes w/tlb mapping f ff f f f f f f f f f f f f f 0 x ff f f f f f f 0 x f ff f f 0 0 0 e f f f f f f f 0 x e0 0 0 0 0 0 0 0 x f ff f f f f f d f f f f f f f 0 x df f f f f f f 0 x 0 f0 0 0 0 0 0 c f f f f f f f 0 x c0 0 0 0 0 0 0 0 x f ff f f f f f b f f f f f f f 0 x bf f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 4f f f f f f f f f 0 0 0 0 0 0 x 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 80 0 0 0 0 0 0 0 x f 3f f f f f f f f f f f f f f 0 x 7f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 00 0 0 0 0 0 0 0 x note in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4101 users manual .
m pd30101 25 figure 3-9. kernel mode address space 64 bits 0.5g bytes w/tlb mapping 0.5g bytes w/tlb mapping 0.5g bytes w/o tlb mapping uncacheable 0.5g bytes w/o tlb mapping cacheable note 2 address error w/tlb mapping address error 1t bytes w/tlb mapping address error 1t bytes w/tlb mapping ckseg3 cksseg ckseg1 ckseg0 xkseg xkuseg xksseg 32 bits note 1 0.5g bytes w/tlb mapping 0.5g bytes w/o tlb mapping cacheable note 2 2g bytes w/tlb mapping kseg3 ksseg kuseg 0.5g bytes w/tlb mapping kseg1 kseg0 0.5g bytes w/o tlb mapping uncacheable no tlb mapping (for details, refer to figure 3-10. ) xkphys f ff f f f f f f f f f f f f f 0 x ff f f f f f f 0 x 0 f0 0 0 0 0 0 f f f f f f f f 0 x f ff f f f f f d f f f f f f f 0 x 0 f0 0 0 0 0 0 c f f f f f f f 0 x f0 0 0 0 0 0 0 0 x f ff f f f f f b f f f f f f f 0 x df f f f f f f 0 x 0 f0 0 0 0 0 0 a f f f f f f f 0 x f ff f f f f f 9 f f f f f f f 0 x 0 f0 0 0 0 0 0 8 f f f f f f f 0 x c0 0 0 0 0 0 0 0 x f ff f f f f f 7 f f f f f f f 0 x bf f f f f f f 0 x 0 c0 0 0 0 0 0 8 f f 0 0 0 0 0 0 x f cf f f f f f 7 f f 0 0 0 0 0 0 x 0 c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x a0 0 0 0 0 0 0 0 x f bf f f f f f f f f f f f f f 0 x 9f f f f f f f 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 7f f f f f f f f f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x 80 0 0 0 0 0 0 0 x f 4f f f f f f f f f 0 0 0 0 0 0 x 7f f f f f f f 0 x 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 3f f f f f f f f f f f f f f 0 x 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 x f 0f f f f f f f f f 0 0 0 0 0 0 x 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 00 0 0 0 0 0 0 0 x notes 1. in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. for details, refer to v r 4101 users manual . 2. whether this area is used as a cache area is specified by the k0 field of the config register.
m pd30101 26 figure 3-10. details of xkphys area address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error address error address error 4g bytes w/o tlb mapping uncacheable address error 4g bytes w/o tlb mapping uncacheable address error 4g bytes w/o tlb mapping uncacheable f bf f f f f f f f f f f f f f 0 x 0 b0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f bf f f f f f f 0 0 0 0 0 0 8 0 x 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f bf f f f f f f f f f f f f 7 0 x 0 b0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f bf f f f f f f 0 0 0 0 0 0 0 0 x 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f af f f f f f f f f f f f f f 0 x 0 a0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f af f f f f f f 0 0 0 0 0 0 8 0 x 0 a0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f af f f f f f f f f f f f f 7 0 x 0 a0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f af f f f f f f 0 0 0 0 0 0 0 0 x 0 a0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 9f f f f f f f f f f f f f f 0 x 0 90 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f 9f f f f f f f 0 0 0 0 0 0 8 0 x 0 90 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f 9f f f f f f f f f f f f f 7 0 x 0 90 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f 9f f f f f f f 0 0 0 0 0 0 0 0 x 0 90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x f 8f f f f f f f f f f f f f f 0 x 0 80 0 0 0 0 0 0 1 0 0 0 0 0 8 0 x f 8f f f f f f f 0 0 0 0 0 0 8 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 8 0 x f 8f f f f f f f f f f f f f 7 0 x 0 80 0 0 0 0 0 0 1 0 0 0 0 0 0 0 x f 8f f f f f f f 0 0 0 0 0 0 0 0 x 0 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 4g bytes w/o tlb mapping cacheable 4g bytes w/o tlb mapping cacheable 3.6.2 address translation virtual addresses are translated into physical addresses by the internal tlb (translation lookaside buffer) in page units. the tlb has a full-associative configuration and has 64 entries at the virtual address side and 32 entries at the physical address side. the page size is variable from 1k to 256k byte. if a tlb entry is not found, a tlb non-coincidence exception occurs in the 32-bit mode, and an xtlb non-coincidence exception occurs in the 64-bit mode. change the contents of the tlb in software. the following figure outlines address translation.
m pd30101 27 figure 3-11. outline of address translation y+8 y+1 y x+1 x 0 x? 31 0 asid vpn offset virtual address <1> <2> <3> selector <4> 31 x x? 0 tlb x = 10, 12, 14, 16, 18 y = 31 (in 32-bit mode) 63 (in 64-bit mode) physical address <1> a virtual address page number (vpn) is compared with vpn in tlb. <2> if the two vpns coincide, a page frame number (pfn) indicating the high-order bits of a physical address is output to the selector. <3> if the low-order 1 bit of vpn is 0, an even page is selected; if it is 1, an odd page is selected. the selected page is output to the high-order bits of the physical address. <4> the offset is output to the low-order bits of the physical address without going through tlb. the tlb entry is read or written by loading/storing among the tlb entry indicated by the index register and random register, entry hi, entry lo1, entry lo0, and page mask registers. how the tlb is manipulated is illustrated below. figure 3-12. outline of tlb manipulation entry lo0 register page mask register entry lo1 register entry hi register index register random register
m pd30101 28 3.7 cache (1) instruction cache the instruction cache has the following features: ? internal cache memory ? capacity: 2k bytes ? direct mapping mode ? virtual index address ? physical tag check ? 4-word (16-byte) cache line figure 3-13. format of instruction cache 127 155 154 132 131 0 0 122 p ptag data 128 v 153 128 127 datap 4 1 ptag : physical tag (bits 31-10 of physical address) v : valid bit data : cache data p : even parity for physical tag and v bit datap : even parity for data (1-bit parity per 4-byte data) (2) data cache the data cache has the following features: ? internal cache memory ? capacity: 1k bytes ? write back ? direct mapping mode ? virtual index address ? physical tag check ? 4-word (16-byte) cache line
m pd30101 29 figure 3-14. format of data cache 128 127 144 143 165 169 168 167 166 63 0 1 1 1 1 22 16 128 ptag datap data 0 w w p v w : even parity for write back bit w : write back bit p : even parity for physical tag and v bit v : valid bit ptag : physical tag (bits 31-10 of physical address) datap : even parity for data (1-bit parity per 1-byte data) data : cache data 3.8 exception processing the v r 4101 enters the kernel mode in which interrupts are disabled when an exception occurs, and executes an exception handler from a fixed exception vector address. to restore from the exception, the program counter, operating mode, and interrupt enable information must be restored to the original status. save this information when the interrupt occurs. when an interrupt occurs, the epc register holds the address of the instruction that has caused the exception, or the address of the instruction immediately before if the exception has occurred in the branch delay slot. this means that the epc register stores the address from which execution is to be started after the exception has been processed. at reset and on occurrence of nmi, the epc register holds a restart address.
m pd30101 30 table 3-2. types of exceptions exception symbol description cold reset this exception occurs if the coldreset (internal) and reset (internal) signals are simultaneously asserted active (for details, refer to figures 4-1 through 4-5 ). as a result, the instruction execution is stopped, and the handler on the reset vector is executed. the internal status, except some bits of the status registers, is undefined. soft reset this exception occurs if the reset (internal) signal is asserted active. as a result, the instruction execution is stopped, and the handler on the reset vector is executed. the internal status before soft reset is retained. however, the current v r 4101 does not support soft reset. nimi this exception occurs if the nmi (internal) signal is asserted active. tlb non-coincidence tlbl/tlbs this exception occurs if there is no tlb entry that coincides with an address to be referenced in the 32-bit mode. extended addressing tlbl/tlbs this exception occurs if there is no tlb entry that coincides with an address tlb non-coincidence to be referenced in the 64-bit mode. tlb invalid tlbl/tlbs this exception occurs if the tlb entry that coincides with the virtual address to be referenced is invalid (v bit = 0). tlb modify mod this exception occurs if the tlb entry that coincides with the virtual address to be referenced is valid but is disabled from being written (d bit = 0) when the store instruction is executed. bus error ibe/dbe this exception occurs when the external agent indicates an error of data on the syscmd bus by using an external interrupt to the bus interface (bus time-out, bus parity error, or invalid physical memory address or access type). address error adel/ades this exception occurs if an attempt is made to execute the lh, sh/lw/sw, ld, or sd instruction to the half word/word/double word not located at the half word/ word/double word boundary, or if an attempt is made to reference the virtual address that cannot be accessed. integer overflow ov this exception occurs if a 2s complement overflow occurs as a result of addition or subtraction. trap tr this exception occurs if the condition is true as a result of executing the trap instruction. system call sys this exception occurs if the syscall instruction is executed. breakpoint bp this exception occurs if the break instruction is executed. reserved instruction ri this exception occurs if an instruction with an undefined op code (bits 31-26) or special instruction with an undefined op code (bits 5-0) is executed. coprocessor non-usable cpu this exception occurs if the coprocessor instruction is executed when the corresponding coprocessor enable bit is not set. interrupt int this exception occurs if one of the eight interrupt sources becomes active. cache error this exception occurs if a parity error is detected in the internal cache or system interface. watch watch this exception occurs if an attempt is made to reference a physical address set by the watch lo/hi register with the load/store instruction.
m pd30101 31 the exception vectors and their offset values in the 64-bit and 32-bit modes are shown below. table 3-3. base address of exception vector in 64-bit mode (virtual address) vector base address vector offset cold reset, soft reset, nmi 0xffff ffff bfc0 0000 0x0000 (bev bit is automatically set to 1.) cache error 0xffff ffff a000 0000 (bev = 0) 0x0100 0xffff ffff bfc0 0200 (bev = 1) tlb non-coincidence, exl =0 0xffff ffff 8000 0000 (bev = 0) 0x0000 xtlb non-coincidence, exl = 0 0xffff ffff bfc0 0200 (bev = 1) 0x0080 others 0x0180 table 3-4. base address of exception vector in 32-bit mode (virtual address) vector base address vector offset cold reset, soft reset, nmi 0xbfc0 0000 0x0000 (bev bit is automatically set to 1.) cache error 0xa000 0000 (bev = 0) 0x0100 0xbfc0 0200 (bev = 1) tlb non-coincidence, exl =0 0x8000 0000 (bev = 0) 0x0000 xtlb non-coincidence, exl = 0 0xbfc0 0200 (bev = 1) 0x0080 others 0x0180
m pd30101 32 4. initialization interface this section explains the initialization interface and processor mode. also explained are reset signal description and type, dependency of signals and timing, and initialization sequence in the mode the user can select. 4.1 reset function the v r 4101 can be reset in the following five ways. for details, refer to the v r 4101 users manual . 4.1.1 rtc reset assert the rtcrst pin active on power application. rtc reset does not save the status information at all, and completely initializes the internal status of the processor. because the dram does not enter the self-refresh mode, the contents of the dram after rtc reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4101 is reset, completely initialize the processor in software. 4.1.2 rstsw assert the rstsw pin active. reset by rstsw initializes all the internal statuses except the rtc timer and pmu. because the dram does not enter the self-refresh mode, the contents of the dram after rstsw reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4101 is reset, completely initialize the processor in software. 4.1.3 deadmans sw the v r 4101 is reset if deadmans sw is not cleared within a specific time after deadmans sw was enabled. reset by deadmans sw initializes all the internal statuses except the rtc timer and pmu. because the dram does not enter the self-refresh mode, the contents of the dram after deadmans sw reset are not guaranteed. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4101 is reset, completely initialize the processor in software. 4.1.4 software shutdown when the software executes the hibernate instruction, the v r 4101 places the dram in the self-refresh mode, deasserts the mpower pin inactive, and enters the reset status. reset by software shutdown initializes all the internal statuses except the rtc timer and pmu. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4101 is reset, completely initialize the processor in software. 4.1.5 haltimer shutdown the v r 4101 enters the reset status if haltimer is not cleared by software within 4 seconds after rtc reset has been cleared. reset by haltimer initializes all the internal statuses except the rtc timer and pmu. after reset, the processor serves as the master of the system bus, the sequence of the cold reset exception is executed, and accessing the reset vector in the rom space is started. because only part of the internal status of the v r 4101 is reset, completely initialize the processor in software.
m pd30101 33 4.2 cpu core registers at reset each of the cpu core registers is reset as follows: ? the ts and sr bits of the status register are cleared to 0. ? the erl and bev bits of the status register are set to 1. ? the upper-limit value (31) is set to the random register. ? the wired register is initialized to 0. ? bits 31 through 28 of the config register are cleared to 0, and bits 22 through 3 are set to 0x04800. the other bits are undefined. ? the values of the registers other than above are undefined. figures 4-1 through 4-5 show the timing of rtc reset, rstsw, deadmans sw, software shutdown, and haltimer shutdown.
m pd30101 34 figure 4-1. rtc reset rtcrst power mpower coldreset (internal) poweron reset (internal) rtc (internal, 32.768 khz) undefined stable oscillation >230 ms >32 ms 7rtc 350 ms stable oscillation 8 ms 16 masterclock note undefined pll (internal) note masterclock is the basic clock in the cpu core. figure 4-2. rstsw rstsw coldreset (internal) mras (0 : 3) ucas/lcas l h power mpower reset (internal) pll (internal) rtc (internal, 32.768 khz) stable oscillation stable oscillation stable oscillation undefined >3rtc 8 ms 16 masterclock note note masterclock is the basic clock in the cpu core.
m pd30101 35 figure 4-3. deadmans sw rstsw power mpower coldreset (internal) reset (internal) pll (internal) rtc (internal, 32.768 khz) h l h stable oscillation stable oscillation 8 ms 16 masterclock note stable oscillation undefined note masterclock is the basic clock in the cpu core. figure 4-4. software shutdown power poweron mpower coldreset (internal) reset (internal) pll (internal) rtc (internal, 32.768 khz) stable oscillation stable oscillation stop undefined 7rtc 350 ms 8 ms 16 masterclock note >32 ms mras (0 : 3)/ ucas/lcas note masterclock is the basic clock in the cpu core.
m pd30101 36 figure 4-5. haltimer shutdown power poweron mpower coldreset (internal) reset (internal) pll (internal) rtc (internal, 32.768 khz) stable oscillation stop 4s >32 ms 7rtc 350 ms 8 ms 16 masterclock note undefined mras (0 : 3)/ ucas/lcas stable oscillation note masterclock is the basic clock in the cpu core. 4.3 poweron sequence the causes that change the status of the v r 4101 from the hibernate mode or shutdown status to the fullspeed mode are called start causes. the start causes include asserting the poweron pin active, asserting the dcd pin active, and alarm from the wakeup timer. when a start cause occurs, the v r 4101 asserts the poweron pin active to inform the external circuit that power to the v r 4101 is about to be turned on. three rtc clocks after the poweron pin has been asserted active, the v r 4101 checks the status of the battinh and gpio9 (battlock) pins. when the battinh or gpio9 (battlock) pin is low, the v r 4101 deasserts the poweron pin inactive one rtc clock after checking the battinh or gpio9 pin status, and is not started. if both the battinh and gpio9 (battclock) pins are high, the v r 4101 deasserts the poweron pin inactive four rtc clocks after the checking, asserts the mpower pin active, and is started. figure 4-6 shows the timing chart where the v r 4101 is started. figure 4-7 shows the timing chart where the v r 4101 is not started because the battinh pin is low.
m pd30101 37 figure 4-6. start sequence of v r 4101 (if started) poweron mpower coldreset (internal) reset (internal) gpio9 (battlock) pll (internal) battinh rtc (internal, 32.768 khz) stop detection of start cause checks status of battinh and gpio9 (battlock) pins cpu starts undefined status stable oscillation figure 4-7. start sequence of v r 4101 (if not started) poweron mpower coldreset (internal) reset (internal) gpio9 (battlock) pll (internal) battinh rtc (internal, 32.768 khz) detection of start cause checks status of battinh and gpio9 ( battlock ) pins cpu does not start l l l h
m pd30101 38 4.4 modes of v r 4101 the v r 4101 supports various modes which can be selected by the user. the mode of the cpu core is specified by writing data to the status register and config register. the mode of the internal peripheral circuits is specified by writing data to the i/o register. this section explains the operation modes of the cpu. 4.4.1 power mode the v r 4101 supports four power modes: fullspeed, standby, suspend, and hibernate. (1) fullspeed mode normally, the processor clock (pclock) operates at 33 mhz. the system bus clock operates at the same rate as the pclock. in the default status, the processor operates in the fullspeed mode. after reset, it returns to the fullspeed mode. (2) standby mode the processor can be set in the standby mode when the standby instruction is executed. in this mode, all the internal clocks of the cpu core, except the timers and interrupts, are kept high. all the peripheral units operate in the same manner as in the fullspeed mode. therefore, dma operation can be executed even in the standby mode. when the standby instruction has completed the wb stage, the v r 4101 stands by until the sysad bus (internal) enters the idle status. after that, the internal clock of the cpu core is shut down, and the pipeline stops operating. however, the pll, timers, interrupt clock, and internal bus clocks (tclock and masterout) continue operating. the processor in the standby mode returns to the fullspeed mode when an interrupt, including the internally generated timer interrupt, occurs. (3) suspend mode the processor can be set in the suspend mode when the suspend instruction is executed. in this mode, the processor stalls the pipeline and keeps all the internal clocks, except the pll and interrupts, high. supply of tclock to the peripheral units is stopped. therefore, the peripheral units, except specific interrupt units (such as the one that controls the dcd pin), cannot operate. in this status, the contents of the registers and cache are retained. when the suspend instruction has completed the wb stage, the v r 4101 places the dram in the self- refresh mode and stands by until the internal sysad bus enters the idle status. after that, the internal clock of the cpu core is shut down, and the pipeline continues operating. supply of tclock to the peripheral units is stopped. however, the pll, timers, interrupt clock, and internal bus clocks (tclock and masterout) continue operating. the processor remains in the suspend mode until it accepts an interrupt. when the processor accepts an interrupt, it returns to the fullspeed mode. (4) hibernate mode the processor can be set in the hibernate mode when the hibernate instruction is executed. in this mode, the processor stops supply of the clock to all the units. in this status, the contents of the registers and cache are retained, and output of tclock and masterout is stopped. the processor remains in the hibernate mode until the power pin is asserted active or the wakeup timer interrupt occurs. if the power pin is asserted active, if the wakeup timer interrupt occurs, or if the dcd pin is asserted active, the processor returns to the fullspeed mode. the power consumption in this mode
m pd30101 39 is almost 0 w (not completely 0 w because a 32.768-khz oscillator and internal circuits that operate at 32.768 khz exist). 4.4.2 privilege mode the v r 4101 supports three system modes: kernel-, supervisor-, and user-extended addressing. these three modes are explained below. (1) kernel-extended addressing mode when the kx bit of the status register is set, extended tlb non-coincidence exception vector is used for tlb non-coincidence of the kernel address. in the kernel mode, the mips iii op code can be always used, regardless of the kx bit. (2) supervisor-extended addressing mode when the sx bit of the status register is set, the mips iii op code can be used in the supervisor mode, and extended tlb non-coincidence exception vector is used for tlb non-coincidence of the supervisor address. (3) user-extended addressing mode when the ux bit of the status bit is set, the mips iii op code can be used in the user mode, and the extended tlb non-coincidence exception vector is used for tlb non-coincidence of the user address. when this bit is cleared, the mips i and ii op codes and 32-bit virtual addresses are used. 4.4.3 reverse endian when the re bit of the status register is set, the endian is reversed in the user mode. however, because the v r 4101 always operates in little endian, fix the rx bit to 0 (reversing is prohibited). 4.4.4 bootstrap exception vector (bev) the bev bit is used to generate an exception while the correct operations of the cache and main memory are tested during self-diagnosis. at reset and on occurrence of the nmi exception, bev is automatically set to 1. when the bev bit of the status register is set, the tlb non-coincidence exception vector is changed to virtual address 0xffff ffff bfc0 0200, and the general exception vector is changed to address 0xffff ffff bfc0 0380. when the bev bit is cleared, the tlb non-coincidence exception vector is changed to 0xffff ffff 8000 0000, and the general exception vector is changed to 0xffff ffff 8000 0180. 4.4.5 cache error check when the ce bit of the status register is set, the contents of the parity error register are written to the parity bit of the data cache instead of the parity generated by the store instruction when the store instruction is executed. if fill of the cache instruction is executed, the contents of the parity error register are written to the parity bit of the instruction cache instead of the instruction parity. 4.4.6 inhibiting parity error when the de bit of the status register is set, the processor does not generate the cache parity error exception. 4.4.7 enabling interrupts (ie) when the ie bit of the status register is cleared, all the interrupts, except reset and non-maskable interrupt, are disabled.
m pd30101 40 5. bcu (bus control unit) 5.1 general the bcu transfers data with the v r 4100 cpu core via sysad bus (internal) inside the v r 4101. it also controls an external lcd controller, dram, rom (flash memory or mask rom), and pcmcia controller via system bus, and transfers data with these devices via add bus and data bus. the bcu basically operates with internal bus clock tclock. table 5-1. bcu registers symbol function bcucntreg bcu control register bcubrreg bcu bus operation interval specification register bcubrcntreg bcu bus operation interval count register bcubclreg bcu bus operation interval enable register bcubclcntreg bcu bus operation interval enable count register bcuspeedreg bcu access cycle change register bcuerrstreg bcu bus error status register bcurfcntreg bcu refresh cycle count register previdreg peripheral unit revision id register
m pd30101 41 6. dmaau (dma address unit) 6.1 general the dmaau controls the addresses for the dma operations of piu, siu (transmission/reception), aiu, and kiu. the dma start physical address of each peripheral unit can be specified in a range of 0x0000 0000 to 0x001 fffe as a half-word address. the dma space of each peripheral unit is a 2k-block including the dma start address, and is aligned at a 2k-byte boundary. the dma operation is not guaranteed if the dma space overlaps with that of other peripheral unit. table 6-1. dmaau registers symbol function paddmaadrlreg dma channel low-order address register for touch panel paddmaadrhreg dma channel high-order address register for touch panel srxdmaadrlreg dma channel low-order address register for siu reception srxdmaadrhreg dma channel high-order address register for siu reception stxdmaadrlreg dma channel low-order address register for siu transmission stxdmaadrhreg dma channel high-order address register for siu transmission auddmaadrlreg dma channel low-order address register for audio output auddmaadrhreg dma channel high-order address register for audio output keydmaadrlreg dma channel low-order address register for keyboard input keydmaadrhreg dma channel high-order address register for keyboard input
m pd30101 42 7. dcu (dma control unit) 7.1 general the dcu controls the dma operation. it controls the dma requests from the peripheral units (siu, kiu, piu, and aiu) and the acknowledge signal from the bcu that performs bus arbitration, and enables or disables the dma operation. the priorities of the dma requests from the respective peripheral units are as follows: aiu > siu reception > siu transmission > piu > kiu table 7-1. dcu registers symbol function dmarstreg dma reset register dmaidlereg dma status register dmasenreg dma enable register dmamskreg dma mask register dmareqreg dma request register
m pd30101 43 8. cmu (clock mask unit) 8.1 general the cmu is used to specify whether the cpu core supplies the clock to each peripheral unit. by supplying the clock only to the necessary peripheral units, the power consumption can be reduced. table 8-1. cmu register symbol function cmuclkmskreg cmu clock mask register 8.2 configuration cscmub piastbb pird piad (0 : 3) addeccmu regcmu msktclk piwrdata (0 : 15) l_tclk rst_gab tclk_piu cmuout (0 : 15) tclk_siu tclk_adu tclk_kiu tclk_giu tclk_term tclk_rtc tclk_dsiu cmuout_msk
m pd30101 44 9. icu (interrupt control unit) 9.1 general the icu receives an interrupt request signal from each peripheral unit and generates an interrupt request signal (int0, int1, or nmi) to the cpu core. table 9-1. icu registers symbol function sysintreg system interrupt register piuintreg piu interrupt register aduintreg aiu interrupt register kiuintreg kiu interrupt register giuintreg giu interrupt register siuintreg siu interrupt register msysintreg system interrupt mask register mpiuintreg piu interrupt mask register maduintreg aiu interrupt mask register mkiuintreg kiu interrupt mask register mgiuintreg giu interrupt mask register msiuintreg siu interrupt mask register nmireg battery interrupt select register softintreg software interrupt register table 9-2. correspondence of interrupts of icu and cpu core sysintreg bit position interrupt source interrupt request signal 13 piu (in suspend mode) int0 12 kiu (in suspend mode) 11 software (by softintreg) 10 bus error 9 siu 6 aiu 8 giu 7 kiu 5 piu 4 pcmcia 3 elapsed time timer 2 rtclong timer int1 1 power-on switch int0 0 battery nmi/int0 (selected by nmireg)
m pd30101 45 9.2 configuration softintreg siuintreg msiuintreg giuintreg mgiuintreg kiuintreg mkiuintreg aduintreg maduintreg piuintreg mpiuintreg and-or and-or and-or and-or and-or 14 14 13 13 5 5 4 4 5 5 penchgint keyscanint buserrint pcmciaint etimerint rtc_long powerint battint msysintreg sysintreg 5 8 14 14 and-or nmi (battint note ) lnt1 (rtc_long) int0 (all interrupts other than battint note and rtc_long) interrupt indication register interrupt mask register and-or logic (checks masking of each bit and summerizes interrupt request of each register.) level 2 register level 1 register note battint can specify whether nmi or int0 is used by nmireg.
m pd30101 46 10. pmu (power management unit) 10.1 general pmu manages and controls power to the internal and external circuits of the v r 4101 as follows: ? controls shutdown ? controls reset ? manages and controls power-on sequence ? manages and controls sequence in power mode table 10-1. pmu registers symbol function pmuintreg pmu interrupt/status register pmucntreg pmu control register 10.1.1 power mode the v r 4101 supports the following four power modes: ? fullspeed mode ? standby mode ? suspend mode ? hibernate mode figure 10-1 illustrates the transition of the power modes. to change the mode from fullspeed to standby, suspend, or hibernate, execute the standby, suspend, or hibernate instruction. to change the mode from standby, suspend, or hibernate to fullspeed, either generate an interrupt, or execute a reset operation. table 10-2 outlines each power mode.
m pd30101 47 figure 10-1. power mode transition standby mode suspend mode fullspeed mode hibernate mode (1) (2) (3) (4) (6) (5) (1) standby instruction, pipeline flash, sysad idle, pclock high level (2) all interrupts (3) suspend instruction, pipeline flash, sysad idle, pclock high level, tclock high level, dram self refresh start (4) batterylnt powersw rtcrst alarm keytouch pentouch batterylock cardlock dcd (5) hibernate instruction, pipeline flash, sysad idle, pclock high level, tclock high level, masterout high level, dram self refresh start (6) powersw alarm dcd table 10-2. outline of power mode mode internal peripheral unit power consumption note 1 rtc icu dcu others (33 mhz, 3.3 v typ.) fullspeed on on on selectable note 2 200 mw standby on on on selectable note 2 100 mw suspend on on off off 13 mw hibernate on off off off 165 m w off off off off off 0 w notes 1. targeted value 2. refer to 8. cmu (clock mask unit) .
m pd30101 48 11. rtc (real-time clock unit) 11.1 general the rtc consists of the following three types of timers. ? rtclong timer this is a 24-bit programmable down counter that counts down at a cycle of 32.768 khz. it can generate an interrupt request at intervals of up to 512 seconds. ? elapsedtime timer this is a 48-bit up counter that counts up at a cycle of 32.768 khz. when this counter counts up to about 272 years, it returns to 0. this counter consists of an 48-bit elapsedtime counter and a 48-bit alarm time register. by comparing these, an interrupt request can be generated at specific time. ? tclock count timer this is a 32-bit free-running counter that counts up at a cycle of tclock, and can be used for performance evaluation. table 11-1. rtc registers symbol function etimelreg elapsedtime timer register, low etimemreg elapsedtime timer register, middle etimehreg elapsedtime timer register, high ecmphreg elapsedtime timer compare register, high ecmplreg elapsedtime timer compare register, low ecmpmreg elapsedtime timer compare register, middle rtcllreg rtclong timer register, low rtclhreg rtclong timer register, high rtclcntlreg rtclong timer count register, low rtclcnthreg rtclong timer count register, high tclkcntlreg tclk count register, low tclkcnthreg tclk count register, high rtcintreg rtc interrupt register
m pd30101 49 11.2 configuration internal data bus internal address bus rtc address decode unit elapsedtime unit rtclong unit tclock count unit bus i/f unit interrupt i/f unit icu
m pd30101 50 12. dsu (deadmans sw unit) 12.1 general the dsu automatically detects a hang-up of the v r 4101 and resets the v r 4101. by stopping a hang-up at the earliest stage by using the dsu, the destruction of data can be minimized. the dsu can set for a cycle of up to 15 seconds in units of 1 second. set the dswclr bit of the dsuclrreg register to 1 within this time in software. if the bit is not set within the time, the cpu is reset (refer to 4. initialization interface ). table 12-1. dsu registers symbol function dsucntreg dsu control register dsusetreg deadmans switch enable register dsuclrreg deadmans switch clear register dsutimreg deadmans switch elapsed time register
m pd30101 51 13. giu (general-purpose i/o unit) 13.1 general the giu controls the gpio (0:11) pins and dcd pin. the gpio (0:11) pins constitute a general-purpose i/o port, but one of the gpio pins is reserved for a specific application. the other 11 pins and dcd pins can be assigned interrupt requests. as a trigger, the edge of the input level, low level, or high level can be selected. table 13-1. giu registers symbol function goutenreg general-purpose port i/o setting register gpotdatreg general-purpose port data register gintstreg general-purpose port interrupt register gintenreg general-purpose port interrupt enable register gcintsreg general-purpose port interrupt trigger setting register glintsreg general-purpose port interrupt level setting register table 13-2. outline of dcd and general-purpose i/o pins pin input buffer type interrupt detection clock (internal) dcd note 1 masterout gpio11 i/o (schmitt) tclock gpio10 i/o (schmitt) masterout gpio9 note 2 i/o (schmitt) masterout gpio8 i/o tclock gpio7 i/o tclock gpio6 i/o tclock gpio5 i/o tclock gpio4 i/o tclock gpio3 i/o tclock gpio2 i/o tclock gpio1 i/o tclock gpio0 i/o tclock notes 1. the dcd pin (input) is internally connected to bit 13 of the gpio register. this pin is used only as an input pin with giu. 2. fix the gpio9 pin to a battery lid lock detection signal (battlock). remark all the pins are set in the input mode at reset.
m pd30101 52 14. piu (touch panel interface unit) 14.1 general the piu detects the x and y coordinates on a panel touched by the pin by using an external a/d converter. it also measures battery voltage. as the external a/d converter, the tlv1543 (conversion accuracy: 10 bits) and tlc2543c (conversion accuracy: 12 bits) are supported. table 14-1. piu registers symbol function piudatareg touch panel data register piucntreg piu control register piuintreg piu interrupt register piusivlreg keyboard scan sampling cycle setting register piustblreg a/d converter control register piucmdreg a/d converter command register piucivlreg piu count register 14.2 example of external circuit configuration touch panel main battery sub battery driver a/d converter 4 2 2 2 pencont (0 : 4) penchgintr v r 4101 piu
m pd30101 53 15. siu (serial interface unit) 15.1 general the siu supports rs-232c communication and irad communication and has one channel each for each communication mode. however, rs-232c communication and irad communication are mutually exclusive. this siu also supports detection of framing errors and detection/transmission of a break, and can also support uart. the parity bit of the transmit/receive data is not automatically processed, but treated as data. table 15-1. siu registers symbol function siurxdatreg siu receive data register siutxdatreg siu transmit data register siucntreg siu control register siudlengthreg serial data length register siuintreg siu interrupt register siurs232creg rs-232c control register siubaudselreg baud rate setting register 15.2 configuration cpu core bcu siu piad piwrdata interrupt request signal (to icu) internal external irdin irdout infrared module rxd txd rs-232c connector siuout control signal (to dcu)
m pd30101 54 16. aiu (audio interface unit) 16.1 general the aiu generates audio signals. it has two preset counters and offers the following two modes: ? buzz mode a signal with a frequency of m and a duty factor of 50% is output for only the duration of n. ? pwm mode a high level is output from the output pin for only the duration of m and a low level is output for only the duration of n. by supply data combining m and n at high speeds, pwm of any oversampling is reproduced. table 16-1. aiu registers symbol function aiudatreg aiu data register aiuresetreg aiu reset register aiumodereg aiu mode register aiuseqenreg aiu sequencer enable register aiumutereg aiu output enable register aiustatreg aiu status register aiustppagereg page boundary interrupt enable register aiuvalidreg aiu counter status register aiuintreg aiu interrupt register aiucount0reg aiu counter 0 aiucount1reg aiu counter 1 aiurepnumreg number of pwm repeats setting register aiubusenreg dma enable register
m pd30101 55 16.2 configuration cpu core bcu dram piwrdata piad dcu internal external audiout0 audiout1 external circuit audio output aiustintr aiuintr aiuendintr aiuidleintr audiout0 audiout1 drqadu dakadu page aiu aiuout (0 : 15) icu interrupt indication remark the audiout0 and audiout1 pins output the same data. either of these pins can be masked by using the aiumutereg register. the volume of the actual audio output can be controlled by using this register and the external circuit.
m pd30101 56 17. kiu (keyboard interface unit) 17.1 general the kiu has eight scan lines and eight detection lines and can detect data input from 64 keys. it can also detect rollover of two or three keys. table 17-1. kiu registers symbol function kiudatreg key scan data register kiuascanreg key auto scan setting register kiuastopreg key scan automatic stop register kiuscanreg key scan start register kiustopreg key scan stop register kiusapreg page boundary interrupt enable register kiuscansreg kiu sequencer enable register kiuwksreg kiu wait time setting register kiuwkireg key scan interval setting register kiusrnreg kiu sequencer stop setting register kiuintreg kiu interrupt register kiurstreg kiu reset register kiuenreg key scan enable register dozekeyintreg key input detect register evvolreg electronic volume control register
m pd30101 57 17.2 configuration cpu core bcu dcu piwrdata piad kiu kiuout (0 : 15) drqkiu dakkiu page kport (0 : 7) kscan (2 : 7) evinc/kscan1 evud/kscan0 keyscanlntr keydatrdylntr keydatlostlntr keylntr keyendlntr dozekeylntr icu interrupt indication internal external kport (0 : 7) kscan (2 : 7) evinc/kscan1 evud/kscan0 keyboard lcd luminance adjustment
m pd30101 58 18. debugsiu (debug serial interface unit) 18.1 general the debugsiu is a dedicated serial interface unit that is used during debugging. it supports a data transfer rate of up to 115 kbps. table 18-1. debugsiu registers symbol function asim00reg debugsiu setting register asim01reg extended bit enable register rxb0rreg debugsiu reception extended data register rxb0lreg debugsiu receive data register txs0rreg debugsiu transfer extended data register txs0lreg debugsiu transfer data register asis0reg debugsiu communication status register intr0reg debugsiu interrupt register bprm0reg baud rate setting register dsiuresetreg debugsiu reset register
m pd30101 59 19. instruction set each instruction of the v r 4101 consists of 1 word (32 bits) located at a word boundary. three instruction formats are available as shown in figure 19-1. by employing the three simplified instruction formats, the decoding of instructions is simplified. complicated operations and addressing modes that are not frequently used are realized by the compiler. 19.1 instruction formats the instruction formats of the v r 4101 are shown below. figure 19-1. cpu instruction format 31 26 25 21 20 16 15 0 op rs rt immediate op target op rs rt rd sa funct 31 26 25 0 31 26 25 21 20 16 15 0 11 10 6 5 i-type (immediate format) j-type (jump format) r-type (register format) op 6-bit instruction code rs 5-bit source register specifier rt 5-bit target (source/destination) register, or conditional branch immediate 16-bit immediate value, branch displacement, or address displacement target 26-bit unconditional branch target address rd 5-bit destination register specifier sa 5-bit shift funct 6-bit function field 19.2 cpu instruction set list all the cpu instructions of the v r 4101 are classified into three sets: instruction set common to all the v r series processors (isa: instruction set architecture), instruction set executed by the v r 4000 series (extended isa), and system control coprocessor instruction set. each instruction set is listed below.
m pd30101 60 table 19-1. cpu instruction set: isa (1/2) instruction description format load/store instruction op base rt offset lb load byte lb rt, offset (base) lbu load byte unsigned lbu rt, offset (base) lh load halfword lh rt, offset (base) lhu load halfword unsigned lhu rt, offset (base) lw load word lw rt, offset (base) lwl load word left lwl rt, offset (base) lwr load word right lwr rt, offset (base) sb store byte sb rt, offset (base) sh store halfword sh rt, offset (base) sw store word sw rt, offset (base) swl store word left swl rt, offset (base) swr store word right swr rt, offset (base) aiu immediate instruction op rs rt offset addi add immediate addi rt, rs, immediate addiu add immediate unsigned addiu rt, rs, immediate slti set on less than immediate slti rt, rs, immediate sltiu set on less than immediate unsigned sltiu rt, rs, immediate andi and immediate andi rt, rs, immediate ori or immediate ori rt, rs, immediate xori exclusive or immediate xori rt, rs, immediate lui load upper immediate lui rt, immediate 3-operand type instruction op rs rt rd sa funct add add add rd, rs, rt addu add unsigned addu rd, rs, rt sub subtract sub rd, rs, rt subu subtract unsigned subu rd, rs, rt slt set on less than slt rd, rs, rt sltu set on less than unsigned sltu rd, rs, rt and and and rd, rs, rt or or or rd, rs, rt xor exclusive or xor rd, rs, rt nor nor nor rd, rs, rt shift instruction op rs rt rd sa funct sll shift left logical sll rd, rt, sa srl shift right logical srl rd, rt, sa sra shift right arithmetic sra rd, rt, sa sllv shift left logical variable sllv rd, rt, rs srlv shift right logical variable srlv rd, rt, rs srav shift right arithmetic variable srav rd, rt, rs
m pd30101 61 table 19-1. cpu instruction set: isa (2/2) instruction description format multiplication/division instruction op rs rt rd sa funct mult multiply mult rs, rt multu multiply unsigned multu rs, rt div divide div rs, rt divu divide unsigned divu rs, rt mfhi move from hi mfhi rd mflo move from lo mflo rd mthi move to hi mthi rs mtlo move to lo mtlo rs jump instruction (1) op target j jump j target jal jump and link jal target jump instruction (2) op rs rt rd sa funct jr jump register jr rs jalr jump and link register jalr rs, rd branch instruction (1) op rs rt offset beq branch on equal beq rs, rt, offset bne branch on not equal bne rs, rt, offset blez branch on less than or equal to zero blez rs, offset bgtz branch on greater than zero bgtz rs, offset branch instruction (2) regimm rs sub offset bltz branch on less than zero bltz rs, offset bgez branch on greater than or equal to zero bgez rs, offset bltzal branch on less than zero and link bltzal rs, offset bgezal branch on greater than or equal to zero and link bgezal rs, offset special instruction special rs rt rd sa funct sync synchronize sync syscall system call syscall break breakpoint break coprocessor instruction (1) op base rt offset lwcz load word to coprocessor z lwcz rt, offset (base) swcz store word from coprocessor z swcz rt, offset (base) coprocessor instruction (2) copz sub rt rd 0 mtcz move to coprocessor z mtcz rt, rd mfcz move from coprocessor z mfcz rt, rd ctcz move control to coprocessor z ctcz rt, rd cfcz move control from coprocessor z cfcz rt, rd coprocessor instruction (3) copz co cofun copz coprocessor z operation copz cofun coprocessor instruction (4) copz bc br offset bczt branch on coprocessor z true bczt offset bczf branch on coprocessor z false bczf offset
m pd30101 62 table 19-2. cpu instruction set: extended isa (1/2) instruction description format load/store instruction op base rt offset ld load doubleword ld rt, offset (base) ldl load doubleword left ldl rt, offset (base) ldr load doubleword right ldr rt, offset (base) lwu load word unsigned lwu rt, offset (base) sd store doubleword sd rt, offset (base) sdl store doubleword left sdl rt, offset (base) sdr store doubleword right sdr rt, offset (base) aiu immediate instruction op rs rt immediate daddi doubleword add immediate daddi rt, rs, immediate daddiu doubleword add immediate unsigned daddiu rt, rs, immediate 3-operand type instruction op rs rt rd sa funct dadd doubleword add dadd rd, rs, rt daddu doubleword add unsigned daddu rd, rs, rt dsub doubleword subtract dsub rd, rs, rt dsubu doubleword subtract unsigned dsubu rd, rs, rt shift instruction op rs rt rd sa funct dsll doubleword shift left logical dsll rd, rt, sa dsrl doubleword shift right logical dsrl rd, rt, sa dsra doubleword shift right arithmetic dsra rd, rt, sa dsllv doubleword shift left logical variable dsllv rd, rt, rs dsrlv doubleword shift right logical variable dsrlv rd, rt, rs dsrav doubleword shift right arithmetic variable dsrav rd, rt, rs dsll32 doubleword shift left logical+32 dsll32 rd, rt, sa dsrl32 doubleword shift right logical+32 dsrl32 rd, rt, sa dsra32 doubleword shift right arithmetic+32 dsra32 rd, rt, sa multiplication/division instruction (1) op rs rt rd sa funct dmult doubleword multiply dmult rs, rt dmultu doubleword multiply unsigned dmultu rs, rt ddiv doubleword divide ddiv rs, rt ddivu doubleword divide unsigned ddivu rs, rt multiplication/division instruction (2) op rs rt rd sa funct madd16 multiply and add 16-bit integer madd16 rs, rt dmadd16 doubleword multiply and add 16-bit integer dmadd16 rs, rt branch instruction (1) op rs rt offset beql branch on equal likely beql rs, rt, offset bnel branch on not equal likely bnel rs, rt, offset blezl branch on less than or equal to zero likely blezl rs, offset bgtzl branch on greatrer than zero likely bgtzl rs, offset
m pd30101 63 table 19-2. cpu instruction set: extended isa (2/2) instruction description format branch instruction (2) regimm rs sub offset bltzl branch on less than zero likely bltzl rs, offset bgezl branch on greater than or equal to zero likely bgezl rs, offset bltzall branch on less than zero and link likely bltzall rs, offset bgezall branch on greater than or equal to zero and link likely bgezall rs, offset exception instruction special rs rt rd sa funct tge trap if greater than or equal tge rs, rt tgeu trap if greater than or equal unsigned tgeu rs, rt tlt trap if less than tlt rs, rt tltu trap if less than unsigned tltu rs, rt teq trap if equal teq rs, rt tne trap if not equal tne rs, rt exception immediate instruction regimm rs sub immediate tgei trap if greater than or equal immediate tgei rs, immediate tgeiu trap if greater than or equal immediate unsigned tgeiu rs, immediate tlti trap if less than immediate tlti rs, immediate tltiu trap if less than immediate unsigned tltiu rs, immediate teqi trap if equal immediate teqi rs, immediate tnei trap if not equal immediate tnei rs, immediate table 19-3. system control coprocessor (cp0) instruction set instruction description format system control coprocessor instruction (1) cop0 sub rt rd 0 mfc0 move from coprocessor 0 mfc0 rt, rd mtc0 move to coprocessor 0 mtc0 rt, rd dmfc0 doubleword move from coprocessor 0 dmfc0 rt, rd dmtc0 doubleword move to coprocessor 0 dmtc0 rt, rd system control coprocessor instruction (2) cop0 co funct tlbr read indexed tlb entry tlbr tlbwi write indexed tlb entry tlbwi tlbwr write random tlb entry tlbwr tlbp probe tlb for matching entry tlbp eret exception return eret system control coprocessor instruction (3) cop0 co funct standby standby standby suspend suspend suspend hibernate hibernate hibernate system control coprocessor instruction (4) cache base sub offset cache cache operation cache sub, offset (base)
m pd30101 64 19.3 instruction execution time in principle, the v r 4101 executes one instruction in one cycle, but some instructions take two cycles or more. (1) the data loaded by a load instruction cannot be used in the delay slot. if an instruction that uses load data is placed in the delay slot, the pipeline stalls. a store instruction stalls by the delay slot if it is followed by a load instruction or mfc0. if a branch instruction whose condition is satisfied or a jump instruction is executed, the instruction at the destination address is executed after the delay slot. table 19-4. number of delay slot cycles instruction category necessary number of cycles (pcycle) load 1 store 1 jump 1 branch 1 (2) the number of cycles indicated in the table below is necessary for executing an integer multiplication/ division or sum-of-products operation instruction. these instructions can be executed in parallel with other instructions, except those that access the hi/ lo registers that store the result of an operation, and multiplication/division or sum-of-products operation instruction. table 19-5. number of execution cycles of integer multiplication/division instructions instruction category necessary number of cycles (pcycle) mult 1 multu 1 div 35 divu 35 dmult 4 dmultu 4 ddiv 67 ddivu 67 madd16 1 dmadd16 1
m pd30101 65 20. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd C0.5 to +4.0 v input voltage v i v dd 3.7 v C0.5 to +4.0 v v dd 3.7 v, pulse less than 10 ns C1.5 to +4.0 v v dd < 3.7 v C0.5 to v dd + 0.3 v v dd < 3.7 v, pulse less than 10 ns C1.5 to v dd + 0.3 v operating temperature t a C10 to +70 c storage temperature t stg C65 to +150 c cautions 1. do not short-circuit two or more output pins simultaneously. 2. if even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. use the product well within these ratings. the specifications and conditions shown in dc characteristics and ac characteristics are the ranges for normal operation and quality assurance of the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol condition min. max. unit input capacitance c i f c = 1 mhz 10 pf i/o capacitance c io pins other than test pin: 0 v 10 pf
m pd30101 66 recommended oscillation circuit (a) crystal resonator connection (t a = C10 to +70 c, v dd = 2.5 to 3.6 v) gnd clkx1 clkx2 c1 c2 rd manufacturer product name frequency recommended circuit constant (khz) c1 (pf) c2 (pf) rd (k w ) seiko instruments inc. sp-t2a 32.768 20 20 220 caution when using a system clock oscillation circuit, perform the wiring of the portion enclosed by the dotted line in the above figure to avoid adverse influence due to wiring capacitance, etc. ? keep the wiring length as short as possible. ? do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. ? make sure that the ground point of the capacitor of the oscillation circuit is at the same potential as gnd. do not ground the capacitor to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. (b) external clock input clkx1 clkx2 open hcmos inverter caution do not connect a load such as wiring capacitance to the clkx2 pin.
m pd30101 67 dc characteristics (t a = C10 to +70 c, v dd = 3.0 to 3.6 v) parameter symbol condition min. typ. max. unit high-level output voltage v oh i oh = C2 ma 0.8 v dd v i oh = C20 m av dd C 0.1 low-level output voltage v ol i ol = 2 ma 0.4 v i ol = 20 m a 0.1 high-level input voltage note 1 v ih1 2.0 v dd + 0.3 v low-level input voltage note 1 v il1 C0.3 0.3 v dd v pulse less than 10 ns C1.5 0.3 v dd v high-level input voltage note 2 v ih2 0.75 v dd v dd + 0.3 v low-level input voltage note 2 v il2 C0.3 0.6 v pulse less than 10 ns C1.5 0.6 v hysteresis voltage note 3 v h 0.17 v dd v supply current note 4 i dd add (0:20) = 120 pf, 60 115 ma other pins = 40 pf, in fullspeed mode external load: 0 pf, in standby mode 30 50 external load: 0 pf, in suspend mode 47 external load: 0 pf, in hibernate mode 50 100 m a input leakage current note 4 i li v dd = 3.6 v, v i = v dd , 0 v 5 m a high-level input leakage current note 5 i lih v dd = 3.6 v, v i = v dd 36 m a output leakage current i lo v dd = 3.6 v, v i = v dd , 0 v 5 m a notes 1. except clkx1, power, rstsw, rtcrst, battinh, battint, and gpio (9:10) pins 2. applied to power, rstsw, rtcrst, battinh, battint, and gpio (9:10) pins 3. hysteresis voltage: difference between the minimum voltage at which the high level of a schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low 4. except kport (0:7) (input pins with pull-down resistor) 5. applied to kport (0:7) (input pins with pull-down resistor)
m pd30101 68 data retention characteristics (t a = C40 to +85 c) parameter symbol condition min. max. unit data retention voltage note 1 v dddr hibernate mode under evaluation 3.6 v (2.5) data retention high-level input v ihdr under evaluation v voltage note 2 (0.9 v dddr ) notes 1. the data retention voltage guarantees retention of the data read from the following registers for the rtc operation, and the data of the compare register (the data in the cpu core cannot be guaranteed). etimelreg, etimemreg, etimehreg, ecomplreg, ecompmreg, ecomphreg, rtcllreg, rtclhreg, rtclcntlreg, rtclcnthreg 2. applied to rtcrst pin remark the values in ( ) are the targeted values. v dd rtcrst 3.0 v 2.5 v v dddr v ihdr
m pd30101 69 ac characteristics (t a = C10 to +70 c, v dd = 3.0 to 3.6 v) ac test input waveform (a) adeoc, adin, cts, data (0:15), dcd, ddin, dsr, gpio (0:8), gpio11, irdin, irq, kport (0:7), lcdrdy, penchgint, rxd, zws 2.0 v 0.3 v dd 2.0 v 0.3 v dd test points v dd 0 v (b) battinh, battint, gpio (9:10), power, rstsw, rtcrst 0.75 v dd 0.2 v dd 0.75 v dd 0.2 v dd test points v dd 0 v ac test output measuring points 0.7 v dd 0.8 v 0.7 v dd 0.8 v test points load condition (a) add (0:20) dut add (0 : 20) c l = 120 pf (b) other output pins dut output pin (other than add (0 : 20)) c l = 40 pf
m pd30101 70 (1) clock parameter parameter symbol condition min. typ. max. unit clkx1 high-level width t wxh with external clock input 15 m s clkx1 low-level width t wxl with external clock input 15 m s clkx1 clock frequency with external clock input 32 32.768 35 khz clkx1 clock cycle t cyx with external clock input 31.250 30.518 28.571 m s clkx1 clock rise time t xr with external clock input 20 ns clkx1 clock fall time t xf with external clock input 20 ns pcmclk high-level width t pclkh 45 ns pcmclk low-level width t pclkl 45 ns pcmclk frequency 8.290 mhz adclk high-level width note 1 t adclkh n C 40 ns adclk low-level width note 1 t adclkl n C 40 ns adclk frequency note 2 m mhz notes 1. calculate the value of n from the value of the seladclk (0:3) bits of the piustblreg register by using the following expression: (seladclk 4 + 2)/33.16 2. calculate the value of m from the value of the seladclk (0:3) bits of the piustblreg register by using the following expression: 16.58/(seladclk 4 + 2) t cyx t wxh t wxl t pclkh t pclkl t xf t xr t adclkh t adclkl pcmclk (output) clkx1 (input) adclk (output) (2) reset parameter parameter symbol condition min. max. unit reset input low-level width t wrsl applied to rtcrst pin 305 m s rtcrst (input) t wrsl
m pd30101 71 (3) system interface parameter parameter symbol condition min. max. unit input level width t inp1 note 1 91.5 m s t inp2 note 2 361.5 ns t inp3 note 3 180.6 ns output level width t outp1 note 4 29 m s t outp2 note 5 30 ns mras (0:3)/ucas/lcas floating t ramz 91.5 m s delay note 6 notes 1. applied to power, rstsw, rtcrst, battinh, battint, gpio9, and dcd pins 2. applied to dsr, irq, penchgint, cts, gpio10, and kport (0:7) pins 3. applied to gpio11, gpio (0:8), irdin, ddin, lcdrdy, zws, adin, adeoc, and rxd pins 4. applied to mpower pin 5. applied to adcs, adclk, adsout, pencnt (0:4), gpio (0:11), rstout, rts, dtr, add (0:20), data (0:15), txd, irdout, ddout, kscan (0:7), audiout (0:1), lcdcs, lcdoe, lcdwe/ romwe, romcs (0:3), romoe, pcmclk, shb, ior, iow, memr, and memw pins 6. applied to mras (0:3), ucas, and lcas pins in respect to input of rstsw pin input signal output signal rstsw (input) note 6 t inpm t outpn m = 1-3 n = 1, 2 t ramz t ramz hi-z
m pd30101 72 (4) edo type dram read parameter (1/2) the target dram is the m pd42s16165l-a70 or m pd42s18165l-a70. parameter symbol condition min. max. unit mras (0:3) pulse width t rasp 70 ns mras (0:3) hold time (vs. ucas/lcas precharge) t rhcp 40 ns mras (0:3) precharge time t rp 50 ns mras (0:3) hold time (vs. ucas/lcas )t rsh 12 ns mras (0:3) ? lcas/ucas delay time t rcd 14 ns mras (0:3) ? ucas/lcas access time t rac 95 ns mras (0:3) ? column address delay time t rad 12 ns ucas/lcas hold time (vs. mras (0:3) )t csh 50 ns ucas/lcas pulse width t hcas 12 ns ucas/lcas precharge time t cp 10 ns ucas/lcas precharge ? mras (0:3) - access time t acp 60 ns ucas/lcas ? ucas/lcas access time t cac 43 ns read cycle time t hpc 30 ns row address setup time (add (9:20)) (vs. mras (0:3) )t asr 0ns row address hold time (vs. mras (0:3) )t rah 10 ns column address setup time (vs. ucas/lcas )t asc 0ns column address setup time (vs. mras (0:3) - )t ral 35 ns column address hold time 1 (vs. ucas/lcas )t cah1 add (9:18) note 1 12 ns column address hold time 2 (vs. ucas/lcas )t cah2 add (9:18) note 2 12 ns column address hold time 3 (vs. ucas/lcas )t cah3 add (19:20) note 2 12 ns column address ? ucas/lcas access time t aa 60 ns ramoe ? ucas/lcas access time t oea 38 ns data input setup time 1 (vs. ucas/lcas )t ds1 20 ns data input hold time 1 (vs. ucas/lcas )t dh1 5ns data input setup time 2 (vs. mras (0:3) - )t ds2 20 ns data input hold time 2 (vs. mras (0:3) - )t dh2 5ns notes 1. applies to addresses other than the last address during block access 2. applied to the last address during block access
m pd30101 73 (4) edo type dram read parameter (2/2) mras (0 : 3) (output) ucas/lcas (output) add (19 : 20) (output) add (9 : 18) (output) ramoe note (output) ((rstsw (input)) data (0:15) (i/o) t rasp t rhcp t rp t csh t hcas t rsh t asr t rcd t rad t rah t ral t asc t cah1 t cah2 t acp t oea hi-z invalid invalid hi-z t rac t aa t cac t ds1 t dh1 t ds2 t dh2 t cp t hpc t cah3 note the v r 4101 does not have an output enable pin (ramoe) for dram. create an output enable pin (ramoe) by using the inverted signal of the rstsw pin.
m pd30101 74 (5) edo type dram write parameter (1/2) the target dram is the m pd42s16165l-a70 or m pd42s18165l-a70. parameter symbol condition min. max. unit mras (0:3) pulse width t rasp 70 ns mras (0:3) hold time (vs. ucas/lcas precharge) t rhcp 40 ns mras (0:3) precharge time t rp 50 ns mras (0:3) hold time (vs. ucas/lcas )t rsh 12 ns mras (0:3) ? lcas/ucas delay time t rcd 14 ns mras (0:3) ? column address delay time t rad 12 ns ucas/lcas hold time (vs. mras (0:3) )t csh 50 ns ucas/lcas pulse width t hcas 12 ns ucas/lcas precharge time t cp 10 ns write cycle time t hpc 30 ns row address setup time (add (9:20)) (vs. mras (0:3) )t asr 0ns row address hold time (vs. mras (0:3) )t rah 10 ns column address setup time (vs. ucas/lcas )t asc 0ns column address setup time (vs. mras (0:3) - )t ral 35 ns column address hold time 1 (vs. ucas/lcas )t cah1 add (9:18) note 1 12 ns column address hold time 2 (vs. ucas/lcas )t cah2 add (9:18) note 2 12 ns column address hold time 3 (vs. ucas/lcas )t cah3 add (19:20) note 2 12 ns ramwe setup time (vs. ucas/lcas )t wcs 0ns ramwe hold time (vs. lcas/ucas )t wch 10 ns data output setup time (vs. lcas/ucas )t d1 0ns data output hold time (vs. lcas/ucas )t d2 10 ns notes 1. applies to addresses other than the last address during block access 2. applied to the last address during block access
m pd30101 75 (5) edo type dram write parameter (2/2) mras (0 : 3) (output) ucas/lcas (output) add (19 : 20) (output) add (9 : 18) (output) ramwe (output) data (0 : 15) (i/o) t rasp t rhcp t rp t csh t rsh t hcas t asr t cp t rcd t hpc t cah3 t ral t rad t asc t rah t cah2 t wch t d2 t d1 t d2 t d1 t wcs t cah1 invalid
m pd30101 76 (6) dram refresh parameter the target dram is the m pd42s161615l-a70 or m pd42s18165l-a70. (a) cas-before-ras refresh parameter parameter symbol condition min. max. unit read/write cycle time t rc 130 ns mras (0:3) pulse width t ras 70 ns mras (0:3) precharge time t rp 50 ns ucas/lcas setup time (vs. mras (0:3) )t csr 5ns ucas/lcas hold time (vs. mras (0:3) )t chr 10 ns ucas/lcas - ? mras (0:3) precharge time t crp 5ns ucas/lcas precharge time t cpn 10 ns mras (0 : 3) (output) ucas/lcas (output) ramwe ( output ) h t csr t ras t chr t rp t crp t cpn t rc (b) cas-before-ras self-refresh parameter parameter symbol condition min. max. unit mras (0:3) pulse width note t rass 100 m s mras (0:3) precharge time t rps 130 ns ucas/lcas hold time (vs. mras (0:3) - )t chs C50 ns note the cas-before-ras self-refresh parameter is valid when t rass exceeds 100 m s. mras (0 : 3) (output) ucas/lcas (output) ramwe ( output ) h t rass t rps t chs
m pd30101 77 (7) normal rom parameter parameter symbol condition min. max. unit access time width from address (add (0:20)) note t acc 60n C 28 ns access time width from romcs (0:3) note t ce 60n C 28 ns access time width from romoe note t oe 60n C 28 ns data input setup time (vs. romcs (0:3) - , romoe - )t ds 20 ns data input hold time (vs. romcs (0:3) - , romoe - )t dh 5ns note set the value of n by using the wroma (0:2) bits of the bcuspeedreg register. wroma2 wroma1 wroma0 n 0009 0018 0107 0116 1005 1014 1103 1112 romcs (0 : 3) (output) romoe (output) data (0 : 15) (input) t acc t ce t oe hi-z invalid invalid t ds t dh hi-z add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) when wroma (0 : 2) = 111b
m pd30101 78 (8) page rom parameter parameter symbol condition min. max. unit access time width 1 from address (add (0:20)) note t acc1 60n C 28 ns access time width 2 from address note t acc2 60m C 28 ns access time width from romcs (0:3) note t ce 60n C 28 ns access time width from romoe note t oe 60n C 28 ns data input setup time t ds 20 ns data input hold time t dh 5ns note set the values of n and m by using the wroma (0:2) bits and wprom (0:1) bits of the bcuspeedreg register, respectively. wroma2 wroma1 wroma0 n wprom1 wprom0 m 0009 003 0018 012 0107 101 0116 11 1005 1014 1103 1112 romcs (0 : 3) (output) romoe (output) data (0 : 15) (input) t acc1 hi-z invalid add (1 : 3) (output) add0, add (4 : 20) (output) invalid hi-z t acc2 t ce t oe t ds t dh t ds t dh
m pd30101 79 (9) flash memory mode read parameter parameter symbol condition min. max. unit address (add (0:20)) ? data output delay time t avqv 180 ns address (add (0:20)) setup time (vs. romcs (0:3) )t avel 0ns address hold time (vs. romoe - )t ghax 10 ns romcs (0:3) setup time (vs. romoe )t elgl 10 ns romcs (0:3) ? data output delay time t elqv 180 ns romoe ? data output delay time t glqv 80 ns address (add (0:20)) setup time (vs. romoe )t avgl 0ns romcs (0:3) hold time (vs. romoe - )t gheh 10 ns romoe high-level width t ghgl 75 ns data input setup time (vs. romoe - )t ds 20 ns data input hold time (vs. romoe - )t dh 5ns romcs (0 : 3) (output) romoe (output) data (0 : 15) (input) invalid add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) invalid t avel t avgl t elgl t glqv t elqv t alqv t ghgl t gheh t ghax t ds t dh remark the dotted line indicates a high-impedance state.
m pd30101 80 (10) flash memory mode write parameter parameter symbol condition min. max. unit write cycle time t avav 150 ns address (add (0:20)) setup time (vs. lcdwe - )t avwh 75 ns address (add (0:20)) setup time (vs. romcs (0:3) )t avel 0ns address hold time (vs. lcdwe - )t whax 10 ns address (add (0:20)) setup time (vs. lcdwe )t avwl 25 ns romcs (0:3) setup time (vs. lcdwe )t elwl 10 ns romcs (0:3) hold time (vs. lcdwe - )t wheh 10 ns lcdwe low-level width t wlwh 75 ns lcdwe high-level width t whwl 75 ns data output setup time (vs. lcdwe - )t dvwh 75 ns data output hold time (vs. lcdwe - )t whdx 10 ns romcs (0 : 3) (output) lcdwe (output) data (0 : 15) (output) invalid add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) t avel t avwl t whwl t whax t wlwh t avwh t avav t dvwh t whdx t wheh t elwl
m pd30101 81 [memo]
m pd30101 82 (11) system bus parameter (lcdrdy) (1/2) parameter symbol condition min. max. unit pcmclk low-level pulse width t pclkl 45 ns pcmclk high-level pulse width t pclkh 45 ns address (add (0:20)) setup time (vs. pcmclk )t avck 15 ns address (add (0:20)) setup time (vs. command signal ) note 1, 2 t avcl 60n C 28 ns address hold time (vs. command signal - ) note 1 t chav 25 ns command signal setup time (vs. pcmclk - ) note 1 t clck 15 ns command signal low-level width note 1, 2 t clch 120n C 28 ns command signal recovery time note 1 t chcl 100 ns ldcrdy sampling time t clr 0ns command signal output hold time (vs. cdrdy - ) note 1, 2 t rhch 60n 120n + 31 ns lcdrdy hold time (vs. command signal - ) note 1 t chrl 0ns data output setup time (vs. command signal ) note 1 t dvcl 0ns data output hold time (vs. command signal - ) note 1 t chdv 25 ns data input setup time (vs. command signal - ) note 1 t ds 20 ns data input hold time (vs. command signal - ) note 1 t dh 15 ns notes 1. with the v r 4101, the memw, memr, iow, and ior pins are called the command signals for the system bus interface. 2. set the value of n by using the wisa (0:2) bits of the bcuspeedreg register. wisa2 wisa1 wisa0 n 0008 0017 0106 0115 1004 1013 110 111
m pd30101 83 (11) system bus parameter (lcdrdy) (2/2) shb (output) memr/memw, ior/iow (output) lcdrdy (input) invalid add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) t avcl t avck invalid invalid pcmclk note pcmclk note t pclkl t pclkh t clr t clck t dvcl t rhch t chcl t chdv t chav t chrl t dh t ds zws (input) data (0 : 15) (output) data (0 : 15) (input) t clch when wisa (0 : 2) = 101b note pcmclk indicates that there are two possible relationships between pcmclk and other system bus interface signals. remark the dotted line indicates a high-impedance state.
m pd30101 84 (12) system bus parameter (zws) (1/2) parameter symbol condition min. max. unit address (add (0:20)) setup time (vs. pcmclk )t avck 15 ns address (add (0:20)) setup time (vs. command signal ) note 1, 2 t avcl 60n C 28 ns address hold time (vs. command signal - ) note 1 t chav 25 ns command signal setup time (vs. pcmclk - ) note 1 t clck 15 ns command signal recovery time note 1 t chcl 100 ns data output setup time (vs. command signal ) note 1 t dvcl 0ns data output hold time (vs. command signal - ) note 1 t chdv 25 ns data input setup time (vs. command signal - ) note 1 t ds 20 ns data input hold time (vs. command signal - ) note 1 t dh 15 ns command signal low-level width note 1, 2 t clch 60n C 28 ns zws delay time (vs. command signal ) note 1, 2 t clzl 60n C 111 ns zws hold time (vs. command signal - ) note 1 t chzh 0ns notes 1. with the v r 4101, the memw, memr, iow, and ior pins are called the command signals for the system bus interface. 2. set the value of n by using the wisa (0:2) bits of the bcuspeedreg register. wisa2 wisa1 wisa0 n 0008 0017 0106 0115 1004 1013 110 111
m pd30101 85 (12) system bus parameter (zws) (2/2) shb (output) memr/memw, ior/iow (output) lcdrdy (input) invalid add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) t avcl t avck invalid pcmclk note pcmclk note t clck t dvcl t clch t chcl t chdv t chav t dh t ds zws (input) data (0 : 15) (output) data (0 : 15) (input) invalid t clzl t chzh note pcmclk indicates that there are two possible relationships between pcmclk and other system bus interface signals. remark the dotted line indicates a high-impedance state.
m pd30101 86 (13) lcd interface parameter parameter symbol condition min. max. unit address setup time (vs. command signal ) note 1 t as 15 ns address hold time (vs. command signal - ) note 1 t ah 0ns command signal recovery time note 1 t ry 30 ns lcdrdy sampling time t clr 0ns command signal output hold time (vs. lcdrdy - ) note 1, 2 t rhch 60n 60n + 151 ns lcdrdy hold time (vs. command signal - ) note 1 t ryz 0ns data output setup time (vs. command signal - ) note 1, 2 t dvch 60n + 120 ns data output hold time (vs. command signal - ) note 1 t chdv 25 ns data input setup time (vs. command signal - ) note 1 t ds 20 ns data input hold time (vs. command signal - ) note 1 t dh 15 ns notes 1. with the v r 4101, the lcdoe and lcdwe pin are called the command signals for the lcd interface. 2. set the value of n by using the wlcda (0:1) bits of the bcuspeedreg register. wlcda1 wlcda0 n 008 016 104 112 shb (output) lcdcs (output) lcdwe, lcdoe (output) add (0 : 8), add (19 : 20) (output) add (9 : 18) (output) t ah invalid t as lcdrdy (input) data (0 : 15) (output) data (0 : 15) (input) invalid invalid t clr t rhch t dvch t chdv t ry t ryz t ds t dh remark the dotted line indicates a high-impedance state.
m pd30101 87 (14) a/d controller interface parameter parameter symbol condition min. max. unit output delay (vs. adclk - )t d-adcsb 400 ns output delay (vs. adclk )t d-adsout 300 ns input setup time (vs. adclk - )t s-piu 80 ns input hold time (vs. adclk - )t h-piu 200 ns adclk adcs, pencont (0 : 4) (output) adsout (output) adeoc, adin, penchgint ( output ) t d-adsout t d-adcsb t h-piu t s-piu (15) audio output interface parameter parameter symbol condition min. max. unit audiout (0:1) output pulse width note 1 t buz buzz mode 30.15l C 1 30.16l + 1 m s audiout (0:1) output high-level width note 2 t pwmh pwm mode 60m C 31 60m + 31 ns audiout (0:1) output low level note 3 t pwml pwm mode 60n C 31 60n + 31 ns notes 1. l is the value set to the aiucount0reg register in the buzz mode. 2. m is the value set to the aiucount0reg register in the pwm mode, or the count data of the high- level pulse (first) prepared for dma transfer. 3. n is the value set to the aiucount1reg register in the pwm mode, or the count data of the low- level pulse (second) prepared for dma transfer. audiout (0 : 1) (output) audiout (0 : 1) (output) in pwm mode in buzz mode t buz t pwmh t buz t pwml
m pd30101 88 (16) keyboard interface parameter parameter symbol condition min. max. unit high-level width note 1 t scan 30k C 1 30.16k + 1 m s idle time (kscann ? kscan (n+1) - ) note 2 t kwait 30l C 1 30.16l + 1 m s key scan interval time note 3 t ki 30m C 1 30.16m + 1 m s key input setup time (vs. kscann - ) note 4 t ks 30n C 1 m s key input hold time (vs. kscann )t kh 0 m s notes 1. k: sum of the values set to the t1count (0:4) bits and t2count (0:4) bits of the kiuwksreg register 2. l: value set to the t3count (0:4) bits of the kiuwksreg register 3. m: value set to kiuwkireg register 4. n: value set to the t1count (0:4) bits of the kiuwksreg register (a) keyboard scan parameter 1 hi-z hi-z hi-z t scan t kwait kscann (output) kscan (n + 1) (output) remark n = 0 to 7 (b) keyboard scan parameter 2 hi-z t kwait kscan0 (output) kscan7 ( output ) hi-z hi-z hi-z hi-z hi-z kscan1 (output) kscan2 (output) hi-z hi-z t kwait +t ki t kwait (c) keyboard parameter hi-z t ks kscann (output) kport (0 : 7) (input) hi-z t kh remark n = 0 to 7
m pd30101 89 (17) serial interface parameter parameter symbol condition min. max. unit txd output pulse width note t txd n C 1 n + 1 m s rxd input pulse width note t rxd (9/16)n m s irdout high-level output pulse width note t irdout (3/16)n C 1 (3/16)n + 1 m s irdin input pulse width t irdin 1 m s note n: transfer rate of baud rate per bit set to the bpr0 (0:2) bits of the siubaudselreg register bpr02 bpr01 bpr00 baud rate (bps) n ( m s) 1 1 1 115200 8.68 1 1 0 57600 17.36 1 0 1 38400 26.04 1 0 0 19200 52.03 0 1 1 9600 104.16 0 1 0 4800 208.33 0 0 1 2400 416.66 0 0 0 1200 833.33 txd (output) t txd rxd (input) irdout (output) irdin (input) t rxd t irdout t irdin
m pd30101 90 (18) debug serial interface parameter parameter symbol condition min. max. unit ddout output pulse width note t ddout n C 1 n + 1 m s ddin input pulse width note t ddin (9/16)n m s note n: transfer rate of baud rate per bit set to the bpr0 (0:2) bits of the bprm0reg register bpr02 bpr01 bpr00 baud rate (bps) n ( m s) 1 1 1 115200 8.68 1 1 0 57600 17.36 1 0 1 38400 26.04 1 0 0 19200 52.03 0 1 1 9600 104.16 0 1 0 4800 208.33 0 0 1 2400 416.66 0 0 0 1200 833.33 ddin (input) ddout (output) t ddin t ddout
m pd30101 91 load coefficient (delay time per load capacitance) parameter symbol condition rating unit min. max. load coefficient cld 5 ns/20 pf
m pd30101 92 21. package drawing 160 pin plastic lqfp (fine pitch) ( 24) note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. item millimeters inches f g 2.25 2.25 0.089 0.089 a 26.0?.2 1.024 +0.008 ?.009 b c 24.0?.2 24.0?.2 0.945?.008 0.945?.008 d 26.0?.2 1.024 h 0.22 0.009?.002 i 0.10 0.004 s 1.7 max. 0.067 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.4?.1 0.055?.004 q 0.125?.075 0.005?.003 +0.05 ?.04 +0.008 ?.009 j 0.5 (t.p.) 0.020 (t.p.) s160gm-50-8ed-2 +0.055 ?.045 +7 ? r3 3 +7 ? 120 121 160 140 41 80 81 a b m c d detail of lead end s q r f g hi j k m n p l
m pd30101 93 22. recommended soldering conditions this m pd30101 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 22-1. surface mounting type soldering conditions soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-103-2 number of times: twice max., time limit: 3 days note (thereafter 10 to 72 hours prebaking required at 125 c) products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). vps package peak temperature: 215 c, duration: 25 to 40 sec. max. (at 200 c or vp15-103-2 above), number of times: twice max., time limit: 3 days note (thereafter 10 to 72 hours prebaking required at 125 c) products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). partial heating pin temperature: 300 c max., duration: 3 sec. max. (per device side) note for the storage period after dry-pack decapsulation, storage conditions are max. 25c, 65 % rh. caution use of more than one soldering method should be avoided (except in the case of partial heating).
m pd30101 94 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd30101 95 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd30101 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4100, v r 4101, v r 4200, v r 4400, and v r series are trademarks of nec corp. this product employs technology which is restricted by the export control regulations of the united states of america. permission of the united states government might be required in case of exporting this product or products in which this product is installed.

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