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preliminary data sheet v850e/dl3, v850e/dj3 32-bit single-chip microcontrollers hardware pd70f3420, pd703420, pd70f3421, pd703421, pd70f3422, pd703422, pd70f3423, pd70f3424, pd70f3425, pd70f3426, pd70f3427 document no. ease-sp-8007-v1.1 ? nec electronics 2007
2 preliminary data sheet ease-sp-8007-v1.1 table of contents chapter 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chapter 2 pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pinconfiguration pd70f3427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pinconfiguration pd70f3426, pd70f3425, pd70f3424 . . . . . . . . . . . . . . . . . . . . 12 2.3 pinconfiguration pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 pin group information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 chapter 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 chapter 4 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 requirements for external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 capacitance connected to regcx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 sub-oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 peripheral pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6 spread spectrum pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 i/o capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 chapter 5 operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 cpu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 chapter 6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 general dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 pin group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 pin group 2: reset and flmd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 pin group 2: p07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.5 adc input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6 pin group 3: gpio and lcd bus interfa ce (pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd703423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.7 pin group 3: gpio and lcd bus and external memory interface (pd70f3427) . . 38 6.8 pin group 6: external memory interface (pd70f3427) . . . . . . . . . . . . . . . . . . . . . . . 39 6.9 lcd common and segment lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.10 stepper motor driver io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11 current limit function of i/o buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.12 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 chapter 7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.1 ac test input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 ac test load condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.4 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5 peripheral function characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.5.1 timer p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.5.2 timer g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.5.3 uarta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 7.5.4 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.5.5 csi b (high voltage operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.6 csi b (low voltage operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3 preliminary data sheet ease-sp-8007-v1.1 7.5.7 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 lcd bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.7 external memory access (pd70f3427) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 chapter 8 analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.1 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 power on clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 8.3 voltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.1 basic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.2 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.3 special conditions for end-of-line programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.4 serial write operation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 chapter 10 special conditions for device operation at extended operating temperature range (ta = -40c ... +105c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 chapter 11 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.1 package drawing pd70f3427gd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2 package drawing pd70f3426gj, pd70f3425gj, pd70f3424gj, pd70f3423gj, pd70f3422gj, pd703422gj, pd70f3421gj, pd703421gj, pd70f3420gj, pd703420gj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4 preliminary data sheet ease-sp-8007-v1.1 table of tables table 1-1: dj3 family overview ................................................................................................. ...... 8 table 3-1: absolute maximum ratings ............................................................................................ 15 table 3-2: absolute maximum ratings currents .............................................................................. 17 table 4-1: external capacitance requirement ............................................................................... 19 table 4-2: main oscillator characteristics ..................................................................................... .20 table 4-3: sub oscillator characteristics ...................................................................................... .22 table 4-4: peripheral pll characteristics ...................................................................................... 24 table 4-5: spread spectrum pll characteristics .......................................................................... 24 table 4-6: ring oscillator characteristics ..................................................................................... .25 table 4-7: i/o characteristics ................................................................................................. ........ 25 table 5-1: cpu clock frequencies ............................................................................................... .26 table 5-2: peripheral clock frequencies ....................................................................................... 2 7 table 6-1: dc general specs .................................................................................................... ..... 28 table 6-2: pin group 1 normal operating range .......................................................................... 29 table 6-3: pin group 1 low voltage operating range .................................................................. 30 table 6-4: pin p05 pulldown resistor ........................................................................................... ... 31 table 6-5: pin group 2 (except p07) normal operating range ..................................................... 32 table 6-6: p07 normal voltage operating range .......................................................................... 33 table 6-7: p07 low voltage operating range ............................................................................... 34 table 6-8: pin group 5 normal operating range .......................................................................... 35 table 6-9: pin group 3 normal operating range .......................................................................... 36 table 6-10: pin group 3 low voltage operating range .................................................................. 37 table 6-11: pin group 3 normal operating range .......................................................................... 38 table 6-12: pin group 3 normal operating range .......................................................................... 39 table 6-13: dc characteristics lcd common and segment lines ................................................. 40 table 6-14: dc characteristics stepper motor driver input normal voltage operation ................... 41 table 6-15: dc characteristics stepper motor driver input low voltage operation ........................ 42 table 6-16: dc characteristics stepper motor driver output normal operation ............................. 43 table 6-17: dc characteristics stepper motor driver output low voltage operation ..................... 44 table 6-18: dc characteristics of current limiting function .......................................................... 46 table 6-19: dc characteristics supply current pd70f3426 ....................................................... 47 table 6-20: dc characteristics supply current pd70f3427 ........................................................ 49 table 6-21: dc characteristics supply current pd70f3425, pd70f3424 ................................. 51 table 6-22: dc characteristics supply current pd70f3423, pd70f3422, pd70f3421, pd70f3420 ................................................................................................................. 53 table 6-23: dc characteristics supply current pd703422, pd703421, pd703420 ................. 55 table 6-24: operational conditions for measurement ....................................................................... 57 table 7-1: reset ac characteristics ............................................................................................ .. 59 table 7-2: interrupt ac characteristics ........................................................................................ .. 60 table 7-3: timer p ac characteristics ......................................................................................... .61 table 7-4: timer g input characteristics ...................................................................................... .62 table 7-5: uarta ac characteristics ............................................................................................ 62 table 7-6: can ac characteristics .............................................................................................. .. 62 table 7-7: csib master mode ac characteristics with digital filter .............................................. 63 table 7-8: csib master mode ac characteristics without digital filter ......................................... 63 table 7-9: csib slave mode ac characteristics with digital filter ................................................ 64 table 7-10: csib slave mode ac characteristics without digital filter ........................................... 64 table 7-11: csib master mode ac characteristics with digital filter .............................................. 66 table 7-12: csib master mode ac characteristics without digital filter ......................................... 66 table 7-13: csib slave mode ac characteristics with digital filter ................................................ 67 table 7-14: csib slave mode ac characteristics without digital filter ........................................... 67 table 7-15: i2c ac characteristics ............................................................................................. ...... 69 table 7-16: lcd bus interface ac characteristics .......................................................................... 71 table 7-17: external memory access asynchronous read timing .................................................. 75 table 7-18: external memory access asynchronous write timing .................................................. 77
5 preliminary data sheet ease-sp-8007-v1.1 table 8-1: a/d converter characteristics ....................................................................................... 79 table 8-2: power on clear characteristics .................................................................................... 80 table 8-3: voltage comparator characteristics .............................................................................. 81 table 9-1: memory operation characteristics ................................................................................ 82 table 9-2: flash memory selfprogramming characteristics ........................................................... 83 table 9-3: flash memory end-of-line programming characteristics (pg-fp4: csi) .................... 84 table 9-4: flash memory end-of-line programming characteristics (pg-fp4: uart) ................. 85 table 9-5: flash memory end-of-line programming characteristics (flash-selfprogramming) .... 86 table 9-6: flash memory ac characteristics ................................................................................. 87 table 10-1: absolute maximum ratings currents 105c (pd70f3427) ........................................... 89 table 10-2: absolute maximum ratings currents 105c (pd70f3426) ........................................... 90 table 10-3: absolute maximum ratings currents 105c (pd70f3425) ........................................... 91 table 10-4: absolute maximum ratings currents 105c (pd70f3424) ........................................... 92
6 preliminary data sheet ease-sp-8007-v1.1 table of figures figure 2-1: pin configuration pd70f3427 .................................................................................. 11 figure 2-2: pin configuration pd70f3426, pd70f3425, pd70f3424 .................................. 12 figure 4-1: recommended main oscillator circuit ....................................................................... 20 figure 4-2: recommended sub oscillator circuit ......................................................................... 22 figure 6-1: current limit function principle ................................................................................. 45 figure 7-1: ac test input/output waveform ................................................................................ 58 figure 7-2: ac test load condition ............................................................................................. 58 figure 7-3: reset timing ....................................................................................................... ....... 59 figure 7-4: interrupt timing ................................................................................................... ....... 60 figure 7-5: timer p input timing ............................................................................................... ... 61 figure 7-6: csi master/slave mode timing .................................................................................. 65 figure 7-7: csi master/slave mode timing inverted clock .......................................................... 65 figure 7-8: csi master/slave mode timing .................................................................................. 68 figure 7-9: i2c timing ......................................................................................................... ......... 70 figure 7-10: lcd bus interface motorola mode timing ................................................................. 72 figure 7-11: lcd bus interface intel mode timing ......................................................................... 72 figure 7-12: lcd bus interface motorola mode turnaround timing .............................................. 73 figure 7-13: lcd bus interface intel mode turnaround timing ..................................................... 73 figure 7-14: sram asynchronous read timing ............................................................................ 76 figure 7-15: sram asynchronous write timing ............................................................................ 78 figure 9-1: flash memory timing ................................................................................................ .87
7 chapter 1 overview preliminary data sheet ease-sp-8007-v1.1 chapter 1 overview the v850e/dj3/dl3 is a product in necel?s v850 family of single-chip microcontrollers designed for automotive applications. 1.1 general the v850e/dj3/dl3 single-chip microcontroller, is a member of necel's v850 32-bit risc family, which match the performance gains attainable with risc-based controllers to the needs of embedded control applications. the v850 cpu offers easy pipeline handling and programming, resulting in com- pact code size comparable to 16-bit cisc cpus. the v850e/dj3/dl3 provides an excellent combination of general purpose peripheral functions, like serial communication interfaces (uart, clocked si), timers and measurement inputs (a/d converter), with dedicated can network support. control and driver for 6 stepper motors are included. the device offers power-saving modes to manage the power consumption effectively under varying conditions. thus equipped, the v850e/dj3/dl3 is ideally suited for automotive applications, like dashboard or body. it is also an excellent choice for other applications where a combination of sophisticated periph- eral functions and can network support is required. this specification covers the following devices of the family: family code part number internal flash internal ram lcd peripherals dl3 pd70f3427gd 1024 kbyte 60 kbytes lcd i/f full set dj3 pd70f3426gj 2048 kbyte 84 kbytes lcd i/f full set dj3 pd70f3425gj 1024 kbyte 32 kbytes lcd i/f full set dj3 pd70f3424gj 512 kbyte 24 kbytes lcd i/f full set dj3 pd70f3423gj 512 kbyte 20 kbytes lcd i/f, lcd c/d reduced set dj3 pd70f3422gj 384 kbyte 16 kbytes lcd i/f, lcd c/d reduced set dj3 pd703422gj 384 kbyte rom 16 kbytes lcd i/f, lcd c/d reduced set dj3 pd70f3421gj 256 kbyte 12 kbytes lcd i/f, lcd c/d reduced set dj3 pd703421gj 256 kbyte rom 12 kbytes lcd i/f, lcd c/d reduced set dj3 pd70f3420gj 128 kbyte 6 kbytes lcd i/f, lcd c/d reduced set dj3 pd703420gj 128kbyte rom 6 kbytes lcd i/f, lcd c/d reduced set
8 chapter 1 overview preliminary data sheet ease-sp-8007-v1.1 the following table gives a more detailed overview of the different derivates and their major features. table 1-1: dj3 family overview (1/2) series name v850e/dl3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 part number udp70f3427 udp70f3426 udp70f3425 udp70f3424 udp70f3423 udp70f3422 udp703422 upd70f3421 upd703421 udp70f3420 udp703420 technology mf2 (flash) mf2 (rom) mf2 (flash) mf2 (rom) mf2 (flash) mf2 (rom) internal memory flash 1mb 2mb note1 1mb 512kb 384kb none 256kb none 128kb none rom none 384kb none 256kb none 128kb ram 60k 84k note2 32kb 24kb 20kb 16kb 12kb 6kb dma 4ch operating clock main (internal) 64mhz typ. 32mhz typ. 24mhz typ. 32mhz typ. 24mhz typ. 32mhz typ. 24mhz typ. ring-osc 240khz typ. subclock 32khz typ. i/o ports 101 98 input ports 16 a/d converter 16 ch 12 ch timers tmz 10 ch 6 ch tmp 4 ch tmg 3 ch 2 ch wdt provided watch provided watch calibration provided serial interfaces afcan 2 ch uarta 2 ch serial interfaces csib 3 ch 2 ch iic 2 ch
9 chapter 1 overview preliminary data sheet ease-sp-8007-v1.1 interrupts external 8 7 internal 91 76 nmi 2 ch other functions rom- correction 8ch (dbtrap) poc provided voltage comparator 2 ch clock supervision provided sound generator 1 ch stepper motor c/d 6 ch lcd c/d none 40 x 4 lcd i/f provided auxilliary fre- quency output provided on-chip debug provided external mem.-i/f provided none operating voltage 3.2v to 5.5v for core functions, adc and steppermotor c/d, 3.0v to 5.5v for all other i/o full operation in range from 4.0v to 5.5v due to poc function (see chapter 8.2 on page 80) package 208-pin qfp 144-pin qfp table 1-1: dj3 family overview (2/2) series name v850e/dl3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 v850e/dj3 part number udp70f3427 udp70f3426 udp70f3425 udp70f3424 udp70f3423 udp70f3422 udp703422 upd70f3421 upd703421 udp70f3420 udp703420
10 chapter 1 overview preliminary data sheet ease-sp-8007-v1.1 notes: 1. for the dj3 derivative pd70f3426, the upper 1mb of the flash memory is connected to the internal system bus (vsb). in case performing consecutive accesses to that part of the flash-memory, a 32-bit data access requires two cycles. 2. for the dj3 derivative pd70f3426, the upper 24kb of the internal ram is connected to the internal system bus (vsb). in case performing consecutive accesses to that part of the internal ram, a 32-bit data access requires two cycles.
11 chapter 2 pinout information preliminary data sheet ease-sp-8007-v1.1 chapter 2 pinout information 2.1 pinconfiguration pd70f3427 - pd70f3427gj figure 2-1: pin configuration pd70f3427 v850e/dj3 (64 mhz) v 8 5 0 e / d j 3 ( 6 4 m h z ) pd70f3427gd p d 7 0 f 3 4 2 7 g d 28 p134/sm41/tog11 93 a4 193 p715/ain15 39 p92/dbd2/d26 101 mvdd53 51 p86/txda0/d16 74 mvdd51 36 dvdd50 189 xt2 165 bvdd51 11 p115/sm22 123 p02/intp2 159 p34/tog21/top01 62 regc0 48 dvss51 118 a22 110 a16 14 p120/sm51 27 smvss51 138 p101/top01 65 cs4 67 cs1 84 d13 55 be0 98 vdd51 156 p25/tig12 103 a9 41 p90/dbd0/d24 169 p64/tip20/scl0 144 p57/ctxd1/txda1 82 d11 75 mvss51 5 p111/sm12 167 p62/tip10/tig25/top10 46 p33/rxda1/d19 111 a17 33 p96/dbd6/d30 136 p103/top21 31 p137/sm44/tog14 68 cs0 203 p75/ain5 37 dvss50 34 p95/dbd5/d29 200 p78/ain8 145 p46/crxd0 78 d7 16 p122/sm53 80 d9 204 p74/ain4 8 smvdd50 15 p121/sm52 94 a5 177 p82/sckb2 186 x2 199 p79/ain9 40 p91/dbd1/d25 26 smvdd51 191 vcmp0 196 p712/ain12 54 be1 172 p67/tip31/top31 206 p72/ain2 30 p136/sm43/tog13 148 p30/txda0/sda1 76 d5 182 regc2 58 p140/bclk 141 p41/sob0 154 p23/tig04 164 p61/tip01/tig21 97 a8 117 a21 171 p66/tip21 91 a2 202 p76/ain6 61 vdd50 131 p84 121 p04/intp4 192 vcmp1 100 vss51 122 p03/intp3 64 wait 195 p713/ain13 1 avref 13 p117/sm24 90 a1 166 bvss51 152 p21/tig02/scl1 162 p37/tig24/tog24/top11 18 p124/sm61 106 a12 180 p85/foutclk 4 p110/sm11 161 p36/tig23/tog23/top31 20 p126/sm63 114 mvss54 163 p60/tip00 63 vss50 25 p133/sm34/tog04 50 p87/rxda0/d17 89 a0 7 p113/sm14 70 d1 10 p114/sm21 81 d10 115 a19 6 p112/sm13 92 a3 88 d15 86 mvdd52 130 p52/ddi 126 p05/drst 49 p32/txda1/d18 133 p51/sgo 140 p40/sib0 119 a23 125 p00/intp0/nmi 57 rd 181 vdd52 201 p77/ain7 104 a10 134 bvdd50 29 p135/sm42/tog12 73 d4 132 p50/intp7/foutclk/sgo a 108 a14 170 p65/tip30/top30/sda0 83 d12 197 p711/ain11 179 p80/sib2 71 d2 43 p106/sob0/d22 85 d14 198 p710/ain10 35 p94/dbd4/d28 173 p45/sckb1 9 smvss50 102 mvss53 150 p17/scl0/crxd2 176 p83 21 p127/sm64 139 p100/tip00/top00 187 reset 113 mvdd54 168 p63/tip11/top11 112 a18 194 p714/ain14 175 p43/sib1 143 p56/crxd1/rxda1 109 a15 59 mvdd50 99 regc1 32 p97/dbd7/d31 19 p125/sm62 53 p141/be2 69 d0 116 a20 142 p42/sckb0 95 a6 188 xt1 105 a11 79 d8 24 p132/sm33/tog03 190 p07/intp6/vcmpo0/flmd1 44 p105/sib0/dbwr/d21 149 p16/sda0/ctxd2 127 p55/dms 137 p102/top20 47 dvdd51 107 a13 42 p107/sckb0/d23 120 p06/intp5 155 p24/tig11 183 vss52 12 p116/sm23 158 p27/tig14 157 p26/tig13 23 p131/sm32/tog02 207 p71/ain1 72 d3 151 p20/sda1 96 a7 160 p35/tig22/tog22/top21 174 p44/sob1 60 mvss50 124 p01/intp1 87 mvss52 45 p104/dbrd/d20 56 wr 178 p81/sob2 128 p54/dck 135 bvss50 205 p73/ain3 17 p123/sm54 147 p31/rxda0/scl1 185 x1 66 cs3 77 d6 52 p142/be3 22 p130/tig01/sm31/tog01 129 p53/ddo 3 avss 38 p93/dbd3/d27 184 flmd0 2 avdd 153 p22/tig03 146 p47/ctxd0 208 p70/ain0
12 chapter 2 pinout information preliminary data sheet ease-sp-8007-v1.1 2.2 pinconfiguration pd70f3426, pd70f3425, pd70f3424 - pd70f3426gj, - pd70f3425gj, - pd70f3424gj figure 2-2: pin configuration pd70f3426, pd70f3425, pd70f3424 55 p40/sib0 63 p30/txda0/sda1 135 p79/ain9 85 p64/tip20 100 p33/rxda1 54 p100/tip00/top00 33 p04/intp4 1 avref 70 p21/tig02/scl1 64 vdd51 45 vss50 75 p26/tig13 104 p106 9 smvss50 16 p122/sm53 21 p127/sm64 109 p92/dbd2 30 p136/sm43/tog13 53 p101/top01 47 p50/intp7/fout/sgo a 115 dvdd50 114 p97/dbd7 51 p103/top21 90 bvss51 40 p54/dck 88 p67/tip31/top31 128 vcmp1 77 p34/tog21/top01 126 p07/intp6/vcmpo0/flmd1 71 p22/tig03 96 p81/sob2 5 p111/sm12 57 p42/sckb0 61 p47/ctxd0 12 p116/sm23 19 p125/sm62 24 p132/sm33/tog03 112 p95/dbd5 62 p31/rxda0/scl1 84 p63/tip11/top11 102 p32/txda1 80 p37/tig24/tog24/top30 60 p46/crxd0 34 p03/intp3 69 p20/sda1 43 vdd50 26 smvdd51 74 p25/tig12 105 p105/sib0/dbwr 41 p53/ddo 124 xt1 15 p121/sm52 20 p126/sm63 108 p91/dbd1 29 p135/sm42/tog12 89 bvdd51 144 p70/ain0 50 bvss50 113 p96/dbd6 52 p102/top20 82 p61/tip01/tig21 134 p710/ain10 125 xt2 87 p66/tip21 127 vcmp0 36 p01/intp1 32 p06/intp5 3 avss 59 p57/txda1/ctxd1 143 p71/ain1 133 p711/ain11 119 vss52 97 p80/sib2 4 p110/sm11 123 reset 11 p115/sm22 18 p124/sm61 23 p131/sm32/tog02 111 p94/dbd4 142 p72/ain2 132 p712/ain12 98 p85/fout 83 p62/tip10/tig25/top10 42 p52/ddi 99 p87/rxda0 79 p36/tig23/tog23/top31 141 p73/ain3 35 p02/intp2 68 p17/scl0 2 avdd 131 p713/ain13 118 regc2 8 smvdd50 106 p104/dbrd 73 p24/tig11 94 p83 7 p113/sm14 14 p120/sm51 140 p74/ain4 107 p90/dbd0 28 p134/sm41/tog11 130 p714/ain14 58 p56/crxd1 121 x1 49 bvdd50 44 regc0 46 p84 81 p60/tig20 91 p45/sckb1 86 p65/tip30/sda0/top30 37 p00/intp0/nmi 139 p75/ain5 129 p715/ain15 38 p05/drst 122 x2 117 vdd52 66 vss51 76 p27/tig14 103 p107/sckb0 27 smvss51 10 p114/sm21 48 p51/sgo 17 p123/sm54 138 p76/ain6 92 p44/sob1 22 p130/tig01/sm31/tog01 110 p93/dbd3 31 p137/sm44/tog14 116 dvss50 56 p41/sob0 101 p86/txda0 137 p77/ain7 120 flmd0 78 p35/tig22/tog22/top21 67 p16/sda0 65 regc1 93 p43/sib1 39 p55/dms 72 p23/tig04 95 p82/sckb2 6 p112/sm13 136 p78/ain8 13 p117/sm24 25 p133/sm34/tog04 v850e/dj3 (64 mhz) v 8 5 0 e / d j 3 ( 6 4 m h z ) pd70f3426gj p d 7 0 f 3 4 2 6 g j pd70f3425gj p d 7 0 f 3 4 2 5 g j pd70f3424gj p d 7 0 f 3 4 2 4 g j
13 chapter 2 pinout information preliminary data sheet ease-sp-8007-v1.1 2.3 pinconfiguration pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420 - pd70f3423gj, - pd70f3422gj, - pd703422gj, - pd70f3421gj, - pd703421gj, - pd70f3420gj, - pd703420gj 55 p40/sib0 63 p30/txda0/sda1 135 p79/ain9 85 p64/tip20/seg16 100 p33/rxda1/seg29 54 p100/tip00/top00 33 p04/intp4 1 avref 70 p21/tig02/scl1/seg1 64 vdd51 45 vss50 75 p26/tig13/seg6 104 p106/seg33 9 smvss50 16 p122/sm53 21 p127/sm64 109 p92/seg38 30 p136/sm43/tog13 53 p101/top01 47 p50/fout/sgoa 115 dvdd50 114 p97/com3 51 p103/top21 90 bvss51 40 p54/dck 88 p67/tip31/top31/seg19 128 vcmp1 77 p34/seg8 126 p07/intp6/vcmpo0/flmd1 71 p22/tig03/seg2 96 p81/seg25 5 p111/sm12 57 p42/sckb0 61 p47/ctxd0 12 p116/sm23 19 p125/sm62 24 p132/sm33/tog03 112 p95/com1 62 p31/rxda0/scl1 84 p63/tip11/top11/seg15 102 p32/txda1/seg31 80 p37/seg11 60 p46/crxd0 34 p03/intp3 69 p20/sda1/seg0 43 vdd50 26 smvdd51 74 p25/tig12/seg5 105 p105/sib0/seg34 41 p53/ddo 124 xt1 15 p121/sm52 20 p126/sm63 108 p91/seg37 29 p135/sm42/tog12 89 bvdd51 144 p70/ain0 50 bvss50 113 p96/com2 52 p102/top20 82 p61/tip01/seg13 134 p710/ain10 125 xt2 87 p66/tip21/seg18 127 vcmp0 36 p01/intp1 32 p06/intp5 3 avss 59 p57/txda1/ctxd1 143 p71/ain1 133 p711/ain11 119 vss52 97 p80/seg26 4 p110/sm11 123 reset 11 p115/sm22 18 p124/sm61 23 p131/sm32/tog02 111 p94/com0 142 p72/ain2 132 p712 98 p85/fout/seg27 83 p62/tip10/top10/seg14 42 p52/ddi 99 p87/rxda0/seg28 79 p36/seg10 141 p73/ain3 35 p02/intp2 68 p17/scl0 2 avdd 131 p713 118 regc2 8 smvdd50 106 p104/seg35 73 p24/tig11/seg4 94 p83/seg23 7 p113/sm14 14 p120/sm51 140 p74/ain4 107 p90/seg36 28 p134/sm41/tog11 130 p714 58 p56/crxd1 121 x1 49 bvdd50 44 regc0 46 p84 81 p60/seg12 91 p45/sckb1/seg20 86 p65/tip30/sda0/top30/seg17 37 p00/intp0/nmi 139 p75/ain5 129 p715 38 p05/drst 122 x2 117 vdd52 66 vss51 76 p27/tig14/seg7 103 p107/sckb0/seg32 27 smvss51 10 p114/sm21 48 p51/sgo 17 p123/sm54 138 p76/ain6 92 p44/sob1/seg21 22 p130/tig01/sm31/tog01 110 p93/seg39 31 p137/sm44/tog14 116 dvss50 56 p41/sob0 101 p86/txda0/seg30 137 p77/ain7 120 flmd0 78 p35/seg9 67 p16/sda0 65 regc1 93 p43/sib1/seg22 39 p55/dms 72 p23/tig04/seg3 95 p82/seg24 6 p112/sm13 136 p78/ain8 13 p117/sm24 25 p133/sm34/tog04 v850e/dj3 v 8 5 0 e / d j 3 pd70f3423gj (32 mhz) p d 7 0 f 3 4 2 3 g j ( 3 2 m h z ) pd70f3422gj (32 mhz) p d 7 0 f 3 4 2 2 g j ( 3 2 m h z ) pd703422gj (24 mhz) p d 7 0 3 4 2 2 g j ( 2 4 m h z ) pd70f3421gj (32 mhz) p d 7 0 f 3 4 2 1 g j ( 3 2 m h z ) pd703421gj (24 mhz) p d 7 0 3 4 2 1 g j ( 2 4 m h z ) pd70f3420gj (32 mhz) p d 7 0 f 3 4 2 0 g j ( 3 2 m h z ) pd703420gj (24 mhz) p d 7 0 3 4 2 0 g j ( 2 4 m h z )
14 chapter 2 pinout information preliminary data sheet ease-sp-8007-v1.1 2.4 pin group information pin groups 1x: pins supplied by bv dd5 note1 1a: ( p00-06, p50-55, p84 ) 1b: ( p16-17, p30-31, p40-42, p46-47, p56-57, p100-103 ) 1c: ( p20-27, p34-37, p60-67 ) 1d: ( p43-45, p80-83, p85 ) pin groups 1x: pins supplied by bv dd5 note2 1a: ( p00-06, p50-55, p84 ) 1b: ( p16-17, p30-31, p40-42, p46-47, p56-57, p100-103 ) 1c: ( p20-27, p34-37, p60-61 ) 1d: ( p62-67, p43-45, p80-83, p85 ) pin group 2: pins supplied by v dd5 2: ( reset , flmd0, p07 ) pin group 3 note1 : gpio and lcd bus interface supplied by dv dd5 3: ( p32-33, p86-87, p90-97, p104-107 ) pin group 3 note2 : gpio and lcd bus and external memory interface supplied by dv dd5 3: ( p32-33, p86-87, p90-97, p104-107, p141-142 ) 3a: ( p94-97 ) 3b: ( p90-93 ) 3c: ( p33, p104-107 ) 3d: ( p32, p86-87, p141-142 ) pin group 4: stepper motor outputs supplied by smv dd5 4a: ( p110-117, p120-123 ) 4b: ( p124-127, p130-137 ) pin group 5: adc inputs supplied by av dd 5: ( p70?p715 ) pin group 6 note2 : external memory interface supplied by mv dd5 6: (a0-23, d0-15, cs0-1 , cs3-4 , wait , rd , wr , be0-1 , p140 ) 6a: ( rd , wr , be0-1 , p140 ) 6b: ( cs0-1 , cs3-4 , wait ) 6c: ( d0-4 ) 6d: ( d5-9 ) 6e: ( d10-14 ) 6f: ( d15, a0-3 ) 6g: ( a4-18 ) 6h: ( a9-13 ) 6i: ( a14-18 ) 6j: ( a19-23 ) pin group 8: voltage comparator inputs supplied by av dd 8: ( vcmp0-1) notes: 1. pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420 2. pd70f3427
15 chapter 3 absolute maximum ratings preliminary data sheet ease-sp-8007-v1.1 chapter 3 absolute maximum ratings condition 1: t a = -40 ... +85c, operation modes: run, halt, idle power dissipation: < 1.3w (pd70f3427, pd70f3426, pd70f3425, pd70f3424) < 1.0w (pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420) duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +85c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 3-1: absolute maximum ratings parameter symbol test conditions ratings a unit supply voltage v dd5 -0.5 ~ +6.5 v av dd -0.5 ~ +6.5 v av ref -0.5 ~ +6.5 v bv dd5 -0.5 ~ +6.5 v dv dd5 -0.5 ~ +6.5 v smv dd5 -0.5 ~ +6.5 v mv dd5 b -0.5 ~ +6.5 v av ss -0.5 ~ +0.5 v bv ss5 -0.5 ~ +0.5 v dv ss5 -0.5 ~ +0.5 v smv ss5 -0.5 ~ +0.5 v mv ss5 b -0.5 ~ +0.5 v input voltage group 1 v i1 v i1 < bv dd5 + 0.5 v -0.5 ~ + 6.5 v group 2 v i2 v i2 < v dd5 + 0.5 v -0.5 ~ + 6.5 v group 3 v i3 v i3 < dv dd5 + 0.5 v -0.5 ~ + 6.5 v group 4 v i4 v i4 < smv dd5 + 0.5 v -0.5 ~ + 6.5 v group 5, 8 avref v ia v ia < av dd + 0.5 v -0.5 ~ + 6.5 v group 6 b v i6 v im < mv dd5 + 0.5 v -0.5 ~ + 6.5 v
16 chapter 3 absolute maximum ratings preliminary data sheet ease-sp-8007-v1.1 note: see ?pinout information? on page 11. for pin to group association. v dd5 is the supply voltage for the internal voltage regulators applied to pins v dd5x . v ss5 is the ground for the internal logic applied to pins v ss5x. a vdd is the supply for analog part of the a/d converter. a vss is the ground for the analog part of the a/d converter. bv dd5 is the supply voltage for the i/o buffers applied to pins bv dd5x. bv ss5 is the ground for the i/o buffers applied to pins bv ss5x. dv dd5 is the supply voltage for the i/o buffers that support the lcd bus i/f applied to pins dv dd5x. dv ss5 is the ground for the i/o buffers that support the lcd bus i/f applied to pins dv ss5x. smv dd5 is the supply voltage for the i/o buffers of the stepper motor drivers applied to pins smv dd5x. smv ss5 is the ground for the i/o buffers of the stepper motor drivers applied to pins smv ss5x. mv dd5 is the supply voltage for the i/o buffers of the external memory interface applied to pins mv dd5x. mv ss5 is the ground for the i/o buffers of the external memory interface applied to pins mv ss5x. special c x1, x2, xt1, xt2, regc0-2 v is -0.5 ~ + 3.6 v output voltage v o -0.5 ~ +6.5 v operating temperature (ambient) t opr -40 ~ +85 c storage temperature t stgb -40 ~ +150 c a. currents are average current over the given life time. transient currents are not relevant as long as the average of transient is below the given value. b. pd70f3427 only. c. these pins are for special use only and should not be used for other connections than speci- fied. pins operate with the internal generated core voltage. table 3-1: absolute maximum ratings (continued) parameter symbol test conditions ratings a unit
17 chapter 3 absolute maximum ratings preliminary data sheet ease-sp-8007-v1.1 condition 1: t a = -40 ... +85c, operation modes: run, halt, idle power dissipation: < 1.3w (pd70f3427, pd70f3426, pd70f3425, pd70f3424) < 1.0w (pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420) duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +85c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 3-2: absolute maximum ratings currents parameter symbol test conditions ratings average a ratings peak b unit output current low 1 pin i ol1 groups 1a, 1b, 1c, 1d 30 40 ma all pins i ola1a group 1a 40 60 ma all pins i ola1b group 1b 40 60 ma all pins i ola1ab sum of groups 1a, 1b 60 100 ma all pins i ola1c group 1c 40 60 ma all pins i ola1d group 1d 40 60 ma all pins i ola1cd sum of groups 1c, 1d 60 100 ma 1 pin i ol2 group 3 c groups 3a, 3b, 3c, 3d d 30 40 ma all pins i ola2 40 60 ma all pins i ola2sab sum of groups 3a, 3b d 60 100 ma all pins i ola2scd sum of groups 3c, 3d d 60 100 ma 1 pin i ol3 group 4a 45 55 ma all pins i ola3 200 270 ma 1 pin i ol4 group 4b 45 55 ma all pins i ola4 200 270 ma 1 pin i ol6 groups 6a-6j d 30 40 ma all pins i ola6 60 100 ma
18 chapter 3 absolute maximum ratings preliminary data sheet ease-sp-8007-v1.1 output current high 1 pin i oh1 groups 1a, 1b, 1c, 1d -30 -40 ma all pins i oha1a group 1a -40 -60 ma all pins i oha1b group 1b -40 -60 ma all pins i oha1ab sum of groups 1a, 1b -60 -100 ma all pins i oha1c group 1c -40 -60 ma all pins i oha1d group 1d -40 -60 ma all pins i oha1cd sum of groups 1c, 1d -60 -100 ma 1 pin i oh2 group 3 c groups 3a, 3b, 3c, 3d d -30 -40 ma all pins i oha2 -40 -60 ma all pins i oha2sab sum of groups 3a, 3b d -60 -100 ma all pins i oha2scd sum of groups 3c, 3d d -60 -100 ma 1 pin i oh3 group 4a -45 -55 ma all pins i oha3 -200 -270 ma 1 pin i oh4 group 4b -45 -55 ma all pins i oha4p -200 -270 ma 1 pin i oh6 groups 6a-6j d -30 -40 ma all pins i oha6 -60 -100 ma a. average currents are average current over the given life time. transient currents are not rele- vant as long as the average of transient is below the given value. b. the peak current sets the limit for short term current flows. c. pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420 d. pd70f3427 only table 3-2: absolute maximum ratings currents (continued) parameter symbol test conditions ratings average a ratings peak b unit
19 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 chapter 4 general characteristics 4.1 requirements for external connections the user have to ensure a low resistive connection of all vss pins on the pcb. this specification denotes this as: v ss5 = bv ss5 = dv ss5 = smv ss5 = mv ss5 (pd70f3427) = av ss = 0 v in the further text. the user has to ensure a low resistive connection of all v dd5x pins. the user has to ensure a low resistive connection of all bv dd5x pins. the user has to ensure a low resistive connection of all smv dd5x pins. the user has to ensure a low resistive connection of all dv dd5x pins. the user has to ensure a low resistive connection of all mv dd5x pins (pd70f3427). 4.2 capacitance connected to regcx the device requires to connect capacitors with the following parameters to each of the pins regc0, regc1 and regc2 individually. the pins regc0, regc1, regc2 must not be connected externally. table 4-1: external capacitance requirement parameter symbol test conditions min. typ max. unit capacitance c reg 3.3 4.7 10 f esr of capacitance c esr f0 = 100khz 0.6
20 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 4.3 main oscillator characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 (pd70f3427) = 0 v a ceramic or crystal resonator has to be connected to the main clock input pins as shown in figure 4-1. note: external clock supply not possible in user mode due to oscillator circuit limitation. figure 4-1: recommended main oscillator circuit note: values of c 1 , c 2 and r depend on the used crystal or resonator and must be specified in coop- eration with crystal/resonator manufacturer. cautions: 1. external clock input is prohibited. 2. when using the main system clock oscilla tor, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high cur- rent flows. do not fetch signals from the oscillator. table 4-2: main oscillator characteristics parameter symbol test conditions min. typ. max. unit oscillation stabilization time t ost osc mode 16 a a. t ost depends on the external crystal. value might be improved after evaluation ms x1, x2 oscillator frequency f osc 3.6 4.0 4.4 mhz x2 x1 c2' c1' r1' q u
21 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 remark: this value is valid only for crystal operation.
22 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 4.4 sub-oscillator characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 (pd70f3427) = 0v a crystal resonator has to be connected to the sub clock input pins as shown in figure 4-2. note: external clock supply not possible in user mode due to oscillator circuit limitation. figure 4-2: recommended sub oscillator circuit note: values of c s1 , c s2 and r s depend on the used crystal and must be specified in cooperation with crystal manufacturer. cautions: 1. external clock input is prohibited. 2. when using the sub system clock oscilla tor, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high cur- rent flows. do not fetch signals from the oscillator. table 4-3: sub oscillator characteristics parameter symbol test conditions min. typ max unit xt1,xt2 oscillator frequency f sosc 32 32.768 35 khz sub oscillator stabilization time t sost 5 a a. t sost depends on the external crystal. value might be improved after evaluation s xt2 xt1 c2' c1' q u r1'
23 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 remark: these values are valid only for crystal operation.
24 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 4.5 peripheral pll characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) 4.6 spread spectrum pll characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 4-4: peripheral pll characteristics parameter symbol test conditions min. typ. max. unit pll startup time t pst osc mode 1.2 ms pll output period jitter a a. not tested in production. specified by design. t pj peak to peak 1 ns pll long term jitter a t lj time = 20s 2 ns table 4-5: spread spectrum pll characteristics parameter symbol test conditions min. typ. max. unit sscg startup time t sscgst osc mode 1.2 ms sscg frequency modulation range a a. not tested in production. specified by design. dither osc mode 0 5 % sscg center frequency during dithering a f dither 1.0 * f nominal sscg modulation frequency a f mod scfmc2-0 = b 000 001 010 011 100 b. the typical modulation frequency can be selected by register scfmc. 20 30 40 50 60 khz
25 chapter 4 general characteristics preliminary data sheet ease-sp-8007-v1.1 4.7 ring oscillator characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) 4.8 i/o capacitances t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v ( pd70f3427) table 4-6: ring oscillator characteristics parameter symbol test conditions min. typ max unit ring oscillator frequency f ring 200 240 300 khz ring oscillator stabilization time a a. not tested in production. specified by design. t rost 20 s table 4-7: i/o characteristics parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz unmeasured pins returned to 0 v 10 pf input/output capacitance, all i/o pins except group 4 c io 15 pf input/output capacitance group 4 c io4 30 pf
26 chapter 5 operation conditions preliminary data sheet ease-sp-8007-v1.1 chapter 5 operation conditions 5.1 cpu clock t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 5-1: cpu clock frequencies clock mode prescale operation mode device cpu operation clock frequency [mhz] osc mode n/a all modes all 4 osc mode, pll x8 1/2 16 osc mode, pll x8 n/a pd70f3427, pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd70f3421, pd70f3420 32 osc mode, sscg x12 1/6 all 8 osc mode, sscg x16 1/4 16 osc mode, sscg x12 1/2 24 osc mode, sscg x16 1/2 pd70f3427, pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd70f3421, pd70f3420 32 osc mode, sscg x12 1/1 pd70f3427, pd70f3426, pd70f3425, pd70f3424 48 osc mode, sscg x16 1/1 pd70f3427, pd70f3426, pd70f3425, pd70f3424 64 osc mode, ring osc n/a all 0.2 osc mode, sub osc n/a 0.032
27 chapter 5 operation conditions preliminary data sheet ease-sp-8007-v1.1 5.2 peripheral clock t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 5-2: peripheral clock frequencies clock clock source max unit pclk0 - 1 main osc 4 mhz main osc, pll x 8 16, 8 mhz pclk2 - 15 main osc 4, 2, ... , 1/2048 mhz iiclk main osc 4 mhz main osc, pll x8 32 mhz spclk0 - 1 main osc 4 mhz main osc, pll x8 16, 8 mhz spclk2 - 15 main osc 4, 2 ... 1/2048 mhz fout (clkout) main osc, pll x8 32 mhz main osc, sscg 32 mhz main osc 4 mhz sub-osc 0.032 mhz ring-osc 0.2 mhz lcdclk main osc 4 mhz ring osc 0.2 mhz sub osc 0.032 mhz wtclk main osc 4 mhz ring osc 0.2 mhz sub osc 0.032 mhz wdtclk main osc 4 mhz ring osc 0.2 mhz sub osc 0.032 mhz wctclk main osc 4 mhz pclk1 see pclk1 mhz
28 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 chapter 6 dc characteristics 6.1 general dc characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-1: dc general specs parameter pin group symbol test conditions min. typ max. unit input leakage 1 i li1 0 <= v i <= bv dd5 -1 +1 a 2 i li2 0 <= v i <= v dd52 -1 +1 a 3 i li3 0 <= v i <= dv dd5 -1 +1 a 5 i lia 0 <= v i <= av dd -0.2 +0.2 a 8 i liad 0 <= v i <= av dd -2 +1 a 4 i lis 0 <= v i <= smv dd5 -10 +10 a
29 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.2 pin group 1 pin groups 1x: pins supplied by bv dd5 1a: ( p00-06, p50-55, p84 ) 1b: ( p16-17, p30-31, p40-42, p46-47, p56-57, p100-103 ) 1c: ( p20-27, p34-37, p60-67 ) 1d: ( p43-45, p80-83, p85 ) t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 4.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-2: pin group 1 normal operating range parameter pin mode a pin group symbol test conditions min. typ max. unit input voltage high schmitt1 1 v ih1 0.7 bv dd5 bv dd5 v schmitt2 p80-85 v ih2 0.8 bv dd5 bv dd5 v cmos1 1 v ih3 0.7 bv dd5 bv dd5 v cmos2 p80-85 v ih4 0.8 bv dd5 bv dd5 v input voltage low schmitt1 1 v il1 0 0.3 bv dd5 v schmitt2 p80-85 v il2 0 0.4 bv dd5 v cmos1 1 v il3 0 0.3 bv dd5 v cmos2 p80-85 v il4 0 0.4 bv dd5 v input hysteresis b schmitt1 1 v hy1 150 mv schmitt2 p80-85 v hy2 150 mv output voltage high limit1 1 v oh i oh = -2.0 ma bv dd5 - 0.45 v limit2 1 v oh i oh = -5.0 ma bv dd5 - 0.45 v output voltage low limit1 1 v ol i ol = 2.0 ma 0.45 v limit2 1 v ol i ol = 5.0 ma 0.45 v maximum output short circuit current high limit1 1 i ohm1 v oh = 0 v -2 -12 ma limit2 i ohm2 -5 -30 ma maximum output short circuit current low limit1 i olm1 v ol = bv dd5 212ma limit2 i olm2 530ma
30 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 4.0 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) a. cmos1, cmos2, schmitt1 and schmitt2 denote the non-schmitt and the two schmitt trigger input characteristics of the device pins. this characteristic can be selected bitwise by soft- ware. cmos2 and schmitt2 are only available on port p8. limit1 and limit2 denote the two output characteristics with current limit functionality of the device pins. the characteristic can be selected bitwise by software. b. not tested in production. specified by design. table 6-3: pin group 1 low voltage operating range parameter pin mode a pin group symbol test conditions min. typ max. unit input voltage high schmitt1 1 v ih1 0.7 bv dd5 bv dd5 v schmitt2 p80-85 v ih2 0.8 bv dd5 bv dd5 v cmos1 1 v ih3 0.7 bv dd5 bv dd5 v cmos2 p80-85 v ih4 0.8 bv dd5 bv dd5 v input voltage low schmitt1 1 v il1 0 0.3 bv dd5 v schmitt2 p80-85 v il2 0 0.35 bv dd5 v cmos1 1 v il3 0 0.3 bv dd5 v cmos2 p80-85 v il4 0 0.4 bv dd5 v input hysteresis b schmitt1 1 v hy1 100 mv schmitt2 p80-85 v hy2 100 mv output voltage high limit1 1 v oh i oh = -1.0 ma bv dd5 - 0.45 v limit2 1 v oh i oh = -2.0 ma bv dd5 - 0.45 v output voltage low limit1 1 v ol i ol = 1.0 ma 0.45 v limit2 1 v ol i ol = 2.0 ma 0.45 v maximum output short circuit current high limit1 1 i ohm1 v oh = 0 v -1 ma limit2 i ohm2 -2 ma maximum output short circuit current low limit1 i olm1 v ol = bv dd5 1ma limit2 i olm2 2ma
31 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) a. cmos1, cmos2, schmitt1 and schmitt2 denote the non-schmitt and the two schmitt trigger input characteristics of the device pins. this characteristic can be selected bitwise by soft- ware. cmos2 and schmitt2 are only available on port p8. limit1 and limit2 denote the two output characteristics with current limit functionality of the device pins. the characteristic can be selected bitwise by software. b. not tested in production. specified by design. table 6-4: pin p05 pulldown resistor parameter pin mode pin group symbol test conditions min. typ max. unit pull down resistor p05 v pd 14 28 56 k
32 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.3 pin group 2: reset and flmd0 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-5: pin group 2 (except p07) normal operating range parameter pin mode pin group symbol test conditions min. typ max. unit input voltage high schmitt1 2 v ih1 0.7 v dd52 v dd52 v input voltage low schmitt1 2 v il1 0 0.3 v dd52 v
33 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.4 pin group 2: p07 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 4.0 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-6: p07 normal voltage operating range parameter pin mode a a. cmos1 and schmitt1 denote the non-schmitt trigger and the schmitt trigger input characteris- tics of the device pins. this characteristic can be selected bitwise by software. symbol test conditions min typ max unit input voltage high schmitt1 v ih1 0.7 v dd52 v dd52 v cmos1 v ih3 0.7 v dd52 v dd52 v input voltage low schmitt1 v il1 0 0.3 v dd52 v cmos1 v il3 0 0.3 v dd52 v input voltage hys- teresis b b. not tested in production. specified by design. schmitt1 v hi1 150 mv output voltage high limit1 v oh i oh = -2.0 ma v dd52 - 0.45 v limit2 v oh i oh = -5.0 ma v dd52 - 0.45 v output voltage low limit1 v ol i ol = 2.0 ma 0.45 v limit2 v ol i ol = 5.0 ma 0.45 v maximum output short circuit current high limit1 i ohm1 v oh = 0 v -2 ma limit2 i ohm2 -5 ma maximum output short circuit current low limit1 i olm1 v ol = v dd52 2ma limit2 i olm2 5ma
34 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 4.0 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-7: p07 low voltage operating range parameter pin mode a a. cmos1 and schmitt1 denote the non-schmitt trigger and the schmitt trigger input characteris- tics of the device pins. this characteristic can be selected bitwise by software. symbol test conditions min typ max unit input voltage high schmitt 1 v ih1 0.7 v dd52 v dd52 v cmos1 v ih3 0.7 v dd52 v dd52 v input voltage low schmitt1 v il1 0 0.3 v dd52 v cmos1 v il3 0 0.3 v dd52 v input voltage hys- teresis b b. not tested in production. specified by design. schmitt1 v hi1 100 mv output voltage high limit1 v oh i oh = -1.0 ma v dd52 - 0.45 v limit2 v oh i oh = -2.0 ma v dd52 - 0.45 v output voltage low limit1 v ol i ol = 1.0 ma 0.45 v limit2 v ol i ol = 2.0 ma 0.45 v maximum output short circuit current high limit1 i ohm1 v oh = 0 v -1 ma limit2 i ohm2 -2 ma maximum output short circuit current low limit1 i olm1 v ol = v dd52 1ma limit2 i olm2 2ma
35 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.5 adc input this chapter describes the digital functions available at the pins supplied by avdd. the number of available analog conversion channels differ between the devices. pin group 5: pins supplied by av dd 5: (p70 .. p715) digital buffer function is only available for p70..p715. t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.2 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-8: pin group 5 normal operating range parameter pin mode a a. schmitt1 denote the schmitt trigger input characteristics of the device pins. symbol test conditions min typ max unit input voltage high schmitt1 v ih1 0.7 av dd5 av dd5 v input voltage low schmitt1 v il1 0 0.3 av dd5 v input voltage hys- teresis b b. not tested in production. specified by design. schmitt1 v hi1 150 mv
36 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.6 pin group 3: gpio and lcd bus interface (pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd703423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420) pin group 3: gpio and lcd bus interface supplied by dv dd5 3: ( p32-33, p86-87, p90-97, p104-107 ) lcd bus function on these pins is not available in pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420 and pd703420. t a = -40 ~ +85c, dv dd5 = 4.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 =av ss = 0 v table 6-9: pin group 3 normal operating range parameter pin mode a a. cmos1, cmos2, schmitt1 and schmitt2 denote the non-schmitt and the two schmitt trigger input characteristics of the device pins. this characteristic can be selected bitwise by soft- ware. cmos2 and schmitt2 are only available on port p8. limit1 and limit2 denote the two output characteristics with current limit functionality of the device pins. the characteristic can be selected bitwise by software. pin group symbol test conditions min. typ max. unit input voltage high schmitt1 3 v ih1 0.7 dv dd5 dv dd5 v schmitt2 p86-87 v ih2 0.8 dv dd5 dv dd5 v cmos1 3 v ih3 0.7 dv dd5 dv dd5 v cmos 2 p86-87 v ih4 0.8 dv dd5 dv dd5 v input voltage low schmitt1 3 v il1 0 0.3 dv dd5 v schmitt2 p86-87 v il2 0 0.4 dv dd5 v cmos1 3 v il3 0 0.3 dv dd5 v cmos2 p86-87 v il4 0 0.4 dv dd5 v input hysteresis b schmitt1 3 v hy1 150 mv schmitt2 p86-87 v hy2 150 mv output voltage high limit1 3 v oh i oh = -2.0 ma dv dd5 - 0.45 v limit2 3 v oh i oh = -5.0 ma dv dd5 - 0.45 v output voltage low limit1 3 v ol i ol = 2.0 ma 0.45 v limit2 3 v ol i ol = 5.0 ma 0.45 v maximum output short circuit current high limit1 3 i ohm1 v oh = 0 v -2 -12 ma limit2 i ohm2 -5 -30 ma maximum output short circuit current low limit1 i olm1 v ol = dv dd5 212ma limit2 i olm2 530ma
37 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 4.0 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v b. not tested in production. specified by design. table 6-10: pin group 3 low voltage operating range parameter pin mode a a. cmos1, cmos2, schmitt1 and schmitt2 denote the non-schmitt and the two schmitt trigger input characteristics of the device pins. this characteristic can be selected bitwise by soft- ware. cmos2 and schmitt2 are only available on port p8. limit1 and limit2 denote the two output characteristics with current limit functionality of the device pins. the characteristic can be selected bitwise by software. pin group symbol test conditions min. typ max. unit input voltage high schmitt1 3 v ih1 0.7 dv dd5 dv dd5 v schmitt2 p86-87 v ih2 0.8 dv dd5 dv dd5 v cmos1 3 v ih3 0.7 dv dd5 dv dd5 v cmos2 p86-87 v ih4 0.8 dv dd5 dv dd5 v input voltage low schmitt1 3 v il1 0 0.3 dv dd5 v schmitt2 p86-87 v il2 0 0.35 dv dd5 v cmos1 3 v il3 0 0.3 dv dd5 v cmos2 p86-87 v il4 0 0.4 dv dd5 v input hysteresis b b. not tested in production. specified by design. schmitt1 3 v hy1 100 mv schmitt2 p86-87 v hy2 100 mv output voltage high limit1 3 v oh i oh = -1.0 ma dv dd5 - 0.45 v limit2 3 v oh i oh = -2.0 ma dv dd5 - 0.45 v output voltage low limit1 3 v ol i ol = 1.0 ma 0.45 v limit2 3 v ol i ol = 2.0 ma 0.45 v maximum output short circuit current high limit1 3 i ohm1 v oh = 0 v -1 ma limit2 i ohm2 -2 ma maximum output short circuit current low limit1 i olm1 v ol = dv dd5 1ma limit2 i olm2 2ma
38 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.7 pin group 3: gpio and lcd bus and external memory interface (pd70f3427) pin group 3: gpio and lcd bus interface and external memory interface supplied by dv dd5 3: ( p32-33, p86-87, p90-97, p104-107, p141-142 ) lcd bus function on these pins is not available in pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420 and pd703420. t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-11: pin group 3 normal operating range parameter pin mode a a. cmos1 denotes the fixed non-schmitt input characteristics of these device pins. this pin group does not support current limitation. pin group symbol test conditions min. typ max. unit input voltage high cmos1 3 v ih3 0.7 dv dd5 dv dd5 v input voltage low cmos1 3 v il3 0 0.3 dv dd5 v output voltage high no limit 3 v oh i oh = -5.0 ma dv dd5 - 0.45 v output voltage low no limit 3 v ol i ol = 5.0 ma 0.45 v
39 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.8 pin group 6: external memory interface (pd70f3427) pin group 6: external memory interface supplied by mv dd5 . 6: (a0-23, d0-15, cs0-1 , cs3-4 , wait , rd , wr , be0-1 , p140) t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = mv ss5 = av ss = 0 v table 6-12: pin group 3 normal operating range parameter pin mode a a. cmos1 denotes the fixed non-schmitt input characteristics of the device pins. this pin group does not support current limitation. pin group symbol test conditions min. typ max. unit input voltage high cmos1 6 v ih6 0.7 mv dd5 mv dd5 v input voltage low cmos1 6 v il6 0 0.3 mv dd5 v output voltage high no limit 6 v oh i oh = -5.0 ma mv dd5 - 0.45 v output voltage low no limit 6 v ol i ol = 5.0 ma 0.45 v
40 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.9 lcd common and segment lines the lcd common and segment function is only available in pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420 and pd703420. t a = -40 ~ +85c, dv dd5 = 4.5 v ~ 5.5 v, bv dd5 = 4.5 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v note: the power supply configuration is restricted, when the lcd is used. the lcd voltages are generated centrally. since the lcd output buffers are supplied by differ- ent supplies (bv dd5 and dv dd5 ) it is necessary that bv dd5 is equal to dv dd5 . note: do not operate buffers of pin group 3 in current limit state, when the lcd function is used. fail- ing to do so may lead to a decreased accuracy of the lcd waveforms. table 6-13: dc characteristics lcd common and segment lines parameter symbol testconditions min. typ max unit lcd segment output volt- age (unloaded) v ods io = 1a v lcdn - 0.2 v lcdn a a. vlcdn (n= 0..3) represents one of the four possible voltage levels at the lcd pins. see table below for reference. v lcdn + 0.2 v lcd common output volt- age (unloaded) v odc io = 1a v lcdn - 0.2 v lcdn v lcdn + 0.2 v lcd split voltage b b. the split voltage is an internal design value. direct measurement is not possible. v lc0 io = 1.5 ma v lcd0 - 0.1 v lcd0 v lcd0 + 0.1 v v lc1 io = 1.0 ma v lcd1 - 0.1 v lcd1 v lcd1 + 0.1 v v lc2 io = 1.0 ma v lcd2 - 0.1 v lcd2 v lcd2 + 0.1 v v lc3 io = 1.5 ma v lcd3 - 0.1 v lcd3 v lcd3 + 0.1 v lcd series resistance c c. the series resistance is an internal design value. direct measurement is not possible. r lcds segment lines, v lcdn to pin 1.8 k r lcdc common lines, v lcdn to pin 1.8 k lcd operation current idd lcd tbd. tbd. a
41 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.10 stepper motor driver io pin group 4: stepper motor outputs supplied by smv dd5 4a: (p110-117, p120-123) 4b: (p124-127, p130-137) t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 4.0 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-14: dc characteristics stepper motor driver input normal voltage operation parameter pin mode a a. cmos1 and schmitt1 denote the non-schmitt trigger and the two schmitt trigger input charac- teristics of the device pins. this characteristic can be selected bitwise by software. symbol test conditions min typ max unit input voltage high schmitt1 v ih1 0.7 smv dd5 smv dd5 v cmos1 v ih3 0.7 smv dd5 smv dd5 v input voltage low schmitt1 v il1 0 0.3 smv dd5 v cmos1 v il3 0 0.3 smv dd5 v input voltage hys- teresis b b. not tested in production. specified by design. schmitt1 v hi1 150 mv
42 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 4.0 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-15: dc characteristics stepper motor driver input low voltage operation parameter pin mode a a. cmos1 and schmitt1 denote the non-schmitt trigger and the two schmitt trigger input charac- teristics of the device pins. this characteristic can be selected bitwise by software. symbol test conditions min typ max unit input voltage high schmitt1 v ih1 0.7 smv dd5 smv dd5 v cmos1 v ih3 0.7 smv dd5 smv dd5 v input voltage low schmitt1 v il1 0 0.3 smv dd5 v cmos1 v il3 0 0.3 smv dd5 v input voltage hys- teresis b b. not tested in production. specified by design. schmitt1 v hi1 100 mv
43 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 4.75 v ~ 5.25 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) note: the stepper output drivers have no current limitation and are not protected regarding short cir- cuit. table 6-16: dc characteristics stepper motor driver output normal operation parameter pin mode symbol test conditions min typ max unit output voltage high v oh i oh = -40 ma, t a = -40c smv dd5 - 0.5 smv dd5 v v oh i oh = -30 ma, t a = +25c smv dd5 - 0.5 smv dd5 v v oh i oh = -27 ma, t a = +85c smv dd5 - 0.5 smv dd5 v output voltage low v ol i ol = 40 ma, t a = -40c 00.5v v ol i ol = 30 ma, t a = +25c 00.5v v ol i ol = 27 ma, t a = +85c 00.5v output voltage devi- ation a a. output voltage deviation defines the difference of the outputs levels of the same stepper motor. v dev = max ( | v ohx - v ohy | , | v olx - v oly | ) @ i ohx = i ohy , i olx =i oly . x and y denote any combination of two pins of the following pin groups: (p110-p113, p114-117, p120-123, p124-p127, p130-p133, p134-p137) v dev 050mv output slew rate b b. the slew rate is not tested, but derived from simulation. t rf 10% - 90%122570ns peak cross current c c. the slew rate control generates a cross current in the output stage to control the energy of the external inductive load. the cross current flows only during the output transistion time t rf . it flows in addition to the output current. the cross current is not tested, but derived from simulation. i cross 50 ma output pulse width d d. the output buffer can not generate high or low pulses shorter than this time, because of its slew rate control system. this value is not tested, but derived from simulation. t mo 125 ns output pulse length deviation e e. the slew rate control function causes a deviation of output pulse time compared to the ideal selected out- put pulse setting. this value is not tested, but derived from simulation. t smdev -10 +5 +45 ns
44 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 4.75 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-17: dc characteristics stepper motor driver output low voltage operation parameter pin mode symbol test conditions min typ max unit output voltage high v oh i oh = -5 ma, smv dd5 - 0.5 smv dd5 v output voltage low v ol i ol = +5 ma, 00.5v
45 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.11 current limit function of i/o buffers the output buffers of the pin groups 1 and 3 incorporate a current limiting function. this function limits the output current of the buffer to a certain value during output signal switching. the limit is disabled when the buffer output voltage is near to its target voltage, thus providing full driva- bility. during full drivability the current may reach values given in absolute maximum ratings for a single pin. the user can select different limit ranges by software (see functional target specification for details). the limit function is independant from the operation mode of the device. a permanent short circuit of outputs is not permitted. the stepper motor driver outputs do not support a current limiting function. figure 6-1: current limit function principle note: the current limit function of the i/o buffers needs additional bias current to control the output stage. the additional bias current depend on the status of each buffer. each buffer with either high or low output and in the stage of current limiting will draw this bias current. iol vol limit max limit min no limit limited -ioh voh no limit limited v odl v odh
46 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) note: the function of the current limiting operation is sensitive against inductive loads under a certain condition: the load of the pin is below the selected current limit and the device could reach a suffi- cient output voltage. the device changed to full drivability. the external circuitry sinks/sources more and more current. the current creates an increasing voltage drop in the output stage of the device. the increasing voltage drop enables the current limiting function. the enabling of the current limit together with an external inductance may lead to an oscilla- tion of the output between the limited and unlimited state. the external inductance creates voltage peaks that change the state of the output buffers current limiting function. recommendation: keep external inductance small (keep external wiring short). the current limit function of pin group 3 is only available for the derivatives pd70f3426, pd70f3425, pd70f3424, pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420. the pin group 3 of the derivative pd70f3427 does not contain a current limit function. table 6-18: dc characteristics of current limiting function a a. these values are not tested. they are given based on design simulation parameter pin mode symbol test condi- tions min typ max unit limit disable threshold voltage for v oh v odh vddx b - 1.6 b. vddx denotes the corresponding voltage supply of the pin. vddx - 1.1 v limit disable threshold voltage for v ol v odl 1.1 1.6 v supply current per buffer for current limitation c c. this current need not be considered during absolute maximum current calculation. limit1 i ddcl1 0.8 ma limit2 i ddcl2 1.7 ma
47 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 6.12 supply current t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 6-19: dc characteristics supply current pd70f3426 a parameter symbol test conditions min typ max unit supply current i dd10 operating (f cpu = 64 mhz; sscg,pll: on) 100 130 ma i dd11 operating (f cpu = 48 mhz; sscg,pll: on) 77 100 ma i dd12 operating (f cpu = 32 mhz; sscg,pll: on) 57 75 ma i dd13 operating (f cpu = 24 mhz; sscg,pll: on) 46 60 ma i dd13 operating (f cpu = 16 mhz; sscg,pll: on) 35 45 ma i dd13 operating (f cpu = 8 mhz; sscg,pll: on) 24 30 ma i dd14 operating (f cpu = 4 mhz; sscg,pll: off) 15 19 ma i dd15 operating (f cpu = 32 khz; sscg,pll: off) 11.3ma i dd16 operating (f cpu = ringosc; sscg,pll: off) 8.1 11 ma i dd20 halt mode (f pll = 64 mhz; sscg,pll: on) 48 65 ma i dd21 halt mode (f pll = 48 mhz; sscg,pll: on) 39 50 ma i dd30 idle mode (f pll = 64 mhz; sscg,pll: on) 57ma
48 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 supply current i dd31 idle mode (f pll = 48 mhz; sscg,pll: on) 57ma i dd5 stop 10 190 a i dd6 watch 350 500 a i dd6a watch monitored 330 530 a i dd7 sub watch 50 200 a i dd7a sub watch monitored 65 215 a i dd7b sub watch on ring- osc 65 215 a a. these values are target values without current consumption due to external circuitry at the io- pins. table 6-19: dc characteristics supply current pd70f3426 a (continued) parameter symbol test conditions min typ max unit
49 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 table 6-20: dc characteristics supply current pd70f3427 a parameter symbol test conditions min typ max unit supply current i dd10 operating (f cpu = 64 mhz; sscg,pll: on) 108 140 ma i dd11 operating (f cpu = 48 mhz; sscg,pll: on) 85 110 ma i dd12 operating (f cpu = 32 mhz; sscg,pll: on) 62 80 ma i dd13 operating (f cpu = 24 mhz; sscg,pll: on) 50 65 ma i dd13 operating (f cpu = 16 mhz; sscg,pll: on) 38 50 ma i dd13 operating (f cpu = 8 mhz; sscg,pll: on) 26 35 ma i dd14 operating (f cpu = 4 mhz; sscg,pll: off) 15 20 ma i dd15 operating (f cpu = 32 khz; sscg,pll: off) 11.3ma i dd16 operating (f cpu = ringosc; sscg,pll: off) 56.6ma i dd20 halt mode (f pll = 64 mhz; sscg,pll: on) 70 90 ma i dd21 halt mode (f pll = 48 mhz; sscg,pll: on) 54 70 ma i dd30 idle mode (f pll = 64 mhz; sscg,pll: on) 57ma i dd31 idle mode (f pll = 48 mhz; sscg,pll: on) 57ma i dd5 stop 10 190 a i dd6 watch 350 500 a i dd6a watch monitored 330 530 a i dd7 sub watch 50 200 a
50 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 supply current i dd7a sub watch monitored 65 215 a i dd7b sub watch on ring-osc 65 215 a a. these values are target values without current consumption due to external circuitry at the io- pins. table 6-20: dc characteristics supply current pd70f3427 a (continued) parameter symbol test conditions min typ max unit
51 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 table 6-21: dc characteristics supply current pd70f3425, pd70f3424 a parameter symbol test conditions min typ max unit supply current i dd10 operating (f cpu = 64mhz; sscg,pll: on) 82 123 ma i dd11 operating (f cpu = 48 mhz; sscg,pll: on) 65 98 ma i dd12 operating (f cpu = 32 mhz; sscg,pll: on) 48 72 ma i dd13 operating (f cpu = 24 mhz; sscg,pll: on) 40 60 ma i dd13 operating (f cpu = 16 mhz; sscg,pll: on) 32 48 ma i dd13 operating (f cpu = 8 mhz; sscg,pll: on) 24 36 ma i dd14 operating (f cpu = 4 mhz; sscg,pll: off) 10 15 ma i dd15 operating (f cpu = 32 khz; sscg,pll: off) 0.2 1.2 ma i dd16 operating (f cpu = ringosc; sscg,pll: off) 3.3 6 ma i dd20 halt mode (f pll = 64 mhz; sscg,pll: on) 40 60 ma i dd21 halt mode (f pll = 48 mhz; sscg,pll: on) 32 48 ma i dd30 idle mode (f pll = 64 mhz; sscg,pll: on) 69ma i dd31 idle mode (f pll = 48 mhz; sscg,pll: on) 57.5ma i dd5 stop 10 190 a i dd6 watch 250 500 a i dd6a watch monitored 265 530 a i dd7 sub watch 50 200 a
52 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 supply current i dd7a sub watch monitored 65 215 a i dd7b sub watch on ring-osc 65 215 a a. these values are target values without current consumption due to external circuitry at the io- pins. table 6-21: dc characteristics supply current pd70f3425, pd70f3424 a (continued) parameter symbol test conditions min typ max unit
53 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 table 6-22: dc characteristics supply current pd70f3423, pd70f3422, pd70f3421, pd70f3420 a parameter symbol test conditions min typ max unit supply current i dd12 operating (f cpu = 32 mhz; sscg,pll: on) 48 72 ma i dd13 operating (f cpu = 24 mhz; sscg,pll: on) 40 60 ma i dd13 operating (f cpu = 16 mhz; sscg,pll: on) 32 48 ma i dd13 operating (f cpu = 8 mhz; sscg,pll: on) 24 36 ma i dd14 operating (f cpu = 4 mhz; sscg,pll: off) 10 15 ma i dd15 operating (f cpu = 32 khz; sscg,pll: off) 0.2 1.2 ma i dd16 operating (f cpu = ringosc = 300 khz; sscg,pll: off) 3.3 6 ma i dd20 halt mode (f pll = 32 mhz; sscg,pll: on) 24 36 ma i dd20 halt mode (f pll = 24 mhz; sscg,pll: on) 20 30 ma i dd21 halt mode (f pll = 16 mhz; sscg,pll: on) 16 24 ma i dd30 idle mode (f pll = 32 mhz; sscg,pll: on) 3.8 5.7 ma i dd30 idle mode (f pll = 24 mhz; sscg,pll: on) 3.5 5.3 ma i dd31 idle mode (f pll = 16 mhz; sscg,pll: on) 3.2 4.8 ma i dd5 stop 10 190 a i dd6 watch 250 500 a i dd6a watch monitored 265 530 a
54 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 supply current i dd7 sub watch 50 200 a i dd7a sub watch monitored 65 215 a i dd7b sub watch on ringosc 65 215 a a. these values are target values without current consumption due to external circuitry at the io- pins. table 6-22: dc characteristics supply current pd70f3423, pd70f3422, pd70f3421, pd70f3420 a (continued) parameter symbol test conditions min typ max unit
55 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 table 6-23: dc characteristics supply current pd703422, pd703421, pd703420 a parameter symbol test conditions min typ max unit supply current i dd12 operating (f cpu = 32 mhz; sscg,pll: on) 48 72 ma i dd13 operating (f cpu = 24 mhz; sscg,pll: on) 40 60 ma i dd13 operating (f cpu = 16 mhz; sscg,pll: on) 32 48 ma i dd13 operating (f cpu = 8 mhz; sscg,pll: on) 24 36 ma i dd14 operating (f cpu = 4 mhz; sscg,pll: off) 10 15 ma i dd15 operating (f cpu = 32 khz; sscg,pll: off) 0.2 1.2 ma i dd16 operating (f cpu = ringosc = 300 khz; sscg,pll: off) 3.3 6 ma i dd20 halt mode (f pll = 32 mhz; sscg,pll: on) 24 36 ma i dd20 halt mode (f pll = 24 mhz; sscg,pll: on) 20 30 ma i dd21 halt mode (f pll = 16 mhz; sscg,pll: on) 16 24 ma i dd30 idle mode (f pll = 32 mhz; sscg,pll: on) 3.8 5.7 ma i dd30 idle mode (f pll = 24 mhz; sscg,pll: on) 3.5 5.3 ma i dd31 idle mode (f pll = 16 mhz; sscg,pll: on) 3.2 4.8 ma i dd5 stop 10 190 a i dd6 watch 250 500 a i dd6a watch monitored 265 530 a i dd7 sub watch 50 200 a
56 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 supply current i dd7a sub watch monitored 65 215 a i dd7b sub watch on ringosc 65 215 a a. these values are target values without current consumption due to external circuitry at the io- pins. table 6-23: dc characteristics supply current pd703422, pd703421, pd703420 a (contin- parameter symbol test conditions min typ max unit
57 chapter 6 dc characteristics preliminary data sheet ease-sp-8007-v1.1 the low current modes (stop, watch, sub watch) are tested under the following conditions: operation modes setting as described in table below. all functional pins with output possibility are set to output with alternating high and low output levels. testequipment is disconnected from output pins. idd is the total sum of currents to the device supply pins v dd5 , bv dd5 , dv dd5 , smv dd5 , av dd - device drives its own leakage currents by its output stages. - the leakage current is included in the given idd values. table 6-24: operational conditions for measurement unit watch watch mon- itored sub watch sub watch on rin- gosc sub watch monitored stop main-oscillator running running stopped stopped stopped stopped sub-oscillator stopped (xt1 clamped) stopped (xt1 clamped) running stopped (xt1 clamped) running stopped ring-oscillator stopped running stopped running running stopped sscg stopped stopped stopped stopped stopped stopped pll stopped stopped stopped stopped stopped stopped cpu system stopped stopped stopped stopped stopped stopped iicclk stopped stopped stopped stopped stopped stopped pclk0, pclk1 stopped stopped stopped stopped stopped stopped pclk2?pclk15 stopped stopped stopped stopped stopped stopped spclk0, spclk1 stopped stopped stopped stopped stopped stopped spclk2?spclk15 stopped stopped stopped stopped stopped stopped fout stopped stopped stopped stopped stopped stopped wtclk running running running running running stopped wdtclk stopped stopped stopped stopped stopped stopped tm0clk stopped stopped stopped stopped stopped stopped lcd disabled disabled disabled disabled disabled disabled adc disabled disabled disabled disabled disabled disabled vcomp disabled disabled disabled disabled disabled disabled regulator a a. regulator in standby: stbctl = 0x03 standby standby standby standby standby standby
58 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 chapter 7 ac characteristics 7.1 ac test input/output waveform figure 7-1: ac test input/output waveform 7.2 ac test load condition figure 7-2: ac test load condition 0.7 x 0.3 x d b test points sm dut load on test c l =50pf
59 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.3 reset t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) figure 7-3: reset timing table 7-1: reset ac characteristics parameter symbol test conditions min. max. unit reset high-level width a a. this signal high time is needed to ensure that the internal reset release operation starts. t wrsh 500 ns reset low-level width b b. this signal low time is needed to ensure that the internal reset is activated. t wrsl 500 ns reset pulse rejection c c. the reset input incorporates an analog filter. pulses shorter than this minimum will be ignored. not tested in production. note: reset pulses shorter than the given value may not be recognized by the device, they do not cause undefined states of the device. t wrrj 50 ns t wrsh t wrsl reset
60 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.4 interrupt timing t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) figure 7-4: interrupt timing note: interrupt timing is generated by analog delay elements. delay characteristics have a wide range in production. table 7-2: interrupt ac characteristics parameter symbol test conditions min typ max unit nmi high-level width a a. pulses longer than this value will pass the input filter. t nih 360 ns nmi low-level width a t nil 360 ns nmi pulse rejection b b. pulses shorter than this value do not pass the input filters. not tested in production. t nirj 50 360 ns intpn c high-level width a c. n = 7?0 t ith 360 ns intpn c low-level width a t itl 360 ns intpn c pulse rejection b t itrj 50 360 ns nmi intpn
61 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.5 peripheral function characteristics the following conditions are valid for all peripheral function characteristics unless otherwise noted. t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) 7.5.1 timer p figure 7-5: timer p input timing table 7-3: timer p ac characteristics parameter symbol test conditions min typ max unit tipmn a high-level width a. m = 3?0, n = 1?0 t tiphd digital filter 45 +3/f pclk0 b b. f pclk0 is the clock frequency of the digital filter connected to the input pin. ns t tiphnb no digital filter, react on both edge 45 +2/f pclk0 ns t tiphns no digital filter, react on single edge 45 +1/f pclk0 ns tipmn a low-level width t tipl digital filter 45 +3/f pclk0 ns t tiplnb no digital filter, react on both edge 45 +2/f pclk0 ns t tiplns no digital filter, react on single edge 45 +1/f pclk0 ns tipmn t tiph t ti p l
62 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.5.2 timer g 7.5.3 uarta 7.5.4 can table 7-4: timer g input characteristics parameter symbol test conditions min typ max unit tigmn a high-level width a. m = 0?1: n = 1?4; m = 2: n = 0...5 t tigh1 digital filter, f pclk0 b = f cclk c b. f spclk0 is the clock frequency of the digital filter connected to the input pin. c. f cclk is the count clock frequency of the timer g. 45 + 3/f pclk0 ns t tigh2 digital filter, f pclk0 > f cclk 45 + 2/f cclk ns t tigh0 no digital filter 45 + 2/f cclk ns tigmn a low-level width t tigl1 digital filter, f pclk0 = f cclk 45 + 3/f pclk0 ns t tigl2 digital filter, f pclk0 > f cclk 45 + 2/f cclk ns t tigl0 no digital filter 45 + 2/f cclk ns table 7-5: uarta ac characteristics parameter symbol test conditions min. max unit transfer rate t uarta 0.3 1000 kbps table 7-6: can ac characteristics parameter symbol test conditions min. max. unit transfer rate t fcan f can a 8 mhz a. f can is the can macro clock frequency. for can clock selection refer to functional specifica- tion of the can. 1mbps
63 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.5.5 csi b (high voltage operation) t a = -40 ~ +85c, dv dd5 = 4.5 v ~ 5.5 v, bv dd5 = 4.5 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), mv dd5 = 3.0 v ~ 3.6 v, v ss5 = bv ss5 = dv ss5 = mv ss5 = smv ss5 = av ss = 0 v (1) csib master mode (a) with digital filter (b) without digital filter table 7-7: csib master mode ac characteristics with digital filter parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 8/f pclk0 ns sckbn high level width t kh1 0.5 t kcy1 - 15 ns sckbn low level width t kl1 0.5 t kcy1 - 15 ns sibn setup time (to sckbn ) t sik1 50 + 4/f pclk0 a a. f pclk0 is the clock frequency of the digital filter connected to the input pin. ns sibn hold time ( from sckbn ) t ksi1 -31 - 4/f pclk0 ns delay time from sckbn to sobn t kso1 6ns table 7-8: csib master mode ac characteristics without digital filter parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 125 ns sckbn high level width t kh1 0.5 t kcy1 - 15 ns sckbn low level width t kl1 0.5 t kcy1 - 15 ns sibn setup time (to sckbn ) t sik1 50 ns sibn hold time (from sckbn ) t ksi1 -31 ns delay time from sckbn to sobn t kso1 6ns
64 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 (2) csib slave mode (a) with digital filter (b) without digital filter note: n = 2?0 table 7-9: csib slave mode ac characteristics with digital filter parameter symbol test conditions min max unit sckbn cycle time t kcy1 8/f pclk0 ns sckbn high level width t kh1 0.5 t kcy1 - 5 ns sckbn low level width t kl1 0.5 t kcy1 - 5 ns sibn setup time (to sckbn ) t sik1 15 + 2/f pclk0 a a. f pclk0 is the clock frequency of the digital filter connected to the input pin. ns sibn hold time (from sckbn ) t ksi1 5 + 2/f pclk0 ns delay time from sckbn to sobn t kso1 45 + 3/f pclk0 ns table 7-10: csib slave mode ac characteristics without digital filter parameter symbol test conditions min max unit sckbn cycle time t kcy1 125 ns sckbn high level width t kh1 50 ns sckbn low level width t kl1 50 ns sibn setup time (to sckbn ) t sik1 15 ns sibn hold time (from sckbn ) t ksi1 5ns delay time from sckbn to sobn t kso1 45 ns
65 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-6: csi master/slave mode timing figure 7-7: csi master/slave mode timing inverted clock t sik n t ksin t kcyn t kln t khn t kso n output data input data sobn sibn sckbn t sik n t ksin t kcyn t kln t khn t kso n output data input data sobn sibn sckbn
66 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.5.6 csi b (low voltage operation) t a = -40 ~ +85c, dv dd5 = 3.15 v ~ 4.5 v, bv dd5 = 3.15 v ~ 4.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), mv dd5 = 3.0 v ~ 3.6 v, v ss5 = bv ss5 = dv ss5 = mv ss5 = smv ss5 = av ss = 0 v (1) csib master mode (a) with digital filter (b) without digital filter table 7-11: csib master mode ac characteristics with digital filter parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 8/f pclk0 ns sckbn high level width t kh1 0.5 t kcy1 - 15 ns sckbn low level width t kl1 0.5 t kcy1 - 15 ns sibn setup time (to sckbn ) t sik1 -93 + 4/f pclk0 a a. f pclk0 is the clock frequency of the digital filter connected to the input pin. ns sibn hold time ( from sckbn ) t ksi1 -49 - 4/f pclk0 ns delay time from sckbn to sobn t kso1 45 ns table 7-12: csib master mode ac characteristics without digital filter parameter symbol test conditions min. max. unit sckbn cycle time t kcy1 125 ns sckbn high level width t kh1 0.5 t kcy1 - 80 ns sckbn low level width t kl1 0.5 t kcy1 - 80 ns sibn setup time (to sckbn ) t sik1 -93 ns sibn hold time (from sckbn ) t ksi1 -49 ns delay time from sckbn to sobn t kso1 45 ns
67 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 (2) csib slave mode (a) with digital filter (b) without digital filter note: n = 2?0 table 7-13: csib slave mode ac characteristics with digital filter parameter symbol test conditions min max unit sckbn cycle time t kcy1 8/f pclk0 ns sckbn high level width t kh1 4/f pclk0 - 5 ns sckbn low level width t kl1 4/f pclk0 - 5 ns sibn setup time (to sckbn ) t sik1 15 + 2/f pclk0 a a. f pclk0 is the clock frequency of the digital filter connected to the input pin. ns sibn hold time (from sckbn ) t ksi1 5 + 2/f pclk0 ns delay time from sckbn to sobn t kso1 100 + 3/f pclk0 ns table 7-14: csib slave mode ac characteristics without digital filter parameter symbol test conditions min max unit sckbn cycle time t kcy1 125 ns sckbn high level width t kh1 50 ns sckbn low level width t kl1 50 ns sibn setup time (to sckbn ) t sik1 15 ns sibn hold time (from sckbn ) t ksi1 5ns delay time from sckbn to sobn t kso1 100 ns
68 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-8: csi master/slave mode timing csi master/slave mode timing inverted clock t sik n t ksin t kcyn t kln t khn t kso n output data input data sobn sibn sckbn t sik n t ksin t kcyn t kln t khn t kso n output data input data sobn sibn sckbn
69 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.5.7 i2c table 7-15: i2c ac characteristics parameter symbol normal mode fast-speed mode unit min max min max scl0 clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf 4.7?1.3? s hold time a a. at the start condition, the first clock pulse is generated after the hold time t hd:sta 4.0?0.6? s scl0 clock low-level width t low 4.7?1.3? s scl0 clock high-level width t high 4.0?0.6? s setup time for start/restart conditions t su:sta 4.7?0.6? s data hold time cbus compatible master t hd:dat 5.0??? s i2c mode 0 b b. the system requires a minimum of 300ns hold time internally for the sda signal ( at v ihmin of scl0 signal ) in order to occupy the undefined area at the falling edge of scl0. 3.45 c 0 note b 0.9 c c. if the system does not extend the scl0 signal low hold time ( t low ), only the maximum data hold time ( t hd:dat ) needs to be satisfied. s data setup time t su:dat 250 ? 100 d d. the fast-speed-mode iic bus can be used in a normal-mode iic bus system. in this case, set the fast-speed-mode iic bus so that it meets the following conditions: - if the system does not extend the scl0n signal?s low state hold time: tsu:dat>/=250ns - if the system extends the scl0n signal?s low state hold time: transmit the following data bit to the sda0 line prior to releasing the scl0 line (t rmax .+t su:dat =1000+250=1250ns: normal mode iic bus specification ). ?ns stop condition setup time t su:sto 4.0?0.6? s noise suppression e e. noise suppression is only available in fast-speed mode. t sp t iiclk f f. t iiclk is the period of the iiclk supplied by the clock controller. ns capacitive load of each bus line c b ? 400 ? 400 pf
70 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-9: i 2 c timing remarks: 1. p: stop condition 2. s: start condition 3. sr: restart condition 4. rise and fall time depend on the actual load of the signal and the selected output cur- rent limit. for a capacitive load the time can be roughly calculated from: (t r = v oh / i oh * c l ), (t f = v oh / i ol * c l ) scl0 p t su: s ta t hd: s ta t low t hi g h t buf sda0 t sp t r t hd: d at t f t su: d at s t hd: s ta sr p t su: s to
71 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.6 lcd bus interface t a = -40 ~ +85c, dv dd5 = 3.15 v ~ 4.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) the following tables give the timing for pin group 3 used as lcd bus interface with schmitt1 input characteristic and unlimited output current. table 7-16: lcd bus interface ac characteristics parameter symbol cond. min. a a. t: 1/f lcd (lcd bus interface macro clock frequency) for clock selection refer to functional specification of the lcd bus interface always keep cyc > 2 always keep wst < (cyc-2) max. unit cycle time t cyc cyc x t - 5 - ns control low-pulse width t cl (wst+1)t - 50 - ns enable active pulse width t elh (wst+1)t - 35 - ns control setup time t rws 0.5 t + 2 - ns control hold time t rwh 0.5 t - ns data output setup time t dos 0.5 t - 20 0.5 t + 12 ns data output hold time t doh [cyc-(wst+1.5)] t - 88 - ns data input setup time t dis 117 - ns data input hold time t dih 0-ns output disable time t od 0.5 t + 5 - ns
72 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-10: lcd bus interface motorola mode timing figure 7-11: lcd bus interface intel mode timing db cs (gpio) dbwr (r/w) dbrd dbrd ( ( e e ) ) (el=0 in lbctl) dbd[7:0] (write) tt rws rwh data dbd[7:0] (read) t dih t elh t dis t cyc (el=1 in lbctl) data t dos t doh db cs (gpio) dba0 (gpio) d b wr d b rd dbd[7:0] (write) data data dbd[7:0] (read) t dih t cyc t cl t dis t t dos doh
73 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-12: lcd bus interface motorola mode turnaround timing figure 7-13: lcd bus interface intel mode turnaround timing dbwr (r/w) dbrd dbrd ( ( e e ) ) (el=0 in lbctl) (el=1 in lbctl) dbd[7:0] data t od data t dos write read write d b wr d b rd dbd[7:0] data t od data t dos write read write
74 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 7.7 external memory access (pd70f3427) t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 3.6 v, (if used as ext. mem. i/f, dv dd5 = 3.0 v ~ 5.5 v otherwise) mv dd5 = 3.0 v ~ 3.6 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = mv ss5 = smv ss5 = av ss = 0 v output pin load capacitance: c l = 50pf
75 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 note: t: 1 / fcpu ( = frequency of system clock) i: number of idle states specified by bcc register w t : total number of waits, w t = w as +w d w as : number of waits specified by asc register w d : number of waits specified by dwc0, dwc1 register in sram mode and during off-page access in page mode. prc register during on-page access in page mode. table 7-17: external memory access asynchronous read timing parameter symbol condi- tions min max unit data input set up time d0-d15 (vs.address) <10> t said (2.0+w t )t-22 ns data input set up time d0-d15 (vs. rd ) <11> t srdid (1.5+w d )t-21 ns data input set up time d16-d31 (vs.address) <10> t said (2.0+w t )t-27 ns data input set up time d16-d31 (vs. rd ) <11> t srdid (1.5+w d )t-26 ns rd low level width <12> t wrdl (1.5+w d )t-12 ns rd low level width (delayed rd) <12a> t wrdl (2+w d )t-12 ns rd high level width <13> t wrdh (1.5+w as +i)t-12 ns rd high level width (delayed rd) <13a> t wrdh (1+w as +i)t-12 ns address to rd delay time <14> t dard (0.5+w as) t-3 ns csn to rd delay time <14a> t dcrd (0.5+w as )t-3 ns rd address delay time <15> t drda it-7 ns rd address delay time (delayed rd) <15a> t drda (-0.5+i)t-7 ns data input hold time (vs. rd ) <16> t hrdid -11 ns data input hold time (vs. delayed rd ) <16a> t hrdid -0.5t-11 ns write data output delay time after rd <17> t drdod (1+i)t-12 ns write data output delay time after delayed rd <17a> t drdod (0.5+i)t-12 ns
76 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-14: sram asynchronous read timing a 0-a23 , cs0 cs4 cs3, cs1, d0-d31
77 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 note: t: 1 / fcpu ( = frequency of system clock) i: number of idle states specified by bcc register w t : total number of waits, w t = w as +w d w as : number of waits specified by asc register w d : number of waits specified by dwc1, dwc2 register table 7-18: external memory access asynchronous write timing parameter symbol condi- tions min max unit address, wr delay time <20> t dawr (0.5+w as )t-4 ns csn, wr delay time <20a> t dawr (0.5+w as )t-4 ns address set up (vs. wr )<21> t sawr (1.5+w t )t-4 ns wr address delay time <22> t dwra (0.5+i)t-8 ns wr csn delay time <22a> t dwra (0.5+i)t-8 ns wr high level width <23> t wwrh (1+ i +w as )t-12 ns wr low level width <24> t wwrl (1+w d )t-8 ns data output set up time d0-15 (vs. wr ) <25> t sodwr (1+w t )t-10 ns data output hold time d0-d15 (vs. wr ) <26> t hwrod 0.5it+2 ns data output set up time d16-31 (vs. wr ) <25> t sodwr (1+w t )t-15 ns data output hold time d16-d31 (vs. wr ) <26> t hwrod it+2 ns
78 chapter 7 ac characteristics preliminary data sheet ease-sp-8007-v1.1 figure 7-15: sram asynchronous write timing a0-a23 , , cs0 cs3 cs4 cs1, d0-d31 d0-d31
79 chapter 8 analog functions preliminary data sheet ease-sp-8007-v1.1 chapter 8 analog functions 8.1 a/d converter the number of available input channels depends on the device: pd70f3427, pd70f3426, pd70f3425, pd70f3424: 16 channel input p70..p715. pd70f3423, pd70f3422, pd703422, pd70f3421, pd703421, pd70f3420, pd703420: 12 channel input p70..p711. t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.2 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 8-1: a/d converter characteristics parameter symbol test conditions min typ max unit resolution - 10 bit reference voltage avref av ss av dd v overall error a a. quantization error of 0.5 lsb is not included - av ss ain av ref , 4.5v (av ref = av dd ) 5.5v +/- 3.5 lsb - av ss ain av ref , 3.5v = av ref, 4.0v av dd 5.5v +/- 10 lsb additional error due to disturbance by digital read of p70..p715 b b. this value is not tested during production. drerr 2 lsb conversion time c c. t conv depends on register setting t conv 3.88 15.50 s analog input voltage v ian av ss av dd v analogue supply current i avdd 10 ma analog input equivalent circuit resistance b r ina 0.3 2.55 k analog input equivalent circuit capacitance b c ina 4.0 8.0 pf analogue supply current i avdd 10 ma reference voltage supply current d i avref 350 a
80 chapter 8 analog functions preliminary data sheet ease-sp-8007-v1.1 8.2 power on clear t a = -40 ~ +85c, v dd5 = 0 ~ 5.5 v, v ss = 0 v note: the poc ensures that the devices stops operation (reset condition) when the device is out- side the operation voltage range, under the condition that the supply voltage slope on v dd5 is 25mv/s. note: full device operation is only available, when the supply voltage is above the maximum threshold voltage. the device may stop operation due to reset condition generated by poc, if the supply voltage dropps below the given max threshold voltage. d. the reference current is mainly a transient current that is influenced by the conversion time. the given value is the maximum value. value is not tested during production. table 8-2: power on clear characteristics parameter symbol test conditions min typ max unit threshold voltage a a. these are target values. final values are fixed after device evaluation. v ip 3.2 4.0 v detection time b b. not tested in production. t detp v dd5 slope > 25mv/s 2s
81 chapter 8 analog functions preliminary data sheet ease-sp-8007-v1.1 8.3 voltage comparator the voltage comparator is supplied by a vdd . t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 8-3: voltage comparator characteristics a a. these are target values. final values are fixed after device evaluation. parameter symbol test conditions min typ max unit threshold voltage (uncalibrated) v iv trma = 15 1.56 1.73 b b. the voltage will be decided after evaluation of the device. 1.92 v threshold voltage (calibrated) c c. the voltage comparator has a cailbration capability. the application has to identify a calibra- tion value for trma during production. this value must then be used by the application to overwrite the initial value of tram after reset. the flow and conditions for the calibration will be defined in a separate document after device evaluation. v iv 1.73 -0.065 1.73 1.73 +0.065 v detection time d d. not tested in production. t detv2 step = 100mv, overdrive = 5mv 2s stabilization time t s 2ms
82 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 chapter 9 memory characteristics 9.1 basic characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 3.2 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) the above maximum operation frequency specification lists the center frequency of the sscg. the maximum dithering range of the sscg is assured for this center frequency. table 9-1: memory operation characteristics parameter symbol device min typ max unit operation frequency f cpu pd70f3427, pd70f3426, pd70f3425, pd70f3424 32k 64m hz pd70f3423, pd70f3422, pd70f3421, pd70f3420 32k 32m hz pd703422, pd703421, pd703420 32k 24m hz
83 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 9.2 flash memory characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 4.5 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) table 9-2: flash memory selfprogramming characteristics parameter symbol test conditions min typ max unit number of rewrites c wrt 1000 times data retention t ret 15 years blank check time a a. blank check of one memory block (4 kb). t ivbl 450 450 s erase time t iert4k one memory block (4k) b b. erase of one memory block (4kb). 25 250 ms t iert256k 64 memory blocks (256k) 64 640 ms write time t iwrt write to words c c. the corresponding library call is configured for 2 word-write per call. 300 2800 s t iwrt4k one memory block (4k) 45 tbd. ms verify time t ivrt 16 20 ms erase/write current d d. additional current that is only needed during erase or write of flash. i ddfl 13ma programming temperature e e. the power dissipation may be reduced by disabling some functionality or reducing the cpu operation speed. t prg -40 +65 c maximum power dissipation 0.8w -40 +85 c
84 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 9.3 special conditions for end-of-line programming t a = +15 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 4.8 v ~ 5.15 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) (1) flash memory end-of-line programming characteristics (pg-fp4) table 9-3: flash memory end-of-line programming characteristics (pg-fp4: csi) parameter symbol device test conditions min typ max unit blank check t ivbl all w/e cycles 5 11s erase time a a. erase of all flash-memory blocks (0 .. 255) t iwrt 11s write time b b. write of complete flash area. t iert pd70f3426, pd70f3425 20 32 s pd70f3424, pd70f3423 10 16 s pd70f3421 5 8 s verify time t ivrt pd70f3426, pd70f3425 16 20 s pd70f3424, pd70f3423 810s pd70f3421 5 7 s
85 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 table 9-4: flash memory end-of-line programming characteristics (pg-fp4: uart) parameter symbol device test conditions min typ max unit blank check t ivbl all w/e cycles 5 11s erase time a a. erase of all flash-memory blocks (0 .. 255) t iwrt 11s write time b b. write of complete flash area. t iert pd70f3426 230 300 s pd70f3425 115 150 s pd70f3424, pd70f3423 60 80 s pd70f3421 30 40 s verify time t ivrt pd70f3426 230 300 s pd70f3425 115 150 s pd70f3424, pd70f3423 60 80 s pd70f3421 30 40 s
86 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 (2) flash memory end-of-line programming characteristic (flash-selfprogramming) table 9-5: flash memory end-of-line programming characteristics (flash-selfprogramming) parameter symbol test conditions min typ max unit blank check a a. blank check of one memory block (4kb). t ivbl w/e cycles 5 450 450 s erase time one memory block (4k) t iwrt4k 25 50 ms erase time 64 memory blocks (256k) t iwrt256k 64 128 ms write time (write two words) b b. the corresponding library call is configured for 2 word per call. t iert 300 600 s write time (one memory block 4k) t iert4k 45 tbd. ms verify time t ivrt tbd. tbd. s
87 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1 9.4 serial write operation characteristics t a = -40 ~ +85c, dv dd5 = 3.0 v ~ 5.5 v, bv dd5 = 3.0 v ~ 5.5 v, av dd = 3.2 v ~ 5.5 v, smv dd5 = 3.2 v ~ 5.5 v, mv dd5 = 3.0 v ~ 5.5 v (pd70f3427) v dd5 = 4.5 v ~ 5.5 v, (see ?power on clear? on page 80 for further functional restriction), v ss5 = bv ss5 = dv ss5 = smv ss5 = av ss = 0 v mv ss5 = 0 v (pd70f3427) note: flmd1 is a shared function of the p07 pin. figure 9-1: flash memory timing table 9-6: flash memory ac characteristics parameter symbol test conditions min typ max unit count start time from rising edge of reset to flmd0 t rfcf 5ms count ending time from rising edge of reset to flmd0 t count 20 ms flmd0 counter high/low level width t ch ,t cl 10 100 s flmd0 counter rise/fall time t r ,t f 50 ns tcl reset flmd0 flmd1 0v v dd 0v v dd 0v v dd trfcf tch tf tr tcount
88 chapter 9 memory characteristics preliminary data sheet ease-sp-8007-v1.1
89 chapter 10 special conditions for device operation at extended operating temperature range preliminary data sheet ease-sp-8007-v1.1 chapter 10 special conditi ons for device operati on at extended operating temperature range (t a = -40c ... +105c) caution: for any device?s operation within the extended operating temperature range (t a = -40 c ... +105c), the device?s total power consumption must be reduced. the following tables within this chapter describe additional device conditions securing the requested decrease of the device?s power consumption. in case any device may operate within the extended operating temperature range (t a = -40c ... +105c) all of the below mentioned conditions must never be exceeded at any time. all of the below mentioned device conditions must be applied in addition to any other parameter that is described within this document. condition 1 (pd70f3427): t a = -40 ... +105c, operation modes: run, halt, idle power dissipation: < 1.0 w duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +105c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 10-1: absolute maximum ratings currents 105c (pd70f3427) parameter symbol test conditions ratings average unit output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 48 mhz 70 ma output current high i oha -70 ma number of active stepper 4 output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 24 mhz 250 ma output current high i oha -250 ma number of active stepper 6
90 chapter 10 special conditions for device operation at extended operating temperature range preliminary data sheet ease-sp-8007-v1.1 condition 1 (pd70f3426): t a = -40 ... +105c, operation modes: run, halt, idle power dissipation: < 1.0 w duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +105c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 10-2: absolute maximum ratings currents 105c (pd70f3426) parameter symbol test conditions ratings average unit output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 48 mhz 40 ma output current high i oha -40 ma number of active stepper 6 output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 24 mhz 250 ma output current high i oha -250 ma number of active stepper 6
91 chapter 10 special conditions for device operation at extended operating temperature range preliminary data sheet ease-sp-8007-v1.1 condition 1 (pd70f3425): t a = -40 ... +105c, operation modes: run, halt, idle power dissipation: < 0.9 w duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +105c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 10-3: absolute maximum ratings currents 105c (pd70f3425) parameter symbol test conditions ratings average unit output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 48 mhz 135 ma output current high i oha -135 ma number of active stepper 6 output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 32 mhz 250 ma output current high i oha -250 ma number of active stepper 6
92 chapter 10 special conditions for device operation at extended operating temperature range preliminary data sheet ease-sp-8007-v1.1 condition 1 (pd70f3424): t a = -40 ... +105c, operation modes: run, halt, idle power dissipation: < 0.88 w duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +105c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v table 10-4: absolute maximum ratings currents 105c (pd70f3424) parameter symbol test conditions ratings average unit output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 48 mhz 180 ma output current high i oha -180 ma number of active stepper 6 output current low all pins i ola sum of groups 1, 2, 3, 5, 6, 7, 8 f sys = 32 mhz 250 ma output current high i oha -250 ma number of active stepper 6
93 chapter 10 special conditions for device operation at extended operating temperature range preliminary data sheet ease-sp-8007-v1.1 condition 1 (pd703420, pd703421, pd70f3421, pd703422, pd70f3422, pd70f3423): t a = -40 ... +105c, operation modes: run, halt, idle power dissipation: < 0.86 w duration: 15000 hours v ss5 = 0v condition 2: t a = -40 ... +105c, operation modes: watch, sub-watch, stop, sub-clock cpu operation power dissipation: < 0.5w duration: 15 years v ss5 = 0v note: no additional condition must be followed.
94 chapter 11 package preliminary data sheet ease-sp-8007-v1.1 chapter 11 package 11.1 package drawing pd70f3427gd 208-pin plastic qfp (fine pitch) (28x28) item millimeters f g 1.25 1.25 b c 28.0 0.2 28.0 0.2 h 0.22 i 0.10 s 3.8 max. k 1.3 0.2 l 0.5 0.2 m 0.17 n 0.10 p 3.2 0.1 + 0.05 ? 0.04 j 0.5 (t.p.) p208gd-50-lml,mml,sml,wml-7 + 0.03 ? 0.07 r5 5 j i ns s detail of lead end q 0.4 0.1 m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 1 208 52 53 156 157 105 104 c a b q r h k m l d p g f s a 30.6 0.2 d 30.6 0.2
95 chapter 11 package preliminary data sheet ease-sp-8007-v1.1 11.2 package drawing pd70f3426gj, pd70f3425gj, pd70f3424gj, pd70f3423gj, pd70f3422gj, pd703422gj, pd70f3421gj, pd703421gj, pd70f3420gj, pd703420gj 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
chapter 12 revision history item date published document no. comment 1 july 5 th , 2005 ease-pl-8007-0v1 first release of this document 2 august 3 rd , 2005 ease-pl-8007-0v2 second release of this document 3 december 13 th , 2005 ease-pl-8007-0v3 update of document overview: - included the derivatives pd70f3427, pd70f3426, pd70f3422, pd703422. - included a note describing the expansion of flash and ram for the derivative pd70f3426. - included the lcd i/f to the reduced peripheral set. dc characteristics: - added typical operating current for 48mhz. - changed vcomp0/1 to vcmp0/1. - corrected the table 6-15. pinout information: - included the pinconfiguration of the new derivatives pd70f3427 and pd70f3426. - introduced the pin-group 6 representing the external memory-interface of the new derivative pd70f3427. - introduced the pin-group 8 representing the voltage com- parator input pins. absolute maximum ratings: - included the dj3 derivatives pd70f3427, pd70f3426, pd70f3422, pd703422. - included the concerned parameters for the pd70f3427?s memory interface. general characteristics: - included the concerned information regarding the external memory interface of the derivative pd70f3427. operation conditions: - included the dj3 derivatives pd70f3427 and pd70f3426 for the corrseponding cpu clock frequencies 32 mhz and 48 mhz. dc-characteristics: - included the dj3 derivatives pd70f3427 and pd70f3426. - separated the characteristics of pin-group 3 for pd70f3427 and the remaining devices. - included the characteristics of pin-group 6 for the device pd70f3427. - included the supply-currents for added derivatives pd70f3427 and pd70f3426. - added a note regarding current limit function of the deriva- tive pd70f3427. - review of chapter "lcd common and segment lines". ac-characteristics: - included the derivatives pd70f3427 and pd70f3426. - included the external memory access specification for the derivative pd70f3427.
97 chapter 12 revision history preliminary data sheet ease-sp-8007-v1.1 3 december 13 th , 2005 ease-pl-8007-0v3 analog functions: - poc characteristics. included a note. flash memory: - included the derivatives pd70f3427 and pd70f3426. package: - included the derivatives pd70f3427 and pd70f3426 - added the package drawings for the derivatives pd70f3427 and pd70f3426. 4 september 4 th , 2006 ease-pl-8007-1v0 redefinition of that document "electrical target specifica- tion" to "preliminary data sheet". family overview: - updated operating clock. operation conditions: - update the cpu clock frequencies. dc-characteristics: - updated the supply-currents for all derivatives. - completion of table 6-23. ac-characteristics: - updated the ac-characteristics for the ext. mem. i/f (pd70f3427). 5 january 18 th , 2007 ease-pl-8007-1v1 dc-characteristics: - included the values for the lcd split voltages - updated the supply-currents for the derivatives pd70f3424, pd70f3426 and pd70f3427. ac- characteristics: - csib updated and expanded characteristics. - lcd bus interface updated. - external memory access updated. analog functions: - added the voltage comparator characteristics stabiliza- tion time. flash memory: - updated parameters for end-of-line programming. included parameters for missing derivatives. special conditions for device operation at extended oper- ating temperature range (t a = -40c ... +105c) - included a new chapter describing the operating condi- tions when device is operating within the extened operating temperature range. item date published document no. comment
98 preliminary data sheet ease-sp-8007-v1.1 although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 taiwan nec electronics taiwan ltd. fax: +886-2-2719-5951 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 01.2 name company from: tel. fax facsimile message
99 preliminary data sheet ease-sp-8007-v1.1 [memo]

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