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| TLE84106EL hex-half-bridge driver ic data sheet, rev. 1.0, april 2010 automotive power
data sheet 2 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.4 power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.4.1 v s undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4.2 v s overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.5 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.1 short circuit of output to supply or ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.2 open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.3 cross-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 status register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 spi bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.1 control - word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3.2 diagnosis - word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents pg-ssop-24-4 type package marking TLE84106EL pg-ssop-24-4 TLE84106EL data sheet 3 rev. 1.0, 2010-04-27 hex-half-bridge driver ic TLE84106EL 1overview features ? 6 half bridge power outputs ? 3.3v / 5v compatible inputs with hysteresis ? independently diagnosable outputs ? 16-bit standard spi interface with daisy chain capability for control and diagnosis ? open load diagnostics in on-state for all outputs ? all outputs with overload and short circuit protection and diagnosis ? overtemperature prewarning and protection ? over- and undervoltage lockout ? cross-current protection ? thermally enhanced exposed pad package ? green product (rohs compliant) ? aec qualified description the TLE84106EL is a protected hex-half-bridge-driver des igned especially for automotive motion control applications such as heating, ventilation and air conditioning (hvac) flap dc motor control. it is par t of the monolythic family in infineon?s smart power technology spt? which combines bipolar and cmos control circuitry with dmos power devices. the 6 half bridge drivers are designed to drive dc motor l oads in sequential or parallel operation. operation modes forward (cw), reverse (ccw), brake and high impedance are cont rolled from a 16-bit spi interface. the diagnosis features such as short circuit, open load, power supply failure and over temperature in combination with its low quiescent current makes this device attractive for automotive applicati ons. the extremely small fine pitch exposed pad pg-ssop-24-4 package in a so -14 body provides good thermal performance and reduces pcb-board space and costs. table 1 product summary operating voltage v s 7 ... 18 v logic supply voltage v dd 3.0 ... 5.5 v maximum supply voltage for load dump protection v s(ld) 40 v minimum overcurrent threshold i sd1-6_motor 0.8 a maximum on-state path resistance at t j = 150 c r dson(total)_hsx+lsy 2 + 2 ? typical quiescent current at t j = 85 c i s (off)) 1a maximum spi access frequency f sclk 5mhz TLE84106EL hex half bridge ic block diagram data sheet 4 rev. 1.0, 2010-04-27 2 block diagram figure 1 block diagram * 1 ' , 1 + & 6 1 6 ' , 6 & / . 6 ' 2 6 3 , , q w h u i d f h % , $ 6 0 2 1 , 7 2 5 8 1 ' ( 5 9 2 / 7 $ * ( 2 9 ( 5 9 2 / 7 $ * ( 0 2 1 , 7 2 5 9 ' ' ( 5 5 2 5 ' ( 7 ( & 7 , 2 1 9 6 & + $ 5 * ( 3 8 0 3 r s h q o r d g g h w h f w l r q f x u u h q w f r q w u r o v k r u w w r e d w w h u \ g h w h f w l r q k l j k v l g h g u l y h u o r z v l g h g u l y h u v k r u w w r e d w w h u \ g h w h f w l r q w h p s v h q v r u r s h q o r d g g h w h f w l r q f x u u h q w f r q w u r o v k r u w w r e d w w h u \ g h w h f w l r q k l j k v l g h g u l y h u o r z v l g h g u l y h u v k r u w w r e d w w h u \ g h w h f w l r q w h p s v h q v r u r s h q o r d g g h w h f w l r q f x u u h q w f r q w u r o v k r u w w r e d w w h u \ g h w h f w l r q k l j k v l g h g u l y h u o r z v l g h g u l y h u v k r u w w r e d w w h u \ g h w h f w l r q w h p s v h q v r u r s h q o r d g g h w h f w l r q f x u u h q w f r q w u r o v k r u w w r e d w w h u \ g h w h f w l r q k l j k v l g h g u l y h u o r z v l g h g u l y h u v k r u w w r e d w w h u \ g h w h f w l r q w h p s v h q v r u r s h q o r d g g h w h f w l r q f x u u h q w f r q w u r o v k r u w w r e d w w h u \ g h w h f w l r q v k r u w w r e d w w h u \ g h w h f w l r q w h p s v h q v r u r s h q o r d g g h w h f w l r q v k r u w w r e d w w h u \ g h w h f w l r q k l j k v l g h g u l y h u o r z v l g h g u l y h u v k r u w w r j u r x q g g h w h f w l r q e l w / r j l f / d w f k 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 w h p s v h q v r u 3 r z h u g u l y h u 3 r z h u v w d j h data sheet 5 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic block diagram figure 2 terms , ' ' 9 ' ' 9 6 ' 2 , 6 ' , , & 6 9 6 , 6 9 ' ' 6 ' 2 6 ' , & 6 9 6 9 6 ' , 9 & 6 9 6 & / . , 6 & / . 6 & / . * 1 ' , * 1 ' 9 , 1 + , , 1 + , 1 + 2 8 7 [ , 2 8 7 [ 9 ' 6 / 6 [ 9 ' 6 + 6 [ , 6 ' 2 7 h u p v h p i TLE84106EL hex half bridge ic pin configuration data sheet 6 rev. 1.0, 2010-04-27 3 pin configuration 3.1 pin assignment figure 3 pin configuration gnd out 2 nc vs2 sclk csn test sdo inh nc out 6 out 4 out 1 out 5 nc sdi vdd test vs1 nc out 3 18 17 16 15 14 13 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd gnd exposed die pad data sheet 7 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic pin configuration 3.2 pin definitions and functions note: all gnd pins must be externally connected toget her to a common gnd potential. all vs pins must be externally connected together to a common vs potential. see figure 17 for more application information. pin symbol function 1 gnd ground 2 out 1 power half-bridge 1 3 out 5 power half-bridge 5 4 nc not connected. this pin can either be left open or connected to ground. 5 sdi serial-data-input 6 vdd logic supply voltage 7 sdo serial-data-output 8 inh inhibit input with internal pull-down; plac e device in standby m ode by pulling the inh line low 9 nc not connected. this pin can either be left open or connected to ground. 10 out 6 power half-bridge 6 11 out 4 power half-bridge 4 12 gnd ground 13 gnd ground 14 out 3 power half-bridge 3 15 nc not connected. this pin can either be left open or connected to ground. 16 vs1 power supply voltage for group 1 supp lying current to out 3, out 4 and out 6. 17 test test input with internal pu ll down. used for production test only. this pin should be left open or connected to ground on board. 18 test test input with internal pu ll down. used for production test only. this pin should be left open or connected to ground on board. 19 csn chip-select-not-input 20 sclk serial clock input 21 vs2 power supply voltage for group 2 supp lying current to out 1, out 2 and out 5. 22 nc not connected. this pin can either be left open or connected to ground. 23 out 2 power half-bridge 2 24 gnd ground edp - exposed die pad; for cooling purposes only; do not use as electrical ground. 1) 1) the exposed die pad at the bottom of the package allows better heat dissipation from the device via the pcb. the exposed die pad is not connected to any active part of the ic. when c onnecting onto pcb, it can either be left floating or connected to gnd for the best emc and thermal performance. TLE84106EL hex half bridge ic general product characteristics data sheet 8 rev. 1.0, 2010-04-27 4 general product characteristics 4.1 absolute maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 c to +150 c 1) not subject to production test, specified by design. pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 supply voltage v s -0.3 40 v v s = v s1 = v s2 4.1.2 logic supply voltage v dd -0.3 5.5 v 0 v < v s < 40 v 4.1.3 logic input voltages (sdi, sclk, csn; inh) v sdi , v sclk , v csn , v inh -0.3 5.5 v 0 v < v s < 40 v 0 v < v dd < 5.5v 4.1.4 logic output voltage (sdo) v sdo -0.3 5.5 v 0 v < v s < 40 v 0 v < v dd < 5.5v currents 4.1.5 continuous supply current for v s1 i s1 01.80a? 4.1.6 continuous supply current for v s2 i s2 01.80a? temperatures 4.1.7 junction temperature t j -40 150 c? 4.1.8 storage temperature t stg -50 150 c? esd susceptibility 4.1.9 esd capability of outx and v s pin v esd -4 4 kv 2) 2) human body model according to ansi eos\esd s5.1 standard (eqv. to mil std 883d and jedec jesd22-a114) 4.1.10 esd capability of other pins v esd -2 2 kv 2) data sheet 9 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic general product characteristics 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage range for normal operation v s(nor) 718v? 4.2.2 extended supply voltage range for operation v s(ext) v uv off v ov off v limit values deviations possible; after v s rising above v uv on 4.2.3 supply voltage slew rate |d v s / d t |? 10 v/s v s increasing and decreasing 1) 1) not subject to production test, specified by design. 4.2.4 logic supply voltage range for normal operation v dd 3.0 5.5 v ? 4.2.5 logic input voltages (di, clk, csn; inh) v di , v clk , v csn , v inh -0.3 5.5 v ? 4.2.6 junction temperature t j -40 150 c? TLE84106EL hex half bridge ic general product characteristics data sheet 10 rev. 1.0, 2010-04-27 4.3 thermal resistance pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case, ta = -40 c r thjc_cold ?4?k/w 1) 1) not subject to production test, specified by design. 4.3.2 junction to case, ta = 85 c r thjc_hot ?5?k/w 1) 4.3.3 junction to ambient, ta = -40 c (1s0p, minimal footprint) r thja_cold_min ?124?k/w 1) 2) 2) specified rthja value is according to jedec jesd51-2,-3 at natural convection on fr 4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 35 m thickness. ta = -40c, ch 1 to ch 6 are dissipating a total of 1.5w (0. 25w each). ta = 85c, ch 1 to ch 6 are dissipating a total of 1.08w (0.18w each). 4.3.4 junction to ambient, ta = 85 c (1s0p, minimal footprint) r thja_hot_min ?103?k/w 1) 2) 4.3.5 junction to ambient, ta = -40 c (1s0p, 300mm2 cu) r thja_cold_300 ?75?k/w 1) 3) 3) specified rthja value is according to jedec jesd51-2,-3 at natural convection on fr 4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boa rd with additional cooling of 300 mm2 copper area and 35 m thickness. ta = -40c, ch 1 to ch 6 are dissipating a total of 1.5w (0.25w each). ta = 85c, ch 1 to ch 6 are dissipating a total of 1.08w (0.18w each). 4.3.6 junction to ambient, ta = 85 c (1s0p, 300mm2 cu) r thja_hot_300 ?60?k/w 1) 3) 4.3.7 junction to ambient, ta = -40 c (1s0p, 600mm2 cu) r thja_cold_600 ?67?k/w 1) 4) 4) specified rthja value is according to jedec jesd51-2,-3 at natural convection on fr 4 1s0p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boa rd with additional cooling of 600 mm2 copper area and 35 m thickness. ta = -40c, ch 1 to ch 6 are dissipating a total of 1.5w (0.25w each). ta = 85c, ch 1 to ch 6 are dissipating a total of 1.08w (0.18w each). 4.3.8 junction to ambient, ta = 85 c (1s0p, 600mm2 cu) r thja_hot_600 ?54?k/w 1) 4) 4.3.9 junction to ambient, ta = -40 c (2s2p) r thja_cold_2s2p ?38?k/w 1) 5) 5) specified rthja value is according to jedec jesd51-2,-3 at natural convection on fr 4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (4 x 35m cu). ta = -40c, ch 1 to ch 6 are dissipating a total of 1.5w (0.25w each). ta = 85c, ch 1 to ch 6 are dissipating a total of 1.08w (0.18w each). 4.3.10 junction to ambient, ta = 85 c (2s2p) r thja_hot_2s2p ?31?k/w 1) 5) data sheet 11 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic general product characteristics 4.4 electrical characteristics electrical characteristics v s = 7 v to 18 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c, inh = high; i out1-6 = 0 a; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. current consumption, inh = gnd 4.4.1 supply quiescent current i sq ?12.5a v s = 13.5 v; v dd = 0 v t j = 85 c 4.4.2 logic supply quiescent current i dd_q ?0.51a t j = 85 c 4.4.3 total quiescent current i sq + i dd_q ?24a t j = 85 c current consumption, inh = high 4.4.4 supply current i s ? 4.5 10 ma power drivers and power stages are off 4.4.5 logic supply current i dd ? 1.5 3 ma spi not active 4.4.6 logic supply current i dd_run ?5?ma v dd = 3.0v; spi 5mhz 4.4.7 total supply current i s + i dd_run ?9.5?ma? over- and undervoltage lockout 4.4.8 uv switch on voltage v uv on ??5.2v v s increasing 4.4.9 uv switch off voltage v uv off 4?5.0v v s decreasing 4.4.10 uv on/off hysteresis v uv hy ?0.25?v v uv on - v uv off 4.4.11 ov switch off voltage v ov off 21 ? 25 v v s increasing; 4.4.12 ov switch on voltage v ov on 20 ? 24 v v s decreasing; 4.4.13 ov on/off hysteresis v ov hy ?1?v v ov off - v ov on ; 4.4.14 v dd power-on-reset v dd por 2.60 2.80 3.00 v v dd increasing 4.4.15 v dd power-off-reset v dd poffr 2.50 2.70 2.90 v v dd decreasing static drain-source on-resistance 4.4.16 high- and low-side switch r dson(1-6) ?0.8? ? i out (1-6) = 0.5 a; t j = 25 c ?1.42 ? i out (1-6) = 0.5 a; t j = 150 c output protection and diagnosis high-side switches 4.4.17 hs overcurrent shutdown threshold i sd_hs -1.6 -1.15 -0.8 a hs switch; v s =13.5v; see figure 7 4.4.18 hs short circuit current limit i sc_hs -2.0 -1.5 -1.0 a 1) 4.4.19 hs_shutdown delay time t dsd 10 25 50 s hs switch; v s =13.5v; see figure 7 TLE84106EL hex half bridge ic general product characteristics data sheet 12 rev. 1.0, 2010-04-27 low-side switches 4.4.20 ls overcurrent shutdown threshold i sd_ls 0.8 1.15 1.6 a ls switch; v s =13.5v; see figure 7 4.4.21 ls short circuit current limit i sc_ls 1.01.52.0a 1) 4.4.22 ls_shutdown delay time t dsd 10 25 50 s ls switch; v s =13.5v; see figure 7 4.4.23 open load detection current i old 3 8 15 ma ls switch; v s =13.5v; see figure 8 4.4.24 open load delay time t dold 200 350 600 s output switching times 4.4.25 high-side on delay-time t donh ?7.512s v s =13.5v, resistive load = 100 ? , see figure 9 and figure 10 4.4.26 high-side off delay-time t doffh ?36s 4.4.27 low-side on delay-time t donl ?6.512s 4.4.28 low-side off delay-time t doffl ?25s 4.4.29 dead time h to l t dhl 1.5 ? ? s 4.4.30 dead time l to h t dlh 2.5 ? ? s 4.4.31 high-side risetime t onh ?4?s 4.4.32 high-side fall time t offh ?2?s 4.4.33 low-side risetime t offl ?1?s 4.4.34 low-side fall time t onl ?1?s input interface, logic inputs inh 4.4.35 high-input voltage v inhh 70 ? ? % v dd ? 4.4.36 low-input voltage v inhl ??30% v dd ? 4.4.37 hysteresis of input voltage v inhhy 50 200 500 mv ? 4.4.38 pull down resistor r pd_inh ? 120 ? k ? ? spi interface delay time from sleep mode to first data in 4.4.39 setup time t set ??100s 1) 4.4.40 time between two consecutive srr commands t srr 100 ? ? s 1) input interface, logic inputs sdi, sclk, csn 4.4.41 high-input voltage v ih 70 ? ? % v dd ? 4.4.42 low-input voltage v il ??30% v dd ? 4.4.43 hysteresis of input voltage v ihy 50 200 500 mv ? 4.4.44 pull up resistor at pin csn r pu_csn ? 140 ? k ? ? 4.4.45 pull down resistor at pin sdi, sclk r pd_sdi, r pd_sclk ? 120 ? k ? ? electrical characteristics (cont?d) v s = 7 v to 18 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c, inh = high; i out1-6 = 0 a; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. data sheet 13 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic general product characteristics 4.4.46 input capacitanc e at pin csn, sdi or sclk c i ? 1015pf0v < v dd < 5.25v 1) input interface, logic outputs sdo 4.4.47 high-output voltage v sdoh v dd - 1.0 v dd - 0.7 ?v i sdoh = -1 ma 4.4.48 low-output voltage v sdol ?0.20.4v i sdol = 1.6 ma 4.4.49 tri-state leakage current i sdolk -10 ? 10 a v csn = v dd 0v < v sdo < v dd data input timing. see figure 12 and figure 15 4.4.50 sclk frequency f clk ??5mhz 1) 4.4.51 sclk period t pclk 500 200 ? ? ? ? ns ns v dd = 5.25v v dd = 3.0v 1) 4.4.52 sclk high time t sclkh 85 ? ? ns 1) 4.4.53 sclk low time t sclkl 85 ? ? ns 1) 4.4.54 sclk setup time t lag 85 ? ? ns 1) 4.4.55 sdi setup time t sdi_setup 50 ? ? ns 1) 4.4.56 sdi hold time t sdi_hold 50 ? ? ns 1) 4.4.57 csn setup time t lead 100 ? ? ns 1) 4.4.58 csn high time t csnh 500 ? ? ns 1) 2) 4.4.59 input signal rise time at pin sdi, sclk, csn t rin ??50ns 1) 4.4.60 input signal fall time at pin sdi, sclk, csn t fin ??50ns 1) data output timing. see figure 14 and figure 15 4.4.61 sdo rise time t rsdo ? 1025nsc load = 40pf 1) 4.4.62 sdo fall time t fsdo ? 1025nsc load = 40pf 1) 4.4.63 sdo valid time t vasdo ? 2050ns v sdo < 0.2 v dd v sdo > 0.7 v dd c load = 40pf 1) 4.4.64 sdo enable time after csn falling edge t ensdo ? ? 50 ns low impedance 1) 4.4.65 sdo disable time after csn rising edge t dissdo ? ? 50 ns high impedance 1) 4.4.66 duty cycle of incoming clock at sclk duty sclk 40 ? 60 % 1) electrical characteristics (cont?d) v s = 7 v to 18 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c, inh = high; i out1-6 = 0 a; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. TLE84106EL hex half bridge ic general product characteristics data sheet 14 rev. 1.0, 2010-04-27 thermal prewarning & shutdown 4.4.67 thermal warning junction temperature t jw_enter 120 140 170 csee figure 6 1) 4.4.68 thermal warning junction temperature - switch off t jw_exit 90 ? 140 c 4.4.69 temperature warning hysteresis ? t jw ?30?k 4.4.70 thermal shutdown junction temperature t jsd 150 175 200 c 4.4.71 thermal switch-on junction temperature t jso 130 ? 180 c 4.4.72 temperature shutdown hysteresis ? t jsd ?20?k 4.4.73 ratio of sd to w temperature t jsd / t jw 1.05 1.20 ? ? 1) not subject to production test, specified by design 2) csn high time : this is the minimum time the user must wait between spi commands electrical characteristics (cont?d) v s = 7 v to 18 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c, inh = high; i out1-6 = 0 a; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. data sheet 15 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic block description 5 block description 5.1 general 5.2 power supply 5.2.1 general the TLE84106EL has two power supply inputs: the half bridge outputs are connected to v s supply, which is connected to the 12v automotive supply rail. the internal logic part is supplied by a separate voltage v dd = 5 v. v s and v dd supplies are separated so that information stored in the logic block remains intact in the event of voltage drop outs or disturbances on v s . the system can therefore continue to operate once v s has recovered, without having to resend commands to the device. a rising edge on v dd triggers an internal power-on reset (por) to initialize the ic at power-on. all data stored internally is deleted, and the outputs are switched to high-impedance status (tristate). a 10f electrolytic and 100nf ceramic capacitor are recommended to be placed as close as possible to the v s supply pin of the device for improved emc performance in the high and low frequency band. 5.2.2 sleep mode the TLE84106EL enters low power mode (or sleep mode) by setting the inh input to low. the inh input has an internal pull-down resistor. in sleep-mode, all output trans istors are turned off and the spi register banks are reset. 5.2.3 reverse polarity protection the TLE84106EL requires an external reverse polarity pr otection. during reverse polarity, the freewheeling diodes across the half bridge output will begin to conduct, causi ng an undesired current flow ( i rb ) from ground potential to battery and excessive power dissipation across the di odes. as such, a reverse polarity protection diode is recommended (see figure 4 ). figure 4 reverse polarity protection 5.2.4 power supply monitoring the power supply rails v s and v dd are monitored for over- and undervoltage. see figure 5 . 9 6 2 8 7 [ * 1 ' + 6 [ / 6 [ , 5 % 9 6 2 8 7 [ * 1 ' + 6 [ / 6 [ 7 / ( [ ( / 7 / ( [ ( / d e ' = 6 & 6 ' 5 3 & 6 TLE84106EL hex half bridge ic block description data sheet 16 rev. 1.0, 2010-04-27 5.2.4.1 v s undervoltage if the supply voltage v s drops below the switch off voltage v uvoff , all output transistors are switched off but logic information remains intact and uncorrupted. the ?undervol tage? (power supply fail, psf) error bit is flagged and can be read out via spi. once v s rises again and reaches the threshold switch on voltage v uvon , the power stages are restarted and the psf error bit is reset. 5.2.4.2 v s overvoltage if the supply voltage v s rises above the switch off voltage v ovoff , all output transistors are switched off and the ?overvoltage? (psf) error bit is set. the error is not latched, i.e. if v s falls again and reaches the switch on voltage v ovon , the power stages are restarted and the error flags are reset. figure 5 output behavior during over- and undervoltage v s condition 5.2.5 reset behavior the following reset triggers have been implemented in the TLE84106EL:- v dd undervoltage reset: the spi interface shall not function if v dd is below the undervoltage threshold, v dd poffr . the digital block will be initialized. the output stages are switched off to hig h-z. the undervoltage reset and srr is released once v dd voltage levels are above the undervoltage threshold, v dd por . reset on inh pin: if the inh pin level is low, the device shall ente r reset and the current consumption is reduced to i sq + i dd_q . v outx v uvoff v uvon v uvhy t t v s under - voltage output & error flag behaviour v ovhy v ovon v ovoff over-voltage output & error flag behaviour on high z psf error bit t high low data sheet 17 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic block description 5.3 temperature monitoring temperature sensors are integrated in the power stage s. the temperature monitoring circuit compares the measured temperature to the warning and shutdown thre sholds. if one or more temperature sensors reach the warning temperature, the temperature warn ing bit, tw is set to high. this bit is not latched (i.e. if the temperature falls below the warning threshold (with hyster esis), the tw bit is reset to low again). if one or more temperature sensors reach the shut-dow n temperature threshold, a ll outputs are shut down and latched (i.e. the output stages remain off until an srr command is sent or a power-on reset is performed). see figure 6 . figure 6 overtemperature behavior v outx t t on high z t j no error ? t jso t jsd t jw_enter tw error bit t high low no error error flag is reset automatically t jw _ex it sd ? jw output is switched off if tj sd is reached and can only be reset via srr TLE84106EL hex half bridge ic block description data sheet 18 rev. 1.0, 2010-04-27 5.4 protection and diagnosis this device features embedded protective functions wh ich are designed to prevent ic destruction under fault conditions described in the following sections. fault conditions are treat ed as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 5.4.1 short circuit of ou tput to supply or ground the high-side switches are protected against short to grou nd where as the low-side swit ches are protected against short to supply. if a switch is turned on and the current rises above the overcurrent shutdown threshold, i sd for longer than the shutdown delay time t dsd , the output transistor is turned off and the co rresponding diagnosis bit, oc, is set. during this delay time, the current is limited to i sc as shown in figure 7 . the output stage remains off and the error bit remains set until a status register reset is sent to the spi or a power-on reset is performed. .. figure 7 high-side and low-side switch - short circuit and overcurrent protection 5.4.2 open load open-load detection in on-state is implemented in the lo w-side switches of the bridge outputs: if the current through the low side transistor is lower than the reference current i old in on-state for longer than the open-load detection delay time t dold , the corresponding open-load, ol diagnosis bit is set. the output transistor, however, remains on. the open load error bit is latched and can be reset by the spi status register reset or by a power-on reset. as an example, if a motor is connected between ou tputs out 1 and out 2 with a broken wire as shown in figure 8 , the resulting diagnostic information is shown in table 2 . open load detection shutdown (ol sd en) bit via the control register can be ac tivated or deactivated as required. if the ol sd en bit is set and an open load on the low-side switch is detect ed, the respective output is disabled. the error remains latched and output is off unt il an srr or power on reset is performed. this has the added advantage of independently diagnosing and isolat ing error flags to the corresponding failed output. w g 6 ' , 6 & w 2 8 7 [ v k r u w w r * 1 ' 6 k r u w f r q g l w l r q r q + l j k r u / r z 6 l g h 6 z l w f k , + 6 b / 6 v k r u w w r 6 x s s o \ 9 v , 6 ' data sheet 19 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic block description figure 8 open load example table 2 open load diagnosis example 5.4.3 cross-current in bridge configurations the high-side and low-side powe r transistors are ensured neve r to be simultaneously ?on? to avoid cross currents. this is realized by integrating de lays in the driver stage of the power outputs, intended to create a dead-time between switching off one power transi stor and switching on of th e other power transistor of the same half-bridge. to ensure that there is no overlap of the switching slopes that would lead to a cross current, the dead-times, t dhl and t dlh are specified. in the event a cross-current has occurred, the device shall turn off both switches and the overcurrent bit is set high. m out 1 out 2 open load control diagnostic information motor connected motor disconnected open load detection (opld) error flag ls1 on hs1 on ls2 on hs2 on motor rotation ls1 opl ls2 opl ls1 opl ls2 opl 0 0 0 0 motor off 0 0 0 0 de-activated 1 0 0 1 clock-wise 0 0 1 0 activated 0 1 1 0 counter clock-wise 0 0 0 1 activated 0 1 0 1 brake high 0 0 0 0 de-activated 1010brake low 1111activated TLE84106EL hex half bridge ic block description data sheet 20 rev. 1.0, 2010-04-27 figure 9 timing bridge outputs high to low figure 10 timing bridge outputs low to high w g 2 ) ) + 2 8 7 [ & 6 1 2 8 7 [ w g 2 1 / w ' + / 2 ) ) 2 1 ! 2 ) ) 2 ) ) 2 ) ) ! 2 1 w 2 ) ) + + l j k 6 l g h r i i g h o d \ w l p h / r z 6 l g h r q g h o d \ w l p h w 2 1 / w g 2 ) ) / 2 8 7 [ & 6 1 2 8 7 [ w g 2 1 + w ' / + 2 ) ) 2 ) ) w 2 1 + w 2 ) ) / + l j k 6 l g h r q g h o d \ w l p h / r z 6 l g h r i i g h o d \ w l p h 2 1 ! 2 ) ) 2 ) ) ! 2 1 data sheet 21 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic spi 6spi 6.1 general the spi is used for bidirectional communication with a control unit. the TLE84106EL acts as spi-slave and the control unit acts as spi-mas ter. the 16-bit control word is read via the sdi serial data in put. the status word appears synchronously at the sdo serial data output. the communication is synchronized by the serial clock input sclk. standard data transfer timing is shown in figure 11 . the clock polarity is data valid on falling edge. sclk must be low during csn transition . the transfer is msb first. the transmission cycle begins when the ch ip is selected with the chip-select- not (csn) input (h to l). then the data is clocked through the shift regi ster. the transmission ends when the csn input changes from l to h and the word which has been read into the shift register beco mes the control word. the sd o output switches then to tristate status, thereby releasing the sd o bus circuit for other uses. the spi allows to parallel multiple spi devices by using multiple csn lines. the spi can also be used with other spi-devices in a daisy-chain configuration. the control word transmitted from the master to the tle 84106el is executed at the end of the spi transmission ( csn l -> h ) and remains valid until a different control word is transmitted or a power on reset occurs. at the beginning of the spi transmission ( csn h -> l ), the di agnostic data currently valid are latched into the spi and transferred to the master. data integrity is maintained by polling multiples of 8 data bits to ensure that a valid command has been received. figure 11 spi data transfer protocol 6 ' , 6 & / . & 6 1 & 6 1 + l j k w r / r z u l v l q j h g j h r i 6 & / . 6 ' 2 l v h q d e o h g 6 w d w x v l q i r u p d w l r q l v w u d q v i h u h g w r 2 x w s x w 6 k l i w 5 h j l v w h u & 6 1 / r z w r + l j k ' d w d i u r p 6 k l i w 5 h j l v w h u l v w u d q v i h u h g w r 2 x w s x w ' u l y h u / r j l f s u h y l r x v v w d w x v f x u u h q w g d w d 6 ' , ' d w d z l o o e h d f f h s w h g r q w k h i d o o l q j h g j h r i & / . 6 l j q d o 6 ' 2 6 w d w h z l o o f k d q j h r q w k h u l v l q j h g j h r i & / . 6 l j q d o w l p h q h z g d w d f x u u h q w v w d w x v 6 ' 2 0 6 % / 6 % TLE84106EL hex half bridge ic spi data sheet 22 rev. 1.0, 2010-04-27 figure 12 spi sclk and csn figure 13 inh and sdi figure 14 spi sdo and csn & 6 1 6 & / . w o d j w o h d g w 6 & / . + w 6 & / . / w o d j w & 6 1 + w o h d g inh t set sdi & 6 1 w ' , 6 6 ' 2 w ( 1 6 ' 2 6 ' 2 data sheet 23 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic spi figure 15 spi sdi, sdo and sclk 6.2 status register reset the spi is using a standard shift-regi ster concept with daisy-ch ain capability. any data transmitted to the spi will be available to the internal logic part at the end of the spi transmission (csn l -> h). to read a specific register, the address of the register is sent by the master to the spi in a first spi frame. the data that corresponds to this address is transmitted by the sdo during the following (sec ond) spi frame to the master. the default address for status register transmission after power-on reset is 0. the status-register-reset command-bit is executed after the next spi transmission. the two bits, address register and srr act as command to read and reset (or not reset) the addressed status-register. the request and response behaviour of the spi is further illustrated in figure 16 below. figure 16 status register reset 6 & / . w 9 $ 6 ' 2 6 ' 2 w 6 ' , b v h w x s w 6 ' , b k r o g 6 ' , csn sclk sdi sdo request 1 request 2 request 3 response 0 response 1 response 2 srr 1 srr 2 srr 3 TLE84106EL hex half bridge ic spi data sheet 24 rev. 1.0, 2010-04-27 6.3 spi bit definitions 6.3.1 control - word control register overview 1514131211109876543210 srr 0 ol_sd _en act_ hb6 act_ hb5 act_ hb4 act_ hb3 act_ hb2 act_ hb1 conf_ hb6 conf_ hb5 conf_ hb4 conf_ hb3 conf_ hb2 conf_ hb1 0 bit control register - locate control register - description diagnosis control 15 srr (all channels) status register reset (srr). if set to high, the errors bits of the co responding status register are reset on the rising edge of csn if sent to the uc. low indicates no reset. 14 0 set to 0 to select hb 1 to 6 13 ol sd en (all channels) open load detection shutdown enable (o l sd en) allows the affected output stage to be switched off if a true open load or underload condition has been detected. this feature can be activated or deactivated by bit 13. activate half-bridge x 12 act_hb 6 h => half bridge 6 is active l => half bridge 6 is in hi-z 11 act_hb 5 h => half bridge 5 is active l => half bridge 5 is in hi-z 10 act_hb 4 h => half bridge 4 is active l => half bridge 4 is in hi-z 9 act_hb 3 h => half bridge 3 is active l => half bridge 3 is in hi-z 8 act_hb 2 h => half bridge 2 is active l => half bridge 2 is in hi-z 7 act_hb 1 h => half bridge 1 is active l => half bridge 1 is in hi-z configure half-bridge x 6 conf_hb 6 h => hsd6 = on & lsd6 = off l => hsd6 = off & lsd6 = on 5 conf_hb 5 h => hsd5 = on & lsd5 = off l => hsd5 = off & lsd5 = on 4 conf_hb 4 h => hsd4 = on & lsd4 = off l => hsd4 = off & lsd4 =on 3 conf_hb 3 h => hsd3 = on & lsd3 = off l => hsd3 = off & lsd3 = on 2 conf_hb 2 h => hsd2 = on & lsd2 = off l => hsd2 = off & lsd2 = on 1 conf_hb 1 h => hsd1 = on & lsd1 = off l => hsd1 = off & lsd1 = on 0 0 least significant bit (lsb) is set to low data sheet 25 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic spi 6.3.2 diagnosis - word note: status hbx represents status of half-bridge driver and not status of control register. note: the psf and tw bits in the first diagnosis word will reflec t the current clock cycle st atus, all other remaining bits are 0. diagnosis register overview 1514131211109876543210 oc psf ol sact_ hb6 sact_ hb5 sact_ hb4 sact_ hb3 sact_ hb2 sact_ hb1 sconf _hb6 sconf _hb5 sconf _hb4 sconf _hb3 sconf _hb2 sconf _hb1 tw table 4 output (status) data register bit status register - locate status register - description 15 oc (all channels) overcurrent error is set if any one of the half-bridges has an overload, short circuit or cross current; the error is latched and the corresponding output is switched off; bit 15 error can only be reset via srr or power-on reset. 14 psf (all channels) power supply failure; bit 14 is set if v s has an overvoltage or undervoltage condition; all outputs are switched off. bit 14 is automatically reset if v s returns to its normal operating range. 13 ol (all channels) open load error is set if any one of the half-bridges has a true open load or underload error condition; the error is latched. the corresponding output is switched off if bit 13, ol sd en of the co ntrol register is activated or high. bit 13 error can only be reset via srr or power-on reset. activated driver status of half-bridge x 12 sact_hb 6 h => half bridge 6 is active l => half bridge 6 is in hi-z 11 sact_hb 5 h => half bridge 5 is active l => half bridge 5 is in hi-z 10 sact_hb 4 h => half bridge 4 is active l => half bridge 4 is in hi-z 9 sact_hb 3 h => half bridge 3 is active l => half bridge 3 is in hi-z 8 sact_hb 2 h => half bridge 2 is active l => half bridge 2 is in hi-z 7 sact_hb 1 h => half bridge 1 is active l => half bridge 1 is in hi-z configured driver status of half-bridge x 6 sconf_hb 6 h => hsd6 = on & lsd6 = off l => hsd6 = off & lsd6 = on 5 sconf_hb 5 h => hsd5 = on & lsd5 = off l => hsd5 = off & lsd5 = on 4 sconf_hb 4 h => hsd4 = on & lsd4 = off l => hsd4 = off & lsd4 = on 3 sconf_hb 3 h => hsd3 = on & lsd3 = off l => hsd3 = off & lsd3 = on 2 sconf_hb 2 h => hsd2 = on & lsd2 = off l => hsd2 = off & lsd2 = on 1 sconf_hb 1 h => hsd1 = on & lsd1 = off l => hsd1 = off & lsd1 = on 0 tw thermal warning bi t; global error flag; this bit is treated as an early warnin g and will be set to high if the junction temperature reaches tjw. the output remains on until one or more sensors reaches tsd causing all outputs to be switched off simultaneously. bit 0 is automatically reset if the junction temperature cools down to tjso d i st ri b u t i o n b y m a r ke t i n g o n l y TLE84106EL hex half bridge ic application information data sheet 26 rev. 1.0, 2010-04-27 7 application information note: the following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. the function of the described circuits must be verified in the real application. 7.1 application diagram figure 17 application example for dc-motor loads for optimum emc performance, a ferrite is recommended to be placed in series and as close as possible to the vdd line of the tle841xy device. this is shown in the a bove application diagram example. the ferrite should have an impedance of 1000ohm at an effective frequency of 100mhz frequency. a recommended ferrite is the mmz1608 type series available in a geometry size of 0603 with a dc resistance of 0.6ohm and allowable dc current of 190ma. 9 6 2 8 7 2 8 7 2 8 7 2 8 7 * 1 ' 0 0 0 2 8 7 2 8 7 9 ' ' , 1 + 6 ' 2 6 ' , & 6 6 & / . ? & $ 1 + q ) ? & $ 1 / & $ 1 + & $ 1 / 6 3 / , 7 6 9 % $ 7 n ? : . q ) 9 n ? : . ; & 6 ' 2 6 ' , & 6 6 & / . 9 & & 9 & & + 6 & $ 1 ? ) , 1 7 5 2 9 6 9 % $ 7 9 % $ 7 9 6 9 & & 9 ' ' ' = 9 ? ) q ) 7 / ( 7 / ( q ) * 1 ' * 1 ' n ? 9 ' ' p r w r u v l q q r q f d v f d g h g f r q i l j x u d w l r q 0 0 0 0 0 p r w r u v l q f d v f d g h g f r q i l j x u d w l r q 0 0 = ? ) data sheet 27 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic application information d i st ri b u t i o n b y m a r ke t i n g o n l y 7.2 thermal appli cation information ta = -40c, ch 1 to ch 6 are dissipating a total of 1.5w (0.25w each). ta = 85c, ch 1 to ch 6 are dissip ating a total of 1.08w (0.18w each). figure 18 zthja curve for different pcb setups figure 19 zthjc curve zth-ja curves for tle 84106el (6 channels on) 0 15 30 45 60 75 90 105 120 135 0,00001 0,0001 0,001 0,01 0,1 1 10 100 1000 10000 pulse [sec] zth-ja [k/w] -40c; 1s0p + 600 mm2 -40c; 1s0p + 300 mm2 -40c; 1s0p +footprint -40c; 2s2p +85c; 1s0p + 600 mm2 +85c; 1s0p + 300 mm2 +85c; 1s0p + footprint +85c; 2s2p zth-jc curves for tle 84106el (6 channels on) 0 1 2 3 4 5 0,00001 0,0001 0,001 0,01 0,1 1 10 100 1000 pulse [sec] zth-jc [k/w] ta = -40c ta = +85c d i st ri b u t i o n b y m a r ke t i n g o n l y TLE84106EL hex half bridge ic application information data sheet 28 rev. 1.0, 2010-04-27 figure 20 board setup board setup based on jesd 51-3, -7 fr4 pcb with 35m cu. 1s0p + 600mm2 cooling area 2s2p / 1s0p + foot print data sheet 29 rev. 1.0, 2010-04-27 TLE84106EL hex half bridge ic package outlines 8 package outlines figure 21 pg-ssop-24-4 (plastic/plastic green - dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-24-4-po v01 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 ?.1 c 0.1 a-b 2x 0.65 0.25 2) m c 0.2 d 24x ?.05 a-b b a index marking c (1.47) 1.7 max. 0.08 c seating plane ?.1 3.9 1) 0.35 x 45? ?.25 0.64 ?.2 d 6 m 0.2 d +0 -0.1 0.1 stand off +0.06 0.19 8? max. cd 2x 0.1 bottom view 24 1 6.4 ?.25 2.65 13 12 ?.25 you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm TLE84106EL hex half bridge ic revision history data sheet 30 rev. 1.0, 2010-04-27 9 revision history 0.30.40.3 TLE84106EL revision history: rev. 1.0, 2010-04-27 version subjects (major changes since last revision) 1.0 final data sheet release edition 2010-04-27 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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