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downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:40 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 1 document id: pmc-1990553, issue 4 PM7325 s/uni?-atlas-3200 2488 mbit/s saturn? user network interface atm layer solution data sheet proprietary and confidential preliminary issue 4: june 2001
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 document id: pmc-1990553, issue 4 legal information copyright ? 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce any part of this document, in any form, without the express written consent of pmc-sierra, inc. pmc-1990553 (p4) disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks s/uni is a registered trademark of pmc-sierra, inc. pos-phy and sci-phy are trademarks of pmc-sierra, inc. patents relevant patent applications and other patents may also exist .
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 document id: pmc-1990553, issue 4 contacting pmc-sierra pmc-sierra 8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 document id: pmc-1990553, issue 4 public revision history issue no. issue date details of change 1 draft 1 draft 2 draft 3 draft 4 draft 5 may 1999 june 1999 aug 1999 aug 1999 sep 1999 initial draft. added detailed functional description, register listing,functional timing. aligns with newest 2-chip embedded-dram solution. corrected and updated information on ul3 and pos interfaces, per-phy counting, packet bypass, routing of aps cells. added operations section. tat and phytat increased to 34 bits. backwards vcra and phyid moved to linkage row to help make room. policing reserved moved to row 1 and parity to row 0, also to make room. frame counts added to per-phy policing. core logic voltage changed to 1.8v. i/o voltage clarified to be 3.3v. parity added on address of sram as well as data. pin and block diagrams corrected. phyid added to secondary key. field b expanded from 11 to 12 bits. unused bits in search table and linkage row redistributed to easily accommodate future expansion. drop_vc does not permit the generation any cells on that connection, whether to ocif or bcif. operation of mcr in gfr policing clarified to explicitly state that mcr operations are performed on frame boundaries only. auto_rdi becomes a per-vc bit. dram bank number changed to the 2 lsbs of the vcra rather than the 2 msbs. per- phy counts updated to include counts of efci and timed-out cells. sram, dram, per-phy policing, and pm microprocessor accesses adjusted to access entire records at once, and to have per-field write and clear-on-read masks. basic description of dram and sram bandwidth allocation added. gen_halfsecclk bit moved to cp. slow background processing interrupt added. capability to switch input bcif to slave mode for use with testers added. placement of interrupts in utopia/pos and sdq blocks changed. burst length set to a maximum of 256 bytes. buffer available thresholds set to a max of 511 bytes. package changed from 432 tbga to 576 tbga to add power/ground balls. documented separate 1.5v supply for the dram. lower bound of temperature range changed to 0 degrees c. address map adjusted for easier decode. added aps cell routing back in.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 document id: pmc-1990553, issue 4 issue no. issue date details of change 2 feb 2000 core logic changed to 1.5v. vc table parity replaced with crc-10. ?bwd pm pending? bit extended for use with fwd pm permission cells. vprmsel replaced with the more descriptive vp_rm_pti6. search key diagrams corrected of typos. added 1 reserved bit to source field of count rollover fifo. fixed tpu_addr signal in figure 6. fixed pm ram access clearonrd defaults. removed dma request enable. moved dmareqinv to the mcif. renamed all references to dma req correctly. added upurs_to_ocif. added 1 bit to cell type field of upurs and bcif causation words to add many more cell types. deleted 1 bit from source id of the bcif causation word to make room. changed all references to autoais to auto_ais to ensure consistency. added apstobcif and actdetobcif bits. inactivetoup applies to connections disabled due to crc errors. bwd lb cells are not routed to the micro at flow end-points unless the source id matches the programmed loopback location id, unless the bwd_lb_to_up_at_end bit is logic 1. xclk added to clock activity monitor. device now powers-up in reset, must be held there to allow the dram to settle for 200 us. per-phy counting bit descriptions of cnt_inv_oam and cnt_rsvd_vci_pti corrected. added vpc counting. added policing rollover fifo enable bits. added free[7:0]. added lbtoocif. added rxphytxphy internal test bit. made maximum frame length test disabled if mfl = all ones, to match atlas. added feature for allowing cc alarms to not generate cos entries, via the oam config status bit. added a globally enabled feature that permits bwd pm cells to carry the fwd pm cell?s time stamp, if the bwd pm cell is able to be generated immediately. added don?t- touch designation for oc-48c cascading. sdq register map substantially reorganized. meanings of buffer available and data available thresholds changed slightly. sdq per-phy counts reduced to 4 bits; aggregate cell count increased to 32 bits. added generic names for ul3/pl3 pins for easier reference. inbandaddr function added to pl3 blocks to accommodate single-phy operation. updated sram configuration diagrams and descriptions to reflect xclk/sclk_o/sysclk scheme. updated sram ac and functional timing to illustrate relationship of sclk_o, sysclk. reduced vc depth to 64k vcs from 128k vcs. updated pl3 pin descriptions to match latest pos-phy release (release 4). added pl3/ul3 ac timing. clarified the meaning of ?noting? non-compliant cells in policing by saying ?just counted?. documented fact that packet counting is based on clp of eom. updated references to other documents (atlas, ul3, i.610). corrected formatting of cos fifo, and simplified the bit description. corrected the reset value of per-phy processing enable register 2.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 document id: pmc-1990553, issue 4 issue no. issue date details of change 3 oct 2000 clarified that upurs_to_ocif overrides xprepo, and that proc_cell or process_phy overrides xprepo. absolute maximum ratings updated (sram interface specced relative to vdd25; absolute min voltage changed to ?0.3, absolute max to vddx+0.3, max current on pins reduced to 10ma). clarified translation options to bcif. added mkt_num register in id register. added dropped-cells counter on mcif. added note that reserved fields in the search and linkage tables must be programmed to logic 0 for proper operation. adjusted format of count rollover fifo. added extra notes about the restriction on the 2 lsbs of the vpc pointer. changed inact_on_par_err to inact_on_dram_err. corrected rxl, txl indirect address register. increased min prop delay on ul3/pl3 to 1.5 ns. changed package from 576 to 768 tbga. split sclk_o into sysclk_o and sramclk_o. added timeout_to_up bit to register 0x100. renamed ais_vpc to sending_ais. changed cos fifo description to show all bits. renamed a few of the cp interrupts to have more expressive names. clarified that returned lb cells are translated like other generated cells (rdi and bwd pm). renamed f4tof5ais to f4tof5oam to reflect the fact it controls both ais and rdi. clarified the difference between block_ptr and fifo_number in the sdq configuration description. clarified that ete loopback cells are looped back at end-to-end points if their llid = all 1, or if it matches the llid of the end point. modified sat_pm_bip16 to sat_fast_pm_counts and made it affect the lost pm cell counts as well. changed drop_vc to have no effect on the generation of oam cells to the bcif. f5 ais cells due to f4 ais carry the f4 ais defect location/type. when f4-to-f5, per-phy or cc ais is generated, then if atlas is within a segment for that vc, both segment and ete ais are generated. changed ?scsb? to ?sceb? for consistency. fixed an inconsistency in fm_interrupt_enable naming. corrected description of efci count. updated pm documentation to better reflect behavior with secbs. added documentation that count rollover for lost pm cell counts can be suppressed. corrected definition of reserved vpi/vci. clarified allowable settings of action 1 and action 2 in gfr policing. note added that 2.5v i/os are not 3.3v tolerant. sdq register map and configuration dramatically simplified: eliminated fifo numbers, buffer thresholds become fixed, banks eliminated, block size increased, starting point restrictions removed, interrupts reorganized. sdq per-phy cell counter measures fill level rather than throughput. updated the txlink documentation. produced much more precise definitions of ptpa and stpa on both input and output. bwd vcra moved from linkage row to vc table row 0. added bcif ac timing. rdb low to microprocessor data valid propagation delay increased to 30 ns. rdb high to microprocessor data tristate extended to 13 ns. wrb high to microprocessor data hold time extended to 3 ns. sramclk_o to sram output data and control valid extended from 4.5 to 5.5 ns (sram setup is 1.5 ns, allowing 1 ns slack). added minimum xclk frequency. power tolerances set to 0.3v on 3.3v power, 0.2v on 2.5v power, 0.075 on 1.5v power. added per-vp policing.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 document id: pmc-1990553, issue 4 issue no. issue date details of change 4 revealed cos_cc_dis bit. changed atm_field default to 0x00. documented the fact that micro accesses can take as long as 40 cycles (for a read) or 90 cycles (for a write) in certain unusual cases. ibcif and obcif default to odd parity, not even parity. phy and link blocks should be left in their default state when not being used. typo to insrst corrected. direction of obcif, ibcif clocks in figures 5,6,7,8 corrected. insrdy documentation corrected to say that insrdy stays high until a full cell has been written in. halfsecclk input pin description altered to point correctly to the gen_halfsecclk bit. documented the proper default state for the one-second cc, ais, and failure counts. updated boundary scan description to match bsdl notation. clarified that sdq, phy, and link interrupts are only asserted for interrupts that are enabled at the tsb level. clarified that min freq for icif_clk and ocif_clk is 75 mhz, but that full bandwidth is only guaranteed at 104 mhz. block size of 1 in bypass sdq explicitly not supported. obcif dropped-cells counter exposed, with a comment about the total bcif capacity. vc_to_bcif documented with the overflow mechanism. rxphy calendar now states that it should be set to at least 64 entries, and preferably as close to 128 entries as possible, for maximum efficiency. clarified that lbtoocif also overrides discarding due to lb_route functionality. clarified dllrun bit functionality. deleted xfererrtoup function; parity errors and rlp_err/tpp_err indications have no effect on atm cells (beyond the assertion of an interrupt for a parity error). recommended that the flush bit be set for all disabled fifos, to eliminate spurious interrupts. clarified that cntundefoam has no effect on oamerri. increased maximum secondary search depth to 18. changed pl3 loading to 30 pf to match the pl3 standard. changed voltage rail spec. to +/-5%. clarified that fm_to_up does not control loopback cells, since lb_route does this. added tm0 details. added thermal information. specified max power at 3.0 w. input high current respecified to ?15 ua/+650 ua on 3.3 v interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 document id: pmc-1990553, issue 4 table of contents public revision history........................................................................................................ 4 table of contents.............................................................................................................. ...8 list of registers.............................................................................................................. ...12 list of figures ................................................................................................................ ....18 list of tables................................................................................................................. .....20 1 definitions ................................................................................................................... 22 2 features ...................................................................................................................... 25 2.1 policing..............................................................................................................27 2.2 performance management ...............................................................................28 2.3 cell counting.....................................................................................................29 3 applications.................................................................................................................3 0 4 references..................................................................................................................31 5 application examples..................................................................................................32 5.1 cascading .........................................................................................................32 5.2 ram configurations ..........................................................................................33 6 block diagram.............................................................................................................34 7 description ..................................................................................................................3 5 8 pin diagram ................................................................................................................38 9 pin description ............................................................................................................45 10 functional description ................................................................................................63 10.1 input and output interfaces ..............................................................................63 10.1.1 ingress mode with utopia level 3 signaling .....................................63 10.1.2 egress mode with utopia level 3 signaling ......................................65 10.1.3 ingress mode with pos-phy level 3 signaling ..................................66 10.1.4 egress mode with pos_phy level 3 signaling ..................................68 10.1.5 polling and servicing calendar ............................................................69 10.1.6 phy mapping .......................................................................................71 10.1.7 scalable data queue ...........................................................................71 10.1.8 packet-bypass mode ...........................................................................72 10.1.9 atm cell format ..................................................................................72 10.2 connection identification...................................................................................73 10.2.1 search table data structure ................................................................77 10.3 vc linkage table ..............................................................................................79
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 document id: pmc-1990553, issue 4 10.4 vc record table ...............................................................................................80 10.5 cell processing .................................................................................................80 10.6 header translation............................................................................................90 10.7 cell rate policing..............................................................................................91 10.7.1 per-vc policing ....................................................................................91 10.7.2 per-phy policing..................................................................................98 10.7.3 guaranteed frame rate policing.......................................................101 10.8 cell counting...................................................................................................103 10.9 operations, administration and maintenance (oam) cell servicing ..............104 10.9.1 fault management cells ....................................................................105 10.9.2 loopback cells...................................................................................107 10.9.3 activation/deactivation cells..............................................................107 10.9.4 system management cells ................................................................107 10.9.5 automated protection switching cells ...............................................108 10.9.6 resource management cells.............................................................108 10.10 f4 to f5 oam processing...............................................................................108 10.11 f5 to f4 oam processing............................................................................... 116 10.12 constraints on f5 and f4 vc table record addresses ................................. 116 10.13 background processes ................................................................................... 117 10.14 performance management ............................................................................. 118 10.14.1 performance management flows ...................................................... 118 10.14.2 performance management record table ..........................................121 10.15 change of connection state fifo..................................................................129 10.16 count rollover fifo .......................................................................................130 10.17 cell routing.....................................................................................................133 10.17.1 output backward oam cell interface ................................................134 10.17.2 input backward oam cell interface ...................................................138 10.17.3 internal dram access .......................................................................139 10.17.4 writing cells .......................................................................................140 10.17.5 reading cells .....................................................................................141 10.18 jtag test access port....................................................................................143 11 normal mode register description...........................................................................144 11.1 list of registers ..............................................................................................144 11.2 core registers ................................................................................................151 11.3 microprocessor cell interface .........................................................................169
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 document id: pmc-1990553, issue 4 11.4 backward cell interface ..................................................................................176 11.5 cell processor.................................................................................................190 11.5.1 general configuration and status ......................................................190 11.5.2 search ................................................................................................219 11.5.3 vc table .............................................................................................225 11.5.4 policing...............................................................................................242 11.5.5 oam fault management ....................................................................259 11.5.6 oam loopback...................................................................................270 11.5.7 oam performance management .......................................................272 11.5.8 change of connection state fifo .....................................................286 11.5.9 count rollover fifo ..........................................................................288 11.5.10 per phy statistics ..............................................................................291 11.6 rx link interface .............................................................................................308 11.7 tx phy interface.............................................................................................318 11.8 input scalable data queue.............................................................................323 11.9 rx phy interface ............................................................................................334 11.10 tx link interface .............................................................................................344 11.11 output scalable data queue ..........................................................................354 11.12 packet bypass scalable data queue .............................................................365 12 test features description .........................................................................................376 12.1 test mode 0 details.........................................................................................378 12.2 jtag test port ................................................................................................379 13 operations.................................................................................................................39 0 13.1 configuring the scalable data queue ............................................................390 13.2 jtag support..................................................................................................392 13.2.1 tap controller ....................................................................................394 13.3 board design recommendations ...................................................................396 14 functional timing......................................................................................................397 14.1 pos-phy level 3 ...........................................................................................397 14.1.1 ingress packet interface ....................................................................397 14.1.2 egress packet interface .....................................................................403 14.2 utopia level 3 ..............................................................................................408 14.2.1 ingress ul3 interface .........................................................................409 14.2.2 egress ul3 interface .........................................................................412 14.3 sram interface...............................................................................................415
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 document id: pmc-1990553, issue 4 14.4 backwards cell interface ................................................................................417 15 absolute maximum ratings ......................................................................................418 16 d.c. characteristics ..................................................................................................419 17 a.c. timing characteristics.......................................................................................421 17.1 conditions .......................................................................................................421 17.2 reset timing ...................................................................................................421 17.3 half-second clock timing...............................................................................421 17.4 microprocessor interface read timing ...........................................................421 17.5 microprocessor interface write timing ...........................................................423 17.6 ul3/pl3 interface timing ...............................................................................424 17.7 bcif interface timing .....................................................................................425 17.8 sram interface timing ...................................................................................426 17.9 jtag interface timing.....................................................................................426 18 ordering and thermal information............................................................................429 18.1 ordering information .......................................................................................429 18.2 thermal information ........................................................................................429 19 mechanical information.............................................................................................429 notes 432
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 document id: pmc-1990553, issue 4 list of registers register 0x000: s/uni-atlas-3200 master configuration and reset .........................151 register 0x001: s/uni-atlas-3200 identity / load counts..........................................154 register 0x002: master interrupt status #1 ...................................................................156 register 0x003: master interrupt status #2 ...................................................................162 register 0x004: master interrupt enable #1 ..................................................................164 register 0x005: master interrupt enable #2 ..................................................................166 register 0x006: master clock monitor ...........................................................................167 register 0x020: microprocessor cell interface control and status ...............................169 register 0x021: microprocessor cell data.....................................................................173 register 0x022: mcif dropped cells counter...............................................................175 register 0x030: input backwards cell interface configuration......................................176 register 0x031: ibcif dropped cells counter ..............................................................178 register 0x032: ibcif read cells counter ...................................................................179 register 0x038: output backwards cell interface configuration...................................180 register 0x039: obcif dropped cells counter ............................................................181 register 0x03a: obcif read cells counter .................................................................182 register 0x040: sysclk delay locked loop register 1..............................................183 register 0x041: sysclk dll register 2 ......................................................................185 register 0x042: sysclk dll register 3 ......................................................................186 register 0x043: sysclk dll register 4 ......................................................................187 register 0x100: cell processor configuration ...............................................................190 register 0x101: cell processor routing configuration..................................................197 register 0x102: cell counting configuration .................................................................203 register 0x104: backward cell interface pacing and head of line blocking................205 register 0x105: per-phy processing enable 1.............................................................207 register 0x106: per-phy processing enable 2.............................................................209 register 0x107: ais/cc pacing and head of line blocking ..........................................211 register 0x108: fwd pm pacing and head of line blocking.........................................213 register 0x109: inoperative phy declaration period and indications...........................215 register 0x10a: inoperative phy indications ................................................................217 register 0x10b: search engine configuration...............................................................219 register 0x10c: sram access control .........................................................................221 register 0x10d: sram data lsw (sram data[31:0]) .................................................223
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 document id: pmc-1990553, issue 4 register 0x10e: sram data msw (sram data [63:32]) .............................................224 register 0x110: vc table maximum index....................................................................225 register 0x111: vc table access control .....................................................................226 register 0x112: vc table write enable 1......................................................................229 register 0x113: vc table write enable 2......................................................................231 register 0x114: vc table data row 0, word 0 (lsw) (ram data [31:0]) ...................232 register 0x115: vc table data row 0, word 1 (ram data [63:32]) ............................233 register 0x116: vc table data row 0, word 2 (ram data [95:64]) ............................234 register 0x117: vc table data row 0, word 3 (msw) (ram data [127:96]) ..............235 register 0x118: vc table data row 1, word 0 (lsw) (ram data [31:0]) ...................236 register 0x119: vc table data row 1, word 1 (ram data [63:32]) ............................236 register 0x11a: vc table data row 1, word 2 (ram data [95:64]) ...........................236 register 0x11b: vc table data row 1, word 3 (msw) (ram data [127:96])..............236 register 0x11c: vc table data row 2, word 0 (lsw) (ram data [31:0])...................237 register 0x11d: vc table data row 2, word 1 (ram data [63:32])............................237 register 0x11e: vc table data row 2, word 2 (ram data [95:64]) ...........................237 register 0x11f: vc table data row 2, word 3 (msw) (ram data [127:96]) ..............237 register 0x120: vc table data row 3, word 0 (lsw) (ram data [31:0]) ...................238 register 0x121: vc table data row 3, word 1 (ram data [63:32]) ............................238 register 0x122: vc table data row 3, word 2 (ram data [95:64]) ...........................238 register 0x123: vc table data row 3, word 3 (msw) (ram data [127:96]) ..............238 register 0x124: vc table data row 4 word 0 (lsw) (ram data [31:0]) ....................239 register 0x125: vc table data row 4, word 1 (ram data [63:32]) ............................239 register 0x126: vc table data row 4, word 2 (ram data [95:64]) ...........................239 register 0x127: vc table data row 4, word 3 (msw) (ram data [127:96]) ..............239 register 0x128: vc table data row 5 word 0 (lsw) (ram data [31:0]) ....................240 register 0x129: vc table data row 5, word 1 (ram data [63:32]) ............................240 register 0x12a: vc table data row 5, word 2 (ram data [95:64]) ...........................240 register 0x12b: vc table data row 5, word 3 (msw) (ram data [127:96])..............240 register 0x12c: vc table data row 6 word 0 (lsw) (ram data [31:0])....................241 register 0x12d: vc table data row 6, word 1 (ram data [63:32])............................241 register 0x12e: vc table data row 6, word 2 (ram data [95:64]) ...........................241 register 0x12f: vc table data row 6, word 3 (msw) (ram data [127:96]) ..............241 register 0x130: per-vc non-compliant cell counting configuration ...........................242 register 0x131: connection policing configuration 1 & 2 .............................................244
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 document id: pmc-1990553, issue 4 register 0x132: connection policing configuration 3 & 4 .............................................245 register 0x133: connection policing configuration 5 & 6 .............................................245 register 0x134: connection policing configuration 7 & 8 .............................................245 register 0x140: phy policing enable 1 .........................................................................246 register 0x141: phy policing enable 2 .........................................................................248 register 0x142: phy policing configuration..................................................................249 register 0x143: per-phy non-compliant cell counting configuration.........................251 register 0x144: phy policing ram address and access control ................................252 register 0x145: phy policing ram data row 0 ...........................................................255 register 0x146: phy policing ram data row 1 ...........................................................256 register 0x147: phy policing ram data row 2 ...........................................................257 register 0x148: phy policing ram data row 3 ...........................................................258 register 0x151: oam defect location octets 3 to 0 .....................................................259 register 0x152: defect location octets 7 to 4..............................................................260 register 0x153: defect location octets 11 to 8.............................................................260 register 0x154: defect location octets 15 to 12...........................................................260 register 0x155: per-phy ais cell generation control 1 ..............................................261 register 0x156: per-phy ais cell generation control 2 ..............................................263 register 0x157: per-phy rdi cell generation control 1 ..............................................264 register 0x158: per-phy rdi cell generation control 2 ..............................................266 register 0x159: per-phy aps indication 1 ...................................................................267 register 0x15a: per-phy aps indication 2 ...................................................................269 register 0x160: oam loopback location id octets 3 to 0............................................270 register 0x161: loopback location id octets 7 to 4....................................................271 register 0x162: loopback location id octets 11 to 8...................................................271 register 0x163: loopback location id octets 15 to 12.................................................271 register 0x170: performance management ram record address, word select and access control.......................................................................................272 register 0x171: performance management ram row 0 word 0 (lsw) ......................274 register 0x172: performance management ram row 0 word 1 .................................275 register 0x173: performance management ram row 0 word 2 (msw) .....................276 register 0x174: performance management ram row 1 word 0 (lsw) ......................277 register 0x175: performance management ram row 1 word 1 .................................277 register 0x176: performance management ram row 1 word 2 (msw) .....................277 register 0x177: performance management ram row 2 word 0 (lsw) ......................278
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 document id: pmc-1990553, issue 4 register 0x178: performance management ram row 2 word 1 .................................278 register 0x179: performance management ram row 2 word 2 (msw) .....................278 register 0x17a: performance management ram row 3 word 0 (lsw)......................279 register 0x17b: performance management ram row 3 word 1 .................................279 register 0x17c: performance management ram row 3 word 2 (msw) ....................279 register 0x17d: performance management ram row 4 word 0 (lsw) .....................280 register 0x17e: performance management ram row 4 word 1 .................................280 register 0x17f: performance management ram row 4 word 2 (msw) .....................280 register 0x180: performance management ram row 5 word 0 (lsw) ......................281 register 0x181: performance management ram row 5 word 1 .................................281 register 0x182: performance management ram row 5 word 2 (msw) .....................281 register 0x183: performance management ram row 6 word 0 (lsw) ......................282 register 0x184: performance management ram row 6 word 1 .................................282 register 0x185: performance management ram row 6 word 2 (msw) .....................282 register 0x186: performance management ram row 7 word 0 (lsw) ......................283 register 0x187: performance management ram row 7 word 1 .................................283 register 0x188: performance management ram row 7 word 2 (msw) .....................283 register 0x189: performance management threshold a ..............................................284 register 0x18a: performance management threshold b..............................................285 register 0x18b: performance management threshold c .............................................285 register 0x18c: performance management threshold d .............................................285 register 0x190: vc table change of connection state fifo status ...........................286 register 0x191: vc table change of connection state fifo data..............................287 register 0x198: count rollover fifo status .................................................................288 register 0x199: count rollover fifo data....................................................................289 register 0x1a0: per-phy counter configuration ..........................................................291 register 0x1a1: per-phy counter control ....................................................................293 register 0x1a8: per-phy clp0 cell count holding register .......................................296 register 0x1a9: per phy clp1 cell count holding register .......................................298 register 0x1aa: per phy valid rm cell counts holding register ...............................299 register 0x1ab: per phy valid oam cell counts holding register.............................300 register 0x1ac: per phy errored oam/rm cell counts holding register..................301 register 0x1ad: per phy invalid vpi/vci/pti cell counts holding register...............302 register 0x1ae: per-phy efci/non-zero gfc cell count holding register ..............303 register 0x1af: per-phy timed-out cell count holding register...............................304
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 document id: pmc-1990553, issue 4 register 0x1b0: per phy last unknown vpi & vci holding register..........................305 register 0x1c0: reserved .............................................................................................307 register 0x200: rxl configuration ................................................................................308 register 0x201: rxl interrupt enable ............................................................................310 register 0x202: rxl interrupt ........................................................................................311 register 0x208: rxl phy indirect address ...................................................................312 register 0x209: rxl phy indirect data .........................................................................313 register 0x20a: rxl calendar length...........................................................................314 register 0x20b: rxl calendar indirect address and data ............................................315 register 0x20c: rxl data type field............................................................................317 register 0x220: txp configuration ................................................................................318 register 0x221: txp interrupt ........................................................................................320 register 0x222: txp interrupt enable ............................................................................321 register 0x223: txp data type field ............................................................................322 register 0x240: input sdq control................................................................................323 register 0x241: input sdq interrupts ............................................................................324 register 0x242: input sdq interrupt id .........................................................................326 register 0x244: input sdq indirect address .................................................................327 register 0x245: input sdq indirect configuration .........................................................329 register 0x246: input sdq cells and packets count....................................................331 register 0x247: input sdq cells accepted aggregate count .......................................332 register 0x248: input sdq cells dropped aggregate count ........................................333 register 0x260: rxp configuration ................................................................................334 register 0x261: rxp interrupt ........................................................................................336 register 0x262: rxp interrupt enable............................................................................337 register 0x263: rxp phy indirect address and data ...................................................338 register 0x264: rxp calendar length...........................................................................340 register 0x265: rxp calendar indirect address and data ............................................341 register 0x266: rxp data type field ............................................................................343 register 0x280: txl configuration.................................................................................344 register 0x281: txl interrupt enable.............................................................................346 register 0x282: txl interrupt.........................................................................................347 register 0x286: txl data type field.............................................................................348 register 0x288: txl phy indirect address....................................................................349 register 0x289: txl phy indirect data .........................................................................350
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 document id: pmc-1990553, issue 4 register 0x28a: txl calendar length ...........................................................................351 register 0x28b: txl calendar indirect address and data ............................................352 register 0x2a0: output sdq control.............................................................................354 register 0x2a1: output sdq interrupts .........................................................................355 register 0x2a2: output sdq interrupt id ......................................................................357 register 0x2a4: output sdq indirect address ..............................................................358 register 0x2a5: output sdq indirect configuration......................................................360 register 0x2a6: output sdq cells and packets count.................................................362 register 0x2a7: output sdq cells accepted aggregate count....................................363 register 0x2a8: output sdq cells dropped aggregate count.....................................364 register 0x2c0: bypass sdq control ...........................................................................365 register 0x2c1: bypass sdq interrupts........................................................................366 register 0x2c2: bypass sdq interrupt id .....................................................................368 register 0x2c4: bypass sdq indirect address.............................................................369 register 0x2c5: bypass sdq indirect configuration.....................................................371 register 0x2c6: bypass sdq cells and packets count ...............................................373 register 0x2c7: bypass sdq cells accepted aggregate count ..................................374 register 0x2c8: bypass sdq cells dropped aggregate count....................................375 register 0x800: master test ..........................................................................................377
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 document id: pmc-1990553, issue 4 list of figures figure 1 s/uni-atlas-3200 application ........................................................................32 figure 2 interface between s/uni-atlas-3200 and external ram...............................33 figure 3 s/uni-atlas-3200 block diagram ..................................................................34 figure 4 pin diagram ......................................................................................................38 figure 5 utopia level 3 ingress interface ....................................................................64 figure 6 utopia level 3 egress interface.....................................................................65 figure 7 pos-phy level 3 ingress interface .................................................................67 figure 8 pos-phy level 3 egress interface ..................................................................68 figure 9 atm cell format ...............................................................................................73 figure 10 vc search key extraction...............................................................................74 figure 11 parameters of the primary and secondary keys............................................75 figure 12 vc search key construction ..........................................................................76 figure 13 construction of primary and secondary keys ................................................78 figure 14 f4 to f5 oam flows .....................................................................................109 figure 15 termination of f4 segment and end-to-end-point connection ...................109 figure 16 termination of f4 segment and end-to-end point connection....................111 figure 17 termination of f4 segment end-point connection ......................................112 figure 18 termination of f4 end-to-end point connection ..........................................113 figure 19 pm flows.......................................................................................................119 figure 20 connection of s/uni-atlas-3200 bcifs ....................................................135 figure 21 input observation cell (in_cell) ................................................................388 figure 22 output cell (out_cell) ..............................................................................388 figure 23 bidirectional cell (io_cell) .........................................................................389 figure 24 layout of output enable and bidirectional cells...........................................389 figure 25 boundary scan architecture .........................................................................393 figure 26 tap controller finite state machine.............................................................394 figure 27 pos-phy level 3 ingress logical timing ....................................................398 figure 28 rxlink pos-phy packet transfer ...............................................................399 figure 29 rxlink back to back pos-phy packet transfer ..........................................400 figure 30 rxlink pos-phy atm cell transfer............................................................401 figure 31 rxphy pos-phy packet transfer...............................................................402 figure 32 rxphy pos-phy atm cell transfer ............................................................403 figure 33 pos-phy level 3 egress logical timing.....................................................404
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 document id: pmc-1990553, issue 4 figure 34 txphy pos-phy packet transfer ................................................................405 figure 35 transmit pos-phy atm cell transfer.........................................................406 figure 36 txlink pos-phy logical timing ..................................................................407 figure 37 txlink pos-phy atm cell transfer timing ................................................408 figure 38 ingress utopia logical timing....................................................................409 figure 39 rxlink utopia cell transfer .......................................................................410 figure 40 rxlink back-to-back utopia cell transfers...............................................410 figure 41 rxphy utopia cell transfer .......................................................................411 figure 42 egress utopia logical timing ....................................................................412 figure 43 txphy utopia cell transfer ........................................................................413 figure 44 txlink utopia transfer...............................................................................414 figure 45 txlink back-to-back utopia transfer ........................................................414 figure 46 interface between s/uni-atlas-3200 and external ram...........................416 figure 47 sram interface functional timing ...............................................................416 figure 48 normal bcif functional timing....................................................................417 figure 49 ibcif as tx slave functional timing............................................................417 figure 50 rstb ac timing...........................................................................................421 figure 51 half-second clock ac timing ......................................................................421 figure 52 microprocessor interface read access ac timing ......................................422 figure 53 microprocessor interface write ac timing ...................................................424 figure 54 utopia level 3 / pos-phy level 3 ac timing ..........................................425 figure 55 bcif interface ac timing .............................................................................425 figure 56 sram interface ac timing ...........................................................................426 figure 57 jtag port interface ac timing ....................................................................428 figure 58 768 tape ball grid array (tbga) .................................................................430
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 document id: pmc-1990553, issue 4 list of tables table 1 signal ball assignment (alphabetical) ...............................................................40 table 2 power/ground ball assignment (alphabetical) ..................................................41 table 3 polling and servicing calendar example ...........................................................69 table 4 phy mapping .....................................................................................................71 table 5 search table ......................................................................................................77 table 6 secondary search table fields .........................................................................78 table 7 vc linkage table...............................................................................................79 table 8 vc record table................................................................................................80 table 9 vc table fields used in cell processing ...........................................................81 table 10 status vc table field ......................................................................................81 table 11 configuration vc table field ...........................................................................82 table 12 internal status vc table field .........................................................................84 table 13 oam configuration vc table field..................................................................86 table 14 vc table miscellaneous fields ........................................................................88 table 15 vc table fields for header translation..........................................................90 table 16 vc table policing fields ..................................................................................91 table 17 policing configuration vc table field .............................................................92 table 18 policing actions ................................................................................................96 table 19 actions on policing with cocup=0 .................................................................96 table 20 actions on policing with cocup=1 .................................................................97 table 21 non-compliant cell count configurations .......................................................97 table 22 actions with per-phy policing..........................................................................98 table 23 internal per-phy policing ram........................................................................99 table 24 per-phy policing actions.................................................................................99 table 25 per-phy policing non-compliant count options ..........................................100 table 26 per-phy/per-vc non-compliant cell counting phyvccount=0 .................100 table 27 per-phy and per-vc non-compliant cell counting phyvccount=1...........101 table 28 f4 to f5 fault management processing ........................................................114 table 29 linkage table fields used in pm ..................................................................118 table 30 pm activation fields.......................................................................................118 table 31 performance management record table ......................................................121 table 32 pm table configuration field.........................................................................122 table 33 qos parameters for performance management...........................................124
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 document id: pmc-1990553, issue 4 table 34 change of state fifo ....................................................................................129 table 35 count rollover fifo format for per-vc count entries................................131 table 36 count rollover fifo format for per-phy count entries .............................131 table 37 count rollover fifo format for pm entries.................................................132 table 38 backwards cell interface cell format............................................................136 table 39 bcif cell information field ............................................................................137 table 40 microprocessor cell information field............................................................141 table 41 suggested fifo size encoding .....................................................................329 table 42 suggested fifo size encoding .....................................................................360 table 43 suggested fifo size encoding .....................................................................371 table 44 test mode register memory map ..................................................................376 table 45 test mode 0 read map..................................................................................378 table 46 test mode 0 write map ..................................................................................379 table 47 instruction register ........................................................................................380 table 48 identification register.....................................................................................380 table 49 boundary scan register ................................................................................380 table 50 suggested fifo size encoding .....................................................................390 table 51 sdq-atlas configuration example .............................................................391 table 52 absolute maximum ratings............................................................................418 table 53 dc characteristics .........................................................................................419 table 54 rtsb ac timing ............................................................................................421 table 55 half-second clock ac timing........................................................................421 table 56 microprocessor interface read access ac timing .......................................421 table 57 microprocessor interface write access ac timing........................................423 table 58 utopia level 3 / pos-phy level 3 ac timing............................................424 table 59 bcif interface ac timing ..............................................................................425 table 60 sram interface ac timing ............................................................................426 table 61 jtag port interface timing............................................................................426 table 62 ordering information ......................................................................................429
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 document id: pmc-1990553, issue 4 1 definitions this table defines the acronyms used in this data sheet. acronym definition ais alarm indication signal. ais cells are oam fault management cells whose function type fields identify them as ais cells as per itu-t i.610. they are sent once per second by an atm network element which has detected certain error conditions, such as a loss of continuity. ais alarm refers to the detection that the s/uni-atlas-3200 is receiving ais cells on a particular vc. bt burst tolerance. the burst tolerance is a policing parameter that indicates the maximum length of a burst (at the peak allowable cell rate) that is permitted before the sustained cell rate test will be violated. bwd pm backwards performance management cell. these pm oam cells are sent by a pm session on reception of a fwd pm cell, and carry data about the cell flow as observed by both the start and end point of the pm flow. bwd lb backwards, or returned loopback cell. an oam loopback cell whose loopback indication bit is zero, indicating it has already been looped back. cbr constant bit rate. cbr service is one of the standard traffic contracts, in which a constant, unchanging amount of bandwidth is guaranteed to the user, with time-of-delivery guarantees. voice traffic is a classic use of cbr service cdv cell delay variation. the cdv tolerance is one of the parameters that determines the policing parameters, particularly the limit parameter of the peak cell rate test. clp cell loss priority. this is a field in the header of an oam cell. high-priority cells are those with clp = 0, and are sometimes referred to as clp0 cells. low priority blocks are sometimes referred to as clp1 cells, and the aggregate flow is referred to as clp0+1. cc continuity check. cc cells are oam fault management cells whose function type fields identfy them as cc cells as per itu-t i.610. they are sent once per second by a flow start point in the absence of user traffic, to indicate that the connection remains active. cc alarm refers to the detection that a vc on the s/uni-atlas-3200 has received neither user cells nor cc cells for a nominal period of 3 seconds. f4 the f4 oam layer is the oam layer associated with the virtual path. in s/uni-atlas- 3200, a vc may be part of an f4 flow or an f5 flow. in the case of an f4 flow being sourced or terminated, a number of vcs which form part of f5 flows may have an associated f4 oam vc, which performs the oam for the f4 flow. this f4 oam vc is specified by the vpc pointer in the linkage table. f5 the f5 oam layer is the oam layer associated with the virtual channel. fm fault management. fault management oam cells include ais cells, rdi cells, cc cells, and lb cells. fwd lb a forward, or parent, loopback cell. an oam loopback cell whose loopback indication bit is 1, indicating it has not yet been looped back. fwd pm forward performance management cell. these pm oam cells are sent by a pm session at an oam start point every n cells, where n is a programmable number ranging from 128 to 32k. they contain information about the cell flow on a vc as seen by the transmitting point. gcra generic cell rate algorithm. the gcra is the ?leaky bucket? policing algorithm described in itu-t i.371.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 document id: pmc-1990553, issue 4 acronym definition gfc generic flow control. at the uni, a congestion-control flow called gfc is used. the gfc field occupies the most significant 4 bits of each atm cell. at the network-network interface, these 4 bits are used for vpi instead. gfr guaranteed frame rate. gfr is one of the standard traffic contracts (like cbr, vbr, and abr) and is a frame-aware standard supporting aal5 partial packet discard. s/uni- atlas-3200 supports gfr policing. lb loopback. loopback cells are oam cells used to test the connectivity of the network, usually during call setup or diagnostics. they are inserted into the network, and looped back at network nodes based on the content of their loopback location id. when loopback cells are first inserted, they are referred to as parent loopback cells. once looped back (indicated by the loopback indication field being zero) they are referred to as returned loopback cells. mcr minimum cell rate. mcr is a parameter of guaranteed frame rate (gfr) traffic contracts. it is analogous to the sustained cell rate (scr) parameter, but is only enforced at frame boundaries. nni network-network interface. npc network parameter control. npc is defined as the set of actions taken by the network to monitor and control traffic at the network-network interface. npc is what the standards call policing at an nni. the main purpose of upc and npc is to protect network resources from malicious as well as unintentional misbehavior, which can affect the qos of other already established connections, by detecting violations of negotiated parameters and taking appropriate actions. such actions may include cell discard and cell tagging. oam operations and maintenance. oam cells include fault management, performance management, loopback, activate/deactivate, and system administration cells, as well as other non-standard cells whose vci or pti identify them as oam cells as per itu-t i.610. parent lb a parent, or forward, loopback cell. an oam loopback cell whose loopback indication bit is 1, indicating it has not yet been looped back. pcr peak cell rate. the pcr is a parameter of most traffic contracts, and is enforced by the policing (upc/npc) functions of the device. phy a physical layer device, or a cell queue associated with a physical-layer interface. pm performance management. pm is a process whereby cells are transmitted over a vc, carrying information about the traffic from the point of view of the start point and end point. from the comparison of the two, statistics about the performance of the connection can be maintained. pti payload type identifier. the pti is a 3-bit cell field that immediately follows the vci, and is used to identify the cell type for vccs. rdi remote defect indication. rdi cells are generated once per second by an oam end point, and looped back to be sent in the reverse direction, to indicate that ais cells have been received at that end point. rtd lb a returned, or backwards, loopback cell. an oam loopback cell whose loopback indication bit is zero, indicating it has already been looped back. rx link when configured as an ingress device, the input of the s/uni-atlas-3200 acts as a link layer device as defined in the utopia level 3 and pos-phy3 specs, and connects to a phy. this interface is a master interface in ul3, and a slave interface in pos-phy3. rx phy when configured as an ingress device, the output of s/uni-atlas-3200 acts as a phy layer device as defined in the ul3 and pos-phy level 3 specs, and connects to a tm or switch that acts as a link layer device. this interface is a slave interface for ul3, and a master interface for pos-phy level 3. scr sustained cell rate. the sustained cell rate is a parameter of some traffic contracts, and indicates the maximum throughput that may be sustained over a long period of time.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 document id: pmc-1990553, issue 4 acronym definition it is typically paired with a peak cell rate (pcr) parameter, and is enforced by the policing (upc/npc) functions of the device. tm traffic management. a traffic management device may be connected to the switch side of the s/uni-atlas-3200. tx link when configured as an egress device, the output of s/uni-atlas-3200 acts as a link layer device as defined in the utopia level 3 and pos-phy level 3 specs, and connects to a phy. this interface is a master interface for both ul3 and pos-phy3. tx master on the egress phy side, the utopia and pos-phy interfaces act as a master, controlling the transfers to the phy. this interface is also referred to as the tx link interface. tx phy when configured as an egress device, the input of s/uni-atlas-3200 acts as a phy layer device.as defined in the ul3 and pos-phy level 3 specs, and connects to a tm or switch that acts as a link layer device. this interface is a slave interface for both ul3 and pos-phy level 3. tx slave on the egress system side, the utopia and pos-phy interfaces act as a slave; that is, s/uni-atlas-3200 looks like a phy from the point of view of the upstream device. this interface is also referred to as the tx phy interface. trcc total received cell count. used in performance monitoring. a rolling 16-bit count of user cells (either clp0, or clp0+1) received by the fwd pm sink point.. tuc total user cell [count]. used in performance monitoring. a rolling 16-bit count of user cells (either clp0, or clp0+1) transmitted by the fwd pm source. tucd total user cell difference. this is the difference between the number of cells transmitted in the block (as indicated in the fwd pm cell) and the number received. for example, tucd0 = {[tuc0(t) ? tuc0(t-1)] mod 64k} - {[trcc0(t) ? trcc0(t-1)] mod 64k}. uni user-network interface. upc usage parameter control. this is what the standards call policing at the user-network interface (uni). the main purpose of upc and npc is to protect network resources from malicious as well as unintentional misbehavior, which can affect the qos of other already established connections, by detecting violations of negotiated parameters and taking appropriate actions. such actions may include cell discard and cell tagging. vc virtual connection. vcs may be virtual path connections (vpcs) or virtual channel connections (vccs). each bidirectional vc serviced by s/uni-atlas-3200 has one vc record in context memory in each direction. vcc virtual channel connection. vcra virtual connection record address. this is the address of the vc?s context table in memory. while it is listed as 17 bits, the msb must be logic 0 in the s/uni-atlas-3200. vpc virtual path connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 document id: pmc-1990553, issue 4 2 features the s/uni?- atlas-3200 device is a monolithic, single chip device that handles atm layer functions for one direction including vpi/vci address translation, cell appending, cell rate policing, per-connection counting, and i.610-compliant oam requirements for 64k vcs (virtual connections). two or more s/uni-atlas-3200 devices can be cascaded to support additional vcs. the device: ? can be configured as an ingress mode device or an egress mode device. ? supports a full duplex 16-bit sci-phy? backwards cell interface port that allows an ingress mode device and an egress mode device to communicate and behave as a single bi- directional device. the sci-phy port is a utopia level 2, non-polled, cell handshaking interface that handles 64-byte extended cells with prepended routing information. this can also be described as a 16-bit, 52 mhz utopia level 1 interface, with prepended routing information. ? with its instantaneous transfer rate of 3200 mbit/s, it supports a cell transfer rate of 5.68x10 6 cells/s (e.g. one sts-48c or four sts-12c streams). ? when configured as an ingress mode device: the input interface supports a 32-bit 104 mhz utopia level 3 link layer (master) interface using multi-phy addressing with user-programmable weighted polling for up to 48 phy queues on a single physical port. extended atm cell lengths of 52 to 64 bytes are supported, with optional hec/udf, prepend, and postpend words. mapping of physical phys to logical phys is supported, to facilitate automated protection switching. the output interface supports a 32-bit 104mhz utopia level 3 phy layer (slave) interface using multi-phy handshaking for up to 48 phy sources. extended atm cell lengths of 52 to 64 bytes are supported, with optional hec/udf, prepend, and postpend words. a non-polled, direct mode is also supported for this interface. alternately, the input interface supports a 32-bit 104 mhz pos-phy? level 3 rx link layer interface, capable of handling a mix of packets and atm cells. each of 48 phy queues on a single physical port must be set up to carry either packets or cells. cells are processed by s/uni-atlas-3200, but packets are not processed and are buffered and passed through transparently. in this case, the output interface supports a 32-bit 104 mhz pos-phy rx phy layer interface. ? when configured as an egress mode device: the input interface supports a 32-bit 104 mhz utopia level 3 phy layer (slave) interface using multi-phy handshaking for up to 48 phy destinations. extended atm cell lengths of 52 to 64 bytes are supported, with optional hec/udf, prepend, and postpend words.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 document id: pmc-1990553, issue 4 the output interface supports a 32-bit 104 mhz utopia level 3 link layer (master) interface using multi-phy addressing with user-programmable weighted polling for up to 48 phy queues on a single physical port. extended atm cell lengths of 52 to 64 bytes are supported, with optional hec/udf, prepend, and postpend words. mapping of logical phys to physical phys is supported, to facilitate automated protection switching. alternately, the input interface supports a 32-bit 104 mhz pos-phy level 3 tx phy layer interface, capable of handling a mix of packets and atm cells. each of 48 phy queues on a single physical port must be set up to carry either packets or cells. cells are processed by s/uni-atlas-3200, but packets are not processed and are buffered and passed through transparently. in this case, the output interface supports a 32-bit 104 mhz pos-phy tx link layer interface. ? is compatible with a wide range of switching fabrics and traffic management architectures including per-vc or per-phy queuing. ? contains a highly-flexible cam-type cell and connection identification, which can use arbitrary phyid/vpi/vci values and/or cell appended bytes for connection identification in both directions. 34-bits of discrimination allows the entire phyid/vpi/vci address range to be resolved. ? includes header translation functions, permitting the translation of the vpi, vci, and/or cell appended bytes. information about the cell and connection type can be included in appended bytes in order to aid downstream processing. ? provides comprehensive cell processing functionality, which includes a highly flexible search engine that covers the entire phyid/vpi/vci address range, programmable dual leaky bucket upc/npc, per-connection clp0 and clp1 cell counts (programmable), oam-pm termination, generation and monitoring, oam-fm termination, generation and alarm generation (monitoring), and oam-lb address matching, termination, and loopback. ? provides a count rollover fifo greatly, which reduces the need to poll internal counts. ? provides available aal5 frame counting via the policing counts. ? provides per-phy output buffering, which resolves head-of-line blocking issues. ? provides a upc/npc function, which is a programmable dual leaky bucket policing device with a programmable action (tag, discard, or count only) for each bucket. a total of 3 programmable 16-bit non-compliant cell counts are provided. the non-compliant cell counts may be programmed to count, for example, dropped clp0 cells, dropped clp1 cells, and tagged clp0 cells. the upc/npc function also has a continuously violating mode, where a programmable action is taken on all cells regardless of their compliance. ? provides guaranteed frame rate policing, including aal5 partial packet discard, so that the remainder of an aal5 packet can be discarded if a single cell in the packet is discarded as a result of violating policing. aal5 packets may also be completely tagged or discarded as appropriate. gfr policing is selectable on a per-connection basis.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 document id: pmc-1990553, issue 4 ? in addition to the per-connection dual leaky bucket, provides a single leaky bucket upc/npc function on a per-phy basis. a programmable action (tag, discard or count only) may be configured for each phy policing device. three programmable non-compliant cell or frame counts are provided for each phy. the non-compliant cell counts may be programmed to count, for example, tagged clp0 cells, dropped cells, and dropped clp0 frames. frame counts are relevant either for gfr policing or for generic frame counting. the per-phy policing parameters and non-compliant cell counts are maintained in an on-chip ram that can be programmed and read via the 32-bit general purpose microprocessor interface. ? allows groups of f5 connections to be policed in aggregate at the f4 level instead of at the f5 level, through the use of the vp_police bit. ? provides oam-fault management on a per-connection basis. simultaneous segment and end-to-end f4 and f5 ais, rdi and cc cell generation, termination and monitoring is supported. alarm bits and interrupt masks are provided on a per-connection basis. f4 to f5 ais alarm splitting and f5 to f4 aggregation are provided. paced insertion of fm cells is provided. ? allows oam-loopback address identification, termination, and loopback to be per- connection configurable. loopback cells may also be extracted to the microprocessor. ? provides a high-speed 32-bit microprocessor bus for configuration, control, and status monitoring. ? provides a fifo buffered cell insertion and extraction capability via the microprocessor bus interface. ? supports dma access for cell extraction. ? uses up to 16 mbit/s of external pipelined zbt sram (with or without parity) for maintaining the data structure for the search tree. a 64 bit data + 8 bit parity 125 mhz bus interface is used to connect to the external sram. ? uses internal dram for maintaining vc context information. ? provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. ? low power 0.18 micron, 1.5 v cmos technology with 2.5 v embedded dram, 2.5 v external sram interface, and 3.3 v other external interfaces. ? 768 tape bga package. 2.1 policing ? policing is performed for adherence to peak cell rate (pcr), cell delay variation (cdv), sustained cell rate (scr) and burst tolerance (bt). violating cells can be dropped, tagged, or just counted. ? policing is performed using the virtual scheduling generic cell rate algorithm (gcra) described in itu-t i.371. ? gfr policing as described in atm forum tm 4.1 is provided, with enforcement of pcr, mcr, clp conformance, and maximum frame length.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 document id: pmc-1990553, issue 4 ? two policing instantiations available per vc. the policed cell streams can be any combination of user cells, oam cells, resource management, high priority cells or low priority cells. ? per-phy policing may also be enabled. each of 48 phy devices may have a single leaky bucket enabled, in addition to the dual leaky bucket of the connection. violating cells or frames can be dropped, tagged, or just counted. ? when aggregating or terminating a vpc, policing may be performed on the vpc instead of the individual vccs. 2.2 performance management ? the s/uni-atlas-3200 device provides oam-performance management functions in each of its two modes (ingress mode and egress mode). when an ingress mode device is used in conjunction with an egress mode device, the combination supports bi-directional pm sessions. a maximum of 512 pm sessions may be simultaneously active in one device. when using an ingress mode + egress mode device, the combination supports upto 512 bi- directional pm sessions. pm is supported on the f4 and f5 levels. the s/uni-atlas-3200 device provides for the generation of forward monitoring and backward reporting pm cells (both segment and end-to-end), the termination of forward monitoring and backward reporting cells, and for non-intrusive monitoring of forward monitoring and backward reporting cells. the following statistics are collected when terminating or monitoring pm flows: forward impaired block. forward lost/misinserted impaired block forward severely errored cell block (lost). forward severely errored cell block (misinserted). forward severely errored cell block (bip-16 violations). forward severely errored cell block combined (non-saturating) forward lost clp0+1 cell count. forward lost clp0 cell count. forward tagged clp0 cell count forward misinserted clp0+1 cell count. forward errored cell count. forward total lost clp0+1 cell count. forward total lost clp0 cell count. forward lost forward monitoring cell count. backward impaired block. backward lost/misinserted impaired block. backward severely errored cell block (lost). backward severely errored cell block (misinserted). backward severely errored cell block (bip-16 violations).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 document id: pmc-1990553, issue 4 backward severely errored cell block combined (non-saturating) backward severely errored cell block combined (saturating) backward lost clp0+1 cell count. backward lost clp0 cell count. backward tagged clp0 cell count. backward misinserted clp0+1 cell count. backward errored cell count. backward total lost clp0+1 cell count. backward total lost clp0 cell count. backward lost fwd monitoring pm cell count. backward lost backward reporting pm cell count. total transmitted clp0+1 cell count. total transmitted clp0 cell count. ? statistics for pm sessions are held in on-chip ram that can be read at any time through the 32-bit general purpose microprocessor port. ? paced insertion of pm cells is provided. ? pm block size generation and termination is per-session programmable ranging from 128 ? 32768 cells. ? each of the 512 pm sessions can be configured to be a source, sink or non-intrusive monitoring point of pm cells. ? pm processes support the aggregation of f5 flows into f4 flows, and the termination of f4 flows into its constituent f5 flows. 2.3 cell counting ? counts maintained on a per-vc basis include total low or high priority user cells, oam cells, rm cells, and invalid cells, cells violating the traffic contract, and total aal5 frames. aggregate counts are also provided when aggregating or terminating vpcs. ? counts maintained on a per-phy basis include: number of clp0 cells received, number of clp1 cells received, number of oam cells received, number of rm cells received, number of errored oam cells, number of errored rm cells, number of cells with unassigned, unprovisioned, or invalid vpi/vci/pti, the number of inserted oam cells timed-out to avoid head-of-line blocking, and the number of cells received with a non-zero gfc and/or with efci indicated in their pti fields. ? the per-vc non-compliant and per-phy non-compliant counts can be used to count total frames, whether or not policing is enabled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 document id: pmc-1990553, issue 4 3 applications ? core atm switches. ? wide area network atm core and edge switches. ? atm enterprise and workgroup switches. ? broadband access multiplexers. ? xdsl access multiplexers.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 document id: pmc-1990553, issue 4 4 references ? itu-t recommendation i.361 ? ?b-isdn atm layer specification?, november 1995. ? itu-t recommendation i.371 ? ?traffic control and congestion control in b-isdn?, may, 1996. ? itu-t recommendation i.610 ? ?b-isdn operation and maintenance principles and functions?, february 1999. ? bell communications research ? asynchronous transfer mode (atm) and atm adaptation layer (aal) protocols, gr-1113-core, issue 1, july 1994. ? bell communications research ? broadband switching system (bss) generic requirements, gr-1110-core, issue 1, september 1994. ? bell communications research ? generic requirements for operations of broadband switching systems, gr-1248-core, issue 3, august, 1996. ? atm forum ? atm user-network interface specification, v3.1 september, 1994. ? atm forum tm4.1 ? atm forum traffic management specification version 4.1, 1999. ? ieee 1149.1 ? standard test access port and boundary scan architecture, may 21, 1990. ? atm forum af-phy-136.000 ? utopia level 3, november 1999. ? pmc-1980495 ? pos-phy level 3: saturn compatible interface for packet over sonet physical layer and link layer devices, issue 4, june 7, 2000.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 document id: pmc-1990553, issue 4 5 application examples the s/uni?0 atlas-3200 device is an integrated circuit that implements the atm layer functions that include header translation, cell rate policing, performance management and fault management. the s/uni-atlas-3200 device is a uni-directional part. when used in the ingress direction, it is intended to be situated between the physical layer (phy) devices and a traffic manager (which schedules traffic into the switch fabric). when used in the egress direction, it is intended to be situated between a traffic manager (which shapes traffic out of the switch fabric) and the phy devices. this application is shown in the figure below. figure 1 s/uni-atlas-3200 application phy traffic manager traffic manager switch fabric utopia or pos-phy (level 3) ingress direction egress direction egress mode s/uni-atlas-3200 (+sram) 16 bit sci phy (backward cell interface) ingress mode s/uni-atlas-3200 (+sram) 5.1 cascading multiple s/uni-atlas-3200 devices can be cascaded when more than 64k vcs are required. in a configuration with ?n? cascaded devices, each device is configured (using the per-phy processing register) to only process cells from some of the 48 possible phys (the phys meant for that device). cells from the other phys (which the device has been told to not process) will be passed through. a passed through cell will have already been processed by an upstream device in the cascade, or will be processed by a downstream device. when cascading, each phys cells will be processed in exactly one device and will be passed through all the other devices. such cascading allows the total number of vcs supported to be ?n? times 64k where ?n? is the number of cascaded devices (and the 48 available phys are partitioned among the ?n? devices). in each device, the 64k vcs that it has available are shared between all the phys that it is processing. cascading does not result in an increase in aggregate throughput.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 document id: pmc-1990553, issue 4 5.2 ram configurations the s/uni-atlas-3200 device uses an external sram to store the search tree data structure. this sram is required to be synchronous pipelined zbt sram with cycle time less than 7 ns, and a bus width of 64 bits + parity. the typical configuration is 8m of sram in a pair of 128kx36 rams. this configuration will support 64k vcs. up to 16m of sram may be used if additional search depth is desired, though no more than 64k vcs are supported. alternatively, the amount of sram may be reduced, if less than 64k vcs are to be supported. figure 2 interface between s/uni-atlas-3200 and external ram 128 k x 36 pipelined zbt sram s/uni-atlas-3200 scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sysclk 128 k x 36 pipelined zbt sram spar[3:0] spar[7:4] sdat[31:0] sdat[63:32] clock source 125 mhz xclk sysclk_o
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 document id: pmc-1990553, issue 4 6 block diagram figure 3 s/uni-atlas-3200 block diagram input microprocessor cell interface (imcif) cell flow input scalable data queue address resolution connection table (embedded dram) cell processor generic microprocessor programming interface microprocessor interface up_dat[31:0] up_addr[11:0] up_csb up_rdb up_intb up_busyb up_wrb up_dmarq up_ale jtag jtag interface tdo tdi tck tms trstb xclk halfsecclk ouput backwards cell interface (obcif) policing, oam, statistics, translation output scalable data queue ul3/pos-phy 3 cell/ packet interface ul3/pl3 inputs[46:0] ul3/pl3 outputs [8:0] ul3/pos-phy 3 cell/packet interface ul3/pl3 outputs [46:0] ul3/pl3 inputs [8:0] input backwards cell interface (ibcif) sci-phy rx slave interface bo_par bo_dat[15:0] bo_soc bo_clav bo_rdenb bo_clk sci-phy rx master intrerface bi_dat[15:0] bi_par bi_soc bi_rclav_twrenb bi_rdenb_tclav bi_clk up_rstb packet bypass scalable data queue icif ingress input: ul3 master or pos phy link layer interface (rxlink) egress input: ul3 slave or pos phy phy layer interface (txphy) ocif ingress output: ul3 slave or pos phy phy layer interface (rxphy) egress input: ul3 master or pos phy link layer interface (txlink) output microprocessor cell interface (omcif) scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o 125 mhz pipelined zbt sram interface sysclk sysclk_o
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 document id: pmc-1990553, issue 4 7 description the PM7325 s/uni?-atlas-3200 device is a monolithic integrated circuit that implements the atm layer functions that include fault and performance management, header translation and cell rate policing. the s/uni-atlas-3200 device is a uni-directional part that is intended to reside between the physical layer (phy) devices and a traffic manager in the ingress side, and a traffic shaper and the phy devices in the egress side. the s/uni-atlas-3200 supports a sustained aggregate throughput of 5.68x10 6 cells/s in each of the ingress and egress modes. the s/uni- atlas-3200 uses external sram to store the search tree data structures. the device is capable of supporting up to 64k connections. apart from the operation of the ul3 or pos-phy? level 3 interfaces, the s/uni-atlas-3200 is fully symmetric, with identical features and configuration options in either direction. the input cell interface can be connected to a phy device supporting up to 48 phy queues via a utopia level 3 or pos-phy level 3 bus, or may emulate up to 48 phys via multi-phy addressing over a utopia level 3 or pos-phy level 3 bus. the 52- or 53-byte atm cell is encapsulated in a data structure that can contain prepended or postpended routing information, and can fill the hec field out to 32 bits. received cells are buffered in a programmable-depth per-phy fifo. all idle cells, physical layer and unassigned cells are discarded, and any cells from phy queues designated as packet phys are routed to the output untouched. for the remaining cells, a subset of atm header and appended bits is used as a search key to find the vc table record for the virtual connection. if a connection is not provisioned and the search terminates unsuccessfully as a result, the cell is discarded and a count of invalid cells is incremented. if the search is successful, subsequent processing of the cell is dependent on the contents of the cell and configuration fields in the vc table record. the s/uni-atlas-3200 performs header translation, if so configured. the atm header is replaced by the contents of fields in the vc table record for that connection. the vci contents are passed through transparently for vpc connections; the pti is passed through transparently for all connections. the clp bit may only be altered via the policing function. appended bytes can be replaced, added or removed. if the s/uni-atlas-3200 is the end point for a f4 or f5 oam flow, the oam cells are terminated and processed. if the s/uni-atlas-3200 is not the end point, the oam cells are passed to the output cell interface with an optional copy passed to the microprocessor cell interface fifo. the reception of ais or rdi cells results in the appropriate alarms (segment or end-to-end alarm). interrupts corresponding to the alarm bits can be masked on a per-connection basis. when configured as a sink of pm cells, upon the arrival of a forward monitoring cell, error counts are updated and a backward reporting cell is optionally generated and routed to the backwards cell interface that is connected to the opposite-direction s/uni-atlas-3200. when configured as a source of pm cells, the s/uni-atlas-3200 generates a forward monitoring cell when the per-session programmable user cell block size is reached. the insertion of pm cells is paced so that bursts of generated cells will not cause a backup.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 document id: pmc-1990553, issue 4 cell rate policing is supported through a dual leaky bucket policer that conforms to the itu-t i.371 generic cell rate algorithm for each connection. each cell that violates the traffic contract can be tagged, discarded, or just counted. to allow full flexibility, each gcra instance can be programmed to police any combination of user cells, oam cells, resource management cells, high priority cells or low priority cells. on a per-connection basis, one of eight policing configurations may be chosen. three 16-bit non-compliant cell counts are provided on a per- connection basis. these counters are programmable and allow for the counting of, for example, dropped clp0 cells, dropped clp1 cells and tagged clp0 cells. on a per-vc basis, the dual leaky bucket policer may be configured to perform atm forum tm 4.1-compliant gfr policing. in this mode, the non-compliant counts may be configured to count received frames, dropped frames, or tagged frames as well as counting dropped or tagged cells. the s/uni-atlas-3200 also supports a single leaky bucket policer on a per-phy basis (up to 48 instances can be programmed). any or all connections on a particular phy can be policed by the phy gcra. each phy gcra has a programmable action field that allows violating cells to be tagged, discarded, or just counted. three configurable non-compliant cell counts (on each phy gcra) are also provided. each phy gcra can be programmed to police any combination of user cells, oam cells, resource management cells, high priority cells or low priority cells. any one of four phy policing configurations may be chosen. the 32-bit microprocessor interface is provided for device configuration, control and monitoring by an external microprocessor. this interface provides access to the external sram and internal dram to allow creation of the data structure, configuration of individual connections, and monitoring of the connections. the microprocessor cell fifo permits insertion and extraction of cells. programmed cell types can be routed to the microprocessor cell fifo (and subsequently read through the microprocessor cell interface). the microprocessor may insert cells into the cell stream which may be processed, translated, counted, routed, and policed by the s/uni-atlas- 3200, or not, at the option of the microprocessor. when the device is in egress mode, the output cell interface is a 32-bit utopia level 3 or pos-phy level 3 transmit link layer interface which can address up to 48 phy queues on a phy device using polled addressing. cells are stored in a per-phy programmable-depth fifo and subsequently transferred to a phy device. a total of 192 cell buffers are provided, which may be divided up among the phys as desired. a phy output buffer requires at least 12 cell buffers if it is to maintain full sts-12 or more on that phy, 4 cell buffers if it is to maintain sts- 3 on that phy, and 2 cell buffers if it is to maintain sts-1 or less on that phy. the fifo depth for each phy can be configured to hold 2, 4, 12, or 48 cells. when the device is in ingress ul3 mode, the output cell interface is a 32-bit utopia level 3 rx phy (slave) interface which may mimic up to 48 phys using polled addressing, or may optionally operate without polling. when configured in ingress pos-phy mode, the output cell interface is a pos-phy level 3 rx phy layer which mimics up to 48 phys. cells are stored in a per-phy programmable-depth fifo and subsequently transferred to a tm or switch device. a total of 192 cell buffers are provided, which may be divided up among the phys as desired. a phy output buffer requires at least 12 cell buffers if it is to maintain full sts-12 or more on that phy, 4 cell buffers if it is to maintain sts-3 on that phy, and 2 cell buffers if it is to maintain sts-1 or less on that phy. the fifo depth for each phy can be configured to hold 2, 4, 12, or 48 cells.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 is implemented in low power 0.18 micron 1.5 volt cmos technology with 2.5 volt embedded dram. the sram interface uses 2.5 volt signalling; all other i/os are 3.3 volts. note that the 2.5 volt interfaces are not 3.3 volt-tolerant. the s/uni-atlas-3200 is packaged in a 768-pin tape bga package.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 document id: pmc-1990553, issue 4 8 pin diagram the s/uni-atlas-3200 is packaged in a 768-pin tape bga package with a body size of 40 mm x 40 mm x 1.54 mm and a ball pitch of 1 mm. this pin diagram is available in a spreadsheet format in pmc-2001760. figure 4 pin diagram abcdefghj kl mnprtuvw 38 sdat_61 vss sdat_58 sdat_55 sdat_52 vdd25 vss sdat_46 sdat_43 vdd15 vss sdat_36 vdd15 vdd25 vdd15 sdat_28 vss sdat_23 sdat_21 37 vdd25 sdat_62 sdat_59 sdat_56 sdat_53 sdat_50 sdat_49 sdat_47 sdat_44 sdat_41 vss sdat_38 sdat_35 sdat_32 vss vss sdat_26 sdat_24 vdd15 36 zetmdl vss vss vdd15 sdat_57 sdat_54 vdd15 sdat_51 sdat_48 sdat_45 sdat_42 sdat_39 sdat_37 sdat_34 sdat_31 sdat_29 sdat_27 vss sdat_22 35 vss vss sramclk_o sdat_63 vss vss vss vss vdd25 vdd25 vss vss sdat_40 vss sdat_33 sdat_30 vss sdat_25 vdd25 34 ocif_dat_ 29 vss ocif_dat_3 1 vdd25 vdd25 sdat_60 vss vss vdd25 vdd25 vss vss vdd33 vdd33 vss vss vdd25 vdd25 vss 33 ocif_dat_ 27 ocif_dat_2 8 ocif_dat_3 0 vdd15 zetmdr vss vss vss vdd33 vdd15 vss vss vdd25 vdd15 vss vss vdd33 vdd15 vss 32 ocif_dat_ 25 vss vdd33 vdd25 vdd15 vdd25 31 ocif_dat_ 24 vss ocif_dat_2 6 vdd25 vdd15 vdd33 30 ocif_dat_ 21 ocif_dat_2 2 ocif_dat_2 3 vss vss vss 29 ocif_dat_ 18 ocif_dat_1 9 ocif_dat_2 0 vss vss vss 28 vdd33 ocif_dat_1 6 ocif_dat_1 7 vdd33 vdd33 vdd15 27 vss ocif_dat_1 3 ocif_dat_1 5 vdd33 vdd33 vdd25 26 ocif_dat_ 10 ocif_dat_1 1 ocif_dat_1 2 ocif_dat_1 4 vss vss 25 vdd15 ocif_dat_9 vss vss vss vss 24 vss ocif_dat_6 ocif_dat_7 ocif_dat_8 vdd25 vdd15 23 vss ocif_dat_3 ocif_dat_4 ocif_dat_5 vdd25 vdd33 22 ocif_dat_ 2 ocif_dat_0 vdd15 ocif_dat_1 vss vss 21 vss ocif_par vss ocif_eop vss vss 20 vdd15 ocif_soc_ sop vss vdd15 vdd33 vdd15 19 ocif_sx ocif_err vdd15 vss vdd33 vdd25 18 ocif_mod _1 ocif_mod_ 0 ocif_clav_ ptpa vdd15 vss vss top view 17 ocif_enb_ stpa vdd33 ocif_addr_ 5 ocif_addr_ 4 vss vss 16 ocif_addr _3 vss ocif_addr_ 2 ocif_addr_ 0 vdd25 vdd15 15 ocif_addr _1 ocif_clk ocif_ctrl vss vdd25 vdd33 14 halfsecclk vdd15 vddq15 vdd15 vss vss 13 vss vddq15 vss vss vss vss 12 vss vss vss vdd33 vdd33 vdd15 11 vddq15 vddq15 vddq15 vdd33 vdd33 vdd25 10 vss vddq15 vss vss vss vss 9 vss vddq15 tck vss vss vss 8 vss dtclk nc vdd25 vdd15 vdd33 7 dtmb vddq15 nc vdd25 vdd15 vdd25 6 vss trstb vddq25 nc vss vdd25 vss vss vdd15 vdd33 vss vss vdd15 vdd25 vss vss vdd15 vdd33 vss 5 nc nc nc nc vss bi_dat_11 vss vss vdd25 vdd25 vss vss vdd33 vdd33 vss vss vdd25 vdd25 vss 4 vddq25 vddq25 vdd15 tdo bi_dat_12 bi_dat_7 vss vss vdd25 vdd25 vss vss bi_rclav_t wrenb vddq15 bo_soc bo_dat_0 bo_dat_2 vss bo_dat_7 3 nc nc tdi bi_dat_13 bi_dat_8 vddq25 bi_dat_4 vddq25 bi_dat_0 vss vddq15 vss bo_rdenb bo_clav vdd33 vss bo_dat_3 vddq15 vss 2 vss tms bi_dat_14 bi_dat_9 bi_dat_5 vddq15 bi_dat_2 bi_dat_1 bi_par bi_clk vss vddq15 vss vddq15 vss bo_dat_1 vss bo_dat_5 bo_dat_6 1 nc bi_dat_15 bi_dat_10 bi_dat_6 vddq15 bi_dat_3 vss vddq15 vss bi_soc bi_rrdenb _tclav vss vss bo_clk bo_par vss vddq15 bo_dat_4 vss abcdefghj kl mnprt uvw
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 document id: pmc-1990553, issue 4 yaaabacadaeafagahaj akal amanaparatauav sdat_ 19 sdat_16 sdat_14 vss sdat_11 sdat_10 vdd25 vss sdat_2 spar_7 spar_4 spar_1 vdd25 vss vss saddr_17 saddr_14 saddr_10 saddr_6 38 vss sdat_17 vss sdat_13 vss sdat_8 vdd25 sdat_4 sdat_1 spar_6 spar_3 spar_0 xclk sysclk_o srwb vdd25 saddr_11 vss vdd15 37 vdd1 5 vss vss vss vdd15 sdat_7 sdat_5 sdat_3 sdat_0 spar_5 spar_2 vss sysclk sceb saddr_15 saddr_12 saddr_7 vss vdd15 36 sdat_ 20 sdat_18 sdat_15 sdat_12 sdat_9 sdat_6 vss vss vss vdd25 vdd25 vss vss saddr_16 vss saddr_8 saddr_4 saddr_2 saddr_1 35 vss vdd25 vdd25 vss vss vdd33 vdd33 vss vss vdd25 vdd25 vss vss saddr_13 saddr_9 vss vdd25 icif_enb_s tpa vdd33 34 vss vdd25 vdd15 vss vss vdd33 vdd15 vss vss vdd25 vdd15 vss vss vdd25 saddr_5 saddr_3 saddr_0 vss icif_addr_ 0 33 vdd33 vdd15 vdd25 icif_clav_ ptpa icif_addr_ 1 icif_addr_ 3 32 vdd25 vdd15 vdd25 icif_clk vdd15 icif_addr_ 4 31 vss vss vss icif_addr_ 2 icif_ctrl icif_mod_ 0 30 vss vss vss icif_addr_ 5 icif_err vss 29 vdd33 vdd33 vdd33 icif_mod_ 1 icif_sx icif_eop 28 vdd15 vdd33 vdd33 icif_soc_s op icif_par vss 27 vss vss vss icif_dat_0 icif_dat_2 icif_dat_3 26 vss vss icif_dat_1 vdd15 icif_dat_5 vdd33 25 vdd25 vdd25 icif_dat_4 icif_dat_6 icif_dat_7 vss 24 vdd15 vdd25 icif_dat_8 icif_dat_9 vdd15 icif_dat_1 0 23 vss vss icif_dat_1 1 icif_dat_1 2 vss icif_dat_1 3 22 vss vss vdd15 icif_dat_1 4 icif_dat_1 5 icif_dat_1 6 21 top view vdd33 vdd33 vss vdd15 icif_dat_1 7 icif_dat_1 8 20 vdd15 vdd33 icif_dat_1 9 vdd15 icif_dat_2 0 vss 19 vss vss icif_dat_2 2 icif_dat_2 1 icif_dat_2 3 vdd15 18 vss vss icif_dat_2 6 icif_dat_2 5 icif_dat_2 4 vdd33 17 vdd25 vdd25 icif_dat_2 9 icif_dat_2 8 vss icif_dat_2 7 16 vdd15 vdd25 vddq15 vss vdd33 icif_dat_3 0 15 vss vss vss vddq15 vss icif_dat_3 1 14 vss vss vddq15 vss vdd15 vss 13 vdd33 vdd33 vdd33 vss vss up_dat_3 1 12 vdd15 vdd33 vdd33 vss vddq15 up_dat_3 0 11 vss vss vss up_dat_2 9 vss vddq15 10 vss vss vss up_dat_2 6 up_dat_2 7 up_dat_2 8 9 vdd25 vdd15 vdd25 vddq25 up_dat_2 5 vss 8 vdd33 vdd15 vdd25 vddq15 vss vddq25 7 vss vdd15 vdd25 vss vss vdd15 vdd33 vss vss vdd15 vdd25 vss vss vss nc up_dat_2 3 vddq15 vddq15 vss 6 vss vdd25 vdd25 vss vss vdd33 vdd33 vss vss vdd25 vdd25 vss vss up_dat_1 5 up_dat_1 9 nc up_dat_2 2 vddq25 vss 5 bo_da t_8 vss vss vddq15 up_wrb vss up_addr_ 2 vss vss vdd25 vdd25 vss vss vddq25 up_dat_1 4 up_dat_1 8 nc up_dat_2 1 up_dat_2 4 4 vss vss bo_dat_1 0 bo_dat_1 2 bo_dat_1 5 up_rdb up_dmare q up_addr_ 1 up_addr_ 6 up_addr_ 9 up_dat_1 up_dat_5 up_dat_6 vddq15 vss up_dat_1 3 vss nc up_dat_2 0 3 vss vss vddq15 bo_dat_1 1 bo_dat_1 4 up_rstb vss up_busyb up_addr_ 3 up_addr_ 5 up_addr_ 8 up_addr_ 11 up_dat_2 up_dat_4 up_dat_8 up_dat_1 0 up_dat_1 2 up_dat_1 7 nc 2 vdd q15 vddq15 bo_dat_9 vddq25 bo_dat_1 3 up_intb up_ale up_csb up_addr_ 0 up_addr_ 4 up_addr_ 7 up_addr_ 10 up_dat_0 up_dat_3 up_dat_7 up_dat_9 up_dat_1 1 vss up_dat_1 6 1 yaaabacadaeafagahaj akal amanaparatauav
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 document id: pmc-1990553, issue 4 table 1 signal ball assignment (alphabetical) signal ball signal ball signal ball signal ball bi_clk k2 icif_dat_28 at16 saddr_15 ap36 sdat_9 ad35 bi_dat_0 j3 icif_dat_29 ar16 saddr_16 an35 spar_0 al37 bi_dat_1 h2 icif_dat_3 av26 saddr_17 ar38 spar_1 al38 bi_dat_10 c1 icif_dat_30 av15 saddr_2 au35 spar_2 ak36 bi_dat_11 f5 icif_dat_31 av14 saddr_3 ar33 spar_3 ak37 bi_dat_12 e4 icif_dat_4 ar24 saddr_4 at35 spar_4 ak38 bi_dat_13 d3 icif_dat_5 au25 saddr_5 ap33 spar_5 aj36 bi_dat_14 c2 icif_dat_6 at24 saddr_6 av38 spar_6 aj37 bi_dat_15 b1 icif_dat_7 au24 saddr_7 at36 spar_7 aj38 bi_dat_2 g2 icif_dat_8 ar23 saddr_8 ar35 sramclk_o c35 bi_dat_3 f1 icif_dat_9 at23 saddr_9 ap34 srwb ap37 bi_dat_4 g3 icif_enb_stpa au34 sceb an36 sysclk am36 bi_dat_5 e2 icif_eop av28 sdat_0 ah36 sysclk_o an37 bi_dat_6 d1 icif_err au29 sdat_1 ah37 tck c9 bi_dat_7 f4 icif_mod_0 av30 sdat_10 ae38 tdi c3 bi_dat_8 e3 icif_mod_1 at28 sdat_11 ad38 tdo d4 bi_dat_9 d2 icif_par au27 sdat_12 ac35 tms b2 bi_par j2 icif_soc_sop at27 sdat_13 ac37 trstb b6 bi_rclav_twrenb n4 icif_sx au28 sdat_14 ab38 up_addr_0 ah1 bi_rrdenb_tclav l1 ocif_addr_0 d16 sdat_15 ab35 up_addr_1 ag3 bi_soc k1 ocif_addr_1 a15 sdat_16 aa38 up_addr_10 al1 bo_clav p3 ocif_addr_2 c16 sdat_17 aa37 up_addr_11 al2 bo_clk p1 ocif_addr_3 a16 sdat_18 aa35 up_addr_2 af4 bo_dat_0 t4 ocif_addr_4 d17 sdat_19 y38 up_addr_3 ah2 bo_dat_1 t2 ocif_addr_5 c17 sdat_2 ah38 up_addr_4 aj1 bo_dat_10 ab3 ocif_clav_ptpa c18 sdat_20 y35 up_addr_5 aj2 bo_dat_11 ac2 ocif_clk b15 sdat_21 w38 up_addr_6 ah3 bo_dat_12 ac3 ocif_ctrl c15 sdat_22 w36 up_addr_7 ak1 bo_dat_13 ad1 ocif_dat_0 b22 sdat_23 v38 up_addr_8 ak2 bo_dat_14 ad2 ocif_dat_1 d22 sdat_24 v37 up_addr_9 aj3 bo_dat_15 ad3 ocif_dat_10 a26 sdat_25 v35 up_ale af1 bo_dat_2 u4 ocif_dat_11 b26 sdat_26 u37 up_busyb ag2 bo_dat_3 u3 ocif_dat_12 c26 sdat_27 u36 up_csb ag1 bo_dat_4 v1 ocif_dat_13 b27 sdat_28 t38 up_dat_0 am1 bo_dat_5 v2 ocif_dat_14 d26 sdat_29 t36 up_dat_1 ak3 bo_dat_6 w2 ocif_dat_15 c27 sdat_3 ag36 up_dat_10 ar2 bo_dat_7 w4 ocif_dat_16 b28 sdat_30 t35 up_dat_11 at1 bo_dat_8 y4 ocif_dat_17 c28 sdat_31 r36 up_dat_12 at2 bo_dat_9 ab1 ocif_dat_18 a29 sdat_32 p37 up_dat_13 ar3
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 document id: pmc-1990553, issue 4 signal ball signal ball signal ball signal ball bo_par r1 ocif_dat_19 b29 sdat_33 r35 up_dat_14 ap4 bo_rdenb n3 ocif_dat_2 a22 sdat_34 p36 up_dat_15 an5 bo_soc r4 ocif_dat_20 c29 sdat_35 n37 up_dat_16 av1 dtclk b8 ocif_dat_21 a30 sdat_36 m38 up_dat_17 au2 dtmb a7 ocif_dat_22 b30 sdat_37 n36 up_dat_18 ar4 halfsecclk a14 ocif_dat_23 c30 sdat_38 m37 up_dat_19 ap5 icif_addr_0 av33 ocif_dat_24 a31 sdat_39 m36 up_dat_2 am2 icif_addr_1 au32 ocif_dat_25 a32 sdat_4 ag37 up_dat_20 av3 icif_addr_2 at30 ocif_dat_26 c31 sdat_40 n35 up_dat_21 au4 icif_addr_3 av32 ocif_dat_27 a33 sdat_41 k37 up_dat_22 at5 icif_addr_4 av31 ocif_dat_28 b33 sdat_42 l36 up_dat_23 ar6 icif_addr_5 at29 ocif_dat_29 a34 sdat_43 j38 up_dat_24 av4 icif_clav_ptpa at32 ocif_dat_3 b23 sdat_44 j37 up_dat_25 au8 icif_clk at31 ocif_dat_30 c33 sdat_45 k36 up_dat_26 at9 icif_ctrl au30 ocif_dat_31 c34 sdat_46 h38 up_dat_27 au9 icif_dat_0 at26 ocif_dat_4 c23 sdat_47 h37 up_dat_28 av9 icif_dat_1 ar25 ocif_dat_5 d23 sdat_48 j36 up_dat_29 at10 icif_dat_10 av23 ocif_dat_6 b24 sdat_49 g37 up_dat_3 an1 icif_dat_11 ar22 ocif_dat_7 c24 sdat_5 af36 up_dat_30 av11 icif_dat_12 at22 ocif_dat_8 d24 sdat_50 f37 up_dat_31 av12 icif_dat_13 av22 ocif_dat_9 b25 sdat_51 h36 up_dat_4 an2 icif_dat_14 at21 ocif_enb_stpa a17 sdat_52 e38 up_dat_5 al3 icif_dat_15 au21 ocif_eop d21 sdat_53 e37 up_dat_6 am3 icif_dat_16 av21 ocif_err b19 sdat_54 f36 up_dat_7 ap1 icif_dat_17 au20 ocif_mod_0 b18 sdat_55 d38 up_dat_8 ap2 icif_dat_18 av20 ocif_mod_1 a18 sdat_56 d37 up_dat_9 ar1 icif_dat_19 ar19 ocif_par b21 sdat_57 e36 up_dmareq af3 icif_dat_2 au26 ocif_soc_sop b20 sdat_58 c38 up_intb ae1 icif_dat_20 au19 ocif_sx a19 sdat_59 c37 up_rdb ae3 icif_dat_21 at18 saddr_0 at33 sdat_6 ae35 up_rstb ae2 icif_dat_22 ar18 saddr_1 av35 sdat_60 f34 up_wrb ad4 icif_dat_23 au18 saddr_10 au38 sdat_61 a38 xclk am37 icif_dat_24 au17 saddr_11 at37 sdat_62 b37 zetmdl a36 icif_dat_25 at17 saddr_12 ar36 sdat_63 d35 zetmdr e33 icif_dat_26 ar17 saddr_13 an34 sdat_7 ae36 icif_dat_27 av16 saddr_14 at38 sdat_8 ae37 table 2 power/ground ball assignment (alphabetical) signal ball signal ball signal ball signal ball vdd15 a20 vdd25 k34 vss a9 vss b36
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 document id: pmc-1990553, issue 4 signal ball signal ball signal ball signal ball vdd15 a25 vdd25 k35 vss aa2 vss b38 vdd15 aa6 vdd25 k4 vss aa3 vss c10 vdd15 ab33 vdd25 k5 vss aa36 vss c12 vdd15 ad36 vdd25 n33 vss aa4 vss c13 vdd15 ae6 vdd25 p38 vss ab36 vss c20 vdd15 af33 vdd25 p6 vss ab37 vss c21 vdd15 aj6 vdd25 u34 vss ab4 vss c25 vdd15 ak33 vdd25 u5 vss ac33 vss c36 vdd15 an11 vdd25 v34 vss ac34 vss d10 vdd15 an15 vdd25 v5 vss ac36 vss d13 vdd15 an19 vdd25 w35 vss ac38 vss d15 vdd15 an23 vdd33 a28 vss ac5 vss d19 vdd15 an27 vdd33 ae33 vss ac6 vss d25 vdd15 ap31 vdd33 ae34 vss ad33 vss d29 vdd15 ap32 vdd33 ae5 vss ad34 vss d30 vdd15 ap7 vdd33 af34 vss ad37 vss d9 vdd15 ap8 vdd33 af5 vss ad5 vss e10 vdd15 ar21 vdd33 af6 vss ad6 vss e13 vdd15 at19 vdd33 an12 vss ae4 vss e14 vdd15 at20 vdd33 an20 vss af2 vss e17 vdd15 at25 vdd33 an28 vss af35 vss e18 vdd15 au13 vdd33 an32 vss ag33 vss e21 vdd15 au23 vdd33 an7 vss ag34 vss e22 vdd15 au31 vdd33 ap11 vss ag35 vss e25 vdd15 av18 vdd33 ap12 vss ag38 vss e26 vdd15 av36 vdd33 ap19 vss ag4 vss e29 vdd15 av37 vdd33 ap20 vss ag5 vss e30 vdd15 b14 vdd33 ap27 vss ag6 vss e35 vdd15 c19 vdd33 ap28 vss ah33 vss e5 vdd15 c22 vdd33 ar11 vss ah34 vss e6 vdd15 c4 vdd33 ar12 vss ah35 vss e9 vdd15 d14 vdd33 ar27 vss ah4 vss f10 vdd15 d18 vdd33 ar28 vss ah5 vss f13 vdd15 d20 vdd33 au15 vss ah6 vss f14 vdd15 d33 vdd33 av17 vss al33 vss f17 vdd15 d36 vdd33 av25 vss al34 vss f18 vdd15 e31 vdd33 av34 vss al35 vss f21 vdd15 e32 vdd33 b17 vss al36 vss f22 vdd15 e7 vdd33 c32 vss al4 vss f25 vdd15 e8 vdd33 d11 vss al5 vss f26
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 document id: pmc-1990553, issue 4 signal ball signal ball signal ball signal ball vdd15 f12 vdd33 d12 vss al6 vss f29 vdd15 f16 vdd33 d27 vss am33 vss f30 vdd15 f20 vdd33 d28 vss am34 vss f33 vdd15 f24 vdd33 e11 vss am35 vss f35 vdd15 f28 vdd33 e12 vss am4 vss f9 vdd15 g36 vdd33 e19 vss am5 vss g1 vdd15 j6 vdd33 e20 vss am6 vss g33 vdd15 k33 vdd33 e27 vss an10 vss g34 vdd15 k38 vdd33 e28 vss an13 vss g35 vdd15 n38 vdd33 f15 vss an14 vss g38 vdd15 n6 vdd33 f23 vss an17 vss g4 vdd15 p33 vdd33 f31 vss an18 vss g5 vdd15 r38 vdd33 f8 vss an21 vss g6 vdd15 u6 vdd33 j33 vss an22 vss h33 vdd15 v33 vdd33 k6 vss an25 vss h34 vdd15 w37 vdd33 n34 vss an26 vss h35 vdd15 y36 vdd33 n5 vss an29 vss h4 vdd25 a37 vdd33 p34 vss an30 vss h5 vdd25 aa33 vdd33 p5 vss an38 vss h6 vdd25 aa34 vdd33 r3 vss an6 vss j1 vdd25 aa5 vdd33 u33 vss an9 vss k3 vdd25 ab34 vdd33 v6 vss ap10 vss l2 vdd25 ab5 vddq15 a11 vss ap13 vss l33 vdd25 ab6 vddq15 aa1 vss ap14 vss l34 vdd25 af37 vddq15 ab2 vss ap17 vss l35 vdd25 af38 vddq15 ac4 vss ap18 vss l37 vdd25 aj33 vddq15 an3 vss ap21 vss l38 vdd25 aj34 vddq15 ar13 vss ap22 vss l4 vdd25 aj35 vddq15 ar15 vss ap25 vss l5 vdd25 aj4 vddq15 at14 vss ap26 vss l6 vdd25 aj5 vddq15 at6 vss ap29 vss m1 vdd25 ak34 vddq15 at7 vss ap3 vss m3 vdd25 ak35 vddq15 au11 vss ap30 vss m33 vdd25 ak4 vddq15 au6 vss ap35 vss m34 vdd25 ak5 vddq15 av10 vss ap38 vss m35 vdd25 ak6 vddq15 b10 vss ap9 vss m4 vdd25 am38 vddq15 b11 vss ar10 vss m5 vdd25 an16 vddq15 b13 vss ar14 vss m6 vdd25 an24 vddq15 b7 vss ar20 vss n1 vdd25 an31 vddq15 b9 vss ar26 vss n2
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 document id: pmc-1990553, issue 4 signal ball signal ball signal ball signal ball vdd25 an33 vddq15 c11 vss ar29 vss p35 vdd25 an8 vddq15 c14 vss ar30 vss r2 vdd25 ap15 vddq15 e1 vss ar34 vss r33 vdd25 ap16 vddq15 f2 vss ar9 vss r34 vdd25 ap23 vddq15 h1 vss at11 vss r37 vdd25 ap24 vddq15 l3 vss at12 vss r5 vdd25 ar31 vddq15 m2 vss at13 vss r6 vdd25 ar32 vddq15 p2 vss at15 vss t1 vdd25 ar37 vddq15 p4 vss at3 vss t3 vdd25 ar7 vddq15 u1 vss au1 vss t33 vdd25 ar8 vddq15 v3 vss au10 vss t34 vdd25 at34 vddq15 y1 vss au12 vss t37 vdd25 d31 vddq25 a4 vss au14 vss t5 vdd25 d32 vddq25 ac1 vss au16 vss t6 vdd25 d34 vddq25 an4 vss au22 vss u2 vdd25 d7 vddq25 at8 vss au33 vss u35 vdd25 d8 vddq25 au5 vss au36 vss u38 vdd25 e15 vddq25 av7 vss au37 vss v36 vdd25 e16 vddq25 b4 vss au7 vss v4 vdd25 e23 vddq25 c6 vss av13 vss w1 vdd25 e24 vddq25 f3 vss av19 vss w3 vdd25 e34 vddq25 h3 vss av24 vss w33 vdd25 f11 vss a10 vss av27 vss w34 vdd25 f19 vss a12 vss av29 vss w5 vdd25 f27 vss a13 vss av5 vss w6 vdd25 f32 vss a2 vss av6 vss y2 vdd25 f38 vss a21 vss av8 vss y3 vdd25 f6 vss a23 vss b12 vss y33 vdd25 f7 vss a24 vss b16 vss y34 vdd25 j34 vss a27 vss b31 vss y37 vdd25 j35 vss a35 vss b32 vss y5 vdd25 j4 vss a6 vss b34 vss y6 vdd25 j5 vss a8 vss b35 vdd25 k34 vss a9 vss b36
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 document id: pmc-1990553, issue 4 9 pin description pin name type pin no function sram interface (95 pins) the sram interface is a 2.5v, 125 mhz zbt sram interface. xclk input crystal clock, nominally 125 mhz. sramclk_o output sram clock out. this clock is derived from xclk, and must drive both the sram and the sysclk input for proper operation. sysclk_o output sysclk output feedback clock. this clock is identical to sramclk_o, but must be connected to the sysclk input. it is used to match the delays that sramclk_o experiences, allowing the timing on the sram interface to be guaranteed. sysclk input system clock. this clock must be driven by the sysclk_o output. sdat[63:0] i/o sram data. during a write, this output is updated on sramclk_o. during reads, this input is sampled on the rising edge of sysclk. one cycle of high-impedance is inserted between changes of direction on this i/o. spar[7:0] i/o sram parity. these bits provide byte parity protection across sdat[63:0] and saddr[17:0]. during writes, spar[7:0] is generated by xoring together 8 bits of odd parity on sdat[63:0] with 3 bits, lsb justified, of odd parity on saddr[17:0]. during writes, this output is updated on the rising edge of sramclk_o. during reads, this input is sampled on the rising edge of sysclk. one cycle of high-impedance is inserted between changes of direction on this i/o. saddr[17:0] output sram address. 18 bits are provided, to support up to a 256kx72 external sram. if less sram is provisioned, the msb of the ram address (which selects the linkage vs search tables) should still be connected to saddr[17]; saddr[16] may be left unconnected if only 8m of external sram is needed, saddr[16:15] if only 4m, and so on. this output is updated on the rising edge of sramclk_o. srwb output sram read/write. indicates whether a read or a write access is to be executed on the sram. updated on the rising edge of sramclk_o. sceb output sram chip enable. when low, activates the external sram for an access. when high, the sram is deselected, and must go high-impedance on the third subsequent rising edge of sramclk_o. updated on the rising edge of sramclk_o.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 document id: pmc-1990553, issue 4 pin name type pin no function input cell/packet interface (49 pins) this interface can work in one of four different modes: mode a (ingress ul3 master input) : rx link layer utopia l3 interface (prefix: rlu_*) mode b (egress ul3 slave input) : tx phy layer utopia l3 interface (prefix: tpu_*) mode c (posphy ingress input) : rx link layer posphy l3 interface (prefix: rlp_*) mode d (posphy egress input) : tx phy layer posphy l3 interface (prefix: tpp_*) one of these four modes may be chosen in software. the choice of mode is static is must not be changed during chip operation. the easiest way to read the table below is to pick a mode of operation (a,b,c, or d) and to read only those lines that pertain to the chosen mode. each pin also has a generic name, which may be used to reference the pin diagrams. icif_clk (a) rlu_clk (a) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc- 48c bandwidth is guaranteed only for 104 mhz. (b) tpu_clk (b) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz. (c) rlp_clk (c) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz. (d) tpp_clk input (d) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz. icif_dat[31:0] (a) rlu_dat[31:0] (a) 32-bit data bus. the data path for data from the phy to the s/uni-atlas-3200. in the 32-bit data path, rlu_dat[31] is the msb, rlu_dat[0] is the lsb. (b) tpu_dat[31:0] (b) 32-bit data bus. the data path for data from the traffic manager/fabric to the s/uni-atlas-3200. in the 32-bit data path, tpu_dat[31] is the msb, tpu_dat[0] is the lsb. (c) rlp_dat[31:0] (c) 32-bit data bus. the rlp_dat[31:0] bus carries the packet octets that are read from the receive fifo and the in-band port address of the selected receive fifo. rlp_dat[31:0] is considered as valid packet data when rlp_val is asserted. when rlp_eop is asserted, the rlp_mod[1:0] bits indicate how many bytes are valid. when rlp_sx is asserted, rlp_dat[7:0] contains the in-band port address, and rlp_dat[31:24] optionally carries the payload type field identifying the packet as atm or pos. rlp_dat[31] is the most significant bit. (d) tpp_dat[31:0] input (d) 32-bit data bus. this bus carries the packet octets that are written to the selected transmit fifo and the in-band port address to select the desired transmit fifo. the tpp_dat bus is considered valid packet data when tpp_enb is asserted. when tpp_sx is asserted, tpp_dat[7:0] contains the in-band port address, and tpp_dat[31:24] optionally carries the payload type field identifying the packet as atm or pos. tpp_dat[31] is the most significant bit.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 document id: pmc-1990553, issue 4 pin name type pin no function icif_par (a) rlu_par (a) parity over rlu_dat (programmable to odd or even) (b) tpu_par (b) parity over tpu_dat (programmable to odd or even) (c) rlp_par (c) parity over data bus (programmable to odd or even) the receive parity (rlp_par) signal indicates the parity calculated over the rlp_dat bus, and is required to be valid whenever rlp_val or rlp_sx are asserted. (d) tpp_par input (d) parity over data bus (programmable to odd or even) the transmit parity (tpp_par) signal indicates the parity calculated over the tpp_dat bus. tpp_par is considered valid only when tpp_enb or tpp_sx are asserted. icif_soc_sop (a) rlu_soc (a) start of cell. active high signal asserted to indicate the start of cell position. whenever rlu_soc is logic 1, the s/uni-atlas- 3200 will assume that the start of cell is present, and will synchronize itself accordingly. (b) tpu_soc (b) start of cell. active high signal asserted to indicate the start of cell position. whenever rlu_soc is logic 1, the s/uni-atlas- 3200 will assume that the start of cell is present, and will synchronize itself accordingly. (c) rlp_sop (c) start of packet. rlp_sop is used to delineate the packet boundaries on the rlp_dat bus. when rlp_sop is high, the start of the packet is present on the rlp_dat bus. rlp_sop is required to be present at the start of every packet and is considered valid when rlp_val is asserted. (d) tpp_sop input (d) start of packet. tpp_sop is used to delineate the packet boundaries on the tpp_dat bus. when tpp_sop is high, the start of the packet is present on the tpp_dat bus. tpp_sop is required to be present at the beginning of every packet and is considered valid only when tpp_enb is asserted.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 document id: pmc-1990553, issue 4 pin name type pin no function icif_eop (a) not used (b) not used (c) rlp_eop (c) end of packet. rlp_eop is used to delineate the packet boundaries on the rlp_dat bus. when rlp_eop is high, the end of the packet is present on the rlp_dat bus. rlp_mod[1:0] indicates the number of valid bytes the last double-word is composed of when rlp_eop is asserted. rlp_eop is required to be present at the end of every packet and is considered valid only when rval is asserted. s/uni-atlas-3200 will always end a transfer at eop, and perform a new rlp_sx cycle. as a result, the minimum average packet size for which oc-48 throughput can be guaranteed is 32 bytes. (d) tpp_eop input (d) end of packet. tpp_eop is used to delineate the packet boundaries on the tpp_dat bus. when tpp_eop is high, the end of the packet is present on the tpp_dat bus. tpp_mod[1:0] indicates the number of valid bytes the last double-word is composed of when tpp_eop is asserted. tpp_eop is required to be present at the end of every packet and is considered valid only when tpp_enb is asserted. s/uni-atlas-3200 will always end a transfer at eop, and perform a new sx cycle. as a result, the minimum average packet size for which oc-48 throughput can be guaranteed is xx bytes. each transfer requires a separate positive ptpa response. as a result, the minimum average packet size which can be guaranteed in single-phy operation is xx bytes.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 document id: pmc-1990553, issue 4 pin name type pin no function icif_mod[1:0] (a) not used (b) not used (c) rlp_mod[1:0] (c) number of bytes in packet modulo 4 rlp_mod[1:0] indicates the number of valid bytes of data in rlp_dat[31:0]. the rlp_mod bus should always be all zero, except during the last double-word transfer of a packet on rlp_dat[31:0]. when rlp_eop is asserted, the number of valid packet data bytes on rlp_dat[31:0] is specified by rlp_mod[1:0] rlp_mod[1:0] = ?00? rlp_dat[31:0] valid rlp_mod[1:0] = ?01? rlp_dat[31:8] valid rlp_mod[1:0] = ?10? rlp_dat[31:16] valid rlp_mod[1:0] = ?11? rlp_dat[31:24] valid rlp_mod[1:0] is considered valid only when rlp_val is asserted. (d) tpp_mod[1:0] input (d) number of bytes in packet modulo 4 tpp_mod[1:0] indicates the number of valid bytes of data in tpp_dat[31:0]. the tpp_mod bus should always be all zero, except during the last double-word transfer of a packet on tpp_dat[31:0]. when tpp_eop and tpp_enb are asserted, the number of valid packet data bytes on tpp_dat[31:0] is specified by tpp_mod[1:0]. tpp_mod[1:0] = ?00? tpp_dat[31:0] valid tpp_mod[1:0] = ?01? tpp_dat[31:8] valid tpp_mod[1:0] = ?10? tpp_dat[31:16] valid tpp_mod[1:0] = ?11? tpp_dat[31:24] valid icif_err (a) not used (b) not used (c) rlp_err (c) error: discard packet. rlp_err is used to indicate that the current packet is aborted and should be discarded. rlp_err shall only be asserted when rlp_eop is asserted. conditions that can cause rlp_err to be set may be, but are not limited to, fifo overflow, abort sequence detection and fcs error. rlp_err is not expected to be asserted for atm cells, and has no effect on their processing. rlp_err is considered valid only when rlp_val is asserted. (d)tpp_err input (d) packet in error. if tpp_err is asserted when tpp_eop and tpp_enb are also asserted, then the packet is flagged in error. tpp_err is not expected to be asserted for atm cells, and has no effect on their processing.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 document id: pmc-1990553, issue 4 pin name type pin no function icif_addr[5:0] i/o (a) rlu_addr[5:0] output (a) phy address. rlu_addr indicates the phyid for which a response is expected on rlu_clav, and (on the last cycle during which rlu_rdenb is deasserted) indicates the phyid on which to transfer then next cell. (b) tpu_addr[5:0] input (b) phy address. tpu_addr indicates the phyid for which tpu_clav is to respond, and (on the last cycle during which tpu_wrenb is deasserted) indicates the phyid which the subsequent cell belongs to. (c) not used input (c) unused (d) tpp_addr[5:0] input (d) phy address (valid values 0 to 47) . the tpp_addr bus is used with the tpp_ptpa signal to poll the transmit fifos packet available status. when tpp_addr is sampled on the rising edge of tpp_clk by the phy, the polled packet available indication tpp_ptpa signal is updated with the status of the port specified by the tpp_addr address on the following rising edge of tpp_clk. icif_ctrl (a) rlu_clav (a) cell available. when sampled high, this pin indicates that the phy can transfer at least one cell on the polled phy, in addition to any cell currently being transferred. if rlu_clav is asserted at least 8 cycles before the end of the cell, then an additional cell may be transferred on the same phy without loss of efficiency. (b) tpu_wrenb (b) write enable. active low signal initiates a cell transfer. used for address selection in multi-phy mode when deasserted. (c) rlp_val (c) data valid. rlp_val indicates the validity of the receive data signals. rlp_val is low between transfers, when rsx is asserted, and when the phy pauses a transfer due to an empty receive fifo. when rlp_val is high, the rlp_dat[31:0], rlp_mod[1:0], rlp_sop, rlp_eop and rlp_err signals are valid. when rlp_val is low, the rlp_dat[31:0], rlp_mod[1:0], rlp_sop, rlp_eop and rlp_err signals are invalid and must be disregarded. when a transfer is paused by holding rlp_enb low, rval will hold its value unchanged, although no new data will be present on rdat[31:0] until the transfer resumes. the rlp_sx signal is valid when rlp_val is low. (d) tpp_enb input (d) write enable. the tpp_enb signal is used to control the flow of data to the s/uni-atlas-3200. when tpp_enb is high, the tpp_dat, tpp_mod, tpp_sop, tpp_eop and tpp_err signals are invalid and are ignored. the tpp_sx signal is valid when tpp_enb is high. when tpp_enb is low, the tpp_dat, tpp_mod, tpp_sop, tpp_eop and tpp_err signals are valid and are processed. tpp_sx is ignored when tpp_enb is low.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 document id: pmc-1990553, issue 4 pin name type pin no function icif_enb_stpa (a) rlu_rdenb (a) read enable. active low signal asserted to initiate a cell transfer. used for address selection during the last cycle before it is asserted. (b) not used (c) rlp_enb (c) read enable. the rlp_enb signal is used to control the flow of data from the phy?s receive fifos. during data transfer, rlp_val will be monitored as it will indicate if the rlp_dat[31:0], rlp_par, rlp_mod[1:0], rlp_sop, rlp_eop, rlp_err and rlp_sx are valid. rlp_enb will be deasserted anytime the s/uni-atlas-3200 is unable to accept data from the phy device. when rlp_enb is sampled high by the phy device, a read should not be performed and the rlp_dat[31:0], rlp_par, rlp_mod[1:0], rlp_sop, rlp_eop, rlp_err, rlp_sx and rlp_val signals must remain unchanged on the following rising edge of rlp_clk. (d) tpp_stpa output (d) selected phy packet available. tpp_stpa is high whenever there are at least 16 32-bit words available in the transmit fifo for the currently selected phy. when tpp_stpa transitions low, it indicates that there are less than 16 32-bit words available in the transmit fifo. the latency on this signal is no more than 8 cycles. if stpa is being used, the source must take this latency into account in using stpa to avoid overflow. the use of stpa is optional; the source may safely rely solely on ptpa. the port whose status tpp_stpa reports is updated on the following rising edge of tpp_clk after the phy address on tpp_dat is sampled by the phy device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 document id: pmc-1990553, issue 4 pin name type pin no function icif_sx (a) not used (b) not used (c) rlp_sx (c) start of transfer. rlp_sx indicates when the in-band port address is present on the rlp_dat bus. when rlp_sx is high and rlp_val is low, the value of rlp_dat[7:0] is the address of the receive fifo to be selected by the phy. subsequent data transfers on the rdat bus will be from the fifo specified by this in-band address. in the case of a single-phy interface, the rlp_sx bit is optional. it may be tied low, in which case the inbandaddr bit in the rxl configuration register should be set to logic 0, and the phyid will always be assumed to be 0. rlp_sx must be high only when rlp_val is low. (d) tpp_sx input (d) start of transfer. tpp_sx indicates when the in-band port address is present on the tpp_dat bus. when tpp_sx is high and tpp_enb is high, the value of tpp_dat[7:0] is the address of the transmit fifo to be selected. subsequent data transfers on the tpp_dat bus will fill the fifo specified by this in-band address. in the case of a single-phy interface, the tpp_sx bit is optional. it may be tied low, in which case the inbandaddr bit in the txp configuration register should be set to logic 0, and the phyid will always be assumed to be 0. tpp_sx is considered valid only when tpp_enb is not asserted. icif_clav_ptpa (a) not used (b) tpu_clav (b) cell available. tpu_clav is asserted high in response to tpu_addr if at least one cell, in addition to any cell currently being transferred, can be accepted on the phy specified by tpu_addr. tpu_clav is updated on the rising edge of tpu_clk following the cycle in which tpu_addr is sampled. (c) not used (d) tpp_ptpa output (d) polled phy packet available. tpp_ptpa is asserted high in response to polling on tpp_addr whenever the selected phy can accept another burst of (at most) 16 32-bit words. a phy may be polled while data is being transferred to it, and it will indicate whether or not it can accept another burst of (at most) 16 32-bit words in addition to the current burst. tpp_ptpa is updated on the rising edge of tpp_clk following the cycle in which tpp_addr is sampled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 document id: pmc-1990553, issue 4 pin name type pin no function output cell/packet interface (49 pins) this interface can work in one of four different modes: mode a (ingress ul3 slave output): rx phy layer utopia l3 interface (prefix: rpu_*) mode b (egress ul3 master output): tx link layer utopia l3 interface (prefix: tlu_*) mode c (ingress posphy 3 output): rx phy layer posphy l3 interface (prefix: rpp_*) mode d (egress posphy 3 output): tx link layer posphy l3 interface (prefix: tlp_*) one of these four modes may be chosen in software. the choice of mode is static is must not be changed during chip operation. the easiest way to read the table below is to pick a mode of operation (a,b,c, or d) and to read only those lines that pertain to the chosen mode. each pin also has a generic name, which may be used to reference the pin diagrams. ocif_clk (a) rpu_clk (a) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz (b) tlu_clk (b) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz (c) rpp_clk (c) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz (d) tlp_clk input (d) clock. valid frequency is 75 to 104 mhz. all signals on this interface are sampled at the rising edge of this clock. full oc-48c bandwidth is guaranteed only for 104 mhz ocif_dat[31:0] (a) rpu_dat[31:0] (a) 32-bit data bus. data path for data from the s/uni-atlas- 3200 to the traffic manager/fabric. rpu_dat[31] is the msb and rpu_dat[0] is the lsb. (b) tlu_dat[31:0] (b) 32-bit data bus. data path for data from the s/uni-atlas- 3200 to the phy. tlu_dat[31] is the msb and tlu_dat[0] is the lsb. (c) rpp_dat[31:0] (c) 32-bit data bus. the rpp_dat[31:0] bus carries the packet octets that are read from the receive fifo and the in-band port address of the selected receive fifo. rpp_dat[31:0] is considered valid only when rpp_val is asserted when rpp_sx is asserted, rpp_dat[7:0] contains the in-band port address, and rpp_dat[31:24] optionally carries the payload type field identifying the packet as atm or pos. rpp_dat[31] is the most significant bit. (d) tlp_dat[31:0] output (d) 32-bit data bus. this bus carries the packet octets that are written to the selected transmit fifo and the in-band port address to select the desired transmit fifo. the tlp_dat bus is considered valid only when tlp_enb is simultaneously asserted. when tlp_sx is asserted, tlp_dat[7:0] contains the in-band port address, and tlp_dat[31:24] optionally carries the payload type field identifying the packet as atm or pos. tlp_dat[31] is the most significant bit.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 document id: pmc-1990553, issue 4 pin name type pin no function ocif_par (a) rpu_par (a) parity over data bus (programmable to odd or even) (b) tlu_par (b) parity over data bus (programmable to odd or even) (c) rpp_par (c) parity over data bus (programmable to odd or even) the receive parity (rpp_par) signal indicates the parity calculated over the rpp_dat bus. rpp_par is valid whenever rpp_val or rpp_sx are asserted. (d) tlp_par output (d) parity over data bus (programmable to odd or even) the transmit parity (tlp_par) signal indicates the parity calculated over the tlp_dat bus. tlp_par is considered valid only when tlp_enb or tlp_sx is asserted. ocif_soc_sop (a) rpu_soc (a) start of cell. active high signal asserted to indicate the start of cell position. it is expected that, in case of loss of synchronization, that rpu_soc will serve to resynchronize the interface. (b) tlu_soc (b) start of cell. active high signal asserted to indicate the start of cell position. it is expected that, in case of loss of synchronization, that tlu_soc will serve to resynchronize the interface. (c) rpp_sop (c) start of packet. rpp_sop is used to delineate the packet boundaries on the rpp_dat bus. when rpp_sop is high, the start of the packet is present on the rpp_dat bus. rpp_sop is required to be present at the start of every packet and is considered valid when rpp_val is asserted.. (d) tlp_sop output (d) start of packet. tlp_sop is used to delineate the packet boundaries on the tlp_dat bus. when tlp_sop is high, the start of the packet is present on the tlp_dat bus. tlp_sop is required to be present at the beginning of every packet and is considered valid only when tlp_enb is asserted.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 document id: pmc-1990553, issue 4 pin name type pin no function ocif_eop (a) not used (b) not used (c) rpp_eop (c) end of packet. rpp_eop is used to delineate the packet boundaries on the rpp_dat bus. when rpp_eop is high, the end of the packet is present on the rpp_dat bus. rmod[1:0] indicates the number of valid bytes the last double- word is composed of when rpp_eop is asserted. reop is required to be present at the end of every packet and is considered valid only when rval is asserted. (d) tlp_eop output (d) end of packet. tlp_eop is used to delineate the packet boundaries on the tlp_dat bus. when tlp_eop is high, the end of the packet is present on the tlp_dat bus. tlp_mod[1:0] indicates the number of valid bytes the last double-word is composed of when tlp_eop is asserted. tlp_eop is required to be present at the end of every packet and is considered valid only when tlp_enb is asserted. the s/uni-atlas-3200 always ends a burst when eop is asserted. the minimum average packet length for which oc-48 throughput may be guaranteed is 32 bytes. ocif_mod[1:0] (a) not used (b) not used (c) rpp_mod[1:0] (c) number of bytes in packet modulo 4 rpp_mod[1:0] indicates the number of valid bytes of data in rpp_dat[31:0]. the rpp_mod bus should always be all zero, except during the last double-word transfer of a packet on rpp_dat[31:0]. when rpp_eop is asserted, the number of valid packet data bytes on rpp_dat[31:0] is specified by rpp_mod[1:0] rpp_mod[1:0] = ?00? rpp_dat[31:0] valid rpp_mod[1:0] = ?01? rpp_dat[31:8] valid rpp_mod[1:0] = ?10? rpp_dat[31:16] valid rpp_mod[1:0] = ?11? rpp_dat[31:24] valid rpp_mod[1:0] is considered valid only when rpp_val is asserted. (d) tlp_mod[1:0] output (d) number of bytes in packet modulo 4 tlp_mod[1:0] indicates the number of valid bytes of data in tlp_dat[31:0]. the tlp_mod bus should always be all zero, except during the last double-word transfer of a packet on tlp_dat[31:0]. when tlp_eop and tlp_enb are asserted, the number of valid packet data bytes on tlp_dat[31:0] is specified by tlp_mod[1:0]. tlp_mod[1:0] = ?00? tlp_dat[31:0] valid tlp_mod[1:0] = ?01? tlp_dat[31:8] valid tlp_mod[1:0] = ?10? tlp_dat[31:16] valid tlp_mod[1:0] = ?11? tlp_dat[31:24] valid
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 document id: pmc-1990553, issue 4 pin name type pin no function ocif_err (a) not used (b) not used (c) rpp_err (c) error: discard packet. rpp_err is used to indicate that the current packet is in error and should be discarded. rpp_err is only asserted when rpp_eop is asserted. rpp_err is considered valid only when rpp_val is asserted. (d) tlp_err output (d) error. packet should be aborted. will only be asserted when teop is simultaneously asserted; only valid when tenb is asserted. ocif_addr[5:0] i/o (a) rpu_addr[5:0] input (a) phy address (valid values 0 to 47). rpu_addr indicates the phyid for which rpu_clav is to respond, and (on the last cycle during which rpu_enb is deasserted) indicates the phyid on which to transfer then next cell. the use of these bits is optional. if the utopia master is not designed to poll this interface, then the rx phy utopia interface can be made to look like a single-phy interface via the serveovrd bit in the rxp configuration register. in this case, s/uni-atlas-3200 will perform weighted-round-robin servicing on all the phy queues internally, and clav will indicate whether a cell is available on any phyid. in this case, these bits should be tied low. (b) tlu_addr[5:0] output (b) phy address. tlu_addr indicates the phyid for which tlu_clav is to respond, and (on the last cycle during which tlu_wrenb is deasserted) indicates the phyid which the subsequent cell belongs to. (c) not used input (c) unused (d) tlp_addr[5:0] output (d) phy address (valid values 0 to 47). the tlp_addr bus is used with the tlp_ptpa signal to poll the transmit fifos packet available status. when tlp_addr is sampled on the rising edge of tlp_clk by the phy, the polled packet available indication tlp_ptpa signal is expected to be updated with the status of the port specified by the tlp_addr address on the following rising edge of tlp_clk.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 document id: pmc-1990553, issue 4 pin name type pin no function ocif_ctrl (a) rpu_clav (a) cell available. rpu_clav is asserted in response to polling on rpu_addr to indicate that at least one complete cell is available on the phyid specified by rpu_clav. if the interface is configured to look like a single-phy interface (via the serveovrd bit in the rxp configuration register) then this bit indicates whether any complete cells are ready for transfer. (b) tlu_wrenb (b) write enable. tlu_wrenb is asserted to enable the transfer of cell data. on the last cycle before it is asserted, the tlu_addr indicates the phyid to which the subsequent cell belongs. (c) rpp_val (c) data valid. rpp_val indicates the validity of the receive data signals. rpp_val is low between transfers, when rpp_sx is asserted, and when the s/uni-atlas-3200 pauses a transfer due to an empty fifo. when a transfer is paused by holding rpp_enb low, rpp_val will hold its value unchanged, although no new data will be present on rdat[31:0] until the transfer resumes. when rpp_val is high, the rpp_dat[31:0], rpp_mod[1:0], rpp_sop, rpp_eop and rpp_err signals are valid. when rpp_val is low, the rpp_dat[31:0], rpp_mod[1:0], rpp_sop, rpp_eop and rpp_err signals are invalid and must be disregarded. the rpp_sx signal is valid when rpp_val is low. (d) tlp_enb output (d) write enable. the tlp_enb signal is used to control the flow of data to the transmit fifos. when tlp_enb is high, the tlp_dat, tlp_mod, tlp_sop, tlp_eop and tlp_err signals are invalid and are ignored by the phy. the tlp_sx signal is valid and is processed by the phy when tlp_enb is high. when tlp_enb is low, the tlp_dat, tlp_mod, tlp_sop, tlp_eop and tlp_err signals are valid and are processed by the phy. also, the tlp_sx signal is ignored by the phy when tlp_enb is low.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 document id: pmc-1990553, issue 4 pin name type pin no function ocif_enb_stpa (a) rpu_rdenb (a) active-low read enable. w hen rpu_rdenb is asserted, a read is executed from the s/uni-atlas-3200 on the phyid which was present on rpu_addr during the cycle before rpu_rdenb was asserted. (b) not used (c) rpp_enb (c) active-low read enable. the rpp_enb signal is used to backpressure the flow of data from the receive fifos. during data transfer, rpp_val must be monitored as it will indicate if the rpp_dat[31:0], rpp_mod[1:0], rpp_sop, rpp_eop, rpp_err and rpp_sx are valid. the system may deassert rpp_enb at anytime if it is unable to accept data from the s/uni-atlas-3200. when rpp_enb is sampled low, a read is performed from the receive fifo and the rpp_dat[31:0], rpp_par, rpp_mod[1:0], rpp_sop, rpp_eop, rpp_err, rpp_sx and rpp_val signals are updated on the following rising edge of rpp_clk. when rpp_enb is sampled low by the phy device, a read is not performed and the rpp_dat[31:0], rpp_par, rpp_mod[1:0], rpp_sop, rpp_eop, rpp_err, rpp_sx and rpp_val signals will not updated on the following rising edge of rpp_clk. (d) tlp_stpa input (d) selected phy packet available. tlp_stpa always provides status indication for the selected port of phy device in order to avoid fifo overflows while polling is performed. the use of tlp_stpa is optional. if use_stpa is logic 0 in the txlink configuration register, then tlp_stpa is ignored. if use_stpa is logic 1, then the s/uni-atlas-3200 will cease transmission immediately after sampling tlp_stpa high, and may switch to another phy at that point. the port which tlp_stpa reports is updated on the following rising edge of tlp_clk after the phy address on tlp_dat is sampled by the phy device. ocif_sx (a) not used (b) not used (c) rpp_sx (c) start of transfer. rpp_sx indicates when the in-band port address is present on the rpp_dat bus. when rpp_sx is high and rpp_val is low, the value of rpp_dat[7:0] is the address of the receive fifo to be selected by the phy. subsequent data transfers on the rdat bus will be from the fifo specified by this in-band address. rpp_sx will not be asserted at the same time as rpp_val. (d) tlp_sx output (d) start of transfer. tlp_sx indicates when the in-band port address is present on the tlp_dat bus. when tlp_sx is high and tlp_enb is high, the value of tlp_dat[7:0] is the address of the transmit fifo to be selected. subsequent data transfers on the tlp_dat bus will fill the fifo specified by this in-band address. tlp_sx will not be asserted at the same time as tlp_enb
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 document id: pmc-1990553, issue 4 pin name type pin no function ocif_clav_ptpa (a) not used (b) tlu_clav (b) cell available. to indicate that space for at least one cell is available in the phy?s transmit cell buffer. for back-to-back transfer to be guaranteed, tlu_clav must be asserted at least 5 cycles before the end of the current transfer. the value of tlu_clav is not used between the selection of an new phyid and the second cycle after tlu_soc is presented on the interface. (c) not used (d) tlp_ptpa input (d) polled phy packet available. tlp_ptpa is used together with tlp_addr to poll for transmit fifos that have room available. s/uni-atlas-3200 expects that if tlp_ptpa is asserted in response to tlp_addr, then that fifo can accept at least one additional burst of 16 32-bit words, in addition to any burst currently being transferred. s/uni-atlas-3200 will terminate a burst at an end of packet even if a full 16 words have not been transferred. tlp_ptpa is expected to be valid in the cycle following the cycle in which tlp_addr was sampled in the phy. backwards input cell interface (21 pins) sci-phy interface (16-bit utopia level 1 with routing information prepended to cells). it can act as an rx master (its default, intended for attachment to an s/uni-atlas-3200 backwards output cell interface) or as a tx slave (used when connecting to a device that is not an s/uni-atlas-3200). bi_clk input ibcif clock. this clock should run between 40 to 52 mhz to ensure sufficient throughput on the backwards cell interface. bi_rrdenb _tclav output receive read enable (in bcif rx master mode)/ transmit cell available (in bcif tx slave mode) in rx master mode, this bit is asserted low to read cells from the interface. in tx slave mode this indicates to the master that a cell is available in the transmit buffer. bi_rclav _twrenb input receive cell available (in bcif rx master mode)/ transmit write enable (in bcif tx slave mode) in rx master mode the slave indicates that it has a cell in its transmit buffer by asserting this signal. in tx slave mode, the master indicates that it is going to transfer data into the slave device by asserting this signal. bi_soc input start of cell. must be asserted when the first word of the cell is on the data bus. bi_dat[15:0] input 16-bit data bus bi_par input parity over bi_dat[15:0]. backwards output cell interface (21 pins) sci-phy interface (16-bit utopia level 1 with routing information prepended to cells) bo_clk input obcif clock. this clock should run between 40 to 52 mhz to ensure sufficient throughput on the backwards cell interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 document id: pmc-1990553, issue 4 pin name type pin no function bo_rdenb input read enable. the s/uni-atlas-3200 will transfer data out onto the data bus when this signal is asserted. bo_clav output cell available. indicates that the s/uni-atlas-3200 has at least one cell to transfer. bo_soc output start of cell. asserted when the first word of the cell is on the data bus. bo_dat[15:0] output data bo_par output parity over bo_par[15:0]. microprocessor access port (52 pins) up_dat[31:0] i/o the bi-directional data bus, up_dat[31:0] is used during s/uni- atlas-3200 microprocessor interface port register reads and write accesses. up_dat[31] is the msb. up_addr[11:0] input the address up_addr[11:0] selects specific microprocessor interface port registers during s/uni-atlas-3200 register accesses. up_addr[11] is the test register select (trs) address pin. trs selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. up_rdb input up_rdb is low during s/uni-atlas-3200 microprocessor interface port register read accesses. the s/uni-atlas-3200 drives the up_dat[31:0] bus with the contents of the addressed register while up_rdb and up_csb are low. up_wrb input up_wrb is low during s/uni-atlas-3200 microprocessor interface port register write accesses. the up_dat[31:0] bus contents are clocked into the addressed register on the rising edge of up_wrb while up_csb is low. up_csb input up_csb is low during s/uni-atlas-3200 microprocessor interface port register accesses. if up_csb is not required (i.e. register accesses controlled using up_rdb and up_wrb signals only), up_csb should be connected to an inverted version of the up_rstb input. up_ale input the microprocessor address strobe, up_ale, is active high and latches the address bus, up_addr[11:0], when low. when up_ale is high, the internal address latches are transparent. it allows the s/uni-atlas-3200 to interface to a multiplexed address/data bus. up_ale has an internal pull up resistor.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 document id: pmc-1990553, issue 4 pin name type pin no function up_dmareq output the dma request (up_dmareq) is asserted when the microprocessor cell interface (mcif) contains a cell to be read. the first read of the mcif data register will return the first word of the cell. up_dmareq is deasserted after the last word of the cell has been read or an abort has been signaled. the polarity of up_dmareq is determined by the dmareqinv bit in the microprocessor cell interface configuration register. by default, up_dmareq is active high. up_busyb output the up_busyb output is asserted while a microprocessor initiated access to external sram or internal dram data is pending (for internal sram accesses, a microprocessor must poll the appropriate busy register bit). the busy bit will be asserted within 20 ns the rising edge of wrb on which the ram access is initiated. the up_busyb output is deasserted after the access has been completed. a microprocessor access to external sram is typically completed within 30 sysclk cycles; an access to internal dram is typically completed within 220 cycles. if the standby bit in the master configuration is set to logic 1, the access time is reduced to typically than 10 sysclk cycles for internal accesses and 25 clock cycles for internal dram accesses. the polarity of the up_busyb output is programmable and defaults to active low. up_intb output the interrupt request (up_intb) output goes low when an s/uni-atlas-3200 interrupt source is active and that source is unmasked. up_intb returns high when the interrupt is acknowledged via an appropriate register access. up_intb is an open drain output. up_rstb input the active low reset (up_rstb) signal provides an asynchronous s/uni-atlas-3200 reset. up_rstb is a schmitt trigger input with an integral pull up resistor. when up_rstb is forced low, all s/uni-atlas-3200 registers are forced to their default states. miscellaneous (1 pin) halfsecclk input half-second clock. this signal must pulse once every half second, in order to correctly perform oam alarm monitoring, oam cell generation, and policing. if the gen_halfsecclk register bit is set to logic 1 in the cell processor configuration register, then the half-second clock may be internally generated from the 125 mhz sysclk input, and the halfsecclk input may be left unused. ieee p1149.1 (jtag) interface (5 pins) tck input the test clock (tck) signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input internal pull-up the test mode select (tms) signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an internal pull up resistor. tdi input internal pull-up the test data input (tdi) signal carries test data into the s/uni- atlas-3200 via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an internal pull-up resistor.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 document id: pmc-1990553, issue 4 pin name type pin no function tdo tristate the test data output (tdo) signal carries test data out of the s/uni-atlas-3200 via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is tri-stated except when the scanning of data is in progress trstb schmitt trigger input internal pull-up the active low test reset (trstb) signal provides an asynchronous s/uni-atlas-3200 test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull-up resistor. the jtag tap controller must be initialized when the s/uni- atlas-3200 is powered up. if the jtag port is not used, trstb must be connected to the rstb input or vss. dram test (2 pins) reserved input internal pull-up this pin must be tied to logic 1 in operation to avoid permanent damage to the device. reserved input internal pull-up this pin must be tied to logic 1 to ensure correct operation. zetmdl i/o this pin must be tied to logic 0 for proper operation zetmdr i/o this pin must be tied to logic 1 for proper operation power/ground vdd33 power 3.3v i/o power. vdd25 power 2.5v i/o power vddq25 power 2.5v dram core power. this supply should be kept quiet to improve dram performance. vddq15 power 1.5v dram core power. this supply should be kept quiet to improve dram performance. vdd15 power 1.5v core power vss ground common ground notes on pin description: 1. all s/uni-atlas-3200 inputs and bi-directionals present minimum capacitive loading and operate at lvttl logic levels. 2. all inputs and bi-directionals have internal pull-up resistors. 3. the recommended power supply sequencing is as follows: 3.1 during power-up, vdd33 must be brought up before or at the same time as vdd25 and vddq25, which must be brought up before or at the same time as vdd15 and vddq15. 3.2 the vdd33 and vdd25 power must be applied before input pins are driven or the input current per pin be limited to less than the maximum dc input current specification. (10 ma) 3.3 power down the device in the reverse sequence.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 document id: pmc-1990553, issue 4 10 functional description 10.1 input and output interfaces the s/uni-atlas-3200 supports two kinds of signaling: utopia level 3, which is used for transferring fixed-length atm cells; and pos-phy level 3, which is used for transferring variable-length packets. applications that require the s/uni-atlas-3200 to transfer mixed cell and packet traffic should use pos-phy signaling. independent of the ul3 or pos signaling, the s/uni-atlas-3200 may operate in two modes: the ingress and the egress mode. the s/uni-atlas-3200 is typically deployed in pairs. one chip of the pair receives cells/packets from phy devices and sends them towards the traffic manager/switch core. this chip is said to be in ingress mode. the other chip of the pair receives cells/packets from the switch core and sends them to the phy devices. this chip is said to be in egress mode. thus, the s/uni-atlas-3200 can be configured in four ways: utopia or pos-phy signaling, and ingress or egress mode. the s/uni-atlas-3200 is in ingress pos-phy mode on reset, which is the state in which all ul3/pos pins that can be either inputs or outputs, are inputs. this avoids contention on startup. 10.1.1 ingress mode with utopia level 3 signaling in this configuration, the s/uni-atlas-3200 receives traffic from a phy, and transmits traffic to a traffic manager. this traffic consists of atm cells, transferred using utopia level 3 signaling.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 document id: pmc-1990553, issue 4 figure 5 utopia level 3 ingress interface cell flow scalable data queues cpu interface microprocessor interface up_dat[31:0] up_addr[11:0] up_csb up_rdb up_intb up_busyb up_wrb up_dmarq up_ale scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sram interface jtag jtag interface tdo tdi tck tms trstb xclk halfsecclk sci-phy interface scalable data queues sci-phy interface backward output cell interface bo_par bo_dat[15:0] bo_soc bo_clav bo_rdenb bo_clk backward input cell interface bi_dat[15:0] bi_par bi_soc bi_rclav/bi_twrenb bi_rdenb/bi_tclav bi_clk up_rstb packet bypass fifo ingress input: ul3 master or pos phy link layer interface egress input: ul3 slave or pos phy phy layer interface ingress output: ul3 slave or pos phy phy layer interface egress output: ul3 master or pos phy link layer interface rlu_dat[31:0] rlu_par rlu_rdenb rlu_soc rlu_clav rlu_addr[5:0] rlu_clk rpu_dat[31:0] rpu_par rpu_soc rpu_clk rpu_clav rpu_rdenb ul3 rx master interface ul3 rx slave interface rpu_addr[5:0] sysclk address resolution connection table (embedded dram) cell processor policing, oam, statistics, translation input microprocessor cell interface (imcif) output microprocessor cell interface (omcif) sysclk_o the s/uni-atlas-3200 input interface must behave as an rx link layer device on the utopia bus. as a link layer device, it controls the address bus, rlu_addr, in order to poll the phy layer device to obtain cell available status. polling is performed in a weighted round- robin fashion controlled by a software-configurable calendar. once the cell available information has been collected through polling, port selection is performed using the same calendar. the calendar is programmed via the rxlink block?s calendar address and data register, and is described in section 10.1.7. the rxlink block can map external phy addresses to different internal phy addresses via a user-programmable port map, as described in section 10.1.6. the rxlink block, assisted by the sdq block (see below) performs these functions. the rxlink configuration registers may be found in section 11.6.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 output interface must behave as an rx phy layer device on the utopia bus. as a phy layer device, it responds with the appropriate cell available status when a channel address is on the bus, rpu_addr. when the link layer device (a tm or switch) engages a transfer, the s/uni-atlas-3200 must respond by sending the next cell for the channel that has been selected. optionally, the s/uni-atlas-3200 will behave as a single-phy device, ignoring rpu_addr. it will service the internal per-phy cell queues in a weighted round-robin fashion controlled by a software-configurable calendar. the calendar is programmed via the rxphy block?s calendar address and data register, and is described in section 10.1.7. the rxphy block, assisted by the sdq block (see below) performs these functions. the rxphy configuration registers may be found in section 11.9. 10.1.2 egress mode with utopia level 3 signaling in this configuration, the s/uni-atlas-3200 receives traffic from a traffic manager, and transmits traffic to a phy. this traffic consists of atm cells, transferred using utopia level 3 signaling. figure 6 utopia level 3 egress interface cell flow scalable data queues cpu interface microprocessor interface up_dat[31:0] up_addr[11:0] up_csb up_rdb up_intb up_busyb up_wrb up_dmarq up_ale jtag jtag interface tdo tdi tck tms trstb xclk halfsecclk sci-phy interface scalable data queues sci-phy interface backward output cell interface bo_par bo_dat[15:0] bo_soc bo_clav bo_rdenb bo_clk backward input cell interface bi_dat[15:0] bi_par bi_soc bi_rclav/bi_twrneb bi_rdenb/bi_tclav bi_clk up_rstb packet bypass fifo ingress input: ul3 master or pos phy link layer interface egress input: ul3 slave or pos phy phy layer interface ingress output: ul3 slave or pos phy phy layer interface egress output: ul3 master or pos phy link layer interface tpu_dat[31:0] tpu_par tpu_wrenb tpu_soc tpu_clav tpu_addr[5:0] tpu_clk tlu_dat[31:0] tlu_par tlu_soc tlu_clk tlu_clav tlu_wrenb tlu_addr[5:0] ul3 tx slave interface ul3 tx master interface address resolution connection table (embedded dram) cell processor policing, oam, statistics, translation input microprocessor cell interface (imcif) output microprocessor cell interface (omcif) scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sram interface sysclk sysclk_o
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 input interface must behave as a tx phy layer device on the utopia bus. as a phy layer device, it responds with the appropriate cell available (buffer) status when a channel address is on the bus, tpu_addr. additionally, when the atm layer device engages a transfer, the s/uni-atlas-3200 must respond by accepting cell for the channel that has been selected. the txphy block, assisted by the sdq (see below) performs these functions. the txphy configuration registers may be found in section 11.7. the s/uni-atlas-3200 output interface must behave as a tx link layer device on the utopia bus. as a link layer device, it controls the address bus, tlu_addr, in order to poll the phy to obtain cell available (buffer) status. polling is performed in a weighted round-robin fashion controlled by a software-configurable calendar. once the cell available information has been collected through polling, port selection is performed using the same calendar. the calendar is programmed via the txlink block?s calendar address and data register, and is described in section 10.1.7. the txlink block can map internal phy addresses to different external phy addresses via a user-programmable port map, as described in section 10.1.6. the txlink block, assisted by the sdq (see below) performs these functions. the txlink configuration registers may be found in section 11.10. 10.1.3 ingress mode with pos-phy level 3 signaling in this configuration, the s/uni-atlas-3200 receives traffic from a phy, and transmits traffic to a traffic manager. this traffic consists of variable-length packets, transferred using pos-phy level 3 signaling.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 document id: pmc-1990553, issue 4 figure 7 pos-phy level 3 ingress interface cell flow scalable data queues cpu interface microprocessor interface up_dat[31:0] up_addr[11:0] up_csb up_rdb up_intb up_busyb up_wrb up_dmarq up_ale jtag jtag interface tdo tdi tck tms trstb xclk halfsecclk sci-phy interface scalable data queues sci-phy interface backward output cell interface bo_par bo_dat[15:0] bo_soc bo_clav bo_rdenb bo_clk backward input cell interface bi_dat[15:0] bi_par bi_soc bi_rclav/bi_twrenb bi_rdenb/bi_tclav bi_clk up_rstb packet bypass fifo egress input: ul3 slave or pos phy phy layer interface ingress output: ul3 slave or pos phy phy layer interface egress output: ul3 master or pos phy link layer interface rpp_clk rpp_enb rpp_dat[31:0] rpp_mod[1:0] rpp_par rpp_val rpp_sop rpp_eop rpp_err rpp_sx rlp_sx rlp_dat[31:0] rlp_mod[1:0] rlp_par rlp_val rlp_sop rlp_eop rlp_err rlp_clk rlp_enb pos3 rx slave link layer interface pos3 rx master phy layer interface packets packets cells cells address resolution connection table (embedded dram) cell processor policing, oam, statistics, translation input microprocessor cell interface (imcif) output microprocessor cell interface (omcif) scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sram interface sysclk sysclk_o the s/uni-atlas-3200 input interface must behave as the rx link-layer on the pos-phy bus. as the link-layer, its function is to accept information sent by the phy-layer, which controls the flow of data and the selection process. the link-layer provides a back-pressure indication (rlp_enb) to prevent it from overflowing. the rxlink block can map external phy addresses to different internal phy addresses via a user-programmable port map, as described in section 10.1.6. the rxlink block, assisted by the sdq block (see below) performs the above functions. the rxlink configuration registers may be found in section 11.9
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 output interface must behave as the rx phy-layer on the pos-phy bus. as the phy-layer, it controls the flow of information to the link-layer. it does so by selecting the channel for transfer on the data bus, rpp_dat. channel selection is performed in a weighted round-robin fashion controlled by a software-configurable calendar. the calendar is programmed via the rxphy block?s calendar address and data register, and is described in section 10.1.7. when a phy queue is serviced, it is permitted to transfer one atm cell or pos- phy packet, or an amount of data equal to the burst size for that phy, whichever is less. the rxphy block, assisted by the output sdq block (see below) performs the above functions. its configuration registers may be found in section 11.9. 10.1.4 egress mode with pos_phy level 3 signaling in this configuration, the s/uni-atlas-3200 receives traffic from a traffic manager, and transmits traffic to a phy. this traffic consists of variable-length packets, transferred using pos- phy level 3 signaling. figure 8 pos-phy level 3 egress interface cell flow scalable data queue cpu interface microprocessor interface up_dat[31:0] up_addr[11:0] up_csb up_rdb up_intb up_busyb up_wrb up_dmarq up_ale jtag jtag interface tdo tdi tck tms trstb xclk halfsecclk sci-phy interface scalable data queue sci-phy interface backward output cell interface bo_par bo_dat[15:0] bo_soc bo_clav bo_rdenb bo_clk backward input cell interface bi_dat[15:0] bi_par bi_soc bi_rclav/bi_twrenb bi_rdenb/bi_tclav bi_clk up_rstb packet bypass sdq ingress input: ul3 master or pos phy link layer interface egress input: ul3 slave or pos phy phy layer interface ingress output: ul3 slave or pos phy phy layer interface egress output: ul3 master or pos phy link layer interface tpp_sx tpp_dat[31:0] tpp_mod[1:0] tpp_par tpp_sop tpp_eop tpp_err tpp_clk tpp_enb tpp_stpa tpp_addr[5:0] pos3 tx slave phy layer interface tlp_clk tlp_enb tlp_dat[31:0] tlp_mod[1:0] tlp_par tlp_sop tlp_eop tlp_err tlp_sx tlp_addr[5:0] tlp_stpa pos3 tx master link layer interface packets packets cells cells tlp_ptpa tpp_ptpa address resolution connection table (embedded dram) cell processor policing, oam, statistics, translation input microprocessor cell interface (imcif) output microprocessor cell interface (omcif) scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sram interface sysclk sysclk_o
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 input interface must behave as the tx phy layer device on the pos- phy bus. as the phy-layer, its function is to accept information sent by the link-layer, to respond to polling on tpp_addr with the appropriate packet available (buffer) status on tpp_ptpa, and to provide backpressure on the selected port on tpp_stpa. the txphy block, assisted by the sdq block (see below) performs the above functions. its configuration registers may be found in section 11.7. the s/uni-atlas-3200 must behave as a tx link-layer on the pos-phy bus. as the link- layer, it controls the flow of information to the phy layer device, by polling the phy layer device to obtain packet available (buffer) status. polling is performed in a weighed round-robin fashion controlled by a software-configurable calendar. once the cell available information has been collected through polling, port selection is performed using the same calendar. the calendar is programmed via the txlink block?s calendar address and data register, and is described in section 10.1.7. when a phy is serviced, it is permitted to transfer one atm cell or pos-phy packet, or an amount of data equal to the programmed burst size for that phy, whichever is less. the txlink block can map internal phy addresses to different external phy addresses via a user-programmable port map, as described in section 10.1.6. the txlink block, assisted by the sdq block (see below) performs the above functions. its configuration registers may be found in section 11.10. 10.1.5 polling and servicing calendar polling and servicing of phy queues is performed in a weighted round-robin fashion. the order of the polling, and the relative weighting of different phys is directly configured by writing a calendar to each of the interface blocks that supports polling or servicing. the calendar is a circular list of phy ids. when polling, the poller continuously presents the phy ids in the order shown in the calendar, and records the resulting cell/buffer available signals. the more often a given phyid appears in the calendar, the more often it gets polled. the length of the calendar is configurable, and the maximum length of the calendar is 128 entries, to allow considerable flexibility in weighting the 48 possible phys. servicing is done in exactly the same way as polling, using the same calendar. when the time comes to select the next cell or packet to transmit, the interface block scrolls forward from its current position through the phy ids in the calendar until it finds one that can transfer a cell. the more often a phy id appears in the calendar, the more frequently it will be serviced, assuming it is enabled and offers traffic. table 3 below illustrates a simple, 16-long calendar for three sts-12 connections (phys 0, 1, and 2) and four sts-3 connections (phys 3, 4, 5, and 6). note how the sts-12 connections have four times as many entries as the sts-3 connections. note also that the entries for any given phy are distributed evenly throughout the calendar in order to ensure maximum usefulness of the polling and maximum fairness of the servicing. table 3 polling and servicing calendar example calendar address calendar data 00 11 22 33
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 document id: pmc-1990553, issue 4 calendar address calendar data 40 51 62 74 80 91 10 2 11 5 12 0 13 1 14 2 15 6 there are two pointers used in the calendar algorithm. they are the polling pointer and the servicing pointer. the servicing pointer moves down the calendar, and the first positive cell available assertion the pointer encounters will be the phy selected for transfer on the next subsequent opportunity. it is recommended that repeated entries in the calendar be spread in a uniform manner in the calendar. this will help maximize the chances of selection in a proportional manner. information that is gathered during polling is kept and maintained in a persistent fashion. according to utopia level 3 specification, once a phy has asserted cell available, it is committed to transmission sometime in the future. the servicing algorithm remembers all assertions for cell available made in the past and advances the servicing pointer through the responses without regard to the age of the response. this algorithm provides flexibility in servicing without starvation so long as the number of entries in the calendar for a phy is proportional to the bandwidth of that phy. both the polling and servicing algorithms are designed to take into account that cell available signals on connections that are selected are not valid until two cycles after txl_soc has been presented. generally, the calendar should be set up at device initialization and subsequently be left unchanged. when the calendar length, or a calendar entry is updated during cell or packet flow, there may be an impact on polling, which may result in loss of data for a short period of time on any phy that is transferring data. for maximum efficiency, it is recommended that the rxphy calendar length be set to at least 64, and preferably as close to 128 as is practical. a shorter set of calendar entries can simply be repeated several times to pad out to a greater length.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 document id: pmc-1990553, issue 4 10.1.6 phy mapping in order to support aps and other applications, the rxlink and txlink blocks have the capability of remapping the phy ids used by the phy devices over the ul3 or pos-phy bus to another phy id to be used internal to the s/uni-atlas-3200 and switch. in both the ingress and egress modes, the translation is done on the side of the device facing the phys, i.e. in the rxlink or txlink block. the rxlink and txlink use the external address in their calendar, and in specifying the mapping table. the remainder of the device, including the data queue blocks, use the translated phy id. to facilitate this function, a table is provided in indirect registers in the rxlink and txlink blocks which allows the microprocessor to specify, for any given external phy address, the internal phyid to which the phy address is to be mapped. table 4 phy mapping phy device address indirect address for calendar & mapping data in mapping table phy id internal to atlas and switch 0 0 37 37 1 1 12 12 22 2 2 ?? 47 47 7 7 10.1.7 scalable data queue in all the above configurations, both the input and output interfaces use scalable data queue blocks (sdqs). there is an input data queue and an output data queue which buffer cells for the input and output, and a bypass data queue which is used for packet bypass. each sdq offers generic storage and buffering for cells or packets. it has a capacity of 12288 bytes, which may be carved up into 1 to 48 different fifos. the depths of the various fifos are highly configurable (within the bounds set by the total available storage). for example, if a system has 48 sts-1 atm phy devices, then one may configure the input and output sdqs to behave as 48 fifos (one per phy), each having 4 cells worth of storage. if there are higher-rate interfaces, then phy buffers may be reduced in size or eliminated, to accommodate larger buffers on higher- rate phys. the input and bypass data queues may be configured to suit the system?s buffering requirements. however, the output data queue must be set to at least 4 cells for data rates greater than sts-1, and to at least 12 cells for data rates greater than sts-3. the registers to configure the input sdq are described in section 11.8, and the registers to configure the output sdq are described in section 11.11. each sdq maintains a set of per-phy 11-bit counters of the number of cells or packets currently in each of the fifos, a 32-bit aggregate count of the total number of cells accepted by all the phy queues, and a 16-bit count of the total number of cells dropped by all the fifos. these counts are separate from the cell processor?s per-phy counters, and are used for diagnostic purposes. section 13.1 describes how to set up the sdqs.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 document id: pmc-1990553, issue 4 10.1.8 packet-bypass mode the s/uni-atlas-3200 can operate in a mixed packet/cell environment. in this case, the phy interfaces must be configured as pos-phy level 3 interfaces. each phy queue can be configured to be in packet mode by writing the enable bit for that phy in the bypass data queue to logic 1, and setting the corresponding bit to logic 0 in the input and output data queues. the phy queue can be configured to be in cell mode by writing the enable bit for that phy in the input and output data queues to logic 1, and setting the corresponding bit to logic 0 in the bypass data queue; in all cases, phys in the input and output sdqs must be set to atm cell mode (fifo_type = 0) and those in the bypass sdq to packet mode (fifo_type = 1). if a phy is in packet mode, it is bypassed around the cell processor via the bypass data queue. effectively, all packet traffic cuts through the s/uni-atlas-3200 unchanged, except for the phy mapping function in the link blocks. conversely, if a phy is in cell mode, then its traffic is assumed to be atm; hence the traffic is subject to the normal cell processing functions including policing, fm and pm, as described in the previous subsections. pos-phy level 3 is capable of transferring both packets and cells. using pos-phy level 3, cells are transferred as fixed-length packets. the format of the packet is configured in the same way as for utopia level 3, by specifying (in the interface blocks) the presence or lack of prepended, postpended, or hec/udf words. thus the length of the atm-cell packets can be 52, 56, 60, or 64 bytes. non-atm packets, of course, can be of any length. if even one of the phy devices is configured to be in packet mode, then the s/uni-atlas-3200 must use pos-phy signaling at both its input and output interfaces. on the other hand, if all the phy devices are configured to be in cell mode, then the s/uni-atlas-3200 may use utopia signaling or pos- phy signaling. 10.1.9 atm cell format whether in pos-phy or utopia mode, the s/uni-atlas-3200 can accept atm cells with or without hec/udf, and with one or two prepended/postpended d-words. the format of the cell must be preprogrammed at each interface, but it may be different at the device output than at the input. total cell lengths of 52, 56, 60, or 64 bytes are supported, and the total number of prepended + postpended d-words must be less than or equal to 2. the format of the extended atm cells is illustrated in figure 9.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 document id: pmc-1990553, issue 4 figure 9 atm cell format note: optional words encased in []. bits 31 -24 bits 23 -16 bits 15 - 8 bits 7- 0 [pre1 pre2 pre3 pre4] [pre5 pre6 pre7 pre8] header 1 header 2 header 3 header 4 [udf1/hec udf 2 udf 3 udf 4] payload 1 payload 2 payload 3 payload 4 :::: payload 45 payload 46 payload 47 payload 48 [post1 post2 post3 post4] [post5 post6 post7 post8] the prepended/postpended bytes and hec/udf will be translated, added, or subtracted as needed based on the translation settings, the input cell format, and the output cell format. 10.2 connection identification the atlas makes use of a flexible approach to identify incoming cells and to determine the record in the vc table with which they are associated. the atlas identifies the vc record of each connection by traversing a search tree in sram using selected portions of the cell header, prepend, postpend and the phy address. to do this, the atlas creates an internal routing word , which is the concatenation of the cell prepend, cell postpend, and cell header. the atlas is programmed to select portions of the routing word plus the phy address to create a vc search key . the vc search key, therefore, consists of portions of the cell?s header, prepend, postpend and phy address. the figure below illustrates the routing word and vc search key construction. this figure is not intended to imply any restrictions on the positioning of field a and field b. these fields may occur anywhere within the appended octets or the atm header. the primary key and secondary key may also intersect.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 document id: pmc-1990553, issue 4 figure 10 vc search key extraction field a field b vpi/vci hec/udf cell prepend + postpend cell header m 0 35 31 64 start b start b -l b start a start a -l a length <= 128 routing word vc search key phy id field a field b vpi/vci primary key secondary key phy id the atlas divides the vc search key into two search keys ? the primary key and the secondary key. the primary key is 17 bits long. it is constructed from two fields ? the phy id field and field a . the phy id field and field a can be programmed to be 0-6 bits and 0-17 bits long, respectively; the primary key is lsb justified and padded on the left with zeroes to make it 17 bits long. the phy id field is the utopia (or pos) address and must, therefore, include sufficient bits to encode all the phys at the phy layer interface of the atlas. field a starts at location starta of the routing word, and has length l a . the number of bits in field a plus the number of bits in the phy id field must be less than or equal to 17. field a and the phyid are always lsb justified within the 17-bit primary key (any unused msbs are set to logic 0). the secondary key is 46 bits long (although only 17 bits can be resolved at-speed in any given search) and consists of three fields. the first field, field b , is 0 to 12 bits long and may start anywhere in the routing word. field b parameters include starting position, startb and length, l b . the second field is the 6-bit phyid (zeroes are padded into the msbs of the phyid if the phyid is less than 6 bits). the third field is the 28-bit vpi/vci taken from the cell header. field b and the vpi/vci field are ?right justified? within the secondary key.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 document id: pmc-1990553, issue 4 figure 11 parameters of the primary and secondary keys la 0-17 bits lp 0-6 bits lp + la <= 17 bits phyid field a vpi + vci phyid field b unused 28 bits 6 bits lb 0-12 bits 0-12 bits 46 bits the user can program the atlas with the length and position parameters of fields a and b. the figure below provides a representation of how the atlas creates the primary and secondary search keys. field location and length registers are used to select field a and field b from the routing word. field a and the phy id are concatenated to form the primary search key. field b, the phy id, and the vpi/vci field are concatenated to form the secondary search key.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 document id: pmc-1990553, issue 4 figure 12 vc search key construction field a size & location field a location registers start a , l a field b size & location field b location registers start b , l b vpi/vci phy id field a primary search key secondary search key once the search keys are assembled, the primary search key is first used to address an external direct look-up table (this is the array of primary search pointers in bits(16:0) of the external search sram at saddr(17) = 0). this table occupies 2 n memory locations, where n = l phy + l a , i.e. the length of the primary search key. the result of this direct lookup is the address of a root node of a search tree. from this root node, the secondary search key is used by a patented search algorithm to find the vc table record address of the connection. the vc table record address is used to access the vc table record in internal dram and to fetch the f4 record address if active and up to two pm record addresses from the external linkage sram at saddr(17) = 1. these addresses are used to access the appropriate records (all of which are stored on chip). the validity of the record addresses fetched from the sram is checked by comparing the secondary search key with the search key (vpi, vci, and field b) stored in first row of the vc table record. any unused bits within this stored search key word must be set to zero. the configuration field of the vc table record contains the nni bit. this bit identifies if the virtual connection belongs to a network-network interface. if the nni bit is set to zero, the connection is part of a uni, which means that the four msbs of the vpi are excluded from the secondary key verification. if the vci field in the vc table is set to all zeros, this signifies the connection is a vpc, and the vci field is to be ignored. if the search process does not lead to the successful identification of the cell concerned (i.e. the search key stored in the vc table does not match the secondary search key used for the search), the cell is declared to be invalid, and will not be output. optionally, the cell may be routed to the microprocessor cell interface for error logging.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 document id: pmc-1990553, issue 4 the length of time required to perform the vc table search is variable. since the primary search key is used in a direct lookup, only one cycle is required to process the primary search key. the secondary search key processing time is highly dependent on the key?s contents, but the maximum number of processing cycles required is equal to the number of bits in the secondary search key which must be examined to make a unique identification. some vpi and vci bits may always be zero; therefore, they need not be used in the search. in some instances, the primary search key may overlap the secondary search key; therefore, the intersecting bits are only required for the confirmation of a search. if the number of bits used by the binary search is no greater than 18, a sustained rate of 5.682x10 6 cells/s is guaranteed. the general expression for guaranteed throughput is given below ()() cells/s period sysclk 18) depth, e binary tre max. max( 2 1 22 20 throughput + = note, however, if the binary tree depth is less than 18, the throughput remains 5.68x10 6 cells/s. 10.2.1 search table data structure the primary and secondary search key table fields reside in the lower 8 mbits of the external sram (saddr[17] = 0). each sram word is 64 bits wide. the primary table record entry is located in bits 17 to 0 of each word and the secondary table record entry is located in bits 63 to 18. there are a total of 128k possible primary and secondary records (all located in the lower 8 mbits of the external sram). the following table shows the format of each 64 bit word in the lower 8mbits of the external sram. table 5 search table 63 0 2 selector (6) left leaf (1) 1 left branch (17) right leaf (1) 1 right branch (17) 1 primary search pointer (17) shaded fields are reserved, and must be programmed to logic 0 for proper operation. the figure below illustrates the relationship between the primary search table key, secondary search table key and the vc table and shows the search tree?s that are used in connection identification.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 document id: pmc-1990553, issue 4 figure 13 construction of primary and secondary keys ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry ingress vc tabl e entry 2 (l p +l a ) -1 0 primary search table secondary search tabl e ingress vc tabl e entry the following gives the immutable coding rules for the search data structures. the coding supports numerous possible algorithms, but the s/uni-atlas-3200 software driver presents an algorithm that is optimized for most applications. primary search table the primary search table contains an array of pointers (the primary search pointers) that point to the roots of binary trees. the table is directly indexed by the contents of the primary search key, as defined above. for any given received cell, the search table entry pointed to by the primary search key contains the primary search pointer which points to the root of the secondary search binary tree for that cell. the entire primary search table must be initialized to all zeros. a table value of zero represents a null pointer; therefore, the initial state means no provisioned connections are defined. if a connection is added which results in a new binary search tree (i.e. it is the only connection associated with a particular primary search key), the appropriate primary search pointer must point to the newly created binary search tree root. if the last connection with a particular primary search key is removed, the associated primary search pointer must be set to all zeros. secondary search table the secondary search table consists of a set of binary search trees. each tree?s root is pointed to by a primary search pointer. each node in the tree is represented by a 42-bit data structure. the fields of the secondary search table are described below. table 6 secondary search table fields name description selector the selector field is a 6 bit field which is the index of the secondary search key bit upon which the branching decision of the binary search is based. an index of zero represents the lsb. if the selected bit is a logic 1, the left leaf and left branch fields are subsequently used. likewise, if the selected bit is a logic 0, the right leaf and right branch are subsequently used. typically, the selector value decreases monotonically with the depth of the tree, but
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 document id: pmc-1990553, issue 4 name description other search sequences are supported by the flexibility of this bit. left leaf this flag indicates if this node is a leaf. if left leaf is a logic 1, the left branch is a leaf and the binary search terminates if the decision bit is a logic 1. if left leaf is a logic 0, the left branch value points to another node in the binary tree. left branch the pointer to the node accessed if the decision bit is a logic 1. if left leaf is a logic 1, left branch contains the 16-bit address identifying the vc linkage record and vc table record for that connection. if left leaf is a logic 0, left branch contains the (up to) 17-bit address pointing to another secondary search table entry. right leaf this flag indicates if this node is a leaf. if right leaf is a logic 1, the right branch is a leaf and the binary search terminates if the decision bit is a logic 0. if right leaf is a logic 0, the right branch field points to another node in the binary tree. right branch the pointer to the node accessed if the decision bit is a logic 0. if right leaf is a logic 1, right branch contains the 16-bit address identifying the vc linkage record and vc table address for that connection. if right leaf is a logic 0, right branch contains the 17-bit address pointing to another secondary search table entry. the above encoding defines the binary search tree recursively. the following special cases must be respected: a binary tree with only one connection must have both the left and right branches pointing to the solitary vc table record. both the left leaf and right leaf flags must be a logic 1. if the primary search table is not used (i.e. l phy = l a = 0), then the primary key is considered to be all-zeroes, and the primary pointer at sa[16:0] = 0x00000 contains the root of the secondary search tree. if the primary search table is in use, no root node shall use location sa[16:0]=0x00000, although this location may be used for nodes at least one level down. a value of 0x00000 in the primary search pointer represents a null pointer. 10.3 vc linkage table the vc linkage table occupies the top half of the external sram address space, and contains pointers to other context entries with which a vc is associated. table 7 vc linkage table 63 0 1 phyid (6) 2 reserved (16) pm 2 active (1) 1 pm 2 address (8) pm 1 active (1) 1 pm 1 address (8) vpc pointer active (1) 2 vpc pointer (16) shaded fields are reserved, and must be programmed to logic 0 for proper operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 document id: pmc-1990553, issue 4 the pm active and pm address fields are used to select performance management entries to be associated with a particular vc. their function is fully described in section 10.14 on pm processing. the vpc pointer active and vpc pointer fields are used to associate a vcc record entry with a vpc record entry when vccs are being aggregated to, or split out from a vpc. all connections that are not vccs being aggregated to, or split out from vpcs must have their vpc pointer active bit set to logic 0. the function of the vpc pointer is more fully described in sections 10.10 and 10.11 on f4 to f5 and f5 to f4 oam processing. note that, if active, the 2 least significant bits of the vpc pointer cannot be equal to the 2 lsbs of the vc record address. failure to adhere to this restriction will result in the connection being treated as inactive. the phyid field indicates the physical layer device that this connection is associated with. this field is used to determine the destination of all generated ais, cc, rdi, lb, and pm cells. this field is also used in determining per-phy statistics and per-phy policing. if it is not the same as the phyid of cells on the connection, proper operation cannot be guaranteed. 10.4 vc record table the vc record table is a 7-row data structure which contains context information for one connection. the vc table is comprised of 64k vc table records stored in internal dram, one record for each of the 64k connections. the vc table is used for connection configuration and connection processing functions. unused bits within the table should be set to logic zero for future backward compatibility. table 8 vc record table row 127 0 0 read- only config action 2 (2) inc 2 (14) limit 2 (14) action 1 (2) inc 1 (14) limit 1 (14) field b (12) vpi (12) vci (16) 2 bwds vcra (16) vc table crc-10 (10) 1 status & config status (10) configuration (14) oam configuration (23) internal status (21) policing configuration (11) reserved (16) maximum frame length (11) gfr state (3) policing reserved (3) ete received defect type (8) segment received defect type (8) 2 counting alternate count 2 (32) alternate count 1 (32) count 2 (32) count 1 (32) 3 policing unused (1) remaining frame count (11) non-compliant count 3 (16) non-compliant count 2 (16) non-compliant count 1 (16) tat2 (34) tat1 (34) 4 trans- lation unused (4) translated vpi (12) translated vci (16) translated hec (8) translated udf (24) translated pre/po 1 (32) translated pre/po 2 (32) 5 seg dl segment received defect location (128) 6 ete dl end-to-end received defect location (128) the fields of the vc table are described in the following sections. 10.5 cell processing after a vpi/vci search has been completed for a cell, the resulting actions are dependent upon the cell contents and the vc table record. particular features such as policing and oam cell processing can be disabled on a global and per-connection basis.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 document id: pmc-1990553, issue 4 the vpi/vci search results in a vcra[15:0] value which points to a vc table record. the fields of each vc table record are described below. when a new vc is provisioned, the management software must initialize the contents of the vc table record. once provisioned, the management software can retrieve the contents of the vc table record. table 9 vc table fields used in cell processing row 127 0 0 action 2 (2) inc 2 (14) limit 2 (14) action 1 (2) inc 1 (14) limit 1 (14) field b (12) vpi (12) vci (16) 2 bwds vcra (16) vc table crc-10 (10) 1 status (10) configuration (14) oam configuration (23) internal status (21) policing configuration (11) reserved (16) maximum frame length (11) gfr state (3) policing reserved (3) ete received defect type (8) segment received defect type (8) 2 alternate count 2 (32) alternate count 1 (32) count 2 (32) count 1 (32) 3 unused (1) remaining frame count (11) non-compliant count 3 (16) non-compliant count 2 (16) non-compliant count 1 (16) tat2 (34) tat1 (34) 4 unused (4) translated vpi (12) translated vci (16) translated hec (8) translated udf (24) translated pre/po 1 (32) translated pre/po 2 (32) 5 segment received defect location (128) 6 end-to-end received defect location (128) table 10 status vc table field bit name description 9 fifo must write this bit should be set to zero when the connection is setup. 8 dram_crc_err when this bit is logic 1, this vc table entry has suffered a dram crc- 10 error. if the inact_on_dram_error register bit in the cell processor configuration register is logic 1, and this bit is a logic 1, then the connection is considered inactive. this bit can only be cleared by a microprocessor write. 7 oam_failure this bit becomes a logic 1 if a segment or end-to-end rdi, ais or cc condition has persisted for 3.5 0.5 seconds. oam_failure is cleared as soon as no rdi, ais or cc condition remains. 6 ais_end_to_end alarm this bit becomes a logic 1 upon receipt of a single end-to-end ais cell. the alarm status is cleared upon the receipt of a single user cell or end- to-end cc cell, or if no end-to-end ais cell has been received within the last 2.5 0.5 sec. 5 ais_segment alarm this bit becomes a logic 1 upon receipt of a single segment ais cell. the alarm status is cleared upon the receipt of a single user cell or segment cc cell, or if no segment ais cell has been received within the last 2.5 0.5 sec. 4 rdi_end_to_end alarm this bit becomes a logic 1 upon receipt of a single end-to-end rdi cell. this bit is cleared if no end-to-end rdi cell has been received within the last 2.5 0.5 sec. 3 rdi_segment alarm this bit becomes a logic 1 upon receipt of a single segment rdi cell. this bit is cleared if no segment rdi cell has been received within the latest 2.5 0.5 sec. 2 cc_end_to_end alarm this bit becomes a logic 1 if no user cell or end-to-end cc cell has been received within the last 3.5 0.5 sec. this bit is cleared upon receipt of a user cell, or end-to-end cc cell. if this connection is an
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 document id: pmc-1990553, issue 4 bit name description end-to-end source point, this alarm may not indicate a problem, as a source point cannot expect to receive cc cells. in this case, the cos_fifo_en bit in the oam confiiguration register may be useful for suppressing these warnings. 1 cc_segment alarm this bit becomes a logic 1 if no user, segment cc cell has been received within the last 3.5 0.5 sec. this bit is cleared upon receipt of a user cell, or segment cc cell. segment cc alarms are declared only if the vc is part of a segment flow (segment_flow = 1) or is a segment end point (segment_end_point = 1) 0 reserved this bit should be set to logic 0. table 11 configuration vc table field bit name description 13 reserved this bit must be programmed to logic 0 for backwards compatibility. 12 reserved this bit must be programmed to logic 0 for backwards compatibility. 11 active identifies the connection as active. this bit is checked during the s/uni-atlas-3200 background processes to determine if the connection is still active. it is the responsibility of the management software to set and clear this bit during activation and deactivation, respectively, of a connection. it is recommended to set this bit to logic 0 until the search and linkage rows have been correctly configured. cells received on a connection for which active is a logic 0 will be dropped, with an optional copy to the microprocessor cell interface if the inactivetoup register bit is a logic 1. these cells will not be counted by the cell processor. 10 nni when the nni bit is logic 0, then the top four bits of the vpi are considered to be part of the gfc field. as such, they will not be used to verify the correctness of the search, and will not be translated unless the xgfc register bit is a logic 1. 9 count config select this bit is used to address one of two possible combinations of programmable cell counts. if this bit is a logic 0, the cell count 1[31:0] and cell count 2[31:0] are programmed from the cfg1 settings in the cell counting configuration register. if this bit is a logic 1, the cell counts are derived from the cfg2 settings in cell counting configuration. 8 apstoup when this bit is a logic 1, all automated protection switching coordination protocol cells are copied to the microprocessor. if the apstobcif bit is also set to logic 1 in the routing configuration register, then aps cells are passed to bcif instead of the microprocessor. aps cells are also passed to the ocif, unless s/uni-atlas-3200 is an oam flow end-point and the apstoocif bit in the routing configuration register is logic 0. 7:6 lb_route[1:0] the lb_route bits determine the handling of loopback cells. regardless of the setting of lb_route, loopback cells are always dropped at flow end points unless lbtoocif is logic 1 in the routing configuration register. lbtoocif = 1 always causes loopback cells to be copied to the ocif, but does not otherwise affect the functionality of lb_route. when lb_route[1:0] = 00 then loopback cells will be dropped at flow end points, but otherwise will be routed to the ocif. this
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 document id: pmc-1990553, issue 4 bit name description setting is intended for nodes that do not support lb functionality. when lb_route[1:0] = 01, then loopback cells will be automatically looped back based on the contents of the loopback indication, source id, and loopback location id. cells with loopback indication = 0 (?returned loopback cells?) will be dropped and routed to the microprocessor cell interface at connection points whose loopback location id register matches the source id of the loopback cell. at flow end points, all returned lb cells may be routed to the microprocessor if the rtd_lb_to_up_at_end register bit is set to logic 1 in the routing configuration field. for cells with loopback indication = 1 (?parent loopback cells?) segment loopback cells will be dropped and looped back if their loopback location id matches the loopback location id register, and looped back but not dropped if their loopback location id is all- zeroes. both segment and end-to-end cells will be dropped and looped back at flow end points if their loopback location id is all- ones, or if it matches the the loopback location id register at the end point. in any event, loopback cells are always dropped at flow end points. cells which are looped back always have their loopback indication bit set to 0, and have their loopback location id field replaced with the contents of the loopback location id registers. when route_lb[1:0] = 10 then loopback cells are handled the same as if route_lb[1:0] = 01, but instead of automatically looping back the cells, cells are routed (without modification to loopback location id or loopback indication) to the microprocessor cell interface. when route_lb[1:0] = 11 then all loopback cells are dropped and routed to the microprocessor cell interface. when using this setting, if the microprocessor later reinserts these cells it should set the proc_cell bit to logic 0 to ensure they do not simply get routed to the microprocessor once again. 5 fm_to_up if this bit is a logic 1, all fault management cells (ais, rdi, cc) are copied to the microprocessor cell interface. the segment_end_point and end_to_end_point bits determines whether or not fm cells are output to the output cell interface. fm_to_up does not control the routing of loopback cells, which are controlled by the lb_route bits. 4 vc_to_bcif if this bit is logic 1, all cells arriving on this connection are copied to the backwards cell interface, unaltered except for the header translation normally specified for cells being routed to obcif (e.g. xlate_to_obcif, obcif_cell_info, etc). if drop_vc = 1 and vc_to_bcif = 1, then it is assumed that a per-vc loopback function is being implemented, and cells from the ibcif will be permitted to proceed to the ocif, and will not be sent to obcif. all other cells will be sent to obcif, and not sent to ocif. if more cells are sent to the obcif than can be accommodated, then cells can be lost due to fifo overflow. rdi and bwd pm cells generated by s/uni-atlas-3200 will not be lost, but loopback cells and cells routed via vc_to_bcif may be lost. the obcif is drained at the lesser of the opposite-direction backward cell interface pacing rate, and the capacity of the bcif link (approximately 1.3 million cells per second).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 document id: pmc-1990553, issue 4 bit name description 3 vc_to_up if this bit is logic 1, all cells arriving on this connection are copied, unaltered except for the insertion of the cell info field, to the microprocessor cell interface 2 drop_vc if this bit is a logic 1, no cells are routed to the ocif. the setting of this bit supercedes all other routing bits. if the drop_vc bit is set, the s/uni-atlas-3200 will not output generated oam cells to the ocif (ais, cc, fwd pm). drop_vc has no effect on the generation of oam cells to the bcif. if drop_vc = 1 and vc_to_bcif = 1, then it is assumed that a per-vc loopback function is being implemented, and cells from the ibcif will be permitted to proceed to the ocif, and will not be sent to obcif. all other cells will be sent to obcif, and not sent to ocif. 1 rollover_fifo_enable enables the 32-bit billing counts to generate entries in the count rollover fifo whenever their msb becomes logic 1. if the count rollover fifo is full, the msb will remain logic 1 until an entry has been successfully generated, at which time the msb will become logic 0. if this bit is logic 0, then the counts operate as normal saturating counters, and must be polled periodically by the microprocessor. 0 cos_fifo_enable enables changes in the status field to result in cos fifo entries. table 12 internal status vc table field bit name description 20 reserved this bit must be programmed to logic 0 for backwards compatibility. 19 reserved this bit must be programmed to logic 0 for backwards compatibility. 18 sending_ais if this bit is logic 1, this connection transmitted an ais cell at the last one-second processing interval. this indicates that, if a half-second background process is being executed, the cause of ais is not new, and no ais should be sent until the next one-second process. this bit should be set to logic 0 when the connection is set up. 17 sending_rdi_seg this bit enables the s/uni-atlas-3200 to generate the first segment rdi cell within 500msec of detecting a condition which requires the generation of segment rdi cells. this bit is set to logic 1 by the s/uni-atlas-3200 when a segment rdi cell is transmitted, and set to logic 0 when the rdi background process determines there is no reason to continue sending segment rdi. in addition to setting this bit when transmitting a segment rdi cell on reception of an ais cell, the s/uni-atlas-3200 will use the 0.5 second background process to scan through all connections and determine if a segment rdi cell is to be transmitted (within 0.5 seconds of detecting the appropriate condition). when the first segment rdi cell is transmitted, this bit is asserted and subsequent segment rdi cells are only transmitted by the 1 second background process. if this bit is logic 0, the s/uni-atlas-3200 has not yet begun to transmit segment rdi cells (possibly due the rdi bcif being full). this bit should be set to logic 0 when the connection is set up. 16 sending_rdi_ete this bit enables the s/uni-atlas-3200 to generate the first end-to- end rdi cell within 500msec of detecting a condition which requires the generation of end-to-end rdi cells.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 document id: pmc-1990553, issue 4 bit name description this bit is set to logic 1 by the s/uni-atlas-3200 when a end-to- end rdi cell is transmitted, and set to logic 0 when the rdi background process determines there is no reason to continue sending end-to-end rdi. in addition to setting this bit when transmitting a end-to-end rdi cell on reception of an ais cell, the s/uni-atlas-3200 will use the 0.5 second background process to scan through all connections and determine if a end-to-end rdi cell is to be transmitted (within 0.5 seconds of detecting the appropriate condition). when the first end-to-end rdi cell is transmitted, this bit is asserted and subsequent end-to-end rdi cells are only transmitted by the 1 second background process. if this bit is logic 0, the s/uni-atlas-3200 has not yet begun to transmit end-to-end rdi cells (possibly due the rdi bcif being full). this bit should be set to logic 0 when the connection is set up. 15:14 oam_failure_count this count is set to 3 (to provide a 3.5 0.5 second count) whenever there is no ais, cc or rdi alarm declared, and is decremented at one-second intervals whenever there is an ais, cc, or rdi alarm. if it is read back as 0, then the oam_failure bit will be set to logic 1, and an interrupt and/or an entry in the cos fifo will be made, as appropriate. this field should be set to 3 when the connection is set up. 13 send_seg_cc_count the send_seg_cc_count is set to logic 1 (to provide a one second count) at connection setup time and each time the s/uni-atlas- 3200 sends a user (or a received segment cc cell) cell on this connection. the count is decremented at one second intervals. if this count reaches zero and is still 0 when it is read in the subsequent second, then a segment cc cell is generated, if the cc_activate_segment bit is set. this bit should be set to logic 1 when the connection is set up. 12 send_end_cc_count the send_end_cc_count is set to logic 1 (to provide a one second count) at connection setup time and each time the s/uni-atlas- 3200 sends a user cell (or a received end-to-end cc cell) on this connection. the count is decremented at one second intervals. if this count reaches zero and is still 0 when it is read in the subsequent second, then an end-to-end cc cell is generated, if the cc_activate_end_to_end bit is set. this bit should be set to logic 1 when the connection is set up. 11:10 seg_cc_count[1:0] the seg_cc_count is set to a value of 3 (to provide a 3.5 +/- 0.5 sec count) upon receipt of a user or segment cc cell, and decremented at one second intervals. if the seg_cc_count reaches 0 and is still 0 when it is read in the subsequent second, the cc_segment alarm is raised. this field should be set to 3 when the connection is set up. 9:8 end_cc_count[1:0] the end_cc_count is set to a value of 3 (to provide a 3.5 +/- 0.5 sec count) upon receipt of a user or end-to-end cc cell, and decrements at one second intervals. if the end_cc_count reaches 0 and is still 0 when it is read in the subsequent second, the cc_end_to_end alarm is raised. this field should be set to 3 when the connection is set up. 7:6 seg_rdi_count[1:0] the seg_rdi_count is set to a value of 2 (to provide a 2.5 +/- 0.5 sec count) upon receipt of a segment rdi cell, and decrements at one second intervals. if the seg_rdi_count reaches 0 and is still 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 document id: pmc-1990553, issue 4 bit name description when it is read in the subsequent second, the rdi_segment alarm is cleared. this field should be set to 0 when the connection is set up. 5:4 end_rdi_count[1:0] the end_rdi_count is set to a value of 2 (to provide a 2.5 +/- 0.5 sec count) upon receipt of an end-to-end rdi cell, and decrements at one second intervals. if the end_rdi_count reaches 0 and is still 0 when it is read in the subsequent second, the rdi_end_to_end alarm is cleared. this field should be set to 0 when the connection is set up. 3:2 seg_ais_count[1:0] the seg_ais_count is set to a value of 2 (to provide a 2.5 +/- 0.5 sec count) upon receipt of a segment ais cell, and decrements at one second intervals. if the seg_ais_count reaches 0 and is still 0 when it is read in the subsequent second, the ais_segment alarm is cleared. this field should be set to 0 when the connection is set up. 1:0 end_ais_count[1:0] the end_ais_count is set to a value of 2 (to provide a 2.5 +/- 0.5 sec count) upon receipt of an end-to-end ais cell, and decrements at one second intervals. if the end_ais_count reaches 0 and is still 0 when it is read in the subsequent second, the ais_end_to_end alarm is cleared. this field should be set to 0 when the connection is set up. table 13 oam configuration vc table field bit name description 22 reserved this bit must be programmed to logic 0 for backwards compatibility. 21 cos_cc_dis when this bit is logic 1, then entering or exiting cc alarm will not generate a cos entry. when this bit is logic 0, cos entries are generated as normal. this feature is intended for use with older equipment that does not correctly support cc, in order to avoid flooding the microprocessor with cc-related cos entries. 20 send_ais_segment if this bit is a logic 1, a segment ais cell is generated once per second (nominally). 19 send_ais_end_to_end if this bit is a logic 1, an end-to-end ais cell is generated once per second (nominally). 18 send_rdi_segment if this bit is a logic 1, a segment rdi cell is generated once per second (nominally). 17 send_rdi_end_to_end if this bit is a logic 1, an end-to-end rdi cell is generated once per second (nominally). 16 cc_activate_segment enables continuity checking on segment flows. if the forcecc register bit is logic 0, then when no user or cc cells are transmitted over a 1.0 second (nominal) interval, a segment cc oam cell is generated. the segment cc cell is generated at an interval of one per second (nominally). if the connection is an f4 oam connection that is being aggregated, then any cells transmitted on any of the constituent f5 connections are considered user cells. if the forcecc register bit is logic 1, then when the cc_activate_segment bit is logic 1, a segment cc cell will be generated at an interval of once per second (nominally), regardless of the flow of user cells. itu-t i.610 9.2.1.1.2, 9.2.2.1.2.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 document id: pmc-1990553, issue 4 bit name description 15 cc_activate_end_to_e nd enables continuity checking on end-to-end flows. if the forcecc register bit is logic 0, then when no user or end-to-end cc cells are transmitted over a 1.0 second (nominal) interval, an end-to-end cc oam cell is generated. the end-to-end cc cell is generated at an interval of one per second (nominally). if the connection is an f4 oam connection that is being aggregated, then any cells transmitted on any of the constituent f5 connections are considered user cells. if the forcecc register bit is logic 1, then when the cc_activate_end_to_end bit is logic 1, an end-to-end cc cell will be generated at an interval of once per second (nominally), regardless of the flow of user cells. itu-t i.610 9.2.1.1.2, 9.2.2.1.2. 14 fm_interrupt_enable this bit enables the generation of segment and end-to-end ais, rdi continuity check, and oam failure alarm interrupts. if this bit is logic 1, the s/uni-atlas-3200 will assert oam failure and segment and end-to- end ais, rdi and continuity check interrupts, as required, regardless of whether or not the s/uni-atlas-3200 is a connection end-point (segment or end-to-end) for the connection. this bit would typically be programmed to logic 1 at segment or end-to-end-points only. if this bit is logic 0, no alarm interrupts will be asserted, however, the status field will reflect the connection state. 13:6 generated oam defect type [7:0] the defect type bits determine the defect type that is inserted into ais cells generated due to the cc_ais_rdi process, via per-phy ais, and via the send_ais_end_to_end or send_ais_segment bits, and into rdi cells generated via the cc_ais_rdi process, via per-phy rdi generation, or via the per-vc bits send_rdi_end_to_end or send_rdi_segment. 5 f4tof5oam the f4tof5oam bit indicates whether or not an f5 (vcc) connection will send ais or rdi cells due to an associated f4 (vpc) connection being in ais alarm. this bit is only significant if the connection is an f5. when an f4 (vpc) is terminated (i.e. there is an f4 connection end-point which is associated with this f5 connection) at the s/uni-atlas-3200, the f5 connections are switched. if the f4 receives ais cells, then the f5 connections will send ais and/or rdi cells once per second, carrying the defect location and defect type contained in the received f4 ais cells. if f4tof5oam is set to logic 0, then this process is disabled, and no f5 ais or rdi cells will be generated based on the condition of the associated f4. 4 auto_rdi the auto_rdi bit enables the generation of segment and end-to-end rdi cells while in an ais alarm or continuity alarm state. if auto_rdi is logic 1, an rdi cell is transmitted (and looped from the cell processor to the reverse cell stream) immediately upon the reception of the first ais cell at a flow end-point. (if the s/uni-atlas-3200 is an end-to-end point for that connection, an end-to-end rdi cell will be generated, if the s/uni-atlas- 3200 is a segment end point, a segment rdi cell will be generated, and if the s/uni-atlas-3200 is both a segment and end-to-end point, both types of rdi cells will be generated) and once per second thereafter until the ais state is exited. similarly, if the cc_ais_rdi bit is logic 1, rdi cells are generated once per second if no user or cc cells have been received in the last 3.5 +/- 0.5 seconds. rdi cells can also be transmitted if the send_rdi_segment and send_rdi_end_to_end bits are set, or if the phyrdi register bits are set. 3 cc_ais_rdi if this bit is a logic 1, ais or rdi cells are generated at one second intervals upon the declaration of a cc_alarm (assuming ais_alarm is not also declared). if the connection is not a segment or ete end point, then ete ais will be generated once per second on declaration of ete cc alarm. if
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 document id: pmc-1990553, issue 4 bit name description segment_flow = 1, then segment ais will be generated on declaration of segment cc alarm. if the connection is a segment end point, then ete ais and segment rdi will be generated once per second on declaration of segment cc alarm. if the connection is an ete end point, then ete rdi will be generated once per second on declaration of ete cc alarm. if the connection is both a segment and an ete point, then segment rdi will be generated once per second on declaration of segment cc alarm, and ete rdi will be generated once per second on declaration of ete cc alarm. ais and rdi cells generated via the cc_ais_rdi process have the defect type programmed in the generated oam defect type field, and the defect location programmed in the global defect location register. in any event, ais/rdi cells will not be generated at a rate of more than one segment and one end-to-end ais cell per second, nominally. in particular, segment and ete ais cells will not be generated via this process if the connection is already receiving segment or ete ais cells, respectively. 2 segment flow the segment_flow bit indicates whether a connection is part of a defined segment. when segment_flow is logic 1, then segment ais cells may be sent due to cc alarm (controlled by cc_ais_rdi), due to per-phy ais declaration (controlled by the per-phy ais generation control registers), or due to ais declaration at the f4 connection associated with an f5 connection (controlled by the f4tof5oam bit). the segmentflow bit should not be set to a logic 1 at segment end-points, or at segment start-points. 1 segment_end_point defines the s/uni-atlas-3200 as a segment termination point. for f4 connections (vpcs), all cells with vci = 3 are terminated and processed. for f5 connections (vccs), all cells with pti = 100 are terminated and processed. 0 end_to_end_point defines the s/uni-atlas-3200 as an end-to-end termination point. for f4 connections (vpcs), all cells with vci = 4 are terminated and processed. for f5 connections (vccs), all cells with pti = 101 are terminated and processed. all segment oam cells are dropped at end-to- end points, but they are not processed unless the segment_end_point bit is also logic 1. table 14 vc table miscellaneous fields name description vci[15:0] specifies the vci associated with this vc. for vpcs and f4 oam connections, this field should be coded to all zeroes, and will be unused. for vccs, this field is compared to the vci of incoming cells to confirm that the search completed correctly. if the vci field and the vci of the incoming cell do not match, the search is considered invalid, and the cell will be dropped, with an optional copy to the microprocessor. this field is also used when generating oam cells, if header translation is disabled. vpi[11:0] specifies the vpi associated with this vc. this field is compared to the vpi of incoming cells to confirm that the search completed correctly. if the vpi field and the vpi of the incoming cell do not match, the search is considered invalid, and the cell will be dropped, with an optional copy to the microprocessor. if the connection is configured as a uni (the nni bit in the configuration field is set to logic 0) then the first 4 bits of the vpi contain the gfc field and are thus not used in the comparison. this field is also used
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 document id: pmc-1990553, issue 4 name description when generating oam cells, if header translation is disabled. if the connection is a uni, the first four bits of the vpi field should be set to zero. field b [11:0] this field is compared against the field b extracted from the cell during the search. if the field b from the vc table and the field b from the incoming cell do not match, the search is considered invalid and the cell is dropped, with an optional copy to the microprocessor. any unused bits in this field should be set to logic 0. if field b is configured to be less than 12 bits, the data should be lsb justified in this field. bwds vcra [15:0] the backwards direction vcra indicates the vc record address of the corresponding vc in the opposite-direction s/uni-atlas-3200. if the obcif_bwd_vcra bit is logic 1 in the cell processor routing configuration register, this field will be inserted, along with the phy id and other routing information, in prepended bytes of cells sent to the backwards cell interface, to permit the opposite-direction s/uni-atlas-3200 to identify the cell without performing a search on it. if obcif_bwd_vcra is logic 1, then it is expected that search_from_ibcif will be logic 0 in the opposite- direction s/uni-atlas-3200. vc table crc-10 [9:0] this field provides a crc-10 over the vc table in dram. if a crc-10 error occurs, the dram_crc_err bit is set, an interrupt is raised, and the connection is optionally rendered inactive, depending on the setting of the inactivate_on_dram_err bit in the cell processor configuration register. cell count 1 and 2 [31:0] alternate cell count 1 and 2 [31:0] these fields contain the billing cell counts, configured by the cell counting configuration register bits. the count config select field in the vc record table?s configuration field selects between the possible configurations . the alternate counts are intended for use in time-of-day billing. when the alternate_count register bit is set to logic 1, the cell count fields in all vc records stop being incremented, and the alternate cell count fields are incremented instead. the handover is done in such a way that no cell counts are missed. these counts represent the number of cells received, including cells from the bcif, and cells from the mcif (assuming proc_cell = 1). this counting occurs before policing is evaluated. the non-compliant cell counts can be subtracted to determine the state of the counts after policing. cells received on connections with the active bit equal to logic 0 will not be counted. received end-to-end defect location [127:0] this field is used to store the defect location from a received end-to-end ais or rdi cell. in the case of received ais cells, this field is used in rdi cells generated due to end-to-end ais declaration, via the auto_rdi function. if rdi cell generation is forced (using either the send_rdi table bits or the per-phy rdi register bits) or generated by the cc_ais_rdi process, the contents of the global generated defect location registers will be used. if the connection is an f4 being split out into f5s, then this field is used to determine the defect location of f5 ais and rdi cells sent due to f4 end-to-end ais declaration. in the case of received rdi cells, the defect location is simply stored for future retrieval. defect locations from rdi cells will not be stored if end-to- end ais alarm has been declared, and will be overwritten on the arrival of ais cells, so this field is only valid for rdi cells if end-to-end rdi alarm is declared and end-to-end ais alarm is not. received end-to-end ais defect type [7:0] this field is used to store the defect type from a received end-to-end ais or rdi cell. in the case of received ais cells, this field is used in rdi cells generated due to end-to-end ais declaration, via the auto_rdi function. if rdi cell
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 document id: pmc-1990553, issue 4 name description generation is forced (using either the send_rdi table bits or the per-phy rdi register bits) or generated by the cc_ais_rdi process, the contents of the generated oam defect type field will be used. if the connection is an f4 being split out into f5s, then this field is used to determine the defect type of f5 ais and rdi cells sent due to f4 end-to-end ais declaration. in the case of received rdi cells, the defect type is simply stored for future retrieval. defect types from rdi cells will not be stored if end-to-end ais alarm has been declared, and will be overwritten on the arrival of ais cells, so this field is only valid for rdi cells if end-to-end rdi alarm is declared and end-to-end ais alarm is not. received segment defect location [127:0] this field is used to store the defect location from a segment ais or rdi cell. in the case of received ais cells, this field is used in rdi cells generated due to segment ais declaration via the auto_rdi function. if rdi cell generation is forced (using either the send_rdi table bits or the per-phy rdi register bits) or generated by the cc_ais_rdi process, the contents of the global defect location registers will be used. if the connection is an f4 being split out into f5s, then this field is used to determine the defect location of f5 ais and rdi cells sent due to f4 segment ais declaration. in the case of received rdi cells, the defect location is simply stored for future retrieval. defect locations from rdi cells will not be stored if segment ais alarm has been declared, and will be overwritten on the arrival of ais cells, so this field is only valid for rdi cells if segment rdi alarm is declared and segment ais alarm is not. received segment ais defect type [7:0] this field is used to store the defect type from a received segment ais or rdi cell. in the case of received ais cells, this field is used in segment rdi cells generated due to segment ais declaration via the auto_rdi function. if rdi cell generation is forced (using either the send_rdi table bits or the per-phy rdi register bits) or generated by the cc_ais_rdi process, the contents of the generated oam defect type field will be used. if the connection is an f4 being split out into f5s, then this field is used to determine the defect location of f5 ais and rdi cells sent due to f4 segment ais declaration. in the case of received rdi cells, the defect type is simply stored for future retrieval. defect types from rdi cells will not be stored if segment ais alarm has been declared, and will be overwritten on the arrival of ais cells, so this field is only valid for rdi cells if segment rdi alarm is declared and segment ais alarm is not. 10.6 header translation once the appended octets, header, hec, and udf have been used in connection identification, they may be replaced with the contents of fields in row 4 of the vc table. table 15 vc table fields for header translation row 127 0 4 unused (4) translated vpi (12) translated vci (16) translated hec (8) translated udf (24) translated pre/po 1 (32) translated pre/po 2 (32)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 accepts cells ranging from 52 bytes (1 d-word of header and 12 of payload) to 64 bytes (2 prepends or postpends, 1 d-word of header, 1 d-word of hec and udf, and 12 of payload). the hec/udf fields are optional, and there may be no prepended/postpended d-words, one or two prepended d-words, one or two postpended d-words, or one prepend and one postpend. the s/uni-atlas-3200 can also send words with any of those combinations. prepended, postpended and hec/udf d-words are added, translated, or deleted as necessary to adjust from the input cell interface configuration to the output cell interface configuration, and to match the global header translation instructions. prepended or postpended words are replaced with or generated from the contents of the translated pre/po1 and translated pre/po2 fields if the xprepo bit is logic 1 in the cell processor configuration register. if xprepo is logic 0, but the output cells have prepends or postpends associated, then generated cells will contain 6a6a6a6a hex in those fields. as an additional option, the prepended/postpended words may be replaced with a descriptive word identifying the cell?s vc record, cell type, and some information about the connection. this cell info field is identical to the microprocessor cell info field described in section 10.17.5; its insertion is controlled by the cell_info_to_ocif bit in the cell processor configuration register. the header contents of each cell can be altered, and replaced with the contents of the translated vpi and translated vci fields. substitution of the vpi/vci contents can be enabled by setting the xvpivci register bit. the pti and clp fields are not modified by the header translation process. if the connection is a virtual path (i.e. the vci value in the vc table is coded as all zeros), the vci field is passed through transparently. as a globally configured option, the gfc field in uni cells can be left unmodified; otherwise, it is replaced by the four most significant bits of the translated vpi field. the hec and udf fields can be passed through transparently, or replaced by the translated hec and translated udf fields of the vc table, as configured by the xhec and xudf bits. 10.7 cell rate policing 10.7.1 per-vc policing the s/uni-atlas-3200 supports two instances of the generic cell rate algorithm (gcra) for each connection. the policing operation is performed according to the virtual scheduling algorithm outlined in itu-t i.371. the per-vc policing fields are held in the vc table in rows 0,1, and 3. table 16 vc table policing fields row 127 0 0 action 2 (2) inc 2 (14) limit 2 (14) action 1 (2) inc 1 (14) limit 1 (14) field b (12) vpi (12) vci (16) 2 bwds vcra (16) vc table crc-10 (10) 1 status (10) configuration (14) oam configuration (23) internal status (21) policing configuration (11) reserved (16) maximum frame length (11) gfr state (3) policing reserved (3) ete received defect type (8) segment received defect type (8) 3 unused (1) remaining frame count (11) non-compliant count 3 (16) non-compliant count 2 (16) non-compliant count 1 (16) tat2 (34) tat1 (34)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 document id: pmc-1990553, issue 4 table 17 policing configuration vc table field bit name description 10 gfr_mcr_ppd if this bit is logic 1, gfr policing is enabled and the mcr test is enabled to discard (i.e. action 2 = discard) then the policer will perform partial packet discard when a connection begins to fail mcr. if this bit is logic 0, then the mcr is only permitted to perform actions on frame boundaries, as per the gfr standard. 9 vp_police if this bit is a logic 1, then policing will be done using the parameters and configuration for the associated f4 rather than for this connection. all cells received on f5s will be considered user cells for the purposes of f4 policing. note that only received cells are ever policed ? generated cells of any sort are immune to policing, and do not affect tats. this bit must be set to logic 0 if the f4 pointer active bit in the linkage row is logic 0. gfr policing is not possible at the f4 level. 8 cocup the conditional conformance update (cocup) bit is used to introduce a coupling between the two gcras. if cocup=0, then gcra1 and gcra2 are completely independent of each other and the updating of the tat1 and tat2 fields are independent. if the cell is conforming to a gcra, the tat field for that gcra will be updated. if cocup is a logic 1, then the updating of the tat fields is conditional on both gcras. the operation is more fully explained below. 7 policing rollover fifo enable enables the non-compliant counts to generate entries in the count rollover fifo whenever their msb becomes logic 1. if the count rollover fifo is full, the msb will remain logic 1 until an entry has been successfully generated, at which time the msb will become logic 0. if this bit is logic 0, then the counts operate as normal saturating counters, and must be polled periodically by the microprocessor. 6 clpcc_clp1_discard if the clp conformance check clp1 discard bit is set to logic 1, then during gfr policing, if a cell arrives with clp = 1 in a frame whose first cell had clp = 0, then the frame will undergo partial packet discard. if the clp=1 cell is the end of packet, then every cell until the next clp = 0 end of packet will be discarded. if this bit is logic 0, then clp = 1 cells in clp = 0 frames will not be treated as non-compliant. 5 phy police if the phy policing bit is logic 1, then phy policing is enabled on this connection. if this bit is logic 0, then this connection is not affected by per- phy policing, and does not affect per-phy policing parameters. 4gfr if the guaranteed frame rate bit is a logic 1, then the frame-aware gfr policing algorithm is enabled. gfr policing is discussed in section 10.7.3. when gfr policing is enabled, gcra 1 must be configured to police the pcr, with the action set to discard, and gcra2 must be configured to police the mcr, with the action set to either tag or discard. actions due to violation of mcr will only be performed on frame boundaries, unless the gfr_mcr_ppd bit is logic 1. if the gfr bit is logic 0, then normal, non- frame-aware policing is performed. 3 violate when the violate bit is logic 1, the policer acts as if gcra2 always fails. actions taken on the cell, and updating of phy tat, gcra1 tat, and non-compliant count values is exactly as if gcra 2 had failed. violate is not compatible with gfr policing. 2:0 policing config select the policing config select bits select one of 8 policing configurations stored in registers. policing config select = 000 selects connection policing configuration # 1, and policing config select = 111 selects connection policing configuration # 8. these configurations dictate which of clp0, clp1, user, oam, rm, and other cells are policed by each gcra.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 document id: pmc-1990553, issue 4 to allow full flexibility, the s/uni-atlas-3200 supports 8 possible configurations, selected by the policing config select bits, which allow each gcra to police any combination of user cells, oam cells, rm cells, high priority cells or low priority cells. the theoretical arrival time fields (tat1 and tat2), increment fields (i1 and i2), and limit fields (l1 and l2) must be initialized before policing is enabled. when the connection is setup, the tat fields must be set to all zeros, and they should not be modified by the management software after the connection has been initialized. the increment and limit fields must be programmed to the desired traffic rate. these fields relate to the traffic contract parameters as follows: () t pcr i ? = 1 (s) period clock (cells/s) rate cell peak field increment = ? = = t pcr i in order to obtain the granularity required in itu-t i.371, the increment fields are encoded as floating-point fields as follows: 511 0 31 0 where 512 1 2 + = m e m i e the exponent, e , is a 5-bit field and the mantissa, m , is a 9-bit field. the increment field is formatted as follows: msb lsb 408 0 em the floating-point encoding format of the increment field ensures the granularity of the s/uni- atlas-3200 is 0.19% in accordance with itu-t i.371 5.4.1.2. the limit field is defined as: t l ? = where (s) variation delay cell = for a sustained cell rate (scr) conformance definition, the parameters relate as follows:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 document id: pmc-1990553, issue 4 () t scr i ? = 1 () t pcr scr mbs t bt l ? ? ? = ? = 1 1 1 where (s) tolerance burst (cells) rate cell peak at the size burst maximum (cells/s) rate cell sustaned = = = bt mbs scr in order to compensate for the potentially large cdv and burst tolerance limits anticipated in atm networks, the limit fields, l1 and l2 are encoded as floating-point values, in the same manner as the increment fields: 511 0 31 0 where 512 1 2 + = m e m l e where e is the 5-bit exponent and m is the 9-bit mantissa. the limit fields are formatted as follows: msb lsb 408 0 em the theoretical arrival time (tat1 and tat2) are encoded as fixed-point values with an integer and fraction portion. the integer portion of the tat field is a 31-bit value, and the fractional portion is a 3-bit value. the tat fields are formatted as follows: 33 3 2 0 integer portion fractional portion the fractional portion of the tat field is measured in fractions of the clock period, t ? . for a 8 ns clock period, the accuracy of the policing algorithm can be measured as follows:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 document id: pmc-1990553, issue 4 % 57 . 0 00565 . 0 ns 76.949 1 ) ns 8 )( 125 . 0 ( min min accuracy ns 949 . 176 max 1 min mbps) 2488 at rate cell maximum the is (this cells/s 5651328 max = = = = = = = t tat pcr t p cr thus, the accuracy of the s/uni-atlas-3200 policing algorithm satisfies the itu-t i.371 recommendation of 1%. it is important to note that since the limit field is a floating-point number, its maximum value exceeds the maximum tat (2147483647) value; therefore, l should not exceed this value. if the encoded value of l is greater than tat max , then l shall be taken to be tat max . thus, max tat l the value of t ? and the range of i and l determine the lowest pcr that can be policed, the pcr granularity supported at the highest expected pcr and the largest cdv expected. () t i pcr ? = max min 1 granularity as a fraction of pcr () t pcr ? = () t l ? = max max the maximum value for increment field supported in the s/uni-atlas-3200 is 2 28 ?1 = 268435455, therefore, the smallest peak (or sustainable) cell rate supported is pcr min = 0.465 cells/s as described previously, the limit field, l is a 14-bit floating point field, with l max = tat max = 2147483647. therefore, with an 8ns cycle time, cdv max = 17.18 s. note, the pcr (or scr) and cdv (or bt) can be changed while the connection is provisioned without disrupting the policing algorithm. that is, the increment and limit fields may be changed at any point, and the policing algorithm will immediately begin policing to the new settings. the action taken on a non-conforming cell is programmed on a per-connection basis by the action1[1:0] and action2[1:0] fields in row 0 of the vc table (action1 controls the action taken when a cell is non-conforming with gcra1, and action2 controls the action taken when a cell is non-conforming with gcra2).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 document id: pmc-1990553, issue 4 table 18 policing actions action1[1:0] and action2[1:0] definition 00 set the police status bit, but take no other action than to increment the appropriate non-compliant cell counts. 01 reduce the priority of high priority cells (i.e. tag clp=0 cells. increment the appropriate non-compliant cell counts. 10 reduce the priority of high priority cells and discard the low priority cells. increment the appropriate non-compliant cell counts. 11 discard all non-conforming cells. increment the appropriate non- compliant cell counts. policing can be effectively disabled for a connection if the increment fields (i1 and i2) are set to all zeros. the conditional conformance update (cocup) bit is used to introduce a coupling between the two gcras. if cocup=0, then gcra1 and gcra2 are completely independent of each other and the updating of the tat1 and tat2 fields are independent. if the cell is conforming to a gcra, the tat field for that gcra will be updated. the table below describes the behavior of the atlas: table 19 actions on policing with cocup=0 gcra2 fail gcra1 pass no action tag discard pass update tat1 update tat2 update tat1 update tat1 update tat1 no action update tat2 no update no update no update tag update tat2 no update no update no update fail discard update tat2 no update no update no update if cocup=1, then gcra1 and gcra2 are coupled and the updating of the tat1 and tat2 fields are conditional. the s/uni-atlas-3200 reacts as described in the table below.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 document id: pmc-1990553, issue 4 table 20 actions on policing with cocup=1 gcra2 fail gcra1 pass no action tag discard pass update tat1 update tat2 update tat1 update tat1 no update no action update tat2 no update no update no update tag update tat2 no update no update no update fail discard no update no update no update no update in both cases (cocup=1 and cocup=0), if a cell fails both gcra1 and gcra2, the most severe action is taken on the cell. the three 16-bit non-compliant counts are programmed in either the ncountx[3:0] or the gfr_ncountx[3:0] fields of the per-vc non-compliant cell counting configuration, depending on whether the gfr bit is set to logic 1 in the policing configuration field of the vc table. each non-compliant count has the following programming options: table 21 non-compliant cell count configurations ncountx[3:0] definition 0000 non-compliant clp=0 cells. 0001 non-compliant clp=0+1 cells. 0010 discarded clp=0 cells. 0011 discarded clp=0+1 cells. 0100 tagged clp=0 cells which are not discarded 0101 non-compliant clp=0 frames (gfr only) 0110 non-compliant clp=0+1 frames (gfr only) 0111 partially or completely discarded clp=0 frames (gfr only) 1000 partially or completely discarded clp=0+1 frames (gfr only) 1001 tagged clp=0 frames which are not discarded (gfr only) 1010 total clp=0 aal5 frames received 1011 total clp=0+1 aal5 frames received 1100 total cells non-compliant to gcra1 1101 total cells non-compliant to gcra2 1110 total cells non-compliant to the phy gcra 1111 reserved the total aal5 frames received counts are available in non-gfr connections, but the other frame-aware counts should not be selected except in the gfr case. counting of clp0 vs. clp 1 frames is based on the clp of the received eop. these non-compliant cell counts may, for instance, be programmed to satisfy the following requirements:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 document id: pmc-1990553, issue 4 ? non-compliant cell count1[15:0]: the number of clp0+1 cells discarded by the upc/npc function. gr-1248-core r9-6. ? non-compliant cell count2[15:0]: the number of clp0 cells discarded by the upc/npc function. gr-1248-core r9-7. ? non-compliant cell count3[15:0]: the number of clp0 cells tagged as clp1 cells by the upc/npc function. gr-1248-core co9-8. if the policing rollover fifo enable bit in the policing configuration field of the vc table is logic 1, then whenever the msb of any of the non-compliant counts is logic 1, an attempt is made to make an entry to the count rollover fifo. if the entry is made successfully, then the msb is set back to logic 0. otherwise, it remains 1 until an entry is sucessfully made. thus each count rollover entry represents 2 15 non-compliant count events. if the policing rollover fifo enable bit is logic 0, then the non-compliant counts will saturate at all 1?s. 10.7.2 per-phy policing the cell processor also maintains a single gcra instance per-phy (48 in total) in an internal ram which may be programmed via the phy policing address and access control register. the per-phy policing may be selectively enabled for any number of connections for a phy. the phy police bit in the policing configuration field of the vc table determines whether or not phy policing is active on that connection. the phyid[5:0] field in the vc linkage table determines which of the 48 internal policing instances is addressed if per-phy policing is active. the per-phy policing is evaluated alongside the per-connection policing. if a cell is discarded as a result of per-phy policing, the per-connection policing parameters are not updated. similarly, if a cell is discarded as a result of per-connection policing, the per-phy policing parameters are not updated. the table below describes the s/uni-atlas-3200 actions when per-phy policing is enabled. table 22 actions with per-phy policing per-phy gcra fail per-vc gcra (note, the per-vc gcras are evaluated as described in table 18, table 19, and table 20) pass no action tag discard pass update vc tat update phy tat update vc tat update vc tat no update no action update phy tat no update no update no update tag update phy tat no update no update no update fail discard no update no update no update no update the per-phy policing has a programmable action field and configurable register bits to police any combination of user cells, oam cells, rm cells, high priority cells and low priority cells. non-compliant cell counts are also maintained on a per-phy basis.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 document id: pmc-1990553, issue 4 it is the responsibility of the management entity to ensure the per-phy policing parameters are programmed correctly. all ram addresses can be written to and read by an external microprocessor. the internal per-phy policing ram is shown below table 23 internal per-phy policing ram address [1:0] 31 0 00 phytat lsb (32) 01 reserved (2) phy i (14) phy l (14) phytat msb (2) 10 phy non-compliant2 (16) phy non-compliant1 (16) 11 unused (10) phy policing rollver fifo en (1) phy vc count (1) phy police config. (2) phy action (2) phy non-compliant3 (16) the phy policing configuration[1:0] field (of the internal phy policing ram at addr[1:0] = 11) selects 1 of 4 settings (in the phy policing configuration register) in the cell processor which allows any combination of clp=0 or clp=1 user cells, segment oam cells, or rm cells to be policed by the phy gcra. when the phy policing rollover fifo en bit is logic 1, then when the msb of any of the non-compliant counts is set, an entry is generated into the count rollover fifo, and the msb is cleared. when the phy policing rollover fifo en bit is logic 0, no entries will be made due to per-phy non-compliant counts, and the counts will saturate at all-ones. the phy i (increment) and l (limit) fields are analogous to the per-vc increment and limit fields and are programmed in the same way. the phy action[1:0] field controls the programmable action to be taken on cells which are non-conforming to the phy gcra. note that tagging on a per-phy basis is incompatible with performing gfr policing on any of the connections on the phy. if gfr is to be supported, then either phy policing should be disabled for those vcs, or the per-phy policing action should be set to ?00? or ?11?.the phy action field is programmed as follows: table 24 per-phy policing actions phy action[1:0] description 00 set the police status bit, but take no other action than to increment the appropriate non-compliant cell counts. 01 reduce the priority of high priority cells (i.e. tag clp=0 cells. increment the appropriate non-compliant cell counts. this option is incompatible with gfr policing on any vcs on the phy. 10 reduce the priority of high priority cells and discard the low
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 document id: pmc-1990553, issue 4 phy action[1:0] description priority cells. increment the appropriate non-compliant cell counts. this option is incompatible with gfr policing on any vcs on the phy. 11 discard all non-conforming cells. increment the appropriate non-compliant cell counts. the phy non-compliant cell counts are programmed in the phyncountx[3:0] fields of the non-compliant cell counting register. each non-compliant cell count has the following programming options: table 25 per-phy policing non-compliant count options phyncountx[3:0] definition 0000 non-compliant clp=0 cells. 0001 non-compliant clp=0+1 cells. 0010 discarded clp=0 cells. 0011 discarded clp=0+1 cells. 0100 tagged clp=0 cells which are not discarded 0101 .. 1001 reserved 1010 total clp=0 aal5 frames received 1011 total clp=0+1 aal5 frames received 1100 total cells non-compliant to gcra1 1101 total cells non-compliant to gcra2 1110 total cells non-compliant to the phy gcra 1111 reserved the phyvccount bit determines whether cells which are non-compliant with the per-vc policer are counted in the per-phy non-compliant cell counts and vice versa (i.e. cells which are non- compliant with the per-phy policer are counted in the per-vc non-compliant cell counts). the table below describes the programming options. table 26 per-phy/per-vc non-compliant cell counting phyvccount=0 per-vc policing phyvccount=0 compliant non-compliant compliant no update. update per-vc non-compliant counts don?t update per-phy non- compliant counts. per-phy policing non-compliant don?t update per-vc non- compliant counts. update per-phy non- compliant counts update per-vc non-compliant counts. update per-phy non- compliant counts.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 document id: pmc-1990553, issue 4 table 27 per-phy and per-vc non-compliant cell counting phyvccount=1 per-vc policing phyvccount=1 compliant non-compliant compliant no update. update per-vc non-compliant counts update per-phy non- compliant counts. per-phy policing non-compliant update per-vc non-compliant counts. update per-phy non- compliant counts update per-vc non-compliant counts. update per-phy non- compliant counts. 10.7.3 guaranteed frame rate policing the s/uni-atlas-3200 supports guaranteed frame rate (gfr) policing in accordance with the atm forum traffic management specification 4.1. a total of four policing actions are observed for gfr policing. they are: maximum frame length (mfl) conformance test, peak cell rate (pcr) test, minimum cell rate (mcr) conformance test, and the clp conformance test. when gfr policing is enabled, the gfr policing algorithm is enabled. the conformance tests are evaluated sequentially, in the following order: 1. mfl conformance test. when an end of message cell in a packet is received, the remaining frame count field of the vc table is loaded, after testing for mfl conformance with the current value, with the value programmed in the maximum frame length field in the vc table. the remaining frame count is then decremented with each cell received in the new frame. if this value reaches zero before an end of message cell is received, the remainder of the frame is discarded (the eom cell is identified by having an sdutyp equal to logic 1). the mfl conformance test can be disabled by setting the mfl field in the vc table to all ones. 2. pcr conformance test. this test is performed using gcra1 in much the same manner as normal cell policing. however, for compliance to the gfr specification, action 1 must be set to 11 (discard). if the pcr conformance test is deemed to be non-compliant, the remainder of the cells in the current frame will be discarded. if the non-compliant cell is the start of packet, then a complete packet discard is executed; if it is in the middle of a packet, a partial packet discard is executed; if it is the end of a packet, it is discarded along with every subsequent cell until a eop is received which is not discarded.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 document id: pmc-1990553, issue 4 3. mcr conformance test. this test is performed using gcra2, however, it differs slightly from the normal cell policing. the mcr conformance test is only performed at the start of a frame. if the first cell of a frame is a conforming cell, then all remaining cells in that frame will be processed as if they are conforming to the mcr conformance test. if the first cell is non-conforming, then the action specified by action2[1:0] will be performed on the entire frame. normally, the mcr conformance test will be programmed to tag non-conforming clp=0 frames (action = 01, clp0 cells policed). if the first cell of a frame is a non- conforming clp=0 cell, then that cell and all other cells in that frame (including the eom) will be tagged. however, the mcr may be programmed to discard (action = 11), in which case a complete packet discard will be performed on frames whose first cell is non-compliant to mcr. in order to support aal5 frame-aware policing on connections that do not support full gfr, the gfr_mcr_ppd bit in the policing configuration register is provided. if this bit is a logic 1, then the mcr is permitted to perform ppd, if configured to discard; tagging will still be performed only on frame boundaries. 4. clp conformance test: this test is performed on every cell in a frame, including the eom. the clp conformance test can be enabled on a per-connection basis; this is controlled by the clpcc_clp1_discard bit of the policing configuration field in the vc table. if the start of frame is a clp = 1 cell, then any subsequent clp=0 cell will be tagged. if the first cell of the frame is a clp=0 cell, then if the clpcc_clp1_discard bit is logic 1, any subsequent clp=1 cell received in the frame will result in a partial packet discard being executed. the relevant gfr fields in the vc are described below: name description gfr if this bit is a logic 1, the s/uni-atlas-3200 will utilize gfr policing on the connection as described above. if this bit is logic 0, the connection will not use the gfr policing, rather it will use the normal cell-based policing described previously. gfr_mcr_ppd if this bit is logic 1, gfr policing is enabled and the mcr test is enabled to discard (i.e. action 2 = discard) then the policer will perform partial packet discard when a connection begins to fail mcr. if this bit is logic 0, then the mcr is only permitted to perform actions on frame boundaries, as per the gfr standard. clpcc_clp1_discard if the clp conformance check clp1 discard bit is set to logic 1, then during gfr policing, if a cell arrives with clp = 1 in a frame whose first cell had clp = 0, then the frame will undergo partial packet discard. if the clp=1 cell is the end of packet, then every cell until the next clp = 0 end of packet will be discarded. if this bit is logic 0, then clp = 1 cells in clp = 0 frames will not be treated as non-compliant. maximum frame length this field indicates the maximum permissible length of a frame for gfr connections. frames exceeding this length will undergo ppd. a maximum frame length of zero is invalid, and is treated as an mfl of 1. remaining frame count when an end of message cell in a packet is received, the remaining frame count field of the vc table is loaded, after testing for mfl conformance with the current value, with the value programmed in the maximum frame length field in the vc table. the remaining frame count is then decremented with each cell received in the new frame. if this value reaches zero before an end of message cell is received, the remainder of the frame is discarded (the eom cell is identified by having
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 document id: pmc-1990553, issue 4 name description an sdutyp equal to logic 1). the mfl conformance test can be disabled by setting the mfl field in the vc table to all ones. this field should be initialized to mfl ? 1. gfr state[2:0] the gfr state is an internally maintained state variable which must be programmed to 0 at connection startup and not changed thereafter. 10.8 cell counting the s/uni-atlas-3200 maintains counts on a per-connection basis, per-phy basis and over the aggregate cell stream. the following parameters are stored on a per-connection basis in the vc tables: ? two 32-bit ?billing? cell counts that may be programmed to count any combination of the following: a. clp0 user cells. b. clp1 user cells. c. clp0 oam cells. d. clp1 oam cells. e. clp0 rm cells. f. clp1 rm cells. g. clp0 cells with invalid vci/pti h. clp1 cells with invalid vci/pti. ? three non-compliant cell counts, which may count (non-compliant clp0 or clp0+1 cells, discarded clp0 or clp0+1 cells, tagged cells, total clp 0 or clp0+1 frames, non- compliant clp0 or clp1 frames, etc.) these counts are described in section 10.7, which covers policing. ? per-phy counts of clp0, clp1, valid oam, valid rm, invalid oam/rm, congested (efci or gfc), timed-out, and bad vpi/vci/pti cells. the two programmable 32-bit cell counts represent the state of the cells before policing. the non-compliant cell counts can be used to derive the cell counts after policing. the programmability of the two 32-bit cell counts allows the ability to provision scheduled measurements and special studies on each connection. when aggregating or terminating a vpc, the vpc oam connection?s 32-bit billing counts are updated based on the total traffic arriving on the vpc. that is, all cells arriving on associated vccs are counted as user cells in the vpc oam connection. this permits aggregate counts to be generated with little microprocessor effort. if performance management is activated, a range of forward monitoring and backward reporting statistics are stored. these statistics are described in section 10.14 which covers performance management.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 can be configured to have some of its counters roll over or saturate at all ones. all per-phy counts, the per-connection cell counts, non-compliant cell counts, and the pm counts are configurable in this manner. the rollover_fifo_en bit in the configuration field of the vc table controls whether the 32-bit per-vc cell counts saturate, or whether they generate count rollover fifo entries when their msb is logic 1, and then reset their msbs to 0. the policing rollover fifo en bit in the policing configuration field performs this function for the non-compliant counts; the phy policing rollover_fifo_en bit in the phy policing ram performs the same function for the per-phy non-compliant counts, as does the phy rollover_fifo_en bit in the per-phy counter configuration register for the other per-phy counts. the pm_rollover_fifo_en bit in the pm configuration field of the internal pm table controls whether the performance management counts generate count rollover fifo entries. the count rollover fifo is described in section 10.16. all per-phy and per-vc counts have a clear on read option. if this bit is logic 1, then when the microprocessor reads the counter value, the value is immediately set to zero. if the per-phy or per-vc clear on read register bit is logic 0, the counter value is not cleared when it is read, and the value must be cleared by explicitly writing all zeros to that counter location. in order to allow for a time-of-day billing mechanism, the s/uni-atlas-3200 provides alternate count fields for the general 32-bit counts. when the alternate_count bit in the cell processor configuration register is set to logic 1, the 32-bit cell counts in all vcs stop incrementing, and the alternate counts are incremented instead. the cell counts may then be read at leisure by the microprocessor. when the alternate_count bit is set to logic 0 again, the counting reverts to the regular 32-bit counts, and the alternate counts may be read (and presumably cleared) at leisure by the microprocessor. one of the objectives of counting is to count, somewhere, every cell that arrives. almost all cells can be counted in the per-vc cell counts. however, cells that do not belong to any particular connection (i.e. they do not search to a valid, active connection) cannot be counted per-vc. these cells have their own per-phy count, the invalid vpi/vci/pti cell count. the only overlap between this count and the per-vc counts is for cells with a reserved vci or pti. the cnt_rsvd_vci_pti bit in the per-phy count configuration register controls whether cells with reserved vci or pti are counted in the invalid vpi/vci/pti cell count. 10.9 operations, administration and maintenance (oam) cell servicing the s/uni-atlas-3200 is capable of terminating and monitoring f4 and f5 segment and end- to-end oam flows. complete processing of fault management cells is provided on all connections. performance management is provided on a limited number of connections (512 simultaneous sessions in each direction are supported). activate/deactivate and undefined oam cells are passed to the microprocessor cell interface or to the output cell interface for external processing. loopback cells are examined, and routed based on their loopback indication, loopback location id, and source id.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 document id: pmc-1990553, issue 4 the programming of the configuration and oam configuration field in the vc table determines how the s/uni-atlas-3200 will behave with respect to a particular connection. upon receipt of an oam cell, the crc-10 is checked. if the check sum is incorrect, the oam cell is not processed (i.e. alarms and counts are not updated) and the per-phy errored oam cell count is incremented. if crc10toup is set in the cell processor routing configuration register, bad-crc oam cells will be routed to the microprocessor cell interface. otherwise, further processing is dependent upon the contents of the oam type field and the programming of the s/uni-atlas-3200 for that connection. if a connection is not provisioned as an end point (segment end-point or end-to-end point), all incoming oam cells (other than certain loopback cells) are passed to the output cell interface (subject to policing, if so configured), regardless of whether or not the oam type or function type fields have defined values. as an option, oam cells may be discarded at non-flow end points if the crc-10 is incorrect. at flow end points, all oam cells are terminated, except activate/deactivate and undefined oam cells which may, optionally, be routed to the ocif for external processing. 10.9.1 fault management cells fault management cells are identified with an oam cell type field of 0001. the s/uni- atlas-3200 supports segment and end-to-end ais, rdi, continuity check (cc) and loopback cells. segment and end-to-end ais alarm status bits in the status field are set upon receipt of a single ais (function type = 0000) cell (segment or end-to-end). if the connection fm_interrupt_enable bit is set, a globally maskable interrupt will be asserted at the change of state of the (segment or end-to-end) ais alarm. the alarm status is cleared upon receipt of a single user or cc cell, or if no ais cell has been received within the last 2.5 +/- 0.5 sec. if the auto_rdi vc table bit is set, an rdi cell (segment or end-to-end) is generated immediately upon receipt of the first ais cell at a flow end point and once a second thereafter until the ais state is exited. the s/uni- atlas-3200 generates rdi cells for insertion in the reverse flow and sends them to the companion chip through the backward cell interface. in addition, the s/uni-atlas-3200 will insert any rdi cells it receives over the backward cell interface into the cell stream it sources. when the s/uni-atlas-3200 receives a segment or end-to-end ais cell, the defect location and defect type fields of the ais cell are copied into the vc table. these fields are used when rdi cells are generated at segment or end-to-end points as a result of the auto_rdi process. segment and end-to-end rdi alarm status bits are set upon receipt of a single rdi (function type = 0001) cell (segment or end-to-end). the defect location and type fields will be copied into the vc table for subsequent retrieval, so long as ais alarm is not declared. while it is not reasonable to expect the reception of both ais and rdi of the same type (i.e. both segment or both end-to- end), if this occurs the ais defect location will be given priority for storage, so that it can be used in the generation of rdi cells. if the connection fm_interrupt_enable bit is set, a globally maskable interrupt will be asserted at the change of state of the (segment or end-to-end) rdi alarm. the alarm status is cleared if no rdi cell has been received within the last 2.5 +/- 0.5 sec.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 document id: pmc-1990553, issue 4 if the cc_activate_segment bit is a logic 1, and no user cells have been transmitted within a 1.0 second (nominal) window, a segment cc cell is generated and sent to the output cell interface. the forced generation of cc cells (independent of the flow of user cells) at one second (nominal) intervals is enabled when the cc_activate_segment bit is logic 1 and the forcecc register bit is logic 1. if the forcecc register bit is logic 0, then the generation of cc cells is dependent on the flow of user cells. regardless of the state of the cc_activate_segment bit, if no user cells or segment cc cells have been received within a 3.5 +/- 0.5 sec window, the cc_alarm_segment status bit is set. if the connection fm_interrupt_enable bit is set, a globally maskable interrupt will be asserted at the change of state of the segment cc alarm. the segment cc alarm is cleared upon the reception of the first user or segment cc cell. if the s/uni-atlas-3200 is configured as a segment end-point, and the auto_rdi and cc_ais_rdi bits of the oam configuration field is set, a segment rdi cell is generated once per second into the reverse direction while the segment cc alarm is declared. in addition, if the auto_ais bit is logic 1, then an ete ais cell is generated once per second while segment cc alarm is declared. if the s/uni-atlas-3200 is not configured as a segment end point, then if the segment_flow bit is logic 1, the auto_ais register bit is set, and the cc_ais_rdi bit is set in the oam configuration field of the vc table, a segment ais cell is generated once per second while segment cc alarm is declared and segment ais alarm is not declared. when ais cells are generated by the s/uni-atlas-3200 due to the auto_ais function, the per-phy ais generation bits, or the per-vc send_ais bits, the generated_defect_type[7:0] field in the vc table is used for the defect type, and the defect location register fields are used for the defect location. when f5 ais cells are generated due to f4 ais, the defect location and type of the f4 ais cell that caused the alarm are sent. similarly, when f4 ete ais cells are sent as a result of reception of segment ais cells (via the apsx function) the defect location and type of the received segment ais cell is used. for each segment oam capability described above, the same capability exists for the end-to- end. the s/uni-atlas-3200 also supports the generation of f5 ais and rdi cells when associated f4 connections, which are terminated, enter the ais alarm state. this is described in detail in section 10.10. the s/uni-atlas-3200 may be configured on a per-phy basis to output ais or rdi cells (or both) on all connections whose phyid matches those set in a programmable register. the per- phy rdi cell generation control and per-phy ais cell generation control registers control the generation of rdi and ais cells on entire phys at once. when the phy ais bits are set, end- to-end cells (and, if segment_flow is logic 1, segment ais cells) are sent once per second, except at flow end points. when the phy rdi bits are set, rdi cells will be sent once per second in the reverse flow direction on all connections which are segment or end-to-end points. in the case of a segment end point, one segment rdi and one end-to-end ais cell will be sent per second, if both the phy ais and phy rdi bits are set.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 document id: pmc-1990553, issue 4 10.9.2 loopback cells the s/uni-atlas-3200 provides support for generating returned loopback cells via the bcifs. generation of parent loopback cells is left up to the microprocessor. if enabled, loopback cells will have their loopback indication and loopback location id examined. cells with loopback indication = 0 will be dropped and routed to the microprocessor cell interface at flow end-points, and at intermediate points whose loopback location id register matches the source id field of the loopback cell. for cells with loopback indication = 1, segment loopback cells will be dropped and looped back if their loopback location id matches the loopback location id register, and looped back but not dropped if their loopback location id is all-zeroes. both segment and end-to-end cells will be dropped and looped back at flow end points if their loopback location id is all-ones. in any event, loopback cells are always dropped at flow end points. cells which are looped back always have their loopback indication bit set to 0, and their loopback location id replaced with the contents of the loopback location id register. alternately, loopback cells may also be routed to the microprocessor for external processing. 10.9.3 activation/deactivation cells activation/deactivation cells are identified with an oam cell type of 1000. they are used by the management entity to implement the handshaking required to initiate or cease the performance management or continuity check processes. the s/uni-atlas-3200 does not process these cells. if this s/uni-atlas-3200 is not an end- point for an oam flow, all activate/deactivate cells are passed to the output cell interface. if the s/uni-atlas-3200 is an oam flow end-point, the activate/deactivate cells are optionally passed to the microprocessor cell interface or to the output cell interface. the flow of activate/deactivate cells is controlled by the actdetoup, actdetobcif and actdetoocif register bits. 10.9.4 system management cells system management cells are identified with an oam cell type of 1111. their use is largely for security puposes, and is under consideration by the itu. the s/uni-atlas-3200 does not process these cells. if the s/uni-atlas-3200 is not a flow end-point for an oam flow, all system management cells are passed to the output cell interface. if the s/uni-atlas-3200 is an oam flow end-point, the system management cells are optionally passed to the microprocessor cell interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 document id: pmc-1990553, issue 4 10.9.5 automated protection switching cells aps coordination protocol cells are identified with an oam cell type of 0101. they are handled like other oam cells, and can be copied to the mcif via the apstoup bit in the configuration field of the vc table, or to the bcif via the combination of the per-vc apstoup bit and the apstobcif bit in the routing configuration register. they are identified by a code in the cell type field of the microprocessor cell info field and the bcif cell info field. aps cp cells may be passed on to the ocif at oam end-points by setting the apstoocif bit to logic 1 in the routing configuration register. 10.9.6 resource management cells resource management (rm) cells are identified by a pti=110 for vc-rm cells and by vci=6 for vp-rm cells. as a programmable option, vp-rm cells can be further qualified by pti=110. the s/uni-atlas-3200 does not process the rm cell payload, but simply passes these cells to the output cell interface with an optionally translated header. as a programmable option, the s/uni-atlas-3200 can copy rm cells to the microprocessor cell interface. 10.10 f4 to f5 oam processing the s/uni-atlas-3200 supports the termination of f4 (vpcs) to f5 (vccs) while maintaining the f4 to f5 transmission of oam cells. each vcc of a vpc must be setup as a separate connection in the vc table. an additional connection must be set up for the f4 oam flow. the search table must be set up so that both segment oam cells (vci=3) and end-to-end oam cells (vci=4) of the vpc resolve to this f4 oam connection, but the vci field in its vc table must be set to all-zeroes to indicate that it is to be handled like an f4 connection. the f4 oam connection may be set up as both a segment and end-to-end point, or as an end-to-end-point only. the vcc connections have a vpc pointer [16:0] and a vpc pointer active bit in the linkage table. the pointer must be configured to point to the f4 oam connection. note that the two least significant bits of the vpc pointer (i.e. the vcra of the f4 oam connection) must be different from the two lsbs of any of its associated vcc connections. failure to adhere to this rule will result in all the vcc connections being treated as inactive until the problem is resolved. if the vpc pointer of a connection is not used, then the vpc pointer active bit must be set to logic 0. if a segment or end-to-end ais alarm condition is indicated on the vpc connection, a background process ensures that vcc ais cells will be transmitted on all vccs associated with that vpc, while the vpc is in ais alarm condition. the continuity check process is also active at the f4 and f5 levels. when a user cell or cc cell is received on a vcc, the vpc connection is updated to ensure it does not enter the cc alarm state. the figure below illustrates how the s/uni-atlas-3200 supports oam flows when terminating vpc connections. note that each vcc connection has its vpc pointer pointing to the f4 oam connection. the f4 oam connection?s vpc pointer active bit must be set to logic 0, and its vpc pointer field is not used.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 document id: pmc-1990553, issue 4 figure 14 f4 to f5 oam flows vcc 1 vpc vcc 2 vcc n vc table entries vcc 1 vcc 2 vcc n f4 oam connection the following f4 to f5 fault management scenarios are supported by the s/uni-atlas-3200. figure 15 termination of f4 segment and end-to-end-point connection connection end-point (end-to-end point) segment end-point f4 (vpc) vcc1 vcc2 vcc3 vcc4 vpc-ais-ete vpc-rdi-ete vcc-ais-ete (connection not within a defined segment) vcc-rdi-seg vcc-rdi-ete vcc5 vcc-rdi-seg vcc-rdi-ete vcc-ais-ete vcc-ais-ete(connection within a defined segment) vcc-ais-seg (connection within a defined segment) in figure 15 above, a vpc flow is being terminated. the vpc flow is both a segment end-point, and a connection (end-to-end) point. in the search table both the segment and end-to-end connections would resolve to a single f4 oam connection. five vccs are being switched out from the vpc connection (all five vccs would be setup as separate connections). in the event that an end-to-end vpc-ais cell is received on end-to-end vpc connection, an end-to-end vpc- rdi cell would be generated (if the auto_rdi bit is logic 1 in the vc table). the end-to-end vpc-rdi cell would carry the end-to-end ais defect location and defect type fields. the response of the switched vccs is as follows:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 document id: pmc-1990553, issue 4 vcc1 belongs to a segment flow, therefore, both end-to-end and segment vcc-ais cells are generated within 0.5 seconds of noticing that the end-to-end vpc connection is in ais alarm. vcc1 will continue to generate ete and segment vcc-ais cells at a rate of one per second (nominally) while the vpc connection is in ais alarm (i.e the ais_end_to_end alarm bit is asserted for the end-to-end vpc connection). vcc2 does not belong to a segment flow, therefore, an end-to-end vcc-ais cell is generated within 0.5 seconds of noticing that the vpc connection is in end-to-end ais alarm. vcc2 will continue to generate end-to-end vcc-ais cells at a rate of one per second (nominally) while the vpc connection is in ais alarm (i.e. the ais_end_to_end alarm bit is asserted for the vpc connection). vcc3 is a segment end-point, therefore a segment vcc-rdi cell (assuming the auto_rdi bit is logic 1 in the vc table) and an end-to-end vcc-ais cell are generated for this connection within 0.5 seconds of noticing that the vpc connection is in end-to-end ais alarm. vcc3 will continue to generate segment vcc-rdi and end-to-end vcc ais cells at a rate of one per second (nominally) while the vpc connection is in end-to-end ais alarm (i.e. the ais_end_to_end alarm bit is asserted for the vpc connection). vcc4 is a connection end-point, therefore an end-to-end vcc-rdi cell is generated (assuming the auto_rdi bit is logic 1 in the vc table) within 0.5 seconds of noticing that the vpc connection is in end-to-end ais alarm. vcc4 will continue to generate end-to-end vcc-rdi cells at a rate of one per second (nominally) while the vpc connection is in end-to-end ais alarm (i.e the ais_end_to_end alarm bit is asserted for the vpc connection). vcc5 is a segment end-point and a connection end-point, therefore a segment vcc-rdi cell and an end-to-end vcc-rdi cell are generated (assuming the auto_rdi bit is logic 1 in the vc table) within 0.5 seconds of noticing that the vpc connection is in end-to-end ais alarm. vcc5 will continue to generate segment vcc-rdi and end-to-end vcc-rdi cells at a rate of one per second (nominally) while the vpc connection is in end-to-end ais alarm (i.e. the ais_end_to_end alarm bit is set). the next scenario has the same connection configurations, however, a vpc-segment ais cell is received.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 document id: pmc-1990553, issue 4 figure 16 termination of f4 segment and end-to-end point connection connection end-point (end-to-end point) segment end-point f4 (vpc) vcc1 vcc2 vcc3 vcc4 vpc-ais-seg vpc-rdi-seg vcc-ais-ete (connection not within a defined segment) vcc-rdi-seg vcc-rdi-ete vcc5 vcc-rdi-seg vcc-rdi-ete vcc-ais-ete vcc-ais-ete (connection within a defined segment) vcc-ais-seg (connection within a defined segment) in figure 16 above, a vpc flow is being terminated. the vpc flow is both a segment end-point, and a connection (end-to-end) point. in the s/uni-atlas-3200 search table, both the segment and end-to-end connections would resolve to a single f4 oam connection. five vccs are being switched out from the vpc connection (all five vccs would be setup as separate connections). in this scenario, a segment vpc-ais cell is received on the vpc connection. a segment vpc- rdi cell would be generated (if the auto_rdi bit is logic 1 in the vc table) and sent to the backwards cell interface. the segment vpc-rdi cell would carry the segment defect location and segment defect type information. the response of the switched vccs is as follows: vcc1 belongs to a segment flow, therefore, a both a segment and an end-to-end vcc-ais cell are generated within 0.5 seconds of noticing that the vpc connection is in segment ais alarm. vcc1 will continue to generate segment and ete vcc-ais cells at a rate of one per second (nominally) while the vpc connection is in ais alarm (i.e the ais_segment alarm bit is asserted for the vpc connection). vcc2 does not belong to a segment flow, therefore, an end-to-end vcc-ais cell is generated within 0.5 seconds of noticing that the vpc connection is in segment ais alarm. vcc2 will continue to generate end-to-end vcc-ais cells at a rate of one per second (nominally) while the vpc connection is in ais alarm (i.e. the ais_segment alarm bit is asserted for the vpc connection). vcc3 is a segment end-point, therefore a segment vcc-rdi assuming the auto_rdi bit is logic 1 in the vc table) and an end-to-end vcc-ais cell are generated for this connection within 0.5 seconds of noticing that the vpc connection is in segment ais alarm. vcc3 will continue to generate segment vcc-rdi and end-to-end vcc ais cells at a rate of one per second (nominally) while the vpc connection is in segment ais alarm (i.e. the ais_segment_alarm bit is asserted for the vpc connection).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 document id: pmc-1990553, issue 4 vcc4 is a connection end-point, therefore an end-to-end vcc-rdi cell is generated (assuming the auto_rdi bit is logic 1 in the vc table) within 0.5 seconds of noticing that the vpc connection is in segment ais alarm. vcc4 will continue to generate end-to-end vcc-rdi cells at a rate of one per second (nominally) while the vpc connection is in segment ais alarm (i.e the ais_segment alarm bit is asserted for the vpc connection). vcc5 is a segment end-point and a connection end-point, therefore a segment vcc-rdi cell and an end-to-end vcc-rdi cell are generated (assuming the auto_rdi bit is logic 1 in the vc table) within 0.5 seconds of noticing that the vpc connection is in segment ais alarm. vcc5 will continue to generate segment vcc-rdi and end-to-end vcc-rdi cells at a rate of one per second (nominally) while the vpc connection is in segment ais alarm (i.e. the ais_segment_alarm bit is set). figure 17 termination of f4 segment end-point connection f4 (vpc) vpc-ais-seg vpc-rdi-seg vpc-ais-ete (only generated if aps is not available) figure 17 above illustrates the scenario where a vpc segment is being terminated at the s/uni- atlas-3200. in this case, because only a segment end-point is defined, it is assumed that the vccs are not switched out of the vpc (because the vpc end-to-end point is not provisioned). to enable this scenario, the vpc pointer active bit would be set to logic 0 in the linkage table entry, and the connection would be configured as a segment end-point. a segment vpc-ais cell is received and terminated. within 0.5 seconds of receiving the segment vpc-ais cell, a segment vpc-rdi cell is generated (assuming the auto_rdi bit is logic 1 in the vc table). as a programmable option, an end-to-end vpc-ais can be generated if end-to-end ais is not already being received. this per-phy configurable option would normally only be enabled if aps is not available. the apsx register bit (where x is 0-47) determines whether or not phyx has protection switching available. if the apsx register bit is logic 0, an end-to-end vpc-ais cell will be generated within 0.5 seconds of entering the vpc segment ais alarm condition and once per second (nominally) thereafter until the vpc segment ais alarm condition is exited.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 document id: pmc-1990553, issue 4 figure 18 termination of f4 end-to-end point connection connection end-point (end-to-end point) segment end-point f4 (vpc) vcc1 vcc2 vcc3 vcc4 vpc-ais-ete vpc-rdi-ete vcc-ais-ete (connection not within a defined segment) vcc-rdi-seg vcc-rdi-ete vcc5 vcc-rdi-seg vcc-rdi-ete vcc-ais-ete vcc-ais-ete (connection within a defined segment) vcc-ais-seg (connection within a defined segment) figure 18 above illustrates the scenario where a vpc is being terminated at an end-to-end point at the s/uni-atlas-3200. in this scenario, the vpc connection is configured as an end-to-end point and has its vpc pointer active bit set to logic 0. if an end-to-end vpc-ais cell is received, it is terminated and an end-to-end vpc rdi cell is generated within 0.5 seconds (assuming the auto_rdi bit is logic 1 in the vc table). the response of the switched vccs is as follows: vcc1 is belongs to a segment flow, therefore both segment and ete vcc-ais cells are generated within 0.5 seconds of noticing that the vpc connection is in ais alarm, and once per second (nominally) thereafter until the vpc connection exits the ais alarm state. vcc2 belongs to an end-to-end flow, therefore an end-to-end vcc-ais cell is generated within 0.5 seconds of noticing that the vpc connection is in ais alarm, and once per second (nominally) thereafter until the vpc connection exits the ais alarm state. vcc3 is a segment end-point, therefore a segment vcc-rdi cell and an end-to-end vcc-ais cell are generated within 0.5 seconds of noticing that the vpc connection is in ais alarm (assuming the auto_rdi bit is logic 1 in the vc table), and once per second (nominally) thereafter until the vpc connection exits the ais alarm state. vcc4 is an end-to-end point, therefore an end-to-end vcc-rdi cell is generated within 0.5 seconds of noticing that the vpc connection is in ais alarm (assuming the auto_rdi bit is logic 1 in the vc table), and once per second (nominally) thereafter until the vpc connection exits the ais alarm state. vcc5 is a segment end-point and an end-to-end point, therefore, a segment vcc-rdi and an end-to-end vcc-rdi cell are generated within 0.5 seconds of noticing that the vpc connection is in ais (assuming the auto_rdi bit is logic 1 in the vc table), and once per second (nominally) thereafter until the vpc connection exits the ais alarm state.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 document id: pmc-1990553, issue 4 note, in the unlikely event that a segment vpc-ais cell is received on the end-to-end vpc connection, no action would be taken at the f5 level. this is because the vpc connection is only configured as an end-to-end point and no segment oam cells should be received. the end-to- end vpc connection would only terminate the segment vpc-ais cell and no further action would be taken at the f4 level. the table below summarizes the behavior of the s/uni-atlas-3200 for f4 to f5 fault management: table 28 f4 to f5 fault management processing actions taken by s/uni- atlas-3200 upon receipt of f4 ais cells vc non end-point vp termination type received cell at f4 level vc connection end-point vc segment end-point vc connection end-point and segment end- point within a vc segment not within a vc segment generate vc end-to-end rdi (4) generate vc segment rdi (1), (4) generate vc end-to-end ais (2), (4) generate vc end-to-end rdi (4) generate vc segment rdi (1), (4) generate vc segment ais (3), (4) generate vc end-to-end ais (4) generate vc end-to-end ais (4) vp end-to- end ais generate vp end-to-end rdi cell on the end-to-end f4 connection. generate vc end-to-end rdi (5), (4) generate vc segment rdi (4) generate vc end-to-end ais (4), (6) generate vc end-to-end rdi (4) (5) generate vc segment rdi (4) generate vc segment ais (3), (4) generate vc end-to-end ais (4), (6) generate vc end-to-end ais (4), (6) vp connection end-point and segment end-point vp segment ais generate vp segment rdi cell on the segment f4 connection. generate vc end-to-end rdi (4) generate vc segment rdi (1), (4) generate vc end-to-end ais (2), (4) generate vc end-to-end rdi (4) generate vc segment rdi (1), (4) generate vc segment ais (3), (4) generate vc end-to-end ais (4) generate vc end-to-end ais (4) vp connection end-point only vp end-to- end ais generate vp end-to-end rdi cell on the end-to-end f4 connection. vp segment ais no action is taken. no action is taken. no action is taken. no action is taken. no action is taken. no action is taken. this represents an unusual case where an f4 segment ais cell is received on a f4 connection end-point. the segment ais cell will be terminated at the vp connection end-point, but no other action is taken.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 document id: pmc-1990553, issue 4 vp end-to- end ais no cells are generated. the vp end-to-end ais cell is passed through. we are assuming that vcs are not switched if the f4 is a segment end-point only. vp segment end-point only vp segment ais generate vpc segment rdi. generate vpc end-to-end ais cell if aps is not available (and end-to-end vp-ais cells are not being received). vp end-to- end ais vp non- end point vp segment ais no cells are generated. the received cells are passed through transparently. we are asssuming that, if a vp connection is a non-end point, then any vccs pointing to that connection are being aggregated into it rather than switched out. this feature is controlled by the f4eaisf5srdi register bit. when this bit is logic 1, a segment vc-rdi cell will be generated when an end-to-end vpc-ais cell is terminated at a vpc end-to- end point, and an associated vcc segment end-point is switched from that vpc. if this bit is logic 0, a segment vc-rdi cell will not be generated in this circumstance. this feature is controlled by the f4eaisf5eais register bit. when this bit is logic 1, an end-to- end vc-ais cell will be generated when an end-to-end vpc-ais cell is terminated at a vpc end- to-end point, and an associated vcc segment end-point is switched from that vpc. if this bit is logic 0, an end-to-end vc-ais cell will not be generated in this circumstance. this feature is controlled by the segmentflow bit in the table oam configuration field of the vc table. if this bit is logic 1, the vcc is considered to be part of a segment flow, and a segment vc-ais cell will be generated when an end-to-end vp-ais cell is terminated at a vpc end-to-end point. this feature is controlled by the f4tof5oam bit in the oam configuration field of the vc table. if this bit is logic 1, the f4 to f5 fault management scenarios are enabled. if this bit is logic 0, no f5 fault management cells will be generated as a result of the reception of f4 fault management cells. however, the continuity check process will still be active on the f4 and f5 levels if the vpc pointer fields are correctly setup. this feature is controlled by the f4saisf5erdi register bit. when this bit is 1, an end-to-end vc-rdi cell will be generated when a segment vpc-ais cell is terminated at a vpc segment end-point, and the vcc is also an end-to-end point. if this bit is logic 0, an end-to-end vc-rdi cell will not be generated in this circumstance. this feature is controlled by the f4saisf5eais register bit. when this bit is logic 1, an end-to- end vc-ais cell will be generated when a segment vpc-ais cell is terminated at a vpc segment end-point. note, the vcc connection is not part of a segment flow (segmentflow=0). if this bit is logic 0, an end-to-end vc-ais cell will not be generated in this circumstance. this feature is controlled on a per-phy basis by the apsx register bit (where x is from 0-47). when the apsx register bit is logic 0, it indicates there is no automatic protection switching on phy x . when a vpc connection is configured as a segment end-point only and a segment vpc- ais cell is received, an end-to-end vpc-ais cell is generated immediately, and once per second (nominally) thereafter. when the apsx register bit is logic 1, an end-to-end vpc-ais cell is not generated in this circumstance. no end-to-end ais will be generated if the connection is already receiving end-to-end ais.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 document id: pmc-1990553, issue 4 when an ais or rdi cell is generated due to cc_ais_rdi, per-phy rdi, send_rdi/ais_end_to_end, or send_rdi/ais_segment, the ais/rdi will contain the defect type programmed into the oam configuration field of the vc table, and the local defect location programmed in the defect location register. when an ais or rdi is generated due to reception of an ais cell, the generated cell will contain the ais defect location and ais defect type fields which are stored in the vc table of the connection which received the ais. for instance, an f5 ete rdi generated as the result of receiving an f4 segment ais would use the segment defect location and type stored for the f4 connection. if an f4 connection enters the ais alarm condition (segment or end-to-end), the associated f5 connections will not declare ais themselves (i.e. the ais_end_to_end alarm and/or the ais_segment alarm bit will not be asserted on the f5 connection). the f5 connections will, however, most likely be in the cc_alarm condition (both segment and end-to-end), because any cell that would clear the cc alarm in the f5 connections would also clear ais alarm in the f4. 10.11 f5 to f4 oam processing the s/uni-atlas-3200 also supports the aggregation of f5 connections into f4 connections. the vcs must be set up in much the same way, with one vc for each vcc, and another vc for the f4 oam connection. however, the oam connection will not be an end point, and the only oam functions performed by the f4 are the sourcing of end-to-end and segment cc cells. the f4 oam connection must still have a valid search onto which cells with vci = 3 or vci=4 terminate, as loopback, rdi, and bwd pm cells from the bcif must search correctly onto the connection (if search_from_bcif is logic 1). the f4 continuity check process in the aggregated f4 is aware of oam and other cells generated on the component f5 flows, and correctly counts them as user cells. f4 forward pm flows may be generated by associating many f5 connections with a single f4 forward pm session. this pm connection will treat all f5 cells (other than, optionally, rm cells) as f4 user cells and will include them in the generated pm counts. 10.12 constraints on f5 and f4 vc table record addresses the vc table record address is a 16 bit number identifying an f5 or f4 flow. this number corresponds to a data structure in the internal dram. each vc table record is stored in one of the 4 banks in the internal dram. the bank in which a record is stored is identified by the least significant two bits of the vc record. thus each record is stored in either bank 0 (vcra[15:0] = xxxxxxxxxxxxxx00), bank 1 (vcra = xxxxxxxxxxxxxx01), bank 2 (vcra[15:0] = xxxxxxxxxxxxxx10) or bank 3 (vcra = xxxxxxxxxxxxxx11).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 document id: pmc-1990553, issue 4 it is required that the records of an f5 flow and its enclosing f4 flow be in different banks. the constituent f5s need not be in the same bank, so long as they are not in the same bank as the f4 connection. if this rule is violated, then all the constituent f5s will be treated as inactive connections. if the inactivetoup bit is logic 1 in the cell processor routing configuration register, then cells will be routed to the microprocessor, permitting this condition to be detected and corrected. 10.13 background processes the s/uni-atlas-3200 performs numerous background processes to perform correct and compliant oam-fault management cell generation, and alarm monitoring as well as maintaining the per-connection and per-phy tat policing parameters. the background processes are triggered either by the internally generated 0.5 second clock event, or by the external 0.5 second clock input pin. each cell processor maintains 4 background processes. they are: ? rdi cell generation. ? ais/cc cell generation. ? tat updating. ? cc, rdi and ais change of state and alarm monitoring. the vc table maximum index register controls the maximum 17-bit vc table address which must be monitored by the various background processes. the rdi cell generation process is controlled by the status of the backward cell interface to which the process must send generated rdi cells. if this fifo is filled, no rdi cells will be generated, and the rdi background process will pause until room becomes available. this ensures that no rdi cells will be lost due to overflow of the backward cell interface. the ais/cc cell generation process is controlled by the status of the output cell interface, and by a programmable threshold that determines the maximum rate at which ais/cc cells can be generated. if an ais or cc cell is generated, the process will be suspended until the expiry of a user programmable counter threshold. however, ais cells will only be generated on phys that have room in the output cell interface to take them. connections which, after a timeout period, still cannot insert an ais cell due to a full output cell interface queue will be skipped, to ensure that other connections are not denied the ability to send ais cells. if a phy has cells destined for it, but its output cell interface fifo is full, and the phy does not accept any cells whatsoever for a programmable number of cell periods (the inoperative phy declaration period register, which defaults to 256 cell periods) then the phy will be declared inoperative, an optional interrupt will be asserted, and any subsequent generated cells destined for that phy (cc, ais, rdi, loopback, bwd pm and fwd pm) will be immediately discarded to prevent them from slowing the generation of cells to the remaining phys. the phy queue will be declared operative again as soon as it accepts a single cell from s/uni-atlas-3200.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 document id: pmc-1990553, issue 4 the tat updating process ensures the policing theoretical-arrival-times track the free running time-of-arrival counter of the atlas.-3200 this ensures that connections which have a long gap between inter-cell arrivals are never mistakenly policed due to a roll over of the free running time-of-arrival counter. the cc, rdi and ais change of state and alarm monitoring process is controlled by the fill status of the change of state fifo. if the change of state fifo is not used, then this process is not throttled by the fifo fill status. if the fifo is used, then notification of changes of state in cc, rdi and ais alarms will be suspended until the fifo is not full. this ensures the management software never misses any change of connection status. the excessive policing status bit is also part of the change of state fifo. it is the responsibility of the management software to ensure the fifo is read often enough so that the alarm declarations remain compliant with bellcore gr-1248-core and itu-t i.610. background processes have scheduled processing time available for execution regardless of the cell data rate. 10.14 performance management 10.14.1 performance management flows the s/uni-atlas-3200 supports a highly configurable internal pm statistics ram. the vc linkage table is used to index two internal pm ram locations. each pointer can access up to 256 unique pm ram locations. these two pointers can be used to perform simultaneous sinking and sourcing of a pm flow, simultaneous f4 and f5 pm flows, etc. the pm pointers are located in the vc linkage table in external sram, and the fields are as follows: table 29 linkage table fields used in pm 63 0 1 phyid (6) 2 reserved (16) pm 2 active (1) 1 pm 2 address (8) pm 1 active (1) 1 pm 1 address (8) vpc pointer active (1) 2 vpc pointer (16) table 30 pm activation fields name description pm active2 indicates the pm session pointed to by pm addr2[7:0] is active. pm active1 indicates the pm session pointed to by pm addr1[7:0] is active. pm addr2[7:0] indicates which internal pm ram address in bank 2 is to be used for a pm session. bank 1 and bank 2 are completely separate. many connections may point to the same pm session; for instance, if an vpc was being split out to its component vccs, each vcc table entry, as well as the f4 oam table entry, might point to a single f4 pm sink session. the same strategy would work for the aggregation of vccs into a vpc. pm addr1[7:0] indicates which internal pm ram address in bank 1 is to be used for a pm session. bank 1 and bank 2 are completely separate. many connections may point to the same pm session; for instance, if an vpc was being split out to its component vccs, each vcc table entry, as well as the f4 oam table entry, might point to a single f4 pm sink session. the same strategy would work for the aggregation of vccs into a vpc.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 document id: pmc-1990553, issue 4 these pm connections may be configured to be sinks, sources or monitoring points of f4 or f5 segment or end-to-end pm flows. the figure below illustrates the pm flow capability of the s/uni-atlas-3200. figure 19 pm flows ingress s/uni-atlas-3200 egress s/uni-atlas-3200 fwd monitoring pm cell (1) backwards reporting pm cell (2) generated fwd monitoring pm cell (2) generated bwd reporting pm cell (1) generated fwd monitoring pm cell (3) bwd reporting pm cell (3) fwd monitoring pm cell (4) generated bwd reporting pm cell (4) the figure above illustrates two unique bi-directional pm flows. in the first pm flow, indicated by (1), the ingress s/uni-atlas-3200 is terminating a forward monitoring pm cell and it generates a backward reporting pm cell through the backward cell interface and the egress s/uni-atlas-3200 . this is one half of the bi-directional pm flow. the second half of the bi- directional flow is indicated by (2). here, the egress s/uni-atlas-3200 is generating a forward monitoring pm cell . another downstream entity (e.g. another atlas device) would terminate that forward monitoring cell and transmit a backward reporting pm cell. this backward reporting pm cell is received at the ingress s/uni-atlas-3200 and terminated. to enable this pm session, the termination of the forward monitoring pm cell (1) and the statistics collected from the termination of the backwards reporting pm cell (2) would be maintained by the ingress s/uni-atlas-3200 processor in one ram location. the generation of the forward monitoring pm cell (2) would be maintained by the egress s/uni-atlas-3200 in one ram location.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 document id: pmc-1990553, issue 4 the tags (3) and (4) indicate the second bi-directional pm flow. at the ingress s/uni-atlas- 3200, the cell processor generates a forward monitoring cell that is transmitted to the output cell interface (and into the switch fabric). a downstream device (e.g. another atlas device) would terminate the forward monitoring pm cell and generate a backward reporting pm cell. this backward reporting pm cell is received at the egress s/uni-atlas-3200 and terminated in its cell processor. this is the first half of the bi-directional flow, indicated by (3). the second half of the bi-directional flow is indicated by (4). here, the egress s/uni-atlas-3200 terminates a forward monitoring pm cell. the egress s/uni-atlas-3200 then generates a corresponding backward reporting pm cell which is transmitted to the ingress s/uni-atlas- 3200 through the backward cell interface and back into the switch core. the generation of the forward monitoring pm cell (4) would be maintained by the ingress s/uni-atlas-3200 in one ram location. the termination of the forward monitoring pm cell (4) and the statistics collected from the termination of the backwards reporting pm cell (3) would be maintained by the egress s/uni-atlas-3200 in one ram location. the above discussion is just one example of the pm flow capability of the s/uni-atlas-3200. each of the pm flows can be configured as a monitoring point in which pm cells are neither generated nor terminated (note, however, pm cells will be terminated at oam flow end points), but merely monitored and their statistics maintained. the s/uni-atlas-3200 can also be configured to monitor/sink/source an f4 pm flow. each f5 connection that is a member of an f4 vpc flow must have one common pm address for the f4 flow. all user cells (at the f4 level) will be considered to be part of the f4 pm flow, and thus counted as such. a pair of s/uni-atlas-3200s can also be configured to perform bi-directional pm on a segment connection and an end-to-end connection (simultaneously) for up to 256 bidirectional connections simultaneously. for each connection in each s/uni-atlas-3200, one pm address in the vc linkage table would be used to point to the pm ram location for the end-to-end pm flow, and the other address would be used to point to the pm ram location for the segment pm flow. the backwards cell interfaces of the two devices permit backwards pm cells to be inserted into the opposite direction. the insertion of forward monitoring pm cells is controlled by the paced forward pm cell generation registers. these registers provide a counter to set the number of cell intervals (defined as 22 sysclk clock cycles) between successive forward monitoring pm cells. this prevents the s/uni-atlas-3200 from generating forward monitoring pm cells back-to-back. each time a forward monitoring pm cell is generated, a counter is loaded with the value set in the paced fwd pm cell generation register, and that register is decremented at intervals of 32 clock cycles. another forward monitoring cell will not be generated until the counter reaches 0. the position of the upc/npc policing needs to be clearly defined. if the s/uni-atlas-3200 is a sink of forward monitoring pm cells, or a monitoring point, the counts maintained in the pm ram represent the state of the device before the upc/npc function. if the s/uni-atlas-3200 is a source of forward monitoring pm cells, the counts maintained in the pm ram represent the state of the device after the upc/npc function.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 document id: pmc-1990553, issue 4 10.14.2 performance management record table the oam-pm statistics are collected in an on-chip ram accessible through the microprocessor port. table 31 performance management record table pm addr [2:0] 79 0 000 pm configuration & status (16) bip-16 (16) current count clp0 (16) current count clp0+1 (16) bler stored (8) fwd bmcsn (8) 001 fwd trcc0 (16) fwd trcc0+1 (16) fwd tuc0 (16) fwd tuc0+1 (16) fwd fmcsn (8) unused (8) 010 bwd trcc0 (16) bwd trcc0+1 (16) bwd tuc0 (16) bwd tuc0+1 (16) bwd fmcsn (8) bwd bmcsn (8) 011 fwd errors (8) fwd impaired (8) fwd lost/mis impaired (8) fwd secb errored (8) fwd secb lost (8) fwd secb misins (8) fwd secbc (8) fwd lost fwd pm cells (8) fwd tagged clp0 (16) 100 fwd misinserted (16) fwd lost clp0 (16) fwd lost clp0+1 (16) fwd total lost clp0 (16) fwd total lost clp0+1 (16) 101 bwd errors (8) bwd impaired (8) bwd lost/mis impaired (8) bwd secb errored (8) bwd secb lost (8) bwd secb misins (8) bwd secbc (8) bwd secbc accum. (8) bwd tagged clp0 (16) 110 bwd misinserted (16) bwd lost clp0 (16) bwd lost clp0+1 (16) bwd total lost clp0 (16) bwd total lost clp0+1 (16) 111 transmitted clp0 count (32) transmitted clp0+1 count (32) bwd lost fwd pm cells (8) bwd lost bwd pm cells (8) the configuration field of the internal pm table is shown below:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 document id: pmc-1990553, issue 4 table 32 pm table configuration field bit name description 15 source_fwdpm if this bit is a logic 1, the pm session is configured to source a pm flow, and a forward monitoring cell is output from the s/uni-atlas-3200 once per block of user cells (nominally). received forward monitoring and backwards reporting cells will not be processed by this pm session. if the session is an f4 session, then any generated f5 fwd pm cells, ais cells, or cc cells will be included in the user cell flow. if the source_fwdpm bit is a logic 0, then the pm session is configured to process received forward monitoring and backwards reporting cells. termination of pm cells depends only on whether the s/uni-atlas- 3200 is configured as an end-to-end or segment end point. 14 generate_bwdpm if this bit is a logic 1 and the source_fwdpm bit is a logic 0, a backward reporting pm cell is generated when an appropriate forward monitoring pm cell is received. the f4_f5b and ete_segb bits determine the type of forward monitoring cells that are processed, and thus the type of backward reporting cell that is generated. if the fwd_pm0 bit is a logic 1, then a backward reporting cell will not be generated (the fwd_pm0 bit is cleared upon receipt of the first forward monitoring pm cell). 13 f4_f5b if this bit is a logic 1, this pm address is for a f4 (vpc) pm flow. f5 cells, including oam cells, are user cells as far as this flow is concerned. if this bit is a logic 0, the pm address is for a f5 (vcc) pm flow. f4 oam cells are ignored. 12 ete_segb if this bit is a logic 1, this pm address is for an end-to-end pm flow. segment pm cells are ignored. if this bit is a logic 0, this pm address is for a segment pm flow. end-to- end pm cells are ignored. despite the setting of this bit, f5 oam cells are treated as user cells if the f4_f5b bit is logic 1. 11 force_fwdpm this bit controls the forced insertion of a forward monitoring pm cell when the s/uni-atlas-3200 is configured to insert forward monitoring pm cells. when the force_fwdpm bit is logic 1, the s/uni-atlas- 3200 will force the insertion of a forward monitoring pm cell when the current cell count of clp0+1 cells reaches n+n/2, where n is the programmed block size, regardless of the state of the forward pm pacing register. if this bit is logic 0, then the s/uni-atlas-3200 will not insert a forward monitoring pm cell unless the forward pm pacing register allows for a pm cell to be inserted. this bit has no effect when source_fwdpm is logic 0. [10:9] threshold_select[1:0] these bits are used to index one of four possible threshold selection register pairs (pm threshold a1/a2 through pm threshold d1/d2) which hold the threshold values for errored, misinserted and lost severely errored cell blocks.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 document id: pmc-1990553, issue 4 bit name description [8:5] blocksize[3:0] the block size of pm cells selects the nominal block of user cells as follows: 0000 128 cells 0001 256 cells 0010 512 cells 0011 1024 cells 0100 2048 cells 0101 4096 cells 0110 8192 cells 0111 16384 cells 1000 32768 cells 1001-1111 reserved. 4 clp0_secbs_only when this bit is a logic 1, then secbs will not be declared due to lost cells whose clp = 1. this setting may be used to accommodate connections on which there is no service guaranteee for clp = 1 cells. 3 pm_rollover_fifo_e n if this bit is logic 0, none of the pm counts will generate entries into the count rollover fifo. if this bit is logic 1 then the performance monitoring counts will generate entries into the count rollover fifo. counts that are designed to roll over in normal operation (the contents of rows 0,1, and 2, plus the secbc counts) do not generate count rollover fifo entries. a bit in the cell processor configuration register (sat_fast_pm_counts) controls whether the four counts that can increment very quickly (bip16 errors, and the counts of lost pm cells) are excluded from generating count rollover fifo entries. when a counter is enabled for making entries into the cro fifo it will do so whenever its msb becomes logic 1, and it will then reset the msb to logic 0. if the count rollover fifo is full, the msb will remain set until such time as it can make an entry in the fifo. the counts continue counting until they saturate. 2 reserved this bit is used for internal purposes, and must be programmed to logic 0 at startup, and must not be altered by the microprocessor thereafter, for proper operation. 1 fwd_pm0 if source_fwdpm is a logic 0, the fwd_pm0 bit must be set to a logic 1 initially. this bit is cleared upon receiving the first forward monitoring cell, along with the current cell count, bip-16, and the entire contents of rows 3 and 4. the fwd_pm0 bit is used to denote the arrival of the first forward monitoring cell. the fwd_pm0 bit suppresses accumulation of the forward error counts. if this bit is not set, error counts will be accumulated. if source_fwdpm is a logic 1, then if this bit is set to a logic 1 initially, rows 1 and 7 will be cleared at the end of the first block of user cells. initializing row 0 is the responsibility of the management software during setup. 0 bwd_pm0 the bwd_pm0 bit must be set to a logic 1 initially. this bit is cleared upon receiving the first backward reporting cell. at that time, the contents of rows 5, 6, and 7 are cleared (except for the bwd secbc count which is copied from the backward reporting cell) and row 2 is initialized with values copied from the backward reporting cell.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 document id: pmc-1990553, issue 4 the qos parameters of the internal pm table are described below. n.b. tucd0 and tucd0+1 (which are referred to in this table) are internally computed values in accordance with bellcore gr-1248-core, itu-t i.610 and itu-t i.356. tucd is the difference between the number of cells transmitted in the block (as indicated in the fwd pm cell) and the number received. for example, tucd0 = {[tuc0(t) ? tuc0(t-1)] mod 64k} - {[trcc0(t) ? trcc0(t-1)] mod 64k}. table 33 qos parameters for performance management name description bip16 (16) when this pm instance is the source of forward monitoring cells, the bit-interleaved parity 16 is the even parity error detection code computed over the information field of the block of user data cells (clp0+1) transmitted after the last forward monitoring pm cell. when this pm instance terminates or monitors forward monitoring cells, bip-16 is the even parity error detection code computed over the information field of user data cells received after the last forward monitoring pm cell. current cell count clp0 (16) when this pm process is the source of forward monitoring cells, this count is incremented each time a clp0 user cell is transmitted. it is used along with the fwd tuc_0 field to determine the tuc_0 field of newly generated forward pm cells. when this pm process terminates/monitors forward monitoring cells, this count is incremented each time a clp0 user cell is received. it is used along with fwd trcc_0 to determine the new trcc_0 upon reception of a forward pm cell, and thus to calculate the total user cell difference clp0. current cell count clp0+1 (16) when this pm process is the source of forward monitoring cells, this count is incremented each time a user cell is transmitted. whenever this count equals or exceeds the programmed pm block size, a request to generate a forward pm cell will be made, subject to cell slot availability and pacing. it is also used along with the fwd tuc_0+1 field to determine the tuc_0+1 field of newly generated forward pm cells. when this pm process terminates/monitors forward monitoring cells, this count is incremented each time a user cell is received. it is used along with fwd trcc_0+1 to determine the new trcc_0+1 upon reception of a forward pm cell, and thus to calculate the total user cell difference clp0+1. bler stored (8) the stored block error result is the block error result calculated on reception of the previous forward pm cell. it is stored in this field until it can be used by the generated backwards reporting cell. fwd trcc_0 (16) total received cell count clp0. this field is used when terminating/ monitoring forward pm cells, and stores a running count modulo 65536 of the total number of received clp0 user cells previous to the most recent forward monitoring cell. fwd trcc_0 is inserted in the trcc_0 field of the generated backwards reporting cell. it is also used along with the current cell count clp0 to determine the new trcc_0 upon reception of a forward pm cell. fwd trcc_0+1 (16) total received cell count clp0+1. this field is used when terminating/ monitoring forward pm cells, and stores a running count modulo 65536 of the total number of received user cells previous to the most recent forward monitoring cell. fwd trcc_0+1 is inserted in the trcc_0+1 field of the generated backwards reporting cell. it is also used along with the current cell count clp0+1 to determine the new trcc_0+1 upon reception of a forward pm cell.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 document id: pmc-1990553, issue 4 name description fwd tuc_0 (16) total clp0 user cells for forward monitoring pm cells. tuc_0 indicates the number modulo 65536 of clp 0 user cells transmitted just before the transmission of a forward pm cell. if this pm process is the source of forward pm cells then this field stores the value of tuc_0 inserted into the most recent generated forward pm cell, and is used together with the current cell count clp0 to determine tuc_0 of the subsequent generated pm cell. this is a running count and does not need to be initialized. if this pm process terminates/monitors forward pm cells, then this field stores the value of tuc_0 received from the most recent forward pm cell, and is used with the received pm cell?s tuc_0 to determine the number of clp0 user cells transmitted between successive forward pm cells. this count will be initialized automatically on reception of the first forward monitoring cell. when not a monitor point, fwd tuc_0 will be inserted in the tuc_0 field of generated backwards reporting cells. fwd tuc_0+1 (16) total clp0+1 user cells. tuc_0+1 indicates the total number modulo 65536 of clp0 and clp1 user cells transmitted just before the transmission of a forward pm cell. if this pm process is the source of forward pm cells then this field stores the value of tuc_0+1 inserted into the most recent generated forward pm cell, and is used together with the current cell count clp0+1 to determine tuc_0+1 of the subsequent generated pm cell. this is a running count and does not need to be initialized. if this pm process terminates/monitors forward pm cells, then this field stores the value of tuc_0+1 received from the most recent forward pm cell, and is used with the received pm cell?s tuc_0+1 to determine the number of user cells transmitted between successive forward pm cells. this count will be initialized automatically on reception of the first forward monitoring cell. when not a monitor point, fwd tuc_0+1 will be inserted in the tuc_0+1 field of generated backwards reporting cells. fwd fmcsn the forward pm cell sequence number. this field contains the sequence number modulo 256 of the most recent forward monitoring cell generated/received. the mcsn is incremented for each pm cell generated/received during the pm session. when forward pm cells are terminated or monitored, the fwd mcsn is used to identify lost forward pm cells. if the fwd fmcsn is out of sequence, then bip-16 calculations are not done, the bit error code is sent as all-ones in the backwards reporting cell, and the fwd lost fwd pm cells counter is incremented by the number of lost fwd pm cells. the calculation and reporting of lost, misinserted, and tagged cells, impaired blocks, and secbs proceeds as normal. any inference of secbs due to lost fwd pm cells is left up to the management software. fwd bmcsn the forward bwd pm monitoring cell sequence number is used to determine the mcsn for generated backwards reporting cells. the fwd bmcsn value is incremented each time a backwards routing cell is generated. there is no need to initialize this running count. bwd trcc_0 (16) total received cell count clp0 for backwards reporting cells. this field stores the trcc_0 value received from the most recent backwards reporting cell, and is used along with the trcc_0 field of newly received backwards reporting cells to determine the number of clp0 user cells received by the far end point between successive forwards monitoring cells. this count will be initialized automatically on reception of the first bwd pm cell.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 document id: pmc-1990553, issue 4 name description bwd trcc_0+1 (16) total received clp0+1 user cell count for backwards reporting cells. this field stores the trcc_0+1 value received from the most recent backwards reporting cell, and is used along with the trcc_0+1 field of newly received backwards reporting cells to determine the number of user cells received by the far end point between successive forwards monitoring cells. this count will be initialized automatically on reception of the first bwd pm cell. bwd tuc_0 (16) total clp0 user cell count for backwards reporting pm cells. this field stores the value of tuc_0 received from the most recent backwards reporting cell, and is used with a newly received bwd pm cell?s tuc_0 to determine the number of cells transmitted by the forward monitoring source point between successive forward pm cells. this count will be initialized automatically on reception of the first bwd pm cell. bwd tuc_0+1 (16) total clp0+1 user cell count for backwards reporting pm cells. this field stores the value of tuc_0+1 received from the most recent backwards reporting cell, and is used with a newly received bwd pm cell?s tuc_0+1 to determine the number of cells transmitted by the forward monitoring source point between successive forward pm cells. this count will be initialized automatically on reception of the first bwd pm cell. bwd fmcsn (8) this field contains the fwd mcsn copied from the most recently received backwards reporting cell. it is used to infer the loss of forward monitoring cells at the far end point. if the bwd fmcsn is out of sequence, then the bwd lost fwd pm cells count is incremented by the number of lost fwd pm cells, which is presumed to be equal to the change in fmcsn less the change in bmcsn. any inference of secbs due to lost fwd pm cells is left up to the management software. bwd bmcsn (8) this field contains the mcsn copied from the most recently received backwards reporting cell. it is used to infer the loss of backwards reporting cells. if the received backwards reporting mcsn is out of sequence, then the bwd lost bwd pm cells count will be incremented by the number of missed mcsns. all other processing will proceed as normal. fwd errored cell count (8) bwd errored cell count (8) the errored cell count represents the number of bip-16 violations (bipv) during a pm session (on clp0+1 cells). the errored cell counter is incremented whenever the number of bipv is greater than 0 and less than merror in the selected threshold register, so long as there are no lost or misinserted cells, and the mcsns are in sequence. fwd impaired blocks (8) bwd impaired blocks (8) the impaired block count represents the sum of pm cell blocks containing at least one bip error, lost cell or misinserted cell (clp0+1 fwd lost/ misinserted impaired blocks (8) bwd lost/ misinserted impaired blocks (8) the lost/misinserted impaired block count represents the sum of the pm cell blocks for which there was at least one lost or misinserted cell (clp0+1). the lost/misinserted block impaired block count is incremented whenever there is a non-zero tucd_0+1. fwd secb errored (8) bwd secb errored (8) severely errored cell block errored cells (clp0+1). the secb errored is incremented whenever the number of bipv errors exceeds merror in the selected threshold register, and there are no lost/misinserted cells, and the mcsns are in sequence. the accumulation of secb errored inhibits the accumulation of the count of bip errors.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 document id: pmc-1990553, issue 4 name description fwd secb lost (8) bwd secb lost (8) severely errored cell block lost cells. when clp0_secbs_only is a logic 0, the secb lost is incremented whenever the number of lost clp0+1 cells exceeds mlost in the selected threshold register. when clp0_secbs_only is a logic 1, secb lost is incremented whenever the number of lost plus tagged clp0 cells exceeds mlost. the accumulation of secb lost inhibits the accumulation of the count of lost clp0 and lost clp0+1 cells. fwd secb misinserted (8) bwd secb misinserted(8) severely errored cell block misinserted cells (clp0+1). the secb misinserted is incremented whenever the number of misinserted cells exceeds mmisins in the selected threshold register. the accumulation of secb misinserted inhibits the accumulation of the count of misinserted cells. fwd secbc (8) forward severely errored cell blocks combined. this running counter increments each time a secb is declared. this value is inserted into the secbc field of generated backwards reporting cells. bwd secbc (8) backward severely errored cell blocks combined. this value is copied from the secbc field of received backwards reporting cells, and represents a rolling modulo-256 count of all severely errored cell blocks. there is no need to initialize this running counter. bwd secbc accum. (8) backward accumulating secbc count. whenever a received bwd pm cell has a secbc field different from the stored bwd secbc, this field is incremented by the modulo-256 difference. this is a saturating counter that initializes itself when the first bwd pm cell is received. fwd lost fwd pm cells (8) the fwd lost fwd pm cells count uses the mcsn of received forward monitoring cells to determine the number of lost fwd pm cells. whenever the mcsn of a received fwd pm cell is out of sequence, this count is incremented by the difference between the expected and received mcsn, and bip-16 calculations are suppressed. fwd tagged clp0 cells (16) bwd tagged clp0 cells (16) whenever there are less clp0 cells received than were transmitted (tucd is negative) then those cells have either been lost or tagged. the inference is made that if clp0 cells were lost, then they should be lost from the clp0+1 stream as well. thus when tucd0 < 0, the lost clp0 cells count is incremented by the lesser of ?tucd0 and -tucd0+1, and the tagged clp0 cell count is incremented by (- tucd0) ? (-tucd0+1), so long as the result is positive. this count is not incremented if the secb lost or secb misins count is incremented. fwd lost clp0 (16) bwd lost clp0 (16) the lost clp0 cell count represents the total number of lost clp0 user cells during a pm session. the lost clp0 cell count is incremented by the lesser of - tucd_0 and ?tucd_0+1, whenever that number is greater than zero. this count is not incremented if the secb lost count is incremented. fwd lost clp0+1 (16) bwd lost clp0+1 (16) the lost clp0+1 cell count represents the total number of lost clp0+1 user cells during a pm session. the lost clp0+1 cell count is incremented by the number of lost clp0+1 cells, whenever tucd_0+1 < 0 . this counter will not increment is the secb lost counter increments (it is therefore sensitive to clp0_secbs_only). fwd misinserted cells (16) bwd misinserted cells (16) the misinserted cell count represents the total number of misinserted clp0+1 user cells during a pm session. the misinserted cell count is incremented by the number of misinserted clp0+1 cells, whenever mmisins tucd_0+1 > 0. (i.e. this count is not incremented if the secb misinserted count is incremented). fwd total lost clp0+1 (16) bwd total lost clp0+1 (16) the total lost clp0+1 cell count represents the total number of lost clp0+1 user data cells during a pm session. this count is not dependent on a threshold. that is, the total lost clp0+1 cell count is always incremented by the number of lost clp0+1 user cells.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 document id: pmc-1990553, issue 4 name description fwd total lost clp0 (16) bwd total lost clp0 (16) the total lost clp0 cell count represents the total number of lost clp0 user data cells during a pm session. this count is not dependent on a threshold. that is, the total lost clp0 cell count is always incremented by the number of lost clp0 user cells. transmitted clp0+1 user cells (32) the transmitted clp0+1 user cell count represents the number of user cells that are originated on a monitored connection by the transmitting end point. if the pm session is configured to source fwd pm cells, then this count is derived from the number of user cells transmitted. if the pm session is configured to monitor or terminate pm flows, then this count is derived from the difference of the tuc 0+1 fields of successive backward reporting cells. transmitted clp0 user cells (32) the transmitted clp0+1 user cell count represents the number of clp0 user cells that are originated on a monitored connection by the transmitting end point. if the pm session is configured to source fwd pm cells, then this count is derived from the number of clp0 user cells transmitted. if the pm session is configured to monitor or terminate pm flows, then this count is derived from the difference of the tuc0 fields of successive backward reporting cells. bwd lost bwd pm cells (8) if the mcsn of a received bwdpm cell is out of sequence, then this count will be incremented by the difference between the expected mcsn and the received mcsn. bwd lost fwd pm cells (8) the bwd lost fwd pm cells count represents the number of forward monitoring cells lost in transit to the far end point. this calculation is performed based on the fwd mcsn field of arriving backwards reporting cells. whenever the fmcsn field of the bwd pm cell is out of sequence, this count is incremented by the difference between the received and expected mcsn. however, if the bwd pm cell?s own mcsn is also out of sequence, this count will increment by the number of apparently lost fwd pm cells minus the number of lost bwd pm cells. pm cell format as defined by itu-t i.610 header fields 5x8 oam cell type (= 0010) 4 oam function type 4 performance management function specific fields 45x8 reserved 6 edc (crc-10) 10 the performance management function specific fields are listed below: fwd = forward monitoring pm cell field bwd = backward reporting pm cell field fwd + bwd fwd + bwd fwd fwd + bwd fwd bwd bwd bwd bwd bwd mcsn (8) tuc_0+1 (16) bedc_0+1 (16) tuc_0 (16) time stamp (32) unused 6ah (27 octets) fwd mcsn (8) secbc (8) trcc_0 (16) block error result (8) trcc_0+1 (16)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 provides only minimal support for the time stamp field option in pm cells. the default value of all ones is inserted in the time stamp field for all generated fwd pm cells. bwd pm cells may contain the time stamp in the received fwd pm cell if the bcif is not full when the fwd pm cell arrives, and the copy_fwpm_timestamp bit is logic 1 in the cell processor configuration register. 10.15 change of connection state fifo as a configurable option, the s/uni-atlas-3200 maintains a fifo that monitors all connections for changes of state (i.e. continuity check alarm, ais alarm, rdi alarm, oam failure, and dram crc error). if a connection has a change of state at some time (e.g. due to the receipt of an ais cell, or due to loss of continuity), a copy of the status field and the 17-bit connection address will be written into the fifo. a maskable interrupt for the fifo is provided to notify when valid data is in the fifo, when it is at least half full, and when it is full. if the fifo becomes full, a background process which checks for changes of state will be suspended. the process will remain suspended until such time as data have been read out of the fifo . it is the responsibility of the management software to ensure the fifo is polled often enough to ensure the monitoring of changes of state remain compliant to the gr-1248- core bellcore and itu-t i.610 standards. table 34 change of state fifo each fifo is 256 entries deep, and the contents of the fifo are shown below: bit name description 31:29 reserved 28 segment end point if this bit is logic 1, the connection is a segment end-point. 27 end-to-end point if this bit is logic 1, the connection is an end-to-end point. 26 segment flow if this bit is logic 1, the connection is part of a defined segment flow. 25 dram crc err if this bit is logic 1, then this vc table entry suffered an error in the dram, and may need to be reinitialized. 24 oam failure this bit becomes a logic 1 if a segment or end-to-end rdi, ais or cc condition has persisted for 3.5 0.5 seconds. oam_failure is cleared as soon as no rdi, ais or cc condition remains. 23 ais end to end alarm this bit becomes a logic 1 upon receipt of a single end-to-end ais cell. the alarm status is cleared upon the receipt of a single user cell or end-to-end cc cell, or if no end-to-end ais cell has been received within the last 2.5 0.5 sec. 22 ais segment alarm this bit becomes a logic 1 upon receipt of a single segment ais cell. the alarm status is cleared upon the receipt of a single user cell or segment cc cell, or if no segment ais cell has been received within the last 2.5 0.5 sec. this bit will only be asserted by connections which have the segment end point or segment flow bits set to logic 1.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 document id: pmc-1990553, issue 4 bit name description 21 rdi end to end alarm this bit becomes a logic 1 upon receipt of a single end-to-end rdi cell. this bit is cleared if no end-to-end rdi cell has been received within the last 2.5 0.5 sec. 20 rdi segment alarm this bit becomes a logic 1 upon receipt of a single segment rdi cell. this bit is cleared if no segment rdi cell has been received within the latest 2.5 0.5 sec. 19 cc end to end alarm this bit becomes a logic 1 if no user cell or end-to-end cc cell has been received within the last 3.5 0.5 sec. this bit is cleared upon receipt of a user cell, or end-to-end cc cell. 18 cc segment alarm this bit becomes a logic 1 if no user or segment cc cell has been received within the last 3.5 0.5 sec. this bit is cleared upon receipt of a user cell or segment cc cell. segment cc alarms are declared only if the vc is part of a segment flow (segment_flow = 1) or is a segment end point (segment_end_point = 1) 17 reserved this bit is reserved and should be masked off. 16 reserved this bit is reserved and should be masked off. [15:0] connection address this field contains the 16-bit connection address with which the change of state is associated. the fifo contents may be read through the microprocessor port. the microprocessor may read the cos fifo, and when the cosvalid bit is asserted, the contents of the cos fifo are valid. the fifo read-pointer is incremented when the change of connection state data register is read (assuming the fifo is not empty). when the change of connection state data register is read, the cos fifo busy bit is asserted. at this time, the state of the cosvalid bit is undefined. the busy bit will be deasserted 3-5 sysclk cycles after the change of connection state data register is read. at this time, the cosvalid bit will be defined and will indicate whether subsequent reads are appropriate. 10.16 count rollover fifo in order to eliminate the need for the microprocessor to periodically poll counts to prevent them from rolling over or saturating, the s/uni-atlas-3200 provides a 256-entry count rollover fifo accessible via the microprocessor port. when the count rollover fifo enable bit is set in the cell processor configuration register, then the various per-vc, per-phy, and performance management counts may be configured to generate count rollover entries. an entry is made to the count rollover fifo every time at least one of these counts has its msb set. once an entry has been made to the fifo, the msb for that count is cleared. thus every entry indicates that 2 15 (for a 16-bit count) or 2 31 (for a 32-bit count) events have occurred. if the count rollover fifo becomes full, the msb remains set until there is room in the count rollover fifo again. the counter continues to operate normally until it reaches an all-ones state, at which time it saturates. so long as the count rollover fifo is cleared out before another 2 15 (or 2 31 ) events can occur, no events will be lost. one exception is provided for pm counts. because the 8-bit counts of bip-16 errors and lost fwd and bwd pm cells may roll over frequently, they may be disabled from generating fifo entries by setting the sat_fast_pm counts bit to logic 1 in the cell processor configuration register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 document id: pmc-1990553, issue 4 the intention is that the microprocessor use these rollover entries to maintain the most-significant bits of the counters in its own memory. the least-significant bits can be accessed by the microprocessor in the normal way whenever precise counts are needed. maskable interrupts are provided when the rollover fifo is not empty, when it is half full, and when it is nearly full. there are four possible sources of rollover fifo entries: per-vc counts, per-phy counts, pm session 2, or pm session 1. the source of the entry determines its format, and is determined by the setting of bits 30:29 of the entry. the most significant bit of the source field is reserved for future use. each source has an associated rollover fifo enable bit to control whether entries are permitted from that source. per-vc counts include the 32-bit general cell counts and the 16-bit policing non-compliant counts. the format of a per-vc rollover fifo entry is as follows: table 35 count rollover fifo format for per-vc count entries bit field description 31 reserved 30:29 source ?00? for a per-vc count entry 28 reserved 27:12 address the 16-bit vc record address that generated this entry 11:7 unused 6 non-compliant 3 when ?1?, policing non-compliant count 3 had its msb set. 5 non-compliant 2 when ?1?, policing non-compliant count 2 had its msb set. 4 non-compliant 1 when ?1?, policing non-compliant count 1 had its msb set. 3 alternate count2 when ?1?, per-vc alternate count 2 had its msb set 2 alternate count1 when ?1?, per-vc alternate count 1 had its msb set 1 count2 when ?1?, per-vc count 2 had its msb set 0 count1 when ?1?, per-vc count 1 had its msb set per-phy counts include per-phy policing counts and the per-phy counts of received clp0 cells, clp1 cells, etc. the format of a per-phy rollover fifo entry is as follows: table 36 count rollover fifo format for per-phy count entries bit field description 31 reserved 30:29 source ?01? for a per-phy count entry 28:23 phy address the 6-bit phy address that generated this entry 22:11 unused 10 timeout when ?1?, the msb of the timed-out cell count was set. 9 efci_nzgfc when ?1?, the msb of the efci/non-zero gfc cell count was set. 8 invalid vpi_vci_pti when ?1?, the phy invalid vpi/vci/pti (search error, unprovisioned or inactive connection, or reserved vci/pti) count had its msb set. 7 bad oam_rm when ?1?, the phy errored rm/oam cells count had its msb set.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 document id: pmc-1990553, issue 4 bit field description 6 rm when ?1?, the phy valid rm cells count had its msb set. 5 oam when ?1?, the phy valid oam cells count had its msb set. 4 clp1 when ?1?, the phy clp1 cells count had its msb set. 3 clp0 when ?1?, the phy clp0 cells count had its msb set. 2 phy non- compliant 3 when ?1?, phy policing non-compliant count 3 had its msb set. 1 phy non- compliant 2 when ?1?, phy policing non-compliant count 2 had its msb set. 0 phy non- compliant 1 when ?1?, phy policing non-compliant count 1 had its msb set. pm counts include forward lost clp0 cells, backward lost clp0+1 cells, etc. table 37 count rollover fifo format for pm entries bit field description 31 reserved 30:29 source ?010? for a pm count entry from pm bank 0, ?011? for a pm count entry from pm bank 1 28:21 pm address the 8-bit pm session address that generated this entry 20 pm direction when pm direction is ?1?, the counts indicated refer to forward counts accumulated by the transmission or reception of fwd pm cells. when pm direction is ?0?, the counts indicated refer to backward counts accumulated by the reception of bwd pm cells. 19 pm source when pm source is logic 1, then the pm session is a pm flow source point, and only the transmitted clp0 and transmitted clp0+1 count indications are valid. 18:17 reserved 16 fwd/bwd errors when ?1?, the fwd or bwd errored cell count had its msb set, depending on the setting of the pm direction bit. because this count may roll over quite frequently, there is a register bit, sat_fast_pm_counts, which forces this error count to saturate, and not generate count rollover fifo entries. 15 fwd/bwd impaired when ?1?, the fwd or bwd impaired block count had its msb set, depending on the setting of the pm direction bit. 14 fwd/bwd lost/misins impaired when ?1?, the fwd or bwd impaired blocks due to lost or misinserted cells count had its msb set, depending on the setting of the pm direction bit. 13 fwd/bwd secb errored when ?1?, the fwd or bwd severely errored cell block due to bip-16 errors count had its msb set, depending on the setting of the pm direction bit. 12 fwd/bwd secb lost when ?1?, the fwd or bwd severely errored cell block due to lost cells count had its msb set, depending on the setting of the pm direction bit. 11 fwd/bwd secb misinserted when ?1?, the fwd or bwd severely errored cell block due to misinserted cells count had its msb set, depending on the setting of the pm direction bit.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 document id: pmc-1990553, issue 4 bit field description 10 bwd secbc (accumulated) when ?1?, the accumulating bwd severly errored cell block combined count had its msb set. this indicator is not used if pm direction is ?1?. 9 fwd/bwd lost fwd pm cells when ?1?, the fwd or bwd lost fwd pm cells count had its msb set, depending on the setting of the pm direction bit. because this count may roll over quite frequently, there is a register bit, sat_fast_pm_counts, which forces this error count to saturate, and not generate count rollover fifo entries. 8 bwd lost bwd pm cells when ?1?, the bwd lost backward pm cells count had its msb set. this indicator is not used if pm direction is ?1?. because this count may roll over quite frequently, there is a register bit, sat_fast_pm_counts, which forces this error count to saturate, and not generate count rollover fifo entries. 7 fwd/bwd tagged cells when ?1?, the fwd or bwd tagged cells count had its msb set, depending on the setting of the pm direction bit. 6 fwd/bwd misinserted cells when ?1?, the fwd or bwd misinserted cells count had its msb set, depending on the setting of the pm direction bit. 5 fwd/bwd lost clp0 cells when ?1?, the fwd or bwd lost high-priority cells count had its msb set, depending on the setting of the pm direction bit. 4 fwd/bwd lost clp0+1 cells when ?1?, the fwd or bwd lost cells count had its msb set, depending on the setting of the pm direction bit. 3 fwd/bwd total lost clp0 cells when ?1?, the fwd or bwd total lost cell count (including those lost in secbs) had its msb set, depending on the setting of the pm direction bit. 2 fwd/bwd total lost clp0+1 cells when ?1?, the fwd or bwd lost cell count (including those lost in secbs) had its msb set, depending on the setting of the pm direction bit. 1 transmitted clp0 count when ?1?, the 32-bit total transmitted clp0 cells count had its msb set. 0 transmitted cl0+1 count when ?1?, the 32-bit total transmitted cells count had its msb set. 10.17 cell routing generated reverse flow cells (backward reporting pm cells, loopback cells, and rdi cells) are routed to the output backward oam cell interfaces of the s/uni-atlas-3200. the output bcif has a 16 cell fifo for buffering these cells before they are sent out. cells generated in the backward direction may be header translated as if they were being transmitted to the ocif depending on the setting of xlate_to_obcif. cells received by the s/uni-atlas-3200 on the input backward cell interface are buffered in a 16 cell fifo , paced, and inserted into the cell flow stream.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 document id: pmc-1990553, issue 4 the destination of each oam cell depends on the type of oam cell and whether or not the s/uni-atlas-3200 is the end-point for that particular oam flow. if the s/uni-atlas-3200 is not an end-point, the oam cells are routed to the same destination as user cells, with the exception of loopback cells. if the s/uni-atlas-3200 is an end point, the default configuration terminates and processes all oam cells except aps, system management, activate/deactivate and undefined oam cells, which may optionally be routed to either the output cell interface, or the backward cell interface, or the microprocessor cell interface. end- to-end points are treated as also being segment end-points as well for the purposes of routing these cells, to aid in localization of problems. the cell information fields prepended to cells sent to the mcif or bcif is intended as an aid to processing these cells. parent loopback oam cells will have their loopback location id examined. depending on the setting of the loopback routing bits in the configuration field of the vc table, loopback cells may be routed to the backwards cell interface, with their loopback indication bit cleared and the local loopback location identifier encoded in their loopback location id field. the source id is not changed. returned loopback oam cells will have their source id examined. depending on the setting of the loopback routing bits in the configuration field of the vc table, returned loopback cells may be dropped and routed to the microprocessor if the source id of the cell matches the local loopback id programmed into the cp loopback id registers. depending on the setting of the rtd_lb_to_up_at_end bit in the cp routing configuration register, returned loopback cells may be routed to the microprocessor at flow end points irrespective of the source id. 10.17.1 output backward oam cell interface the output backwards cell interface is an extended cell length 16-bit, 52 mhz utopia level 1 rx slave ?sci-phy? interface. generated rdi and backwards reporting cells, along with loopback cells, use this interface to access the opposite direction bcif. a 16-cell fifo is provided on the output bcif, and another 16 cell in the input bcif, to facilitate these transfers. the default configuration is shown in figure 20
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 document id: pmc-1990553, issue 4 figure 20 connection of s/uni-atlas-3200 bcifs 16 bit sci phy (backward cell interface) ingress direction ingress mode s/uni-atlas-3200 (+sram) egress mode s/uni-atlas-3200 (+sram) utopia or pos-phy (level 3) egress direction obcif ibcif bo_rdenb bo_dat[15:0] bo_par bo_clav bo_soc bi_rrdenb_ tclav bi_dat[15:0] bi_par bi_rclav_ twrenb bi_soc obcif ibcif bo_rdenb bo_dat[15:0] bo_par bo_clav bo_soc bi_rrdenb_ tclav bi_dat[15:0] bi_par bi_rclav_ twrenb bi_soc in addition to rdi, bwd pm, and lb cells, there are bits to route entire vcs, system management cells, or undefined oam cells to the bcif. these options permit the bcif interface to be connected to a tester for debug purposes, or to an asic for external processing of certain cells (so long as the rdi, bwdpm, and lb cells are passed on to the opposite direction atlas). in order to allow cells to be inserted in the reverse direction, the s/uni-atlas-3200 prepends routing information stored in the vc table onto the cell. this information consists of the phyid and backwards direction vcra fields from the vc table. the cell format, which is always a 64-byte cell, is shown in table 38.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 document id: pmc-1990553, issue 4 table 38 backwards cell interface cell format bit 15 bit 0 user prepend/postpend bytes 1 and 2 user prepend/postpend bytes 3 and 4 cell information field (9 bits) phyid (6 bits) reserved(1) vc record address (16 bits) 16 lsbs of ul3 udf field vpi (12 bits) 4 msbs of vci 12 lsbs of vci pti (3) clp (1) hec field 8 msbs of udf payload 1 ? payload 24 the user prepend/postpend bytes, along with the hec and udf fields, are the same as the respective bytes on the ul3 interfaces. in the case of cells that are looped back, they contain whatever data was already in these fields; in the case of generated cells (rdi, bwd pm, and rtd lb) the contents are undefined. it is expected that the cell will be header translated (xlate_from_ibcif = 1) bit in the reverse direction if the contents of the prepend or hec/udf fields are to be used. if the optional xlate_to_obcif bit is logic 1, then the vpi, vci, prepend/postpend, hec, and udf fields may contain data from the vc table as configured by the cell_info_to_ocif, xvpivci, xgfc, xprepo, xhec, and xudf bits. the insertion of the phyid, backwards vcra, and cell information fields are controlled by the obcif_phyid, obcif_bwd_vcra, and obcif_cell_info register bits. however, if the phyid is not inserted, cells from the bcif cannot be correctly reinserted in the reverse flow. if the backwards vcra is not inserted, then the cell contents (as modified by the xlate_to_obcif in conjunction with the xvpivci etc. bits) must be able to be searched correctly, and the search_from_ibcif bit must be set to logic 1. the cell info field is purely for the convenience of an asic or tester, to assist in identifying the cell and the connection from which it came. the bcif cell info field is very similar to part of the microprocessor cell info field, and is defined as follows:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 document id: pmc-1990553, issue 4 table 39 bcif cell information field cell_info[8:0] definition bit 8 source bit 7 nni bit 6 vpc bit 5 oam_type bit 4 typ[4] bit 3 typ[3] bit 2 typ[2] bit 1 typ[1] bit 0 typ[0] source: the source of the cell, encoded as follows: 0 : input cell interface, microprocessor cell interface, or backwards cell interface 1 : generated rdi or bwd pm cell, or looped-back oam-lb cell. it is intended that all of these cells be passed to the opposite direction s/uni-atlas-3200. nni: indicates the connection is associated with a network-network interface (nni). a logic 0 means the connection belongs to a user-network interface (uni). vpc: indicates the connection is provisioned as a virtual path connection (vpc). a logic 0 means the connection is provisioned as a virtual channel connection (vcc). oam_type: a logic 1 identifies a segment oam cell. a logic 0 identifies an end-to-end oam cell. this bit is only valid when the cell type indicates one of the oam types. typ[4:0]: cell type. this field is encoded as follows: typ[4:0] cell type 00000 user 00001 oam ais 00010 oam rdi 00011 oam continuity check 00100 oam parent loopback 00101 oam returned loopback 00110 oam forward monitoring pm 00111 oam backward reporting pm 01000 oam automated protection switching 01001 oam activate/deactivate 01010 oam undefined 01011 oam system management 01100 forward rm 01101 backward rm 01110 invalid pti/vci
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 document id: pmc-1990553, issue 4 typ[4:0] cell type 01111 unprovisioned connection 10000 inactive connection, or mis-configuration of the vpc pointer. 10001 search error 10010 cell transfer error (bad pos-3 or ul3 parity, or invalid phyid) 10011 oam cell with errored crc-10 10100 rm cell with errored crc-10 10101 generated ais 10110 generated cc 10111 generated forward monitoring pm 11000..11111 reserved 10.17.2 input backward oam cell interface the input backwards cell interface is an extended cell length, 16-bit, 52 mhz utopia level 1 ?sci-phy? interface. normally this interface acts as an rx master interface, though it can be configured as a tx slave interface for the purposes of attaching a tester or asic to it. generated rdi and backwards reporting cells, along with loopback cells, use this interface to enter the s/uni-atlas-3200 from the opposite-direction s/uni-atlas-3200. cells received on this interface must carry the phyid as shown in table 38, be 64 bytes in length, and either be able to be searched correctly (if search_from_ibcif = 1) or carry the vc record address as shown in table 38. note that if a device other than s/uni-atlas-3200 is placed between two s/uni- atlas-3200s, the source bit is provided for the purpose of differentiating cells that must be reinserted in the opposite direction (source = 1) and cells which are routed to the bcif for further processing (source = 0). however, any cells produced by such a device must contain the embedded phyid for proper operation. the input backward oam cell interface (input bcif) stores all received cells in a 16-cell fifo until such time as they are transmitted by the cell processor. the s/uni-atlas-3200 will insert cells from the input backward oam cell interfaces at the insertion rate programmed into the backward cell interface pacing register bits. the bcif insertion rate is the minimum rate at which cells will be inserted from the input bcif; cells will be inserted at a higher rate when there is excess capacity in the cell processor and output cell interface, and there are no cells from the input cell interface waiting to be processed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 document id: pmc-1990553, issue 4 in the event the phy queue for which the cell at the head of the fifo is destined becomes inoperative (i.e. no cells are accepted for that phy), that cell must be dealt with so that it does not prevent other phy devices from having cells inserted in the cell stream. the cell processor can be programmed with a head-of-line time out function to deal with this problem. if a phy queue does not make room available within a specified time, the s/uni-atlas-3200 can take a programmable action on that cell. the time out counter is defined in terms of cell periods at the sysclk rate, where one cell period is equal to 22 clock cycles. the head-of-line time out can be programmed to take into account the worst case time for cell transmission (e.g. 48 cell periods, plus 2-3 cell periods for robustness, at an sts-1 rate). the s/uni-atlas-3200 may be programmed to discard the cell, or to route the cell to the microprocessor interface, where it may be stored and re-inserted at a later time when the phy problem has been resolved. this function is provided solely to retain a quality of service for other phy devices in case a catastrophic event occurs on a particular phy queue. in normal operating mode, this situation will never be encountered. the head-of-line time out can optionally be disabled. cells from the ibcif are, by default, header-translated much like cells from the input cell interface. for routing and processing, they are treated as cells that were not received, but (potentially) are transmitted. thus, they are never included in terminated or monitored pm flows, oam cells are not dropped at flow end points, and ais, cc, and rdi alarms are not affected. cells from the ibcif are, however, subject to counting and/or policing if their cell type (usually oam cells) are configured to be counted and/or policed. cells from the bcif may optionally not be translated (if the xlate_from_ibcif register bit is logic 0) or may have the prepend/postpend 2 word from the vc record table inserted onto the prepend/postpend 1 or hec/udf words (via the ibcif_p2_to_p1 and ibcif_p2_to_hecudf bits). these bits are useful when using the bcifs in a non-standard way, and reside in the cell processor routing configuration register. 10.17.3 internal dram access microprocessor access to the internal dram is provided to allow access to the vc table records. the access registers allow the microprocessor to read or write an entire vc table record in one operation. the cell counts, alternate cell counts, and non-compliant counts each have a clear on read register bit that allows the corresponding count to be cleared whenever a read is performed. each field in the vc table is individually maskable during writes, to permit settings to be changed without affecting the operation of the device. the vc table records are protected by a crc-10 calculated over the entire entry. this crc is automatically generated by s/uni-atlas-3200 during microprocessor write operations and normal processing, and is automatically checked during reads, including microprocessor reads, of the dram. internal dram access bandwidth is shared between the internal processing cell processing operations and microprocessor accesses. the microprocessor is guaranteed enough bandwidth to perform at least 140,000 dram accesses per second. this is enough to support over 8000 connection setups/teardowns and allow a read or write the vc table record for all 64k vcs. additional microprocessor access to the dram may consume bandwidth required to send oam- fm and oam-pm cells and to do background processes, if the aggregate (user cells + generated oam cells) is in excess of oc-48.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 document id: pmc-1990553, issue 4 10.17.4 writing cells the s/uni-atlas-3200 contains a one cell buffer for the assembly of a cell by the microprocessor for presentation on the output cell interface. optional header translation and crc-10 protection provides full support of diagnostic and oam requirements. cells inserted via the microprocessor cell interface are inserted into the cell stream by the atm layer cell processor. the atm layer cell processor gives an equal priority between cells received from the input cell interface and cells received from the microprocessor cell interface. therefore, it is the responsibility of the management software to ensure that cells are not inserted via the microprocessor cell interface too frequently (i.e. the management software must ensure these inserted cells are paced). writes are performed through the microprocessor cell interface control and status and microprocessor cell interface data registers. the steps below outline how to insert a cell through this interface: 1. poll the insrdy register bit of the microprocessor cell interface control and status register until it is a logic 1. alternatively, service the interrupts that result from setting the insrdye bit in the master interrupt enable register. the insrdyi bit in the master interrupt status register is set whenever the insrdy bit goes high. 2. write the wrsoc bit in the microprocessor cell interface control and status register. at the same time, ensure that the crc10, proc_cell and phy[5:0] register bits are set to their correct values, depending on what operation is required. if the proc_cell register bit is a logic 1, then the cell will be processed in the cell processor as if it came from the input cell interface. if the proc_cell register bit is logic 0, then the cell will be passed through without being searched, processed, or counted in any way, as if it were inserted into the cell stream after the cell processor. phy[5:0] represents the phy address that the cell is associated with and will be included in the search key used for vc identification and used to determine the destination phy queue. 3. write the cell contents to the microprocessor cell interface data register. each subsequent write enters the next word in the cell. the words shall be written in the following order, and all 64 bytes must be written even if some are not used: word # contents 11 st prepended/postpended d-word 22 nd prepended/postpended d-word 3 atm header: gfc, vpi, vci, pti, clp 4 hec and udf fields 51 st atm payload d-word 62 nd atm payload d-word ?? 16 12 th atm payload d-word
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 document id: pmc-1990553, issue 4 the s/uni-atlas-3200 automatically handles cell length mismatches, and will place prepends/postpends in the appropriate locations when transmitting cells. note that if there is only one prepended word used in cells leaving s/uni-atlas-3200, that the 1 st prepended/postpended d-word field (word 1) would be filled with data for that prepend/postpend, and word 2 would be a don?t-care. 10.17.5 reading cells cells received on the input cell interface or the backward cell interface can be routed to the 16- cell microprocessor cell interface fifo based on the type of cell. maskable interrupt statuses are generated upon the receipt of a cell and upon buffer overflow. if a buffer overflow occurs, entire cells are lost. cells are written into the mcif fifo without header translation, as a 64-byte cell. as an option, the prepended information can be overwritten with the phyid, vc record address, and information about the cell and connection. this information, together, is the microprocessor cell info field and is used to interpret why the cell was routed to the microprocessor, and to provide cell status information. the cell_info_to_up bit in the cell processor configuration register controls this function. the microprocessor cell info word has the following format: table 40 microprocessor cell information field prepend 1 [31:0] definition bits 31:13 unused bit 12 source[1] bit 11 source[0] bit 10 end_to_end_point bit 9 segment_end_point bit 8 timeout bit 7 nni bit 6 vpc bit 5 oam_type bit 4 typ[4] bit 3 typ[3] bit 2 typ[2] bit 1 typ[1] bit 0 typ[0] prepend 2 [31:0] bits 31:23 unused bits 22:17 phyid[5:0] bit 16 reserved bits 15:0 vc record address[15:0]
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 document id: pmc-1990553, issue 4 source[1:0]: the source of the cell, encoded as follows: 00 : input cell interface 01 : backwards cell interface 10 : generated forward pm, ais, or cc cell 11 : reserved. end_to_end_point: indicates the connection is provisioned as an oam flow end point. if the cell type indicates an unprovisioned connection, search error, or cell transfer error, this bit is not valid. segment_end_point: indicates the connection is provisioned as an oam flow segment end point. if the cell type indicates an unprovisioned connection, search error, or cell transfer error, this bit is not valid. timeout: indicates the cell was removed from a backward cell interface or microprocessor cell interface because the head-of-line blocking timer has expired, or the associated phy has been declared inoperative. when this bit is set, only the source, phyid and typ fields are valid. nni: indicates the connection is associated with a network-network interface (nni). a logic 0 means the connection belongs to a user-network interface (uni). vpc: indicates the connection is provisioned as a virtual path connection (vpc). a logic 0 means the connection is provisioned as a virtual channel connection (vcc). oam_type: a logic 1 identifies a segment oam cell. a logic 0 identifies an end-to-end oam cell. this bit is only valid when the cell type indicates one of the oam types. typ[4:0]: cell type. this field is encoded as follows: typ[4:0] cell type 00000 user 00001 oam ais 00010 oam rdi 00011 oam continuity check 00100 oam parent loopback 00101 oam returned loopback 00110 oam forward monitoring pm 00111 oam backward reporting pm 01000 oam automated protection switching 01001 oam activate/deactivate 01010 oam undefined 01011 oam system management 01100 forward rm 01101 backward rm 01110 invalid pti/vci 01111 unprovisioned connection
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 document id: pmc-1990553, issue 4 typ[4:0] cell type 10000 inactive connection, or mis-configuration of the vpc pointer. 10001 search error 10010 cell transfer error (bad pos-3 or ul3 parity, or invalid phyid) 10011 oam cell with errored crc-10 10100 rm cell with errored crc-10 10101 generated ais 10110 generated cc 10111 generated forward monitoring pm 11000..11111 reserved phyid[5:0]: the index of the phy device associated with the cell. vcra[15:0]: the vc record associated with the cell the up_dmareq output and the extca bits of the mcif extract buffer control and status registers are asserted if one or more complete cells are available in the buffer. the first read of the mcif after either the extca bit or the up_dmareq is asserted returns the first word of the cell. subsequent reads return the remainder of the cell. the sequence of words is the same as for buffer writes (see above). at any time, the read pointer can be returned to the beginning of the cell by setting the restart bit. the current cell is discarded upon setting the abort bit. the up_dmareq output is deasserted during the read of the last word of the cell. 10.18 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest are supported. the s/uni-atlas- 3200 identification code is 073250cd hexadecimal.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 document id: pmc-1990553, issue 4 11 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-atlas- 3200. normal mode registers (as opposed to test mode registers) are selected when trs (up_addr[11]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-atlas-3200 to determine the programming state of the block. 3. writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni-atlas- 3200 operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-atlas-3200 operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. 11.1 list of registers register 0x000: s/uni-atlas-3200 master configuration and reset..........................151 register 0x001: s/uni-atlas-3200 identity / load counts..........................................154 register 0x002: master interrupt status #1....................................................................156 register 0x003: master interrupt status #2....................................................................162 register 0x004: master interrupt enable #1 ..................................................................164 register 0x005: master interrupt enable #2 ..................................................................166 register 0x006: master clock monitor ...........................................................................167 register 0x020: microprocessor cell interface control and status ...............................169 register 0x021: microprocessor cell data.....................................................................173 register 0x022: mcif dropped cells counter...............................................................175 register 0x030: input backwards cell interface configuration......................................176 register 0x031: ibcif dropped cells counter ..............................................................178 register 0x032: ibcif read cells counter ...................................................................179
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 document id: pmc-1990553, issue 4 register 0x038: output backwards cell interface configuration...................................180 register 0x039: obcif dropped cells counter ............................................................181 register 0x03a: obcif read cells counter .................................................................182 register 0x040: sysclk delay locked loop register 1..............................................183 register 0x041: sysclk dll register 2 ......................................................................185 register 0x042: sysclk dll register 3 ......................................................................186 register 0x043: sysclk dll register 4 ......................................................................187 register 0x100: cell processor configuration ...............................................................190 register 0x101: cell processor routing configuration..................................................197 register 0x102: cell counting configuration .................................................................203 register 0x104: backward cell interface pacing and head of line blocking................205 register 0x105: per-phy processing enable 1 .............................................................207 register 0x106: per-phy processing enable 2 .............................................................209 register 0x107: ais/cc pacing and head of line blocking .......................................... 211 register 0x108: fwd pm pacing and head of line blocking.........................................213 register 0x109: inoperative phy declaration period and indications ...........................215 register 0x10a: inoperative phy indications ................................................................217 register 0x10b: search engine configuration...............................................................219 register 0x10c: sram access control .........................................................................221 register 0x10d: sram data lsw (sram data[31:0]) .................................................223 register 0x10e: sram data msw (sram data [63:32]) .............................................224 register 0x110: vc table maximum index ....................................................................225 register 0x111: vc table access control ......................................................................226 register 0x112: vc table write enable 1 ......................................................................229 register 0x113: vc table write enable 2 ......................................................................231 register 0x114: vc table data row 0, word 0 (lsw) (ram data [31:0]) ....................232 register 0x115: vc table data row 0, word 1 (ram data [63:32]) .............................233 register 0x116: vc table data row 0, word 2 (ram data [95:64]) .............................234 register 0x117: vc table data row 0, word 3 (msw) (ram data [127:96]) ...............235 register 0x118: vc table data row 1, word 0 (lsw) (ram data [31:0]) ....................236 register 0x119: vc table data row 1, word 1 (ram data [63:32]) .............................236 register 0x11a: vc table data row 1, word 2 (ram data [95:64]) ............................236 register 0x11b: vc table data row 1, word 3 (msw) (ram data [127:96])...............236 register 0x11c: vc table data row 2, word 0 (lsw) (ram data [31:0]) ...................237 register 0x11d: vc table data row 2, word 1 (ram data [63:32]).............................237
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 document id: pmc-1990553, issue 4 register 0x11e: vc table data row 2, word 2 (ram data [95:64]) ............................237 register 0x11f: vc table data row 2, word 3 (msw) (ram data [127:96])...............237 register 0x120: vc table data row 3, word 0 (lsw) (ram data [31:0])....................238 register 0x121: vc table data row 3, word 1 (ram data [63:32]) .............................238 register 0x122: vc table data row 3, word 2 (ram data [95:64]) ............................238 register 0x123: vc table data row 3, word 3 (msw) (ram data [127:96])...............238 register 0x124: vc table data row 4 word 0 (lsw) (ram data [31:0]).....................239 register 0x125: vc table data row 4, word 1 (ram data [63:32]) .............................239 register 0x126: vc table data row 4, word 2 (ram data [95:64]) ............................239 register 0x127: vc table data row 4, word 3 (msw) (ram data [127:96])...............239 register 0x128: vc table data row 5 word 0 (lsw) (ram data [31:0]).....................240 register 0x129: vc table data row 5, word 1 (ram data [63:32]) .............................240 register 0x12a: vc table data row 5, word 2 (ram data [95:64])............................240 register 0x12b: vc table data row 5, word 3 (msw) (ram data [127:96]) ..............240 register 0x12c: vc table data row 6 word 0 (lsw) (ram data [31:0]) ....................241 register 0x12d: vc table data row 6, word 1 (ram data [63:32]) ............................241 register 0x12e: vc table data row 6, word 2 (ram data [95:64])............................241 register 0x12f: vc table data row 6, word 3 (msw) (ram data [127:96])...............241 register 0x130: per-vc non-compliant cell counting configuration ...........................242 register 0x131: connection policing configuration 1 & 2 .............................................244 register 0x132: connection policing configuration 3 & 4 .............................................245 register 0x133: connection policing configuration 5 & 6 .............................................245 register 0x134: connection policing configuration 7 & 8 .............................................245 register 0x140: phy policing enable 1 .........................................................................246 register 0x141: phy policing enable 2 .........................................................................248 register 0x142: phy policing configuration..................................................................249 register 0x143: per-phy non-compliant cell counting configuration.........................251 register 0x144: phy policing ram address and access control .................................252 register 0x145: phy policing ram data row 0 ...........................................................255 register 0x146: phy policing ram data row 1 ...........................................................256 register 0x147: phy policing ram data row 2 ...........................................................257 register 0x148: phy policing ram data row 3 ...........................................................258 register 0x151: oam defect location octets 3 to 0 .....................................................259 register 0x152: defect location octets 7 to 4..............................................................260 register 0x153: defect location octets 11 to 8 .............................................................260
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 document id: pmc-1990553, issue 4 register 0x154: defect location octets 15 to 12...........................................................260 register 0x155: per-phy ais cell generation control 1...............................................261 register 0x156: per-phy ais cell generation control 2...............................................263 register 0x157: per-phy rdi cell generation control 1 ..............................................264 register 0x158: per-phy rdi cell generation control 2 ..............................................266 register 0x159: per-phy aps indication 1....................................................................267 register 0x15a: per-phy aps indication 2 ...................................................................269 register 0x160: oam loopback location id octets 3 to 0............................................270 register 0x161: loopback location id octets 7 to 4....................................................271 register 0x162: loopback location id octets 11 to 8 ...................................................271 register 0x163: loopback location id octets 15 to 12.................................................271 register 0x170: performance management ram record address, word select and access control ...................................................................................................272 register 0x171: performance management ram row 0 word 0 (lsw) ......................274 register 0x172: performance management ram row 0 word 1 .................................275 register 0x173: performance management ram row 0 word 2 (msw) .....................276 register 0x174: performance management ram row 1 word 0 (lsw) ......................277 register 0x175: performance management ram row 1 word 1 .................................277 register 0x176: performance management ram row 1 word 2 (msw) .....................277 register 0x177: performance management ram row 2 word 0 (lsw) ......................278 register 0x178: performance management ram row 2 word 1 .................................278 register 0x179: performance management ram row 2 word 2 (msw) .....................278 register 0x17a: performance management ram row 3 word 0 (lsw)......................279 register 0x17b: performance management ram row 3 word 1 .................................279 register 0x17c: performance management ram row 3 word 2 (msw).....................279 register 0x17d: performance management ram row 4 word 0 (lsw)......................280 register 0x17e: performance management ram row 4 word 1 .................................280 register 0x17f: performance management ram row 4 word 2 (msw) .....................280 register 0x180: performance management ram row 5 word 0 (lsw) ......................281 register 0x181: performance management ram row 5 word 1 .................................281 register 0x182: performance management ram row 5 word 2 (msw) .....................281 register 0x183: performance management ram row 6 word 0 (lsw) ......................282 register 0x184: performance management ram row 6 word 1 .................................282 register 0x185: performance management ram row 6 word 2 (msw) .....................282 register 0x186: performance management ram row 7 word 0 (lsw) ......................283
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 document id: pmc-1990553, issue 4 register 0x187: performance management ram row 7 word 1 .................................283 register 0x188: performance management ram row 7 word 2 (msw) .....................283 register 0x189: performance management threshold a ..............................................284 register 0x18a: performance management threshold b..............................................285 register 0x18b: performance management threshold c .............................................285 register 0x18c: performance management threshold d .............................................285 register 0x190: vc table change of connection state fifo status ............................286 register 0x191: vc table change of connection state fifo data...............................287 register 0x198: count rollover fifo status .................................................................288 register 0x199: count rollover fifo data....................................................................289 register 0x1a0: per-phy counter configuration ..........................................................291 register 0x1a1: per-phy counter control ....................................................................293 register 0x1a8: per-phy clp0 cell count holding register .......................................296 register 0x1a9: per phy clp1 cell count holding register .......................................298 register 0x1aa: per phy valid rm cell counts holding register................................299 register 0x1ab: per phy valid oam cell counts holding register .............................300 register 0x1ac: per phy errored oam/rm cell counts holding register ..................301 register 0x1ad: per phy invalid vpi/vci/pti cell counts holding register ...............302 register 0x1ae: per-phy efci/non-zero gfc cell count holding register ..............303 register 0x1af: per-phy timed-out cell count holding register ...............................304 register 0x1b0: per phy last unknown vpi & vci holding register ..........................305 register 0x1c0: reserved .............................................................................................307 register 0x200: rxl configuration.................................................................................308 register 0x201: rxl interrupt enable ............................................................................310 register 0x202: rxl interrupt......................................................................................... 311 register 0x208: rxl phy indirect address....................................................................312 register 0x209: rxl phy indirect data .........................................................................313 register 0x20a: rxl calendar length...........................................................................314 register 0x20b: rxl calendar indirect address and data ............................................315 register 0x20c: rxl data type field ............................................................................317 register 0x220: txp configuration.................................................................................318 register 0x221: txp interrupt.........................................................................................320 register 0x222: txp interrupt enable ............................................................................321 register 0x223: txp data type field.............................................................................322 register 0x240: input sdq control................................................................................323
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 document id: pmc-1990553, issue 4 register 0x241: input sdq interrupts ............................................................................324 register 0x242: input sdq interrupt id .........................................................................326 register 0x244: input sdq indirect address .................................................................327 register 0x245: input sdq indirect configuration .........................................................329 register 0x246: input sdq cells and packets count....................................................331 register 0x247: input sdq cells accepted aggregate count .......................................332 register 0x248: input sdq cells dropped aggregate count ........................................333 register 0x260: rxp configuration ................................................................................334 register 0x261: rxp interrupt ........................................................................................336 register 0x262: rxp interrupt enable............................................................................337 register 0x263: rxp phy indirect address and data....................................................338 register 0x264: rxp calendar length...........................................................................340 register 0x265: rxp calendar indirect address and data ............................................341 register 0x266: rxp data type field ............................................................................343 register 0x280: txl configuration .................................................................................344 register 0x281: txl interrupt enable.............................................................................346 register 0x282: txl interrupt .........................................................................................347 register 0x286: txl data type field .............................................................................348 register 0x288: txl phy indirect address ....................................................................349 register 0x289: txl phy indirect data..........................................................................350 register 0x28a: txl calendar length ...........................................................................351 register 0x28b: txl calendar indirect address and data.............................................352 register 0x2a0: output sdq control.............................................................................354 register 0x2a1: output sdq interrupts .........................................................................355 register 0x2a2: output sdq interrupt id ......................................................................357 register 0x2a4: output sdq indirect address ..............................................................358 register 0x2a5: output sdq indirect configuration......................................................360 register 0x2a6: output sdq cells and packets count.................................................362 register 0x2a7: output sdq cells accepted aggregate count ....................................363 register 0x2a8: output sdq cells dropped aggregate count .....................................364 register 0x2c0: bypass sdq control ...........................................................................365 register 0x2c1: bypass sdq interrupts........................................................................366 register 0x2c2: bypass sdq interrupt id .....................................................................368 register 0x2c4: bypass sdq indirect address .............................................................369 register 0x2c5: bypass sdq indirect configuration.....................................................371
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 document id: pmc-1990553, issue 4 register 0x2c6: bypass sdq cells and packets count ...............................................373 register 0x2c7: bypass sdq cells accepted aggregate count ...................................374 register 0x2c8: bypass sdq cells dropped aggregate count ....................................375 register 0x800: master test...........................................................................................377
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 document id: pmc-1990553, issue 4 11.2 core registers register 0x000: s/uni-atlas-3200 master configuration and reset bit type function default 31:18 unused x 17 r/w reserved 0 16 r/w reserved 0 15 r/w free[7] 0 14 r/w free[6] 0 13 r/w free[5] 0 12 r/w free[4] 0 11 r/w free[3] 0 10 r/w free[2] 0 9 r/w free[1] 0 8 r/w free[0] 0 7 r/w pos_ul3b 1 6 r/w egress_ingressb 0 5 r/w dram_busy_en 0 4 r/w sram_busy_en 0 3 r/w busypol 0 2r/w reserved 0 1 r/w standby 1 0 r/w reset 1 reset the reset bit allows the s/uni-atlas-3200 to be reset under software control. if the reset bit is a logic one, the entire s/uni-atlas-3200 is held in reset. on a hardware reset, this bit is set to logic 1, and must be written to logic 0 to bring the device out of reset. holding the s/uni-atlas-3200 in a reset state places it into a low power, stand-by mode. in order to initialize the embedded dram, this bit must remain logic 1, with the sysclk dll locked (dllrun = 1 in the master clock monitor register) for at least 200 us following a hardware reset. once the 200 us have elapsed, this bit may be written to logic 0, and configuration of the device may proceed. note, unlike the hardware reset input, rstb, the software reset bit does not force the s/uni- atlas-3200 digital output pins tristate.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 document id: pmc-1990553, issue 4 standby the standby bit disables cell processing to avoid passing corrupted cells while initializing the s/uni-atlas-3200. when standby is a logic 1, the s/uni-atlas-3200 makes all bus cycles available for external sram and internal dram access (i.e. micro access to the search tree or context is given highest priority, and no other processing will interrupt the sram and dram busses). if the standby bit is set while cell processing is in progress, the processing of cells currently in the pipeline is completed, but no more cells are accepted. reserved this bit should be programmed to logic 0 for proper operation. busypol the busypol bit sets the polarity of the busyb primary output. if busypol is a logic 0, the busyb primary output is active low. if busypol is a logic 1, the busyb output is active high. sram_busy_en when this bit is logic 1, the busy signal from the s/uni-atlas-3200 will be asserted whenever the external sram is busy. when 0, the busy signal will not react to sram activity. dram_busy_en when this bit is logic 1 the busy signal from the s/uni-atlas-3200 will be asserted whenever the internal dram is busy. when 0 the busy signal will not react to dram activity. pos_ul3b when pos_ul3b is logic 1, then the device uses pos-phy level 3 signaling. when pos_ul3b is logic 0, the device uses utopia level 3 signaling. this bit defaults to logic 1 to ensure that all pins that can be inputs or outputs, power up as inputs.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 document id: pmc-1990553, issue 4 egress_ingressb when egress_ingressb is logic 1, the device is in egress mode, and the txphy and txlink blocks are used. when egress_ingressb is logic 0, the device is in ingress mode and the rxlink and rxphy blocks are used. when in egress mode, the rxlink and rxphy blocks should be left in soft reset. when in ingress mode, the txlink and txphy blocks should be left in soft reset. free[7:0] these bits have no function. they can be used by software to store configuration information, software version codes, or other user information. reserved this bit must be programmed to logic 0 for correct operation.. reserved this bit must be programmed to logic 0 for correct operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 document id: pmc-1990553, issue 4 register 0x001: s/uni-atlas-3200 identity / load counts bit type function default 31:24 unused x 23 r mkt_num[15] 0 22 r mkt_num[14] 1 21 r mkt_num[13] 1 20 r mkt_num[12] 1 19 r mkt_num[11] 0 18 r mkt_num[10] 0 17 r mkt_num[9] 1 16 r mkt_num[8] 1 15 r mkt_num[7] 0 14 r mkt_num[6] 0 13 r mkt_num[5] 1 12 r mkt_num[4] 0 11 r mkt_num[3] 0 10 r mkt_num[2] 1 9 r mkt_num[1] 0 8 r mkt_num[0] 1 7r tip x 6 r type[2] 0 5 r type[1] 1 4 r type[0] 0 3 r id[3] 0 2 r id[2] 0 1 r id[1] 0 0 r id[0] 0 writing to this register simultaneously loads all the aggregate and per-phy counts in the input, output, and bypass sdq fifos, and the counts in the bcifs. while this load is in progress, the tip bit will be logic 1 in this register. when the load is complete, the tip bit becomes 0. id[3:0] the id bits can be read to provide a binary number indicating the s/uni-atlas-3200 feature version. type[2:0] the type bits can be read to distinguish the s/uni-atlas-3200 from the other members of the s/uni-atlas-3200 family of devices. ?001? in this field indicates the s/uni-atlas, while ?010? indicates the s/uni-s/uni-atlas-3200.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 document id: pmc-1990553, issue 4 tip the transfer in progress bit is logic 1 while the input bcif, output bcif, input sdq, output sdq, or sdq fifo counts are being updated. once the update is complete, tip becomes logic 0 to indicate that the counts are valid; however, another transfer should not be requested for at least 100ns after tip returns to 0. mkt_num[15:0] the marketing number register returns 0x7325, the marketing number of the s/uni-s/uni- atlas-3200.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 document id: pmc-1990553, issue 4 register 0x002: master interrupt status #1 bit type function default 31 r reg3i x 30 r obciffulli x 29 r obovfli x 28 r ibciffulli x 27 r ibprtyi x 26 r ibovfli x 25 r ibsoci x 24 r upcai x 23 r upovri x 22 r insrdyi x 21 r reserved x 20 r slowbgi x 19 r deadphyi x 18 r croi x 17 r xcroi x 16 r crofulli x 15 r cosi x 14 r xcosi x 13 r cosfulli x 12 r phypoli x 11 r poli x 10 r oam_faili x 9 r end_rdii x 8 r seg_rdii x 7 r end_aisi x 6 r seg_aisi x 5 r end_cci x 4 r seg_cci x 3 r srch_erri x 2 r oam_erri x 1 r inval_pti_vcii x 0 r unprov_i x unprovi the unprovi bit indicates that a cell with an unprovisioned vpi/vci combination or invalid routing bits has been received. when logic 1, the unprovi bit indicates that one or more vc table searches have not resulted in a match. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 document id: pmc-1990553, issue 4 inval_ptivcii the inval_ptivcii bit indicates a cell with an invalid pti or vci field has been received. when logic 1, the inval_ptivcii bit indicates one or more f5 cells have the pti field with pti=?111?, f4 cells with an invalid vci field (vci 7 through 15) or at least one vp resource management cell has been received with pti not equal to ?110?. this bit is cleared when this register is read. oam_erri the oamerri bit indicates one or more oam cell with an incorrect oam type, function type or error detection code field (crc-10) has been received. when logic 1, the oamerri bit indicates one or more errored oam cells have been received. this bit may also indicate one or more resource management cell with an incorrect crc-10 has been received. this bit is cleared when this register is read. srch_erri the search error bit (srcherri) indicates that a vpi/vci search in the vc table has failed due to an improperly constructed secondary search table (i.e. the secondary search takes more than 45 branches) or a parity bit error on the external sram (correlate with sprty[7:0]). this bit is cleared when this register is read. seg_cci the seg_cci bit indicates that a segment continuity check alarm bit in the vc table has changed state. when logic 1, the seg_cci bit indicates the segment_cc_alarm bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read. end_cci the end_cci bit indicates that an end-to-end continuity check alarm (in the vc table) has changed state. when logic 1, the end_cci bit indicates the end_to_end_cc_alarm bit in the vc table has changed state for one or more virtual connection. this bit is cleared when this register is read. seg_aisi the seg_aisi bit indicates that a segment ais alarm (in the vc table) has changed state. when logic 1, the seg_aisi bit indicates the segment ais alarm bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 document id: pmc-1990553, issue 4 end_aisi the end_aisi bit indicates that an end-to-end ais alarm (in the vc table) has changed state. when logic 1, the end_aisi bit indicates the end-to-end ais alarm bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read. seg_rdii the seg_rdii bit indicates that a segment rdi alarm (in the vc table) has changed state. when logic 1, the seg_rdii bit indicates the segment rdi alarm bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read. end_rdii the end_rdii bit indicates that an end-to-end rdi alarm (in the vc table) has changed state. when logic 1, the end_rdii bit indicates the end-to-end rdi alarm bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read. oam_faili the oam_faili bit indicates that the oam_failure bit in the vc table has changed state for one or more virtual connections. this bit is cleared when this register is read. poli the poli bit indicates a non-compliant cell has been received. when logic 1, the poli bit indicates one or more cells have violated the traffic contract since the last read of this register. this bit is cleared when this register is read. phypoli the phy policing interrupt bit (phypoli) indicates that one or more cells have violated one or more per-phy policing contracts. when logic 1, the phypoli bit indicates one or more cells have violated one or more of the 48 phy policing instances. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 document id: pmc-1990553, issue 4 cosfulli the change of state fifo full interrupt bit (cosfulli) indicates that the change of state fifo is full. when logic 1, the cosfulli indicates that the change of state fifo is full, and no more change of state notifications can be written into the fifo. this suspends a background process until fifo space becomes free. it is the responsibility of the management software to ensure this fifo is read often enough to ensure the notification of changes of state are compliant with bellcore and itu standards. this bit is cleared when this register is read. xcosi the excessive change of state fifo interrupt bit (xcosi) indicates that the change of state fifo is half-full. when logic 1, the xcosi indicates that the change of state fifo is half-full with changes of connection state information. this indicates that the change of state fifo should be read quickly to avoid the change of state fifo from becoming full. it is the responsibility of the management software to ensure the change of state fifo is read often enough to ensure the notification of changes of state are compliant with bellcore and itu standards. this bit is cleared when this register is read. cosi the change of state interrupt bit (cosi) indicates that the change of state fifo has become non-empty. crofulli the count rollover fifo full interrupt bit (crofulli) indicates that the count rollover fifo is full. when logic 1, the crofulli indicates that the count rollover fifo is full, and no more rollover notifications can be written into the fifo. this causes the counts to retain their msbs high until room is made in the count rollover fifo. xcroi the excessive count rollover fifo interrupt bit (xcroi) indicates that the count rollover fifo is half-full. this indicates that the count rollover fifo should be read quickly to avoid it becoming full. croi the count rollover fifo interrupt bit (croi) indicates that the count rollover fifo has become non-empty.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 document id: pmc-1990553, issue 4 deadphyi the inoperative phy interrupt bit (deadphyi) indicates that a phy has had cells ready to be transmitted, and has not accepted any cells whatsoever, for a programmable period of time. the inoperative phy may be identified by reading the inoperative phy indication registers. slowbgi the slow background process interrupt (slowbgi) indicates that, for three consecutive seconds, the tat update background process was unable to complete a full set of background processing. this may indicate that the s/uni-atlas-3200 is overloaded with both cells and microprocessor accesses to dram or sram. upcai the upcai bit indicates that a cell has been written into the microprocessor cell extract fifo, and is ready for extraction by an external processor. when logic 1, the upcai bit indicates that the extca bit in the microprocessor cell interface control and status register has been asserted. the upcai bit is cleared when this register is read. upovri the upovri bit indicates that a cell was written to the output microprocessor interface, but the fifo was full, and so the cell was discarded. insrdyi the insrdyi bit indicates the microprocessor cell interface insert fifo is ready for another cell. this bit is cleared when this register is read. ibsoci the input bcif soc interrupt indicates that either the ibcif received a soc when it was not expecting it, or did not receive a soc when it was expecting one. this bit is cleared when this register is read. ibovfli the ibovfli bit is set to logic 1 when a cell has been written into the input bcif when the ibcif was already full this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 document id: pmc-1990553, issue 4 ibprtyi when logic 1, the ibprtyi bit indicates a parity error over the ibdat[15:0] data bus. this bit is cleared when this register is read. ibciffulli when logic 1, the ibciffulli bit indicates that the input backward cell interface fifo is full, and cannot accept any more cells generated by the opposite direction s/uni-atlas- 3200. this results in the opposite direction?s output bcif being backed up. if the ibciffulli interrupt persists, the rate at which cells are allowed from the bcif may have to be increased, so that rdi and backward reporting pm cells can be generated at the appropriate intervals. this bit is cleared when this register is read. obovfli when logic 1, the obovfli bit indicates that a cell was written to the output bcif when it was already full. this indicates that one or more cells destined to be routed to the obcif (such as loopback cells) has been dropped. rdi and backward pm cells will not be dropped in this fashion, since the information needed to generate them later is stored in the vc and pm tables. obciffulli when logic 1, the obciffulli bit indicates that the output backward cell interface fifo is full, and cannot accept any more cells generated by the cell processor. this affects how often rdi and backward reporting pm cells can be generated and sent to the backwards direction s/uni-atlas-3200. if the obciffulli interrupt persists, the rate at which cells are allowed into the cell stream from the bcif in the backwards direction s/uni-atlas- 3200 may have to be increased, so that rdi and backward reporting pm cells can be generated at the appropriate intervals. this bit is cleared when this register is read. reg3i the reg3i bit indicates that at least one bit in register 0x003, s/uni-atlas-3200 master interrupt status #2 is currently asserted.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 document id: pmc-1990553, issue 4 register 0x003: master interrupt status #2 bit type function default 31:23 r reserved x 22 r bypass_sdq_i 21 r output_sdq_i x 20 r tx_link_i x 19 r rx_phy_i x 18 r input_sdq_i x 17 r tx_phy_i x 16 r rx_link_i x 15 r reserved x 14 r oclkdllerri x 13 r iclkdllerri x 12 r sysclkdllerri x 11 r reserved x 10 r reserved x 9r reserved x 8 r dram_erri x 7 r sprtyi[7] x 6 r sprtyi[6] x 5 r sprtyi[5] x 4 r sprtyi[4] x 3 r sprtyi[3] x 2 r sprtyi[2] x 1 r sprtyi[1] x 0 r sprtyi[0] x sprtyi[7:0] the sprtyi[7:0] bits indicate a parity error has been detected on the external sram interface sdat[63:0], data bus. when logic 1, the sprtyi[7:0] bits indicate the following: sprtyi[7]:parity error over inputs sdat[63:56] sprtyi[6]:parity error over inputs sdat[55:48] sprtyi[5]:parity error over inputs sdat[47:40] sprtyi[4]:parity error over inputs sdat[39:32] sprtyi[3]:parity error over inputs sdat[31:24] sprtyi[2]:parity error over inputs sdat[23:16] sprtyi[1]:parity error over inputs sdat[15:8] sprtyi[0]:parity error over inputs sdat[7:0] all bits are cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 document id: pmc-1990553, issue 4 dram_erri the dram_erri bit indicates that a dram read detected a crc-10 violation. this bit is cleared when this register is read. sysclkdllerri the sysclk dll error interrupt indicates that the dll on sysclk found that it was outside of its capture range. this bit is cleared when this register is read. iclkdllerri: the input clock dll error interrupt indicates that the dll on iclk found that it was outside of its capture range. this bit is cleared when this register is read. oclkdllerri the output clock dll error interrupt indicates that the dll on oclk found that it was outside of its capture range. this bit is cleared when this register is read. rx_link_i the rx link interrupt bit indicates that the rx link block has declared an interrupt, which may be read (and cleared) in the rxl interrupt register. only interrupts whose enable bits are logic 1 in the rxl interrupt enable register in section 11.6 will cause this bit to become logic 1. tx_phy_i the tx phy interrupt bit indicates that the tx phy block has declared an interrupt, which may be read (and cleared) in the txp interrupt register. only interrupts whose enable bits are logic 1 in the txp interrupt enable register in section 11.7 will cause this bit to become logic 1. input_sdq_i the input sdq interrupt bit indicates that the input sdq block has declared an interrupt, which may be read (and cleared) in the input sdq interrupt register. only interrupts whose enable bits are logic 1 in the input sdq interrupts register in section 11.8 will cause this bit to become logic 1.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 document id: pmc-1990553, issue 4 rx_phy_i the rx phy interrupt bit indicates that the rx phy block has declared an interrupt, which may be read (and cleared) in the rxp interrupt register. only interrupts whose enable bits are logic 1 in the rxp interrupt enable register in section 11.9 will cause this bit to become logic 1. tx_link_i the tx link interrupt bit indicates that the tx link block has declared an interrupt, which may be read (and cleared) in the txl interrupt register. . only interrupts whose enable bits are logic 1 in the txl interrupt enable register in section 11.10 will cause this bit to become logic 1. output_sdq_i the output sdq interrupt bit indicates that the output sdq block has declared an interrupt, which may be read (and cleared) in the output sdq interrupt register. only interrupts whose enable bits are logic 1 in the output sdq interrupts register in section 11.11 will cause this bit to become logic 1. bypass_sdq_i the bypass sdq interrupt bit indicates that the bypass sdq block has declared an interrupt, which may be read (and cleared) in the bypass sdq interrupt register. only interrupts whose enable bits are logic 1 in the bypass sdq interrupts register in section 11.12 will cause this bit to become logic 1.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 document id: pmc-1990553, issue 4 register 0x004: master interrupt enable #1 bit type function default 31 r/w reserved 0 30 r/w obciffulle 0 29 r/w obovfle 0 28 r/w ibciffulle 0 27 r/w ibprtye 0 26 r/w ibovfle 0 25 r/w ibsoce 0 24 r/w upcae 0 23 r/w upovre 0 22 r/w insrdye 0 21 r/w reserved 0 20 r/w slowbge 0 19 r/w deadphye 0 18 r/w croe 0 17 r/w xcroe 0 16 r/w crofulle 0 15 r/w cose 0 14 r/w xcose 0 13 r/w cosfulle 0 12 r/w phypole 0 11 r/w pole 0 10 r/w oam_faile 0 9 r/w end_rdie 0 8 r/w seg_rdie 0 7 r/w end_aise 0 6 r/w seg_aise 0 5 r/w end_cce 0 4 r/w seg_cce 0 3 r/w srch_erre 0 2 r/w oam_erre 0 1 r/w inval_pti_vci_e 0 0 r/w unprov_e 0 the above enable bits control the corresponding interrupt status bits in the s/uni-atlas-3200 master interrupt status #1 register. when an enable bit is set to logic 1, the intb output is asserted low when the corresponding interrupt status bit is a logic 1.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 document id: pmc-1990553, issue 4 register 0x005: master interrupt enable #2 bit type function default 31:23 r/w reserved x 22 r/w bypass_sdq_e 0 21 r/w output_sdq_e 0 20 r/w tx_link_e 0 19 r/w rx_phy_e 0 18 r/w input_sdq_e 0 17 r/w tx_phy_e 0 16 r/w rx_link_e 0 15 r/w reserved 0 14 r/w oclkdllerre 0 13 r/w iclkdllerre 0 12 r/w sysclkdllerre 0 11 r/w reserved 0 10 r/w reserved 0 9r/w reserved 0 8 r/w dram_erre 0 7 r/w sprtye[7] 0 6 r/w sprtye[6] 0 5 r/w sprtye[5] 0 4 r/w sprtye[4] 0 3 r/w sprtye[3] 0 2 r/w sprtye[2] 0 1 r/w sprtye[1] 0 0 r/w sprtye[0] 0 the above enable bits control the corresponding interrupt status bits in the s/uni-atlas-3200 master interrupt status #2 register. when an enable bit is set to logic 1, the intb output is asserted low when the corresponding interrupt status bit is a logic 1.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 document id: pmc-1990553, issue 4 register 0x006: master clock monitor bit type function default 31:9 unused x 8r/w rstdll 0 7 r dllrun x 6 r halfsecclka x 5r obcifclka x 4r ibcifclka x 3r oclka x 2r iclka x 1r xclka x 0 r sysclka x this register provides activity monitoring on s/uni-atlas-3200 clocks. when a monitored clock signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the clock activity bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read at periodic intervals to detect clock or dll failures. sysclka the system clock active (sysckla) bit monitors for low to high transitions on the sysclk input. sysclka is set high on a rising edge of sysclk, and is set low when this register is read. xclka the crystal clock active (xckla) bit monitors for low to high transitions on the xclk input. xclka is set high on a rising edge of xclk, and is set low when this register is read. iclka the input clock active (iclka) bit monitors for low to high transitions on the rlu_clk/tpu_clk/rlp_clk/tpp_clk input. iclka is set high on a rising edge of this clock, and is set low when this register is read. oclka the output clock active (oclka) bit monitors for low to high transitions on the rpu_clk/tlu_clk/rpp_clk/tlp_clk input. oclka is set high on a rising edge of this clock, and is set low when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 document id: pmc-1990553, issue 4 ibcifclka the input bcif clock active (ibcifclka) bit monitors for low to high transitions on the bi_clk input. ibcifclka is set high on a rising edge of this clock, and is set low when this register is read. obcifclka the output bcif clock active (obcifclka) bit monitors for low to high transitions on the bo_clk input. obcifclka is set high on a rising edge of this clock, and is set low when this register is read. halfsecclka the half second clock active (halfsecclka) bit monitors for low to high transitions on the halfsecclk input. halfsecclka is set high on a rising edge of this clock, and is set low when this register is read. rstdll: the reset delay locked loop register bit (rstdll) controls the resetting of the s/uni- atlas-3200 dll components. if this bit is logic 1, the sysclk, oclk, and iclk dll components will be reset. dllrun the delay locked loop run register bit (dllrun). when logic 1, this bit indicates that all dll components have locked to their input clocks. this bit is only valid when sysclk, icif_clk, and ocif_clk are running.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 document id: pmc-1990553, issue 4 11.3 microprocessor cell interface register 0x020: microprocessor cell interface control and status bit type function default 31:27 unused x 26 r insrdy x 25 w wrsoc 0 24 r/w phy[5] 0 23 r/w phy[4] 0 22 r/w phy[3] 0 21 r/w phy[2] 0 20 r/w phy[1] 0 19 r/w phy[0] 0 18 r/w proc_cell 0 17 r/w crc10 0 16 r/w insrst 0 15:6 unused x 5r rsoc 0 4 r extca x 3 w abort 0 2 w restart 0 1 r/w dmareqinv 0 0 r/w extrst 0 bits [15 0] cell extraction extrst the extrst is used to reset the microprocessor extract cell interface. when extrst is set to logic 0, the extract fifo operates normally. when extrst is logic 1, the extract fifo is immediately emptied and ignores writes. the extract fifo remains empty and continues to ignore writes until a logic 0 is written to extrst. while asserted, extrst overrides all other bits affecting the microprocessor extract cell interface. dmareqinv the dmareqinv bit inverts the polarity of the up_dmareq output. if dmareqinv is a logic 0, the up_dmareq output is active high. if dmareqinv is a logic 1, the up_dmareq output is active low.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 document id: pmc-1990553, issue 4 restart the restart cell read (restart) bit resets the microprocessor cell read pointer. if restart is set to logic 1 during a cell read, the next word read from the microprocessor cell data register will be the first word of the current cell. subsequent reads from the microprocessor cell data register return the remaining words of the cell. restart is not readable, and is cleared upon a read of the microprocessor cell data register. restart and abort should not be simultaneously asserted. abort the read abort (abort) bit allows the microprocessor to discard a cell without reading the contents. if abort is logic 1, the current cell being read is purged from the extract fifo and the dmareq output will be deasserted. abort is not readable, and is cleared upon a read of the microprocessor cell data register. abort and restart should not be simultaneously asserted. extca the microprocessor cell available (extca) status bit indicates that at least one cell is present in the cell extract buffer. extca is set to logic 1 when the last word of a cell is received. extca is cleared to logic 0 when the last word in the buffer is read by the microprocessor. if multiple cells exist in the buffer, then extca will remain at logic 1 until the last word of the last cell is read. assertion of the extca status bit also results in a maskable interrupt. rsoc the rsoc bit is logic 1 when the data in mcd[31:0] contains the first d-word (of 16) in a cell. this word will be part of the microprocessor cell info field if the cell_info_to_up bit is set in the cp configuration register. bits [31 16] cell insertion insrst the insrst bit is used to reset the microprocessor insert cell interface. when insrst is set to logic 0, the insert fifo operates normally. when insrst is set to logic 1, the insert fifo is immediately emptied and ignores writes. the insert fifo remains empty and continues to ignore writes until a logic 0 is written into insrst. any transfer from the insert fifo currently in progress will be aborted. while asserted, insrst overrides all other bits affecting the microprocessor insert cell interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 document id: pmc-1990553, issue 4 crc10 the crc10 bit forces the generation of the error detection code (edc) for cells written into the insert fifo. if crc10 is set to logic 1 prior to assembling the cell in the buffer, the last 10-bits of the cell are overwritten with the crc-10 value calculated over the information field (payload) of the cell. when crc10 is logic 1, the last 16 bits of the cell are typically written to zero, and the crc-10 replaces the 10 least significant bits. proc_cell the cell process enable (proc_cell) bit controls the processing of the current cell written into the insert fifo. if proc_cell was set to logic 1 prior to writing the cell in the buffer, the current is subject to all cell processing functions, just as if the cell had been inserted through the input cell interface. therefore, the header information and phyid must correspond to a provisioned vc, or the cell will be discarded. if proc_cell is logic 0, the current cell is passed to the output cell interface without modification, with the exception that appended bytes may be added or stripped off to ensure a correct cell length for the selected interface. the cell need not belong to a provisioned connection. the cell is not processed. phyid[5:0] the phy identification bits determine the phy association of the current cell being written by the microprocessor. the state of the phy[5:0] when the wrsoc is set selects the phy device for that cell: phy[5:0] = 000000, phy #1/single phy. phy[5:0] = 000001, phy #2 phy[5:0] = 000010, phy #3 ? phy[5:0] = 101111, phy #48. wrsoc the write start of cell (wrsoc) bit must identify the first word of the current cell that the microprocessor is writing. if wrsoc is logic 1, the next word written into the microprocessor cell data register becomes the first word of the cell. subsequent writes to the microprocessor cell data register fill the remainder of the cell sequentially, to a total of 16 writes. if wrsoc is set again before a complete cell is written, the existing contents will be overwritten without transmission. wrsoc is not readable.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 document id: pmc-1990553, issue 4 insrdy the insert buffer ready status (insrdy) bit indicates that the insert fifo is ready to accept another cell. insrdy is cleared once a full cell of 64 bytes has been written into the mcif. reassertion of the insrdy bit results in the assertion of a maskable interrupt.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 document id: pmc-1990553, issue 4 register 0x021: microprocessor cell data bit type function default 31 r/w mcd[31] x 30 r/w mcd[30] x 29 r/w mcd[29] x 28 r/w mcd[28] x 27 r/w mcd[27] x 26 r/w mcd[26] x 25 r/w mcd[25] x 24 r/w mcd[24] x 23 r/w mcd[23] x 22 r/w mcd[22] x 21 r/w mcd[21] x 20 r/w mcd[20] x 19 r/w mcd[19] x 18 r/w mcd[18] x 17 r/w mcd[17] x 16 r/w mcd[16] x 15 r/w mcd[15] x 14 r/w mcd[14] x 13 r/w mcd[13] x 12 r/w mcd[12] x 11 r/w mcd[11] x 10 r/w mcd[10] x 9 r/w mcd[9] x 8 r/w mcd[8] x 7 r/w mcd[7] x 6 r/w mcd[6] x 5 r/w mcd[5] x 4 r/w mcd[4] x 3 r/w mcd[3] x 2 r/w mcd[2] x 1 r/w mcd[1] x 0 r/w mcd[0] x
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 document id: pmc-1990553, issue 4 mcd[31:0] the mcd[31:0] contains the cell data destined to, or read from, the microprocessor cell interface. for the cell extract fifo, the extca bit and associated maskable interrupt indicate that a cell is available to be read. alternatively, the assertion of the dmareq output signals the presence of the cell. reads of this register return the words of the cell starting with the first. if necessary, the read pointer can be reset to the start of the current cell by setting the restart bit. alternatively, the read pointer can be reset to the start of the next cell by setting the abort bit. in a polled mode, the insrdy register bit indicates that the microprocessor may write another cell. for interrupt driven systems, the insrdyi interrupt status bit and associated maskable interrupt indicate that a cell may be written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 document id: pmc-1990553, issue 4 register 0x022: mcif dropped cells counter bit type function default 31:8 unused x 7:0 r dcount[7:0] x this register provides a count of cells dropped due to parity errors or fifo overflow. dcount[7:0] a write to this register or the s/uni-atlas-3200 identity/load counts register loads this register with the number of cells dropped by the omcif due fifo overflow since the last such write, and resets the internal counter to zero. the update is done in such a fashion that no events are missed if a counter reset and a dropped cell occur simultaneously. during this transfer, the tip bit in the s/uni-atlas-3200 identity/load counts register will be logic 1. the contents of this register are valid when the tip bit returns to logic 0. if this register is not polled regularly, the count value will saturate at 0xff.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 document id: pmc-1990553, issue 4 11.4 backward cell interface register 0x030: input backwards cell interface configuration bit type function default 31:5 unused x 4 r/w calevel0 0 3 r/w ibcif_drop_prty 0 2 r/w ibcif_even_prty 0 1 r/w ibcif_txslave 0 0r/w ibcifrst 1 calevel0 if calevel0 is logic 1, bi_clav is deasserted after the last word of the cell is transferred into the fifo. (i.e. the fifo is full). if calevel0 is logic 0, then bo_clav is deasserted 4 words before the end of the last cell that can be accepted, to indicate that the input bcif cannot accept another cell. ibcifrst the ibcifrst bit is used to reset the 16-cell input backwards cell interface fifo. when ibcifrst is set to logic zero, the fifo operates normally. when ibcifrst is set to logic one, the fifo is immediately emptied and ignores reads and writes. the fifo remains empty and continues to ignore reads and writes until a logic zero is written to ibcifrst. n.b. this fifo must be reset at startup. ibcif_txslave when this bit is a logic 0, then the input backwards cell interface is an rx master interface, and is configured to interact with another s/uni-atlas-3200 output backwards cell interface. when this bit is logic 1, the input backwards cell interface is a tx slave interface, and is configured to interact with a tester or asic. ibcif_even_prty when this bit is logic 1, the bi_par pin is expected to complete even parity for the bi_dat[15:0] bus. when it is logic 0, the bi_par pin is expected to complete odd parity for the bi_dat[15:0] bus.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 document id: pmc-1990553, issue 4 ibcif_drop_prty when this bit is logic 1, all cells written into the input bcif which have bad parity are discarded. when this bit is logic 0, cells written into the input bcif are not discarded due to parity errors. in any event, parity errors may be configured to cause interrupts by setting the ibprtye bit to logic 1 in the master interrupt enable #1 register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 document id: pmc-1990553, issue 4 register 0x031: ibcif dropped cells counter bit type function default 31:8 unused x 7:0 r dcount[7:0] x this register provides a count of cells dropped due to parity errors or fifo overflow. dcount[7:0] a write to this register, to the ibcif read cells counter, or the s/uni-atlas-3200 identity/load counts register loads this register with the number of cells dropped by the ibcif due to parity errors or fifo overflow since the last such write, and resets the internal counter to zero. the update is done in such a fashion that no events are missed if a counter reset and a dropped cell occur simultaneously. during this transfer, the tip bit in the s/uni- atlas-3200 identity/load counts register will be logic 1. the contents of this register are valid when the tip bit returns to logic 0; however, another transfer should not be requested for at least 100ns after tip returns to 0. if this register is not polled regularly, the count value will saturate at 0xff.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 document id: pmc-1990553, issue 4 register 0x032: ibcif read cells counter bit type function default 31:24 unused x 23:0 r ccount[23:0] x this register provides a count of all cells read out of the ibcif fifo. ccount[23:0] a write to this register, to the ibcif dropped cells counter, or the s/uni-atlas-3200 identity/load counts register loads this register with the number of cells read out of the ibcif since the last such write, and resets the internal counter to zero. the update is done in such a fashion that no events are missed if a counter reset and a dropped cell occur simultaneously. during this transfer, the tip bit in the s/uni-atlas-3200 identity/load counts register will be logic 1. the contents of this register are valid when the tip bit returns to logic 0; however, another transfer should not be requested for at least 100ns after tip returns to 0. if this register is not polled regularly, the count value will saturate at 0xffffff.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 document id: pmc-1990553, issue 4 register 0x038: output backwards cell interface configuration bit type function default 31:5 unused x 4 r/w calevel0 0 3r/w reserved 0 2 r/w obcif_even_prty 0 1r/w reserved 0 0r/w obcifrst 1 calevel0 if calevel0 is logic 1, bo_clav is deasserted after the last word of the fifo is transferrred (i.e. the fifo is empty). if calevel0 is logic 0, then bo_clav is deasserted 4 words before the end of the last cell to indicate that the output bcif cannot transfer another cell. obcifrst the obcifrst bit is used to reset the 16-cell output backwards cell interface fifo. when obcifrst is set to logic zero, the fifo operates normally. when obcifrst is set to logic one, the fifo is immediately emptied and ignores reads and writes. the fifo remains empty and continues to ignore reads and writes until a logic zero is written to obcifrst. n.b. this fifo must be reset at startup. obcif_even_prty when this bit is logic 1, the bo_par pin completes even parity for the bo_dat[15:0] bus. when it is logic 0, the bo_par pin completes odd parity for the bo_dat[15:0] bus. reserved the reserved bits must be programmed to logic 0 for correct operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 document id: pmc-1990553, issue 4 register 0x039: obcif dropped cells counter bit type function default 31:8 unused x 7:0 r dcount[7:0] x this register provides a count of cells dropped by the obcif due tofifo overflow. overflow of the obcif can only occur for loopback cells, and cells routed to the bcif via the vc_to_bcif function. rdi cells and bwd pm cells will be delayed and sent later if the obcif is full, and thus cannot be lost due to fifo overflow. the obcif is drained at the lesser of the opposite- direction backward cell interface pacing rate, and the capacity of the bcif link (approximately 1.3 million cells per second). dcount[7:0] a write to this register or the s/uni-atlas-3200 identity/load counts register loads this register with the number of cells dropped by the obcif due to fifo overflow since the last such write, and resets the internal counter to zero. the update is done in such a fashion that no events are missed if a counter reset and a dropped cell occur simultaneously. during this transfer, the tip bit in the s/uni-atlas-3200 identity/load counts register will be logic 1. the contents of this register are valid when the tip bit returns to logic 0; however, another transfer should not be requested for at least 100ns after tip returns to 0. if this register is not polled regularly, the count value will saturate at 0xff.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 document id: pmc-1990553, issue 4 register 0x03a: obcif read cells counter bit type function default 31:24 unused x 23:0 r ccount[23:0] x this register provides a count of all cells read out of the obcif fifo. ccount[23:0] a write to this register or the s/uni-atlas-3200 identity/load counts register loads this register with the number of cells read out of by the obcif since the last such write, and resets the internal counter to zero. the update is done in such a fashion that no events are missed if a counter reset and a dropped cell occur simultaneously. during this transfer, the tip bit in the s/uni-atlas-3200 identity/load counts register will be logic 1. the contents of this register are valid when the tip bit returns to logic 0; however, another transfer should not be requested for at least 100ns after tip returns to 0. if this register is not polled regularly, the count value will saturate at 0xffffff
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 document id: pmc-1990553, issue 4 register 0x040: sysclk delay locked loop register 1 bit type function default 31: 8 unused x 7 unused x 6 unused x 5 r/w func 0 4 r/w override 0 3 unused x 2 unused x 1 r/w vern_en 0 0r/w lock 0 the dll configuration register controls the basic operation of the dll. caution : the following register bits should not be changed after reset. modifying any of the default values can result in unpredictable or no operation at all. it is highly recommend that these register bits remain unchanged. lock the lock register is used to force the dll to ignore phase offsets indicated by the phase detector after the lock has been achieved. when lock is set to logic zero, the dll will track phase offsets measured by the phase detector between the rfclk and the reference clock inputs. when lock is set to logic one, the dll will not change the tap after the phase detector indicates of zero phase offset between the rfclk and the reference clock inputs for the first time. vern_en the vernier enable register (vern_en) forces the dll to ignore the phase detector and use the tap number specified by the vernier[7:0] register bits. when vern_en is set to logic zero, the dll operates normally adjusting the phase offset based on the phase detector. when vern_en is set to logic one, the delay line uses the tap specified by the vernier[7:0] register bits. override the override control (override) disables the dll operation. when override is set low, the dll generates the dllclk by delaying the rfclk until the rising edge of the reference clock occurs at the same time as the rising edge of rfclk. when override is set high, the dllclk output is a buffered version of the rfclk input. this feature provides a back-up strategy in case the dll does not operate correctly.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 document id: pmc-1990553, issue 4 func the functional control (func) is a multipurpose configuration signal for top-level uses. the tsb func output is high when func is set high. the tsb func output is low when func is set low.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 document id: pmc-1990553, issue 4 register 0x041: sysclk dll register 2 bit type function default 31:8 unused x 7 r/w vernier[7] 0 6 r/w vernier[6] 0 5 r/w vernier[5] 0 4 r/w vernier[4] 0 3 r/w vernier[3] 0 2 r/w vernier[2] 0 1 r/w vernier[1] 0 0 r/w vernier[0] 0 the vernier control register provides the delay line tap control when using the vernier option. vernier[7:0] the vernier tap register bits vernier[7:0] specifies the phase delay through the dll when using the vernier feature. when vern_en is set high, the vernier[7:0] registers specify the delay tap used. when vern_en is set low, the vernier[7:0] register is ignored. a vernier[7:0] value of all zeros specifies the delay tap with the minimum delay through the delay line. a vernier[7:0] value of all ones specifies the delay tap with the maximum delay through the delay line.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 document id: pmc-1990553, issue 4 register 0x042: sysclk dll register 3 bit type function default 31:8 unused x 7 r tap[7] x 6 r tap[6] x 5 r tap[5] x 4 r tap[4] x 3 r tap[3] x 2 r tap[2] x 1 r tap[1] x 0 r tap[0] x the dll delay tap status register indicates the delay tap used by the dll to generate the outgoing clock. writing to this register performs a software reset of the dll. tap[7:0] the tap status register bits tap[7:0] specifies the delay line tap the dll is using to generate the outgoing clock dllclk. when tap[7:0] is logic zero, the dll is using the delay line tap with minimum phase delay. when tap[7:0] is all logic one, the dll is using the delay line tap with maximum phase delay. tap[7:0] is invalid when vernier enable vern_en is set to one.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 document id: pmc-1990553, issue 4 register 0x043: sysclk dll register 4 bit type function default 31:8 unused x 7 r sysclki x 6r refclki x 5 r errori x 4 r changei x 3 unused x 2 r error x 1 r change 0 0 r run 0 the dll control status register provides information of the dll operation. run the dll lock status register bit run indicates the dll has found a delay line tap in which the phase difference between the rising edge of refclk and the rising edge of syslck is zero. after system reset, run is logic zero until the phase detector indicates an initial lock condition. when the phase detector indicates lock, run is set to logic 1. the run register bit is cleared only by a system reset or a software reset (writing to register 0x042). change the delay line tap change register bit change indicates the dll has moved to a new delay line tap. change is set high for eight sysclk cycles when the dll moves to a new delay line tap. changei the delay line tap change event register bit (changei) indicates the change register bit has changed value. when the change register changes from a logic zero to a logic one, the changei register bit is set to logic one. the changei register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. refclki the reference clock event register bit refclki provides a method to monitor activity on the reference clock. when the refclk primary input changes from a logic zero to a logic one, the refclki register bit is set to logic one. the refclki register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 document id: pmc-1990553, issue 4 sysclki the system clock event register bit syslcki provides a method to monitor activity on the system clock. when the sysclk primary input changes from a logic zero to a logic one, the sysclki register bit is set to logic one. the sysclki register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 document id: pmc-1990553, issue 4 register 0x048: iclk delay locked loop register 1 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x040 for a complete description. register 0x049: iclk dll register 2 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x041 for a complete description. register 0x04a: iclk dll register 3 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x042 for a complete description. register 0x04b: iclk dll register 4 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x043 for a complete description. register 0x050: oclk delay locked loop register 1 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x040 for a complete description. register 0x051: oclk dll register 2 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x041 for a complete description. register 0x052: oclk dll register 3 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x042 for a complete description. register 0x053: oclk dll register 4 the operation of this register is identical to the sysclk delay locked loop. refer to register 0x043 for a complete description.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 document id: pmc-1990553, issue 4 11.5 cell processor 11.5.1 general configuration and status register 0x100: cell processor configuration bit type function default 31:29 unused x 28 r/w copy_fwpm_timestamp 0 27 r/w gen_halfsecclk 0 26 r/w f4saisf5eais 0 25 r/w f4saisf5erdi 0 24 r/w f4eaisf5eais 0 23 r/w f4eaisf5srdi 0 22 r/w forcecc 0 21 r/w auto_ais 0 20 r/w cos_dram_err_en 0 19 r/w reserved 0 18 r/w cos_fail_en 0 17 r/w cos_fail_only 0 16 r/w cos_en 0 15 r/w sat_fast_pm_counts 0 14 r/w cro_fifo_en 0 13 r/w alternate_count 0 12 r/w vp_rm_pti6 0 11 r/w search_verify_en 1 10 r/w inact_on_dram_err 0 9 r/w sram_even_parity 0 8 r/w cell_info_to_ocif 0 7 r/w timeout_to_up 0 6r/w reserved 0 5 r/w cell_info_to_up 0 4r/w xgfc 0 3 r/w xudf 0 2r/w xhec 0 1r/w xprepo 0 0 r/w xvpivci 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 document id: pmc-1990553, issue 4 xvpivci if the xvpivci bit is logic 1, vpi/vci translation is globally enabled. the atm cell vpi/vci bytes can be replaced by the contents of the translated vpi and translated vci words of the vc table. if the gvpivci bit is logic 0, the incoming vpi/vci combination is passed transparently. note that if the connection is f4 (ie. vpc, where the vci field in the search key is coded as all zeros), then the vci is passed through transparently, and if the connection is at a uni, the translation of the gfc field is controlled by xgfc. xprepo if the xprepo bit is logic 1, substitution of prepend and postpend bytes is globally enabled. any prepend or postpend bytes of an atm cell are replaced by the contents of the translated pre/po1 and translated pre/po 2 words of the vc table. if xprepo is logic 0, prepend and postpend bytes pass through transparently. xhec if the xhec bit is logic 1, the hec field of an atm cell is replaced by the contents of the translated hec word of the vc table. if ghec is logic 0, the hec field of an atm cell is passed transparently. xudf if the xudf bit is logic 1, the udf field of an atm cell is replaced by the contents of the translated udf field in the vc table. if gudf is logic 0, the udf field of an atm cell is passed transparently. xgfc if the xgfc bit is logic 1 and the connection belongs to a uni, then the gfc field is replaced by the top 4 bits of the translated vpi field in the vc table. if xgfc is logic 0 and the connection belongs to a uni, the gfc field is passed through transparently. if the connection belongs to an nni, then this bit has no effect. cell_info_to_up the cell info to up bit allows the microprocessor cell info field to replace the two prepend/postpends of a cell extracted to the microprocessor interface. this allows an external microprocessor to immediately determine the reason a cell was routed to the microprocessor cell interface, the phy it was on, and the vc record that processed it.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 document id: pmc-1990553, issue 4 timeout_to_up when the timeout_to_up bit is logic 1, then cells from the bcif which are discarded, either because they timed out (see the backward cell interface pacing and head of line blocking register) or because their phy was declared to be inoperative (see the inoperative phy declaration period and indications register) will be routed to the microprocessor so they can be reinserted later. when timeout_to_up is logic 0, these cells will simply be dropped. cell_info_to_ocif if this bit is logic 1, then the microprocessor cell info field described in section 10.17.5 replaces the two prepend/postpends of cells sent to the output cell interface. this cell info word permits a device interpreting the cell to determine the cell?s source, phyid, its vc record address, what type of cell it is, and certain information about its connection. cell_info_to_ocif supercedes prepend/postpend translation (xprepo). note that cells inserted at the microprocessor with proc_cell set low, or cells received on phys with process_phy set to logic 0 will not be processed, and thus cell_info_to_ocif will not affect them. sram_even_parity if this bit is logic 1, the s/uni-atlas-3200 generates and checks even parity for the sram. if 0 the s/uni-atlas-3200 generates and checks odd parity. inact_on_dram_err when this bit is logic 1, then if a dram crc-10 violations is detected on any vc connection, that connection will be treated as inactive until its dram_crc_err bit is written back to logic 0. this ensures that an errored connection cannot route cells spuriously. all cells which experience dram crc errors will, in any case, be discarded. search_verify_en: the search verify enable bit controls whether or not the secondary search key is used as part of the cell confirmation step. if this bit is set to logic 1 then, after the vc search is complete, the secondary search key extracted from the cell is compared to the vpi, vci, and fieldb fields of the vc table. cells that fail this comparison will be dropped, and optionally routed to the microprocessor. cells which terminate on an f4 connection will not have the vci compared, and cells that terminate on uni connections will not have the 4 msbs of the vpi compared (they form the gfc field in a uni).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 document id: pmc-1990553, issue 4 if this bit is set to logic 0 then all cells with a valid primary key will be considered part of a valid connection. this bit will typically be set low if the cell is identified completely using only the primary key. vp_rm_pti6 the vp_rm_pti6 bit controls the identification of the vpc resource management (vp- rm) cells. if vp_rm_pti6 is a logic 0, vp-rm cells are identified by a vci=6, the pti field is ignored. if vp_rm_pti6 is a logic 1, vp-rm cells are identified by a vci=6 and a pti=110. if the pti field is not equal to 110, the cell is flagged as invalid and optionally can be routed to the microprocessor cell interface by the cell processor. alternate_count the alternate_count bit determines whether cell counting is done using the regular cell counts, or whether the alternate counts are used. this feature is intended for use in time-of- day billing. when alternate_count is set to logic 1, the regular cell counts cease incrementing, and the alternate counts increment instead. the regular cell counts may then be read and cleared at leisure. when alternate_count is set to logic 0, the alternate counts cease incrementing, and the regular counts increment instead, and the alternate counts may then be read and cleared at leisure. it is the responsibility of the management software to ensure the count locations are cleared before the s/uni-atlas-3200 begins incrementing at these locations. cro_fifo_en when the cro_fifo_en bit is logic 1, the count rollover fifo is enabled. generic, per- phy, policing, and pm counts in the cell processor which have their msbs set will generate entries into the count rollover fifo. this eliminates the need to periodically poll counts to prevent saturation. the count rollover fifo is separately enableable per-vc for billing counts, policing, per- pm session for pm, per-phy for phy policing counts, and globally for the per-phy cell counts. both the cro_fifo_en bit and the individual enable bits must be logic 1 for the cro fifo to be enabled for that group of counts. sat_fast_pm_counts the bip-16 errors count, and the counts of lost fwd and bwd pm cells in the pm table are 8-bit counts that can quickly accumulate value. as a result, it may be desirable to prevent them from generating count rollover entries, and simply to let them saturate. setting this bit to logic 1 causes these counts to never generate count rollover fifo entries.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 document id: pmc-1990553, issue 4 cos_en the change of state fifo enable (cos_en) bit enables the monitoring of changes in connection state. if cos_en is logic 1, all connections which undergo changes in state (i.e. ais, rdi or cc alarm states) can be logged in a change of state fifo. this fifo is 256 entries deep and holds a copy of the per-connection status field of the vc table. using this feature eliminates the need to periodically poll each connection to determine if any changes in state have occurred. if the cos fifo becomes full, background processes which monitor for changes in connection state will be suspended until such time as the fifo becomes able to accept notifications of changes in state. therefore, it is the responsibility of the management software to ensure the cos fifo is read often enough so that changes in state remain compliant with the bellcore and itu standards. if cos_en is logic 0, the cos fifo is disabled, and the background processes will not be suspended. if cos_en is logic 0, it is the responsibility of the management software to poll each connection to determine changes in connection state (as reflected in the status field of the vc table) and notify higher layers of any changes in state. the updating of the cos fifo can be enabled/disabled on a per-connection basis with the cos_fifo_enable bit of the configuration field of the vc table. cos_fail_only if the microprocessor has no need to know about changes of connection state unless they rise to the level of a service failure (i.e. an oam fault that persists for at least 4.5 +/- 0.5 seconds) then, by setting this bit to logic 1, it may permit changes of state to be written to the cos fifo only when the oam_fail bit changes state. when this bit is set to logic 0, entries will be made to the cos fifo, on connections for which it is enabled, if any of the oam alarms, changes state. in any event, the cos_dram_err_en controls whether dram crc errors cause cos entries. cos_fail_en when this bit is logic 1, changes on the oam_fail bit in the status field of a vc table entry will result in entries to the cos fifo, so long as the cos fifo is enabled both globally and for that vc. when this bit is logic 0, changes in the oam_fail bit will not result in cos fifo entries. reserved this bit should be programmed to logic 0. cos_dram_err_en when this bit is logic 1, a crc-10 error on the dram causes a change of state entry to be generated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 document id: pmc-1990553, issue 4 auto_ais the auto_ais bit enables the generation of segment or end-to-end ais cells while in a continuity alarm state. if auto_ais is logic 1, an ete ais cell is transmitted once per second if no user or cc cells have been received in the last 3.5 +/- 0.5 seconds. segment ais cells will also be generated if the segmentflow bit for the connection is logic 1. automatic ais generation is enableable on a per-vc basis via the cc_ais_rdi bit. ais cells can also be transmitted if the send_ais_segment and send_ais_end_to_end bits in the vc table are set. forcecc the forcecc bit controls whether or not the insertion of cc cells is dependent on the user cell traffic. if forcecc is logic 0, cc cells are only generated if the cc_activate_segment or cc_activate_end_to_end per-connection bits are logic 1 and if no user cells have been transmitted within one second (nominal). if forcecc is logic 1, cc cells are generated at a rate of once per second (nominal) if the cc_activate_segment or cc_activate_end_to_end bits are logic 1. f4eaisf5srdi the f4eaisf5srdi register bit controls the generation of f5 segment rdi cells upon the reception of an f4 end-to-end ais cell. when this bit is logic 1, a segment vc-rdi cell will be generated when an end-to-end vpc-ais cell is terminated at a vpc end-to-end point and an associated vcc segment end-point is switched from that vpc. if this bit is logic 0, a segment vc-rdi cell will not be generated in this circumstance. f4eaisf5eais the f4eaisf5eais register bit controls the generation of f5 end-to-end ais cells upon the reception of an f4 end-to-end ais cell. when this bit is logic 1, an end-to-end vc-ais cell will be generated when an end-to-end vpc-ais cell is terminated at a vpc end-to-end point, and an associated vcc segment end-point is switched from that vpc. if this bit is logic 0, an end-to-end vc-ais cell will not be generated in this circumstance. f4saisf5erdi the f4saisf5erdi register bit controls the generation of f5 end-to-end rdi cells upon the reception of an f4 segment ais cell. if this bit is logic 1, an end-to-end vc-rdi cell will be generated when a segment vpc-ais cell is terminated at a vpc segment end-point, and the vcc is also an end-to-end point. if this bit is logic 0, an end-to-end vc-rdi cell will not be generated in this circumstance.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 document id: pmc-1990553, issue 4 f4saisf5eais the f4saisf5eais register bit controls the generation of f5 end-to-end ais cells upon the reception of an f4 segment ais cell. if this bit is logic 1, an end-to-end vc-ais cell will be generated when a segment vpc-ais cell is terminated at a vpc segment end-point. if this bit is logic 0, an end-to-end ais cell will not be generated in this circumstance. gen_halfsecclk the gen_halfsecclk bit determines the trigger for processing that relies on background processing, such as ais, rdi and cc cell generation. if the gen_halfsecclk is a logic 1, the 0.5 second clock is derived from sysclk, which is assumed to be 125 mhz. if gen_halfsecclk is a logic 0, processing is initiated on the rising edge of the halfsecclk input. copy_fwpm_timestamp when the copy_fwpm_timestamp bit is logic 1, then when a bwd pm cell is generated to the bcif immediately upon reception of a fwd pm cell (i.e. the bcif is not full when the fwd pm cell arrives) then the timestamp of the generated bwd pm cell is set equal to the timestamp of the fwd pm cell. if the bcif is full when the fwd pm cell arrives, or if this bit is logic 0, then the timestamp of the bwd pm cell is set to the default all-ones.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 document id: pmc-1990553, issue 4 register 0x101: cell processor routing configuration bit type function default 31 r/w lbtoocif 0 30 r/w apstobcif 0 29 r/w apstoocif 0 28 r/w reserved 0 27 r/w rtd_lb_to_up_at_end 0 26 r/w xlate_from_ibcif 1 25 r/w ibcif_p2_to_p1 0 24 r/w ibcif_p2_to_hecudf 0 23 r/w xlate_to_obcif 0 22 r/w obcif_cell_info 1 21 r/w obcif_bwd_vcra 1 20 r/w obcif_phyid 1 19 r/w sysmantobcif 0 18 r/w sysmantoup 0 17 r/w sysmantoocif 0 16 r/w undeftobcif 0 15 r/w undeftoup 0 14 r/w undeftoocif 0 13 r/w actdetobcif 0 12 r/w actdetoup 0 11 r/w actdetoocif 0 10 r/w crc10toup 0 9 r/w dropcrceoam 0 8 r/w inactivetoup 0 7 r/w invptivcitoup 0 6 r/w dropinvptivci 0 5 r/w badvctoup 0 4 r/w dropcrcerm 0 3 r/w droprm 0 2 r/w rmtobcif 0 1r/w rmtoup 0 0r/w pmtoup 0 pmtoup if this bit is logic 1, all performance management oam cells are copied to the microprocessor cell interface at flow end-points. regardless of the state of this bit, all pm oam cells are output to the output cell interface if the s/uni-atlas-3200 is not an end- point for that connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 document id: pmc-1990553, issue 4 rmtoup if the rmtoup bit is logic 1, all rm cells are copied to the microprocessor cell interface. rm cells are identified pti=110 for vc-rm cells and by vci=6 for vp-rm cells. if the vp_rm_pti6 register bit is logic 1, vp-rm cells are further qualified by pti=110. rmtobcif if the rmtobcif bit is logic 1, all rm cells are copied to the backwards cell interface. rm cells are identified pti=110 for vc-rm cells and by vci=6 for vp-rm cells. if the vp_rm_pti6 register is logic 1, vp-rm cells are further qualified by pti=110. droprm if the droprm bit is logic 1, all rm cells are dropped (i.e. not passed to the ocif) though they may be passed to the mcif or bcif based on the rmtobcif and rmtoup register bits. rm cells are identified pti=110 for vc-rm cells and by vci=6 for vp-rm cells. if the vp_rm_pti6 register bit of the search engine configuration configuration register is logic 1, vp-rm cells are further qualified by pti=110. dropcrcerm if this bit is logic 1, all forward and backward rm cells with an incorrect crc-10 are discarded. if this bit is logic 0, then all forward and backward rm cells are output to the output cell interface regardless of whether their crc-10 is correct or not. badvctoup if the badvctoup bit is logic 1, all cells with an unprovisioned vpi/vci are dropped and routed to the microprocessor cell interface. if this bit is logic 0, those cells are discarded by the s/uni-atlas-3200 without being routed to the microprocessor cell interface. dropinvptivci if this bit is logic 1, all f5 (vcc) cells with pti=111 and all f4 (vpc) cells with a vci of 7 through 15 are not routed to the output cell interface. if dropinvptivci is logic 0, these cells are passed transparently. invptivcitoup if the invptivcitoup bit is logic 1, all f5 (vcc) cells with an invalid pti field (pti=111) and all f4 (vpc) cells with an invalid vci field (vci 7 through 15) are copied to the microprocessor cell interface. the dropinvptivci register bit determines whether cells with invalid pti or vci fields are passed to the output cell interface.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 document id: pmc-1990553, issue 4 inactivetoup when inactivetoup is logic 1, all cells received on connections whose active bit is logic 0 in the vc table (as well as cells received on connections that have their dram_crc_err bit logic 1 if the inact_on_dram_err register bit is logic 1, and all cells whose connections have misconfigured vpc pointers) are copied to the microprocessor cell interface. regardless of the state of this bit, all cells received on inactive connections are dropped by the cp (i.e. not sent to the output cell interface). dropcrceoam if the dropcrceoam bit is logic 1, all oam cells with an errored crc-10 are dropped (i.e. not routed to the output cell interface). regardless of the state of this bit, if the s/uni- atlas-3200 is a flow end-point, all oam cells with an errored crc-10 are dropped. crc10toup if the crc10toup bit is logic 1, all oam cells or rm cells with an errored crc-10 are copied to the microprocessor cell interface. regardless of the state of this bit, the dropcrceoam and dropcrcerm bits determine whether or not the s/uni-atlas- 3200 will route errored oam and rm cells, respectively, to the output cell interface. actdetoocif if the actdetoocif bit is logic 1, all activate/deactivate cells are routed to the output cell interface. if actdetoocif is logic 0, then at flow end points, all activate/deactivate cells are dropped. regardless of the state of this bit, all activate/deactivate cells are routed to the output cell interface if the s/uni-atlas-3200 is not a flow end point for that connection. actdetoup if the actdetoup bit is logic 1, all activate/deactivate oam cells are copied to the microprocessor cell interface at flow end-points. if the s/uni-atlas-3200 is not a flow end-point for the connection, the activate/deactivate cells are not copied to the microprocessor cell interface. regardless of the state of this bit, all activate/deactivate cells are passed to the output cell interface if the s/uni-atlas-3200 is not an end point for that connection. actdetobcif if the actdetobcif bit is logic 1, all activate/deactivate oam cells are copied to the backwards cell interface at flow end-points. if the s/uni-atlas-3200 is not a flow end- point for the connection, the activate/deactivate cells are not copied to the backwards cell interface. regardless of the state of this bit, all activate/deactivate cells are passed to the output cell interface if the s/uni-atlas-3200 is not an end point for that connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 document id: pmc-1990553, issue 4 undeftoocif if the undeftoocif bit is logic 1, all oam cells with an undefined oam type or function type value are copied to the output cell interface at flow end-points. regardless of the state of this bit, all oam cells with an undefined oam type or function type value are output to the output cell interface if the s/uni-atlas-3200 is not an end point for that connection. undeftoup if the undeftoup bit is logic 1, all oam cells with an undefined oam type or function type value are copied to the microprocessor cell interface at flow end-points. regardless of the state of this bit, all oam cells with an undefined oam type or function type value are output to the output cell interface if the s/uni-atlas-3200 is not an end point for that connection. undeftobcif if the undeftobcif bit is logic 1, all oam cells with an undefined oam type or function type value are copied to the backwards cell interface at flow end-points. regardless of the state of this bit, all oam cells with an undefined oam type or function type value are output to the output cell interface if the s/uni-atlas-3200 is not an end point for that connection. sysmantoocif if the sysmantoocif bit is logic 1, all system management cells are routed to the output cell interface. if the sysmantoocif is logic 0, then at flow end-points, all system management cells are dropped. regardless of the state of this bit, all system management cells are routed to the output cell interface if the s/uni-atlas-3200 is not a flow end-point for that connection. sysmantoup if this bit is logic 1, all system management oam cells are copied to the microprocessor cell interface at flow end-points. regardless of the state of this bit, all system management oam cells are output to the output cell interface if the s/uni-atlas-3200 is not an end- point for that connection. sysmantobcif if this bit is logic 1, all system management oam cells are copied to the backwards cell interface at flow end-points. regardless of the state of this bit, all system management oam cells are output to the output cell interface if the s/uni-atlas-3200 is not an end- point for that connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 document id: pmc-1990553, issue 4 obcif_phyid if this bit is logic 1, then the phyid field of the vc linkage table overwrites a portion of the prepended bytes of cells routed to the output backwards cell interface, as shown in table 38. if this bit is logic 0, then these bits will not be overwritten, but cells sent to the obcif will not be able to be correctly reinserted by an s/uni-atlas-3200 input bcif. obcif_bwd_vcra if this bit is logic 1, then the backwards direction vcra field of the vc table overwrites a portion of the prepended bytes of cells routed to the output backwards cell interface, as shown in table 38. if this bit is logic 0, then these bits will not be overwritten, but cells sent to the obcif must be able to be searched correctly by the receiving s/uni-atlas-3200. obcif_cell_info if this bit is logic 1, then 9 bits of information about the cell and its associated connection overwrite a portion of the prepended bytes of cells routed to the output backwards cell interface, as shown in table 38 and table 39. if this bit is logic 0, then these bits will not be overwritten. xlate_to_obcif if this bit is logic 1, then cells routed to the output backwards cell interface will be header- translated as if they were destined to the output cell interface, i.e. as controlled by the xvpivci, xprepo, xhec, xudf, and cell_info_to_ocif bits. the obcif_cell_info, obcif_phyid, and obcif_bwd_vcra bits will still cause overwriting of portions of the cell. this bit is normally logic 1 when the search_from_ibcif bit is logic 1. when this bit is logic 0, cells routed to the output bcif are not translated, and cells generated to the output bcif carry the vpi and vci programmed into the vpi and vci fields of the vc table. ibcif_p2_to_hecudf when this bit is logic 1, then all cells from the input backwards cell interface will have the prepend/postpend 2 word of the vc table inserted into their hec and udf. this feature is used if the hec and udf are used as a routing word or identification tag, and cells from the ibcif require different treatment from cells from the input cell interface. this bit will overwrite changes made via the xlate_from_ibcif bit. ibcif_p2_to_p1 when this bit is logic 1, then all cells from the input backwards cell interface will have the prepend/postpend 2 word of the vc table inserted into their prepend/postpend 1. this feature is used if the first prepend/postpend word is used as a routing word or identification tag, and cells from the ibcif require different treatment from cells from the input cell interface. this bit will overwrite changes made via the xlate_from_ibcif bit.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 document id: pmc-1990553, issue 4 xlate_from_ibcif when this bit is logic 1, then all cells from the input backwards cell interface are translated as if they came from the input cell interface, i.e. as controlled by the xvpivci, xprepo, xhec, and xudf, and cell_info_to_ocif bits. this is the default choice. when this bit is logic 0, no header translation is performed on cells from ibcif except as specified by ibcif_p2_to_hecudf and ibcif_p2_to_p1. reserved this function is not supported. rtd_lb_to_up_at_end when this bit is logic 1, then on connections with lb_route = ?01? or ?10?, returned loopback cells are routed to the microprocessor at flow end points whether or not the source id of the rtd lb cell matches the value programmed in the loopback id registers. when this bit is logic 0, returned loopback cells are routed to the micro only if the source id in the cell matches the value programmed in the loopback id registers. apstoocif when apstoocif is logic 1, aps coordination protocol cells are not dropped at oam flow end-points. when apstoocif is logic 0, aps cells are dropped at flow end-points like other oam cells. aps cells may be copied to the microprocessor cell interface or bcif on a per- vc basis via the apstoup bit in the vc configuration field of the vc table, and the apstobcif bit in this register. apstobcif if the apstobcif bit is logic 1, then for those connections which the apstoup bit is set to logic 1 in the vc table configuration field, the aps cells will be routed to the bcif instead of to the microprocessor. lbtoocif when lbtoocif is logic 1, loopback cells are not dropped at flow end-points or due to lb_route functionalitybut will be passed to the ocif. when lbtoocif is logic 0, all loopback cells are dropped at flow end-points. regardless of the setting of this bit, the routing of loopback cells to mcif and bcif is controlled by the lb_route[1:0] bits in the vc table oam configuration field. this bit is intended to be used when an external device is handling the oam-lb function.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 document id: pmc-1990553, issue 4 register 0x102: cell counting configuration bit type function default 31 r/w cfg2_count2[7] 0 30 r/w cfg2_count2[6] 0 29 r/w cfg2_count2[5] 0 28 r/w cfg2_count2[4] 0 27 r/w cfg2_count2[3] 0 26 r/w cfg2_count2[2] 0 25 r/w cfg2_count2[1] 0 24 r/w cfg2_count2[0] 0 23 r/w cfg2_count1[7] 0 22 r/w cfg2_count1[6] 0 21 r/w cfg2_count1[5] 0 20 r/w cfg2_count1[4] 0 19 r/w cfg2_count1[3] 0 18 r/w cfg2_count1[2] 0 17 r/w cfg2_count1[1] 0 16 r/w cfg2_count1[0] 0 15 r/w cfg1_count2[7] 0 14 r/w cfg1_count2[6] 0 13 r/w cfg1_count2[5] 0 12 r/w cfg1_count2[4] 0 11 r/w cfg1_count2[3] 0 10 r/w cfg1_count2[2] 0 9 r/w cfg1_count2[1] 0 8 r/w cfg1_count2[0] 0 7 r/w cfg1_count1[7] 0 6 r/w cfg1_count1[6] 0 5 r/w cfg1_count1[5] 0 4 r/w cfg1_count1[4] 0 3 r/w cfg1_count1[3] 0 2 r/w cfg1_count1[2] 0 1 r/w cfg1_count1[1] 0 0 r/w cfg1_count1[0] 0 the cfg1 bits are used when the count config select bit in the vc table is set to logic 0. the cfg2 bits are used when the count config select bit in the vc table is set to logic 1. these bits apply to both the cell counts and the alternate cell counts.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 document id: pmc-1990553, issue 4 count1[7:0] the count1[7:0] controls which cells the cell processor includes in its first per-connection 32-bit cell count. the count1[7:0] field is programmed as follows: cell type user cells oam cells rm cells invalid pti/vci clp bit10101010 register bit count1 [7] count1 [6] count1 [5] count1 [4] count1 [3] count1 [2] count1 [1] count1 [0] a logic 1 written to any of the count1[7:0] bits enables counting on that particular stream. for example, to enable counting of clp=0+1 user and oam cells only, the register configuration would be count1[7:0] = 0xf0. if count1[7:0] = 0x00, the first generic cell count for all connections is disabled. oam and rm cells include those with invalid crc-10s. invalid pti/vci cells include f5 cells with pti = ?111?, f4 cells with vci = 0, f4 cells with vci = 7 through 15, and (if vp_rm_pti6 is set to logic 1 in the routing configuration register) f4 rm cells which have pti not equal to ?110?. note that cells which cannot reliably be identified with a particular connection (those that suffer utopia parity errors and failed searches) and cells that are generated by s/uni-atlas-3200 are not counted at all. count2[7:0] the count2[7:0] register bits controls which cells the cell processor includes in its second per-connection 32-bit cell count. the count2[7:0] field is programmed exactly the same as the count1[7:0] field.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 document id: pmc-1990553, issue 4 register 0x104: backward cell interface pacing and head of line blocking bit type function default 31 r/w bhbto[15] 0 30 r/w bhbto[14] 0 29 r/w bhbto[13] 0 28 r/w bhbto[12] 0 27 r/w bhbto[11] 0 26 r/w bhbto[10] 0 25 r/w bhbto[9] 0 24 r/w bhbto[8] 0 23 r/w bhbto[7] 0 22 r/w bhbto[6] 0 21 r/w bhbto[5] 0 20 r/w bhbto[4] 0 19 r/w bhbto[3] 0 18 r/w bhbto[2] 0 17 r/w bhbto[1] 0 16 r/w bhbto[0] 0 15 r/w bcp[15] 0 14 r/w bcp[14] 0 13 r/w bcp[13] 0 12 r/w bcp[12] 0 11 r/w bcp[11] 0 10 r/w bcp[10] 0 9 r/w bcp[9] 0 8 r/w bcp[8] 0 7 r/w bcp[7] 0 6 r/w bcp[6] 0 5 r/w bcp[5] 1 4 r/w bcp[4] 0 3 r/w bcp[3] 0 2 r/w bcp[2] 0 1 r/w bcp[1] 0 0 r/w bcp[0] 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 document id: pmc-1990553, issue 4 bcp[15:0] bcp[15:0] sets the number of cell interval between transfers of cells from the input backward cell interface (ibcif). the minimum rate of transfer is 1 in 65535 cell intervals. when bcp[15:0] = 0x0000 back-to-back transfer from the backward cell interface is possible, if there are no transfer requested from the input cell interface or the microprocessor cell interface. the default is set to 1 in 32 cell intervals. a cell interval is 22 sysclk cycles. bhbto[15:0] bhbto[15:0] sets the timeout limit, in cell intervals, before a cell at the head of the backward cell interface fifo is discarded. this is to prevent a malfunctioning phy holding a backward reporting pm cell or rdi cell at the head of the fifo, thus blocking all others cells that follow. default is set to all zeros, which disables this timeout feature. a cell interval is 22 sysclk cycles.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 document id: pmc-1990553, issue 4 register 0x105: per-phy processing enable 1 bit type function default 31 r/w processphy[31] 1 30 r/w processphy[30] 1 29 r/w processphy[29] 1 28 r/w processphy[28] 1 27 r/w processphy[27] 1 26 r/w processphy[26] 1 25 r/w processphy[25] 1 24 r/w processphy[24] 1 23 r/w processphy[23] 1 22 r/w processphy[22] 1 21 r/w processphy[21] 1 20 r/w processphy[20] 1 19 r/w processphy[19] 1 18 r/w processphy[18] 1 17 r/w processphy[17] 1 16 r/w processphy[16] 1 15 r/w processphy[15] 1 14 r/w processphy[14] 1 13 r/w processphy[13] 1 12 r/w processphy[12] 1 11 r/w processphy[11] 1 10 r/w processphy[10] 1 9 r/w processphy[9] 1 8 r/w processphy[8] 1 7 r/w processphy[7] 1 6 r/w processphy[6] 1 5 r/w processphy[5] 1 4 r/w processphy[4] 1 3 r/w processphy[3] 1 2 r/w processphy[2] 1 1 r/w processphy[1] 1 0 r/w processphy[0] 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 document id: pmc-1990553, issue 4 processphy[31:0] if the processphy bit for a particular phy is logic 0, then cells from that phy will not be searched or processed, and will be passed through the s/uni-atlas-3200 unrecorded and untouched, except for the phy mapping functions, and adjustments to the length of the cells (i.e. deleting prepends, postpends, and the hec/udf, or adding indeterminate data in these positions). if the processphy bit is logic 1, then cells from that phy are processed normally. this feature is typically used when cells from a certain phy are to be processed in another device, such as another s/uni-atlas-3200. this allows multiple s/uni-atlas-3200s to be cascaded, each handling cells from some of the phys. this can be used to support more than 64k vcs in total.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 document id: pmc-1990553, issue 4 register 0x106: per-phy processing enable 2 bit type function default 31 unused 30 unused 29 unused 28 unused 27 unused 26 unused 25 unused 24 unused 23 unused 22 unused 21 unused 20 unused 19 unused 18 unused 17 unused 16 unused 15 r/w processphy[47] 1 14 r/w processphy[46] 1 13 r/w processphy[45] 1 12 r/w processphy[44] 1 11 r/w processphy[43] 1 10 r/w processphy[42] 1 9 r/w processphy[41] 1 8 r/w processphy[40] 1 7 r/w processphy[39] 1 6 r/w processphy[38] 1 5 r/w processphy[37] 1 4 r/w processphy[36] 1 3 r/w processphy[35] 1 2 r/w processphy[34] 1 1 r/w processphy[33] 1 0 r/w processphy[32] 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 document id: pmc-1990553, issue 4 processphy[32:47] if the processphy bit for a particular phy is logic 0, then cells from that phy will not be searched or processed, and will be passed through the s/uni-atlas-3200 unrecorded and untouched, except for the phy mapping functions, and adjustments to the length of the cells (i.e. deleting prepends, postpends, and the hec/udf, or adding indeterminate data in these positions). if the processphy bit is logic 1, then cells from that phy are processed normally. this feature is typically used when cells from a certain phy are to be processed in another device, such as another s/uni-atlas-3200. this allows multiple s/uni-atlas-3200s to be cascaded, each handling cells from some of the phys. this can be used to support more than 64k vcs in total.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 document id: pmc-1990553, issue 4 register 0x107: ais/cc pacing and head of line blocking bit type function default 31 r/w aisccto[15] 0 30 r/w aisccto[14] 0 29 r/w aisccto[13] 0 28 r/w aisccto[12] 0 27 r/w aisccto[11] 0 26 r/w aisccto[10] 0 25 r/w aisccto[9] 0 24 r/w aisccto[8] 0 23 r/w aisccto[7] 0 22 r/w aisccto[6] 0 21 r/w aisccto[5] 0 20 r/w aisccto[4] 0 19 r/w aisccto[3] 0 18 r/w aisccto[2] 0 17 r/w aisccto[1] 0 16 r/w aisccto[0] 0 15 r/w aisccp[15] 0 14 r/w aisccp[14] 0 13 r/w aisccp[13] 0 12 r/w aisccp[12] 0 11 r/w aisccp[11] 0 10 r/w aisccp[10] 0 9 r/w aisccp[9] 0 8 r/w aisccp[8] 0 7 r/w aisccp[7] 0 6 r/w aisccp[6] 0 5 r/w aisccp[5] 1 4 r/w aisccp[4] 0 3 r/w aisccp[3] 0 2 r/w aisccp[2] 0 1 r/w aisccp[1] 0 0 r/w aisccp[0] 0 aisccp[15:0] aisccp[15:0] sets the number of cell intervals between the insertion of consecutive ais or cc cells into the cell stream. the minimum rate of transfer is 1 in 65535 cell intervals. when aisccp[15:0] = 0x0000 back-to-back ais or cc cells are possible, if there are no cells from the input cell interface or the microprocessor cell interface. the default is set to 1 in 32 cell intervals.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 document id: pmc-1990553, issue 4 aisccto[15:0] aisccto[15:0] sets the timeout limit, in cell periods, before an ais or cc cell being inserted by a background process is discarded. this is to prevent a malfunctioning phy from causing the background process to wait indefinitely to insert an ais or cc, thus blocking all other connections from inserting ais or cc cells. default is set to all zeros, which disables this timeout feature.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 document id: pmc-1990553, issue 4 register 0x108: fwd pm pacing and head of line blocking bit type function default 31 r/w fpmto[15] 0 30 r/w fpmto[14] 0 29 r/w fpmto[13] 0 28 r/w fpmto[12] 0 27 r/w fpmto[11] 0 26 r/w fpmto[10] 0 25 r/w fpmto[9] 0 24 r/w fpmto[8] 0 23 r/w fpmto[7] 0 22 r/w fpmto[6] 0 21 r/w fpmto[5] 0 20 r/w fpmto[4] 0 19 r/w fpmto[3] 0 18 r/w fpmto[2] 0 17 r/w fpmto[1] 0 16 r/w fpmto[0] 0 15 r/w fpmp[15] 0 14 r/w fpmp[14] 0 13 r/w fpmp[13] 0 12 r/w fpmp[12] 0 11 r/w fpmp[11] 0 10 r/w fpmp[10] 0 9r/w fpmp[9] 0 8r/w fpmp[8] 0 7r/w fpmp[7] 0 6r/w fpmp[6] 0 5r/w fpmp[5] 1 4r/w fpmp[4] 0 3r/w fpmp[3] 0 2r/w fpmp[2] 0 1r/w fpmp[1] 0 0r/w fpmp[0] 0 fpmp[15:0] fpmp[15:0] sets the number of cell intervals between the insertion of consecutive forward pm cells into the cell stream. the minimum rate of transfer is 1 in 65535 cell intervals. when fpmp[15:0] = 0x0000 back-to-back fwd pm cells are possible, though unlikely. the default is set to 1 in 32 cell intervals.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 document id: pmc-1990553, issue 4 fpmto[15:0] fpmto[15:0] sets the timeout limit, in cell periods, before a forward pm cell being inserted into the cell flow is discarded. this is to prevent a malfunctioning phy from blocking all other connections from inserting fwd pm cells. default is set to all zeros, which disables this timeout feature.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 document id: pmc-1990553, issue 4 register 0x109: inoperative phy declaration period and indications bit type function default 31 r deadphy[15] 0 30 r deadphy[14] 0 29 r deadphy[13] 0 28 r deadphy[12] 0 27 r deadphy[11] 0 26 r deadphy[10] 0 25 r deadphy[9] 0 24 r deadphy[8] 0 23 r deadphy[7] 0 22 r deadphy[6] 0 21 r deadphy[5] 0 20 r deadphy[4] 0 19 r deadphy[3] 0 18 r deadphy[2] 0 17 r deadphy[1] 0 16 r deadphy[0] 0 15 r/w deadphyto[15] 0 14 r/w deadphyto[14] 0 13 r/w deadphyto[13] 0 12 r/w deadphyto[12] 0 11 r/w deadphyto[11] 0 10 r/w deadphyto[10] 0 9 r/w deadphyto[9] 0 8 r/w deadphyto[8] 0 7 r/w deadphyto[7] 0 6 r/w deadphyto[6] 0 5 r/w deadphyto[5] 0 4 r/w deadphyto[4] 0 3 r/w deadphyto[3] 0 2 r/w deadphyto[2] 0 1 r/w deadphyto[1] 0 0 r/w deadphyto[0] 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 document id: pmc-1990553, issue 4 deadphyto[15:0] deadphyto sets the number of cell periods before a phy which has cells available for it, but which does not accept any cells whatsoever, is declared inoperative. inoperative phys automatically have any ais, cc, fwd pm, or cells from the bcif or mcif discarded, to avoid head-of-line blocking problems resulting from repeatedly waiting for these cells to time out. once the phy accepts even a single cell, the inoperative declaration is removed. the dead phy timeout field defaults to 0, which disables this feature. deadphy[15:0] when a phy is declared inoperative as per the setting of deadphyto, the corresponding deadphy bit is set to logic 1. an optional interrupt (deadphyi) is declared. phys which are not configured in the osdq will be declared dead shortly after startup. the resulting interrupt should be cleared, allowing subsequent declarations on configured phys to generate an interrupt.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 document id: pmc-1990553, issue 4 register 0x10a: inoperative phy indications bit type function default 31 r deadphy[47] 0 30 r deadphy[46] 0 29 r deadphy[45] 0 28 r deadphy[44] 0 27 r deadphy[43] 0 26 r deadphy[42] 0 25 r deadphy[41] 0 24 r deadphy[40] 0 23 r deadphy[39] 0 22 r deadphy[38] 0 21 r deadphy[37] 0 20 r deadphy[36] 0 19 r deadphy[35] 0 18 r deadphy[34] 0 17 r deadphy[33] 0 16 r deadphy[32] 0 15 r deadphy[31] 0 14 r deadphy[30] 0 13 r deadphy[29] 0 12 r deadphy[28] 0 11 r deadphy[27] 0 10 r deadphy[26] 0 9 r deadphy[25] 0 8 r deadphy[24] 0 7 r deadphy[23] 0 6 r deadphy[22] 0 5 r deadphy[21] 0 4 r deadphy[20] 0 3 r deadphy[19] 0 2 r deadphy[18] 0 1 r deadphy[17] 0 0 r deadphy[16] 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 218 document id: pmc-1990553, issue 4 deadphy[47:16] when a phy is declared inoperative as per the setting of deadphyto, the corresponding deadphy bit is set to logic 1. an optional interrupt (deadphyi) is declared. phys which are not configured in the osdq will be declared dead shortly after startup. the resulting interrupt should be cleared, allowing subsequent declarations on configured phys to generate an interrupt.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 219 document id: pmc-1990553, issue 4 11.5.2 search register 0x10b: search engine configuration bit type function default 31 : 27 unused x 26 r/w search_from_ibcif 0 25 r/w lphy[2] 0 24 r/w lphy[1] 0 23 r/w lphy[0] 0 22 r/w la[4] 0 21 r/w la[3] 0 20 r/w la[2] 0 19 r/w la[1] 0 18 r/w la[0] 0 17 r/w starta[6] 0 16 r/w starta[5] 0 15 r/w starta[4] 0 14 r/w starta[3] 0 13 r/w starta[2] 0 12 r/w starta[1] 0 11 r/w starta[0] 0 10 r/w lb[3] 0 9r/w lb[2] 0 8r/w lb[1] 0 7r/w lb[0] 0 6 r/w startb[6] 0 5 r/w startb[5] 0 4 r/w startb[4] 0 3 r/w startb[3] 0 2 r/w startb[2] 0 1 r/w startb[1] 0 0 r/w startb[0] 0 search_from_ibcif when this bit is a logic 1, cells from the input backwards cell interface are searched by the search engine as if they were from the input cell interface. when this bit is logic 0, the cells are assumed to carry the 16-bit vc record address to which they belong in prepended bytes, as shown in table 38. in any event, the cells must carry the phyid as shown in table 38.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 220 document id: pmc-1990553, issue 4 lphy[2:0] the contents of lphy[2:0] determine the number of phy id bits in the primary search key. if less than all six phy address lines should be considered during the key search (as in the case where only a single phy interface is used) then lphy[2:0] must be programmed with the values below. lphy[2] lphy[1] lphy[0] number of phy id bits in primary key 1 1 1 reserved 11 0 6 1 0 1 5 (lsb?s) 1 0 0 4 (lsb?s) 0 1 1 3 (lsb?s) 0 1 0 2 (lsb?s) 0 0 1 1 (lsb) 0 0 0 0 (single phy interface) starta[6:0] starta[6:0] forms the binary address of the msb of the field a within the routing word. starta[6] is the msb of the address. la[4:0] la[4:0] gives the length of the field a in bits. the length is stored in la[4:0] as binary value with la[4] as msb. if no field a is to be used then la[4:0] should be set to ?00000?. valid values for this field range from ?00000? to ?10001.? as a programming example: if a 10 bit field a should be extracted starting at the 120 th bit of the routing word, we would set la =?01010? (length = 10) and starta=?1110111? (starting address = 119), i.e. write 0x0a77 to this register. startb[6:0] startb[6:0] forms the binary address of the msb of the field b within the routing word. startb[6] is the msb of the address. lb[3:0] lb[3:0] gives the length of the field b in bits. the length is stored in lb[3:0] as binary value with lb[3] as msb. if no field b is to be used then lb[3:0] should be set to ?0000?. valid values for this field range from ?0000? to ?1100.? as a programming example: if a 10 bit field b should be extracted starting at the 120 th bit of the routing word, we would set lb =?1010? (length = 10) and startb = ?1110111? (starting address = 119), i.e. write 0x0a77 to this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 221 document id: pmc-1990553, issue 4 register 0x10c: sram access control bit type function default 31 r/w rwb 1 30 r busy x 29 unused x 28 unused x 27 unused x 26 unused x 25 unused x 24 unused x 23 unused x 22 unused x 21 unused x 20 unused x 19 unused x 18 unused x 17 r/w search/linkage 0 16 r/w sa[16] 0 15 r/w sa[15] 0 14 r/w sa[14] 0 13 r/w sa[13] 0 12 r/w sa[12] 0 11 r/w sa[11] 0 10 r/w sa[10] 0 9 r/w sa[9] 0 8 r/w sa[8] 0 7 r/w sa[7] 0 6 r/w sa[6] 0 5 r/w sa[5] 0 4 r/w sa[4] 0 3 r/w sa[3] 0 2 r/w sa[2] 0 1 r/w sa[1] 0 0 r/w sa[0] 0 this register allows the microprocessor to access the sram address indicated by sa[16:0], and perform the operation specified by the rwb bit on either the search table or the linkage table. writing to this register initiates a microprocessor access request cycle.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 222 document id: pmc-1990553, issue 4 sa[16:0] this register holds the sram address to be used for the microprocessor initiated accesses. sa[16:0] map directly to device pins saddr[16:0]. search/linkage this bit indicates whether the operation is to address a searching row or a linkage row. the access is to a search row if this bit is logic 0, and to a linkage row if this bit is logic 1. this bit maps directly to device pin saddr[17]. busy the busy bit is high while a microprocessor initiated access request to the sram is pending. this register should be polled until the busy bit goes low before another microprocessor access request is initiated. a microprocessor access request is typically completed within 22 sysclk cycles. the maximum possible latency for a read is 40 cycles, and for a write is 90 cycles. if the standby bit in the s/uni-atlas-3200 master configuration register is a logic 1, the typical access time is reduced to less than 7 sysclk cycles. rwb the rwb bit selects the operation to be performed on the addressed vc table: when rwb is set to a logic 1, a read from the sram is requested; when rwb is set to a logic 0, a write to the sram is requested.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 223 document id: pmc-1990553, issue 4 register 0x10d: sram data lsw (sram data[31:0]) bit type function default 31 r/w sram_data [31] 0 30 r/w sram_data [30] 0 29 r/w sram_data [29] 0 28 r/w sram_data [28] 0 27 r/w sram_data [27] 0 26 r/w sram_data [26] 0 25 r/w sram_data [25] 0 24 r/w sram_data [24] 0 23 r/w sram_data [23] 0 22 r/w sram_data [22] 0 21 r/w sram_data [21] 0 20 r/w sram_data [20] 0 19 r/w sram_data [19] 0 18 r/w sram_data [18] 0 17 r/w sram_data [17] 0 16 r/w sram_data [16] 0 15 r/w sram_data[15] 0 14 r/w sram_data[14] 0 13 r/w sram_data [13] 0 12 r/w sram_data [12] 0 11 r/w sram_data [11] 0 10 r/w sram_data [10] 0 9 r/w sram_data [9] 0 8 r/w sram_data [8] 0 7 r/w sram_data [7] 0 6 r/w sram_data [6] 0 5 r/w sram_data [5] 0 4 r/w sram_data [4] 0 3 r/w sram_data [3] 0 2 r/w sram_data [2] 0 1 r/w sram_data [1] 0 0 r/w sram_data [0] 0 for writes, this register contains data to be written to the lower 32 bits of the specified sram entry. for reads this register contains the data that was read from the 32 lsbs of the specified sram entry.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 224 document id: pmc-1990553, issue 4 register 0x10e: sram data msw (sram data [63:32]) bit type function default 31 r/w sram_data[63] 0 30 r/w sram_data[62] 0 29 r/w sram_data[61] 0 28 r/w sram_data[60] 0 27 r/w sram_data[59] 0 26 r/w sram_data[58] 0 25 r/w sram_data[57] 0 24 r/w sram_data[56] 0 23 r/w sram_data[55] 0 22 r/w sram_data[54] 0 21 r/w sram_data[53] 0 20 r/w sram_data[52] 0 19 r/w sram_data[51] 0 18 r/w sram_data[50] 0 17 r/w sram_data[49] 0 16 r/w sram_data[48] 0 15 r/w sram_data[47] 0 14 r/w sram_data[46] 0 13 r/w sram_data[45] 0 12 r/w sram_data[44] 0 11 r/w sram_data[43] 0 10 r/w sram_data[42] 0 9 r/w sram_data[41] 0 8 r/w sram_data[40] 0 7 r/w sram_data[39] 0 6 r/w sram_data[38] 0 5 r/w sram_data[37] 0 4 r/w sram_data[36] 0 3 r/w sram_data[35] 0 2 r/w sram_data[34] 0 1 r/w sram_data[33] 0 0 r/w sram_data[32] 0 for writes, this register contains data to be written to the most significant 32 bits of the specified sram entry. for reads this register contains the data that was read from the 32 msbs of the specified sram entry.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 225 document id: pmc-1990553, issue 4 11.5.3 vc table register 0x110: vc table maximum index bit type function default 31:17 unused x 16 r/w reserved 0 15 r/w maxvc[15] 0 14 r/w maxvc[14] 0 13 r/w maxvc[13] 0 12 r/w maxvc[12] 0 11 r/w maxvc[11] 0 10 r/w maxvc[10] 0 9r/w maxvc[9] 0 8r/w maxvc[8] 0 7r/w maxvc[7] 0 6r/w maxvc[6] 0 5r/w maxvc[5] 0 4r/w maxvc[4] 0 3r/w maxvc[3] 0 2r/w maxvc[2] 0 1r/w maxvc[1] 0 0r/w maxvc[0] 0 maxvc[15:0] the maxvc[15:0] bits represent the current maximum vc table index (vcra[15:0]). it is used by the background processes of the vc table as the first connection upon which the background processes act. the index is decremented with each subsequent connection serviced. an accurate value in this location maximizes the efficiency of the s/uni-atlas- 3200. fixing this register to all ones guarantees that all 64k connections will be serviced by the background processes. because the background processes require access to the linkage table in external sram, do not set maxvc[15:0] to a value greater than supported by the depth of external sram provisioned. setting maxvc[15:0] to all zeros effectively halts the background tasks for all locations except vcra[15:0]=0x00000.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 226 document id: pmc-1990553, issue 4 register 0x111: vc table access control bit type function default 31 r/w rwb 1 30 r busy x 29 r/w cc_clearonrd 0 28 r/w ac_clearonrd 0 27 r/w ncc_clearonrd 0 26 unused x 25 unused x 24 unused 23 r dram_crc_err x 22 unused 21 unused 20 unused 19 unused 18 unused 17 unused 16 r/w reserved 0 15 r/w vcra[15] 0 14 r/w vcra[14] 0 13 r/w vcra[13] 0 12 r/w vcra[12] 0 11 r/w vcra[11] 0 10 r/w vcra[10] 0 9 r/w vcra[9] 0 8 r/w vcra[8] 0 7 r/w vcra[7] 0 6 r/w vcra[6] 0 5 r/w vcra[5] 0 4 r/w vcra[4] 0 3 r/w vcra[3] 0 2 r/w vcra[2] 0 1 r/w vcra[1] 0 0 r/w vcra[0] 0 this register allows the microprocessor to access the vc table record indicated by vcra[16:0], and perform the operation specified by the rwb bit on the data. writing to this register initiates a microprocessor access request cycle. the vc table write enable registers 1 and 2 can be used to enable which fields are include in write operations, and should be programmed before this register is written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 227 document id: pmc-1990553, issue 4 reserved this bit must be programmed to logic 0. vcra[15:0] this register holds the vc record address to be used to address the vc table internal dram through microprocessor initiated accesses. it identifies the desired vc table entry. dram_crc_err when this bit is logic 1, then the crc of the vc being read was incorrect. this bit is valid after a read or write request has been made and the busy bit has gone low. this bit is valid either on a read, or on a write (if any of the write mask bits are logic 0). because write or a clear-on-read operation will correct the dram crc, it is important that the status of this bit be checked. cc_clronrd if cc_clronrd is logic 1, then after a read access, the cell count fields of the vc table are automatically written to all ?0?. other bits in the table are preserved in the write back . if cc_clronrd = ?0?, no write back to clear the count bits is initiated. ac_clronrd if ac_clronrd is logic 1, then after a read access, the alternate cell count fields of the vc table are automatically written to all ?0?. other bits in the table are preserved in the write back . if ac_clronrd = ?0?, no write back to clear the count bits is initiated. ncc_clronrd if ncc_clronrd is logic 1, then after a read access, the non-compliant count fields of the vc table are automatically written to all ?0?. other bits in the table are preserved in the write back . if ncc_clronrd = ?0?, no write back to clear the count bits is initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 228 document id: pmc-1990553, issue 4 busy the busy bit is high while a microprocessor initiated access request to the dram is pending. this register should be polled until the busy bit goes low before another microprocessor access request is initiated. a microprocessor access request will be completed within 220 sysclk cycles. if the standby bit in the s/uni-atlas-3200 master configuration register is a logic 1, the access time is reduced to less than 22 sysclk cycles. rwb the rwb bit selects the operation to be performed on the addressed vc table: when rwb is set to a logic 1, a read from the dram is requested; when rwb is set to a logic 0, a write to the dram is requested.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 229 document id: pmc-1990553, issue 4 register 0x112: vc table write enable 1 bit type function default 31 r/w unused x 30 r/w wr_action2 1 29 r/w wr_inc2 1 28 r/w wr_limit2 1 27 r/w wr_action1 1 26 r/w wr_inc1 1 25 r/w wr_limit1 1 24 r/w wr_field_b 1 23 r/w wr_vpi 1 22 r/w wr_vci 1 21 r/w wr_bwds_vcra 1 20 r/w reserved 0 19 r/w wr_status 1 18 r/w wr_config 1 17 r/w wr_oam_config 1 16 r/w wr_internal_status 1 15 r/w wr_police_config 1 14 r/w wr_max_fr_len 1 13 r/w wr_unused1 1 12 r/w wr_gfr_state 1 11 r/w wr_police_rsvd 1 10 r/w wr_ete_rx_dt 1 9 r/w wr_seg_rx_dt 1 8 r/w wr_alt_count_1 1 7 r/w wr_alt_count_2 1 6 r/w wr_cell_count_1 1 5 r/w wr_cell_count_2 1 4 r/w wr_unused3 1 3 r/w wr_rem_fr_cnt 1 2 r/w wr_non_comp_1 1 1 r/w wr_non_comp_2 1 0 r/w wr_non_comp_3 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 230 document id: pmc-1990553, issue 4 the bits in this register are write enables. when a write access is requested via the vc table access control register, then those fields which have their write enable set to logic 1 will be altered by the write, and those which have their write enable set to logic 0 will retain their previous values the fields correspond to the fields described in table 8, the vc record table. unused_1 and unused_3 refer to the reserved bits in row1 and row 3 respectively; the reserved bit should always be programmed to logic 0 for proper operation, because it controls writing to (as opposed to automatic generation of) crc-10 for the vc record table. the wr_bwds_vcra bit also controls the writing of the two reserved bits adjacent to the bwds_vcra field.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 231 document id: pmc-1990553, issue 4 register 0x113: vc table write enable 2 bit type function default 31:11 r/w unused x 10 r/w wr_tat2 1 9r/w wr_tat1 1 8 r/w wr_unused4 1 7 r/w wr_trans_vpi 1 6 r/w wr_trans_vci 1 5 r/w wr_trans_hec 1 4 r/w wr_trans_udf 1 3 r/w wr_trans_prepo_1 1 2 r/w wr_trans_prepo_2 1 1 r/w wr_seg_dl 1 0 r/w wr_ete_dl 1 the bits in this register are write enables. when a write access is requested via the vc table access control register, then those fields which have their write enable set to logic 1 will be altered by the write, and those which have their write enable set to logic 0 will retain their previous values the fields correspond to the fields described in table 8, the vc record table. unused4 refers to the unused bits in row4.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 232 document id: pmc-1990553, issue 4 register 0x114: vc table data row 0, word 0 (lsw) (ram data [31:0]) bit type function default 31 r/w row0_data [31] 0 30 r/w row0_data [30] 0 29 r/w row0_data [29] 0 28 r/w row0_data [28] 0 27 r/w row0_data [27] 0 26 r/w row0_data [26] 0 25 r/w row0_data [25] 0 24 r/w row0_data [24] 0 23 r/w row0_data [23] 0 22 r/w row0_data [22] 0 21 r/w row0_data [21] 0 20 r/w row0_data [20] 0 19 r/w row0_data [19] 0 18 r/w row0_data [18] 0 17 r/w row0_data [17] 0 16 r/w row0_data [16] 0 15 r/w row0_data[15] 0 14 r/w row0_data[14] 0 13 r/w row0_data [13] 0 12 r/w row0_data [12] 0 11 r/w row0_data [11] 0 10 r/w row0_data [10] 0 9 r/w row0_data [9] 0 8 r/w row0_data [8] 0 7 r/w row0_data [7] 0 6 r/w row0_data [6] 0 5 r/w row0_data [5] 0 4 r/w row0_data [4] 0 3 r/w row0_data [3] 0 2 r/w row0_data [2] 0 1 r/w row0_data [1] 0 0 r/w row0_data [0] 0 for writes, this register contains data to be written to word 0 of row 0 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from word 0 of row 0 of the vc table record specified by vcra[15:0].
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 233 document id: pmc-1990553, issue 4 register 0x115: vc table data row 0, word 1 (ram data [63:32]) bit type function default 31 r/w row0_data[63] 0 30 r/w row0_data[62] 0 29 r/w row0_data[61] 0 28 r/w row0_data[60] 0 27 r/w row0_data[59] 0 26 r/w row0_data[58] 0 25 r/w row0_data[57] 0 24 r/w row0_data[56] 0 23 r/w row0_data[55] 0 22 r/w row0_data[54] 0 21 r/w row0_data[53] 0 20 r/w row0_data[52] 0 19 r/w row0_data[51] 0 18 r/w row0_data[50] 0 17 r/w row0_data[49] 0 16 r/w row0_data[48] 0 15 r/w row0_data[47] 0 14 r/w row0_data[46] 0 13 r/w row0_data[45] 0 12 r/w row0_data[44] 0 11 r/w row0_data[43] 0 10 r/w row0_data[42] 0 9 r/w row0_data[41] 0 8 r/w row0_data[40] 0 7 r/w row0_data[39] 0 6 r/w row0_data[38] 0 5 r/w row0_data[37] 0 4 r/w row0_data[36] 0 3 r/w row0_data[35] 0 2 r/w row0_data[34] 0 1 r/w row0_data[33] 0 0 r/w row0_data[32] 0 for writes, this register contains data to be written to word 1 of row 0 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from word 1 of row 0 of the vc table record specified by vcra[15:0].
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 234 document id: pmc-1990553, issue 4 register 0x116: vc table data row 0, word 2 (ram data [95:64]) bit type function default 31 r/w row0_data[95] 0 30 r/w row0_data[94] 0 29 r/w row0_data[93] 0 28 r/w row0_data[92] 0 27 r/w row0_data[91] 0 26 r/w row0_data[90] 0 25 r/w row0_data[89] 0 24 r/w row0_data[88] 0 23 r/w row0_data[87] 0 22 r/w row0_data[86] 0 21 r/w row0_data[85] 0 20 r/w row0_data[84] 0 19 r/w row0_data[83] 0 18 r/w row0_data[82] 0 17 r/w row0_data[81] 0 16 r/w row0_data[80] 0 15 r/w row0_data[79] 0 14 r/w row0_data[78] 0 13 r/w row0_data[77] 0 12 r/w row0_data[76] 0 11 r/w row0_data[75] 0 10 r/w row0_data[74] 0 9 r/w row0_data[73] 0 8 r/w row0_data[72] 0 7 r/w row0_data[71] 0 6 r/w row0_data[70] 0 5 r/w row0_data[69] 0 4 r/w row0_data[68] 0 3 r/w row0_data[67] 0 2 r/w row0_data[66] 0 1 r/w row0_data[65] 0 0 r/w row0_data[64] 0 for writes, this register contains data to be written to word 2 of row 0 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from word 2 of row 0 of the vc table record specified by vcra[15:0].
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 235 document id: pmc-1990553, issue 4 register 0x117: vc table data row 0, word 3 (msw) (ram data [127:96]) bit type function default 31 r/w row0_data[127] 0 30 r/w row0_data[126] 0 29 r/w row0_data[125] 0 28 r/w row0_data[124] 0 27 r/w row0_data[123] 0 26 r/w row0_data[122] 0 25 r/w row0_data[121] 0 24 r/w row0_data[120] 0 23 r/w row0_data[119] 0 22 r/w row0_data[118] 0 21 r/w row0_data[117] 0 20 r/w row0_data[116] 0 19 r/w row0_data[115] 0 18 r/w row0_data[114] 0 17 r/w row0_data[113] 0 16 r/w row0_data[112] 0 15 r/w row0_data[111] 0 14 r/w row0_data[110] 0 13 r/w row0_data[109] 0 12 r/w row0_data[108] 0 11 r/w row0_data[107] 0 10 r/w row0_data[106] 0 9 r/w row0_data[105] 0 8 r/w row0_data[104] 0 7 r/w row0_data[103] 0 6 r/w row0_data[102] 0 5 r/w row0_data[101] 0 4 r/w row0_data[100] 0 3 r/w row0_data[99] 0 2 r/w row0_data[98] 0 1 r/w row0_data[97] 0 0 r/w row0_data[96] 0 for writes, this register contains data to be written to word 3 of row 0 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from word 3 of row 0 of the vc table record specified by vcra[15:0].
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 236 document id: pmc-1990553, issue 4 register 0x118: vc table data row 1, word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 1 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 1 of the vc table record specified by vcra[15:0]. register 0x119: vc table data row 1, word 1 (ram data [63:32]) register 0x11a: vc table data row 1, word 2 (ram data [95:64]) register 0x11b: vc table data row 1, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 237 document id: pmc-1990553, issue 4 register 0x11c: vc table data row 2, word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 2 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 2 of the vc table record specified by vcra[15:0]. register 0x11d: vc table data row 2, word 1 (ram data [63:32]) register 0x11e: vc table data row 2, word 2 (ram data [95:64]) register 0x11f: vc table data row 2, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 238 document id: pmc-1990553, issue 4 register 0x120: vc table data row 3, word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 3 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 3 of the vc table record specified by vcra[15:0]. register 0x121: vc table data row 3, word 1 (ram data [63:32]) register 0x122: vc table data row 3, word 2 (ram data [95:64]) register 0x123: vc table data row 3, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 239 document id: pmc-1990553, issue 4 register 0x124: vc table data row 4 word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 4 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 4 of the vc table record specified by vcra[15:0]. register 0x125: vc table data row 4, word 1 (ram data [63:32]) register 0x126: vc table data row 4, word 2 (ram data [95:64]) register 0x127: vc table data row 4, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 240 document id: pmc-1990553, issue 4 register 0x128: vc table data row 5 word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 5 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 5 of the vc table record specified by vcra[15:0]. register 0x129: vc table data row 5, word 1 (ram data [63:32]) register 0x12a: vc table data row 5, word 2 (ram data [95:64]) register 0x12b: vc table data row 5, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 241 document id: pmc-1990553, issue 4 register 0x12c: vc table data row 6 word 0 (lsw) (ram data [31:0]) for writes to the vc table, this and the next three registers contain data to be written to row 6 of the vc table record specified by vcra[15:0]. the actual writes will take into account vc table write enable registers 1 and 2. for reads this register contains the data that was read from row 6 of the vc table record specified by vcra[15:0]. register 0x12d: vc table data row 6, word 1 (ram data [63:32]) register 0x12e: vc table data row 6, word 2 (ram data [95:64]) register 0x12f: vc table data row 6, word 3 (msw) (ram data [127:96])
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 242 document id: pmc-1990553, issue 4 11.5.4 policing register 0x130: per-vc non-compliant cell counting configuration bit type function default 31:24 unused x 23 r/w gfr_ncount3[3] 0 22 r/w gfr_ncount3[2] 0 21 r/w gfr_ncount3[1] 0 20 r/w gfr_ncount3[0] 0 19 r/w gfr_ncount2[3] 0 18 r/w gfr_ncount2[2] 0 17 r/w gfr_ncount2[1] 0 16 r/w gfr_ncount2[0] 0 15 r/w gfr_ncount1[3] 0 14 r/w gfr_ncount1[2] 0 13 r/w gfr_ncount1[1] 0 12 r/w gfr_ncount1[0] 0 11 r/w ncount3[3] 0 10 r/w ncount3[2] 0 9 r/w ncount3[1] 0 8 r/w ncount3[0] 0 7 r/w ncount2[3] 0 6 r/w ncount2[2] 0 5 r/w ncount2[1] 0 4 r/w ncount2[0] 0 3 r/w ncount1[3] 0 2 r/w ncount1[2] 0 1 r/w ncount1[1] 0 0 r/w ncount1[0] 0 ncountx[3:0] the ncountx[3:0] bits determine how the per-connection non-compliant cell counts #1 through #3 of the vc table is defined: ncountx[3:0] definition 0000 non-compliant clp=0 cells. 0001 non-compliant clp=0+1 cells. 0010 discarded clp=0 cells. 0011 discarded clp=0+1 cells. 0100 tagged clp=0 cells which are not discarded 0101 ? 1001 reserved
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 243 document id: pmc-1990553, issue 4 ncountx[3:0] definition 1010 total clp=0 aal5 frames received 1011 total clp=0+1 aal5 frames received 1100 total cells non-compliant to gcra1 1101 total cells non-compliant to gcra2 1110 total cells non-compliant to the phy gcra 1111 reserved gfr_ncountx[3:0] the gfr_ncountx[3:0] bits determine how the per-connection non-compliant cell counts #1 through #3 of the vc table are defined for connections with gfr policing enabled (gfr = 1): ncountx[3:0] definition 0000 non-compliant clp=0 cells. 0001 non-compliant clp=0+1 cells. 0010 discarded clp=0 cells. 0011 discarded clp=0+1 cells. 0100 tagged clp=0 cells which are not discarded 0101 non-compliant clp=0 frames (gfr only) 0110 non-compliant clp=0+1 frames (gfr only) 0111 partially or completely discarded clp=0 frames (gfr only) 1000 partially or completely discarded clp=0+1 frames (gfr only) 1001 tagged clp=0 frames which are not discarded (gfr only) 1010 total clp=0 aal5 frames received 1011 total clp=0+1 aal5 frames received 1100 total cells non-compliant to gcra1 1101 total cells non-compliant to gcra2 1110 total cells non-compliant to the phy gcra 1111 reserved
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 244 document id: pmc-1990553, issue 4 register 0x131: connection policing configuration 1 & 2 bit type function default 31 r/w cfg2_gcra2[7] 0 30 r/w cfg2_gcra2[6] 0 29 r/w cfg2_gcra2[5] 0 28 r/w cfg2_gcra2[4] 0 27 r/w cfg2_gcra2[3] 0 26 r/w cfg2_gcra2[2] 0 25 r/w cfg2_gcra2[1] 0 24 r/w cfg2_gcra2[0] 0 23 r/w cfg2_gcra1[7] 0 22 r/w cfg2_gcra1[6] 0 21 r/w cfg2_gcra1[5] 0 20 r/w cfg2_gcra1[4] 0 19 r/w cfg2_gcra1[3] 0 18 r/w cfg2_gcra1[2] 0 17 r/w cfg2_gcra1[1] 0 16 r/w cfg2_gcra1[0] 0 15 r/w cfg1_gcra2[7] 0 14 r/w cfg1_gcra2[6] 0 13 r/w cfg1_gcra2[5] 0 12 r/w cfg1_gcra2[4] 0 11 r/w cfg1_gcra2[3] 0 10 r/w cfg1_gcra2[2] 0 9 r/w cfg1_gcra2[1] 0 8 r/w cfg1_gcra2[0] 0 7 r/w cfg1_gcra1[7] 0 6 r/w cfg1_gcra1[6] 0 5 r/w cfg1_gcra1[5] 0 4 r/w cfg1_gcra1[4] 0 3 r/w cfg1_gcra1[3] 0 2 r/w cfg1_gcra1[2] 0 1 r/w cfg1_gcra1[1] 0 0 r/w cfg1_gcra1[0] 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 245 document id: pmc-1990553, issue 4 the cfg1 configuration is selected if the per-connection policingconfiguration[2:0]=000. the cfg2 configuration is selected if the per-connection policingconfigselect[2:0] =001 gcra1[7:0] the following table indicates upon which cell streams the first policing instance acts: cell type rm segment oam end-to-end oam user clp bit01010101 reg bit gcra1 [0] gcra1 [1] gcra1 [2] gcra1 [3] gcra1 [4] gcra1 [5] gcra1 [6] gcra1 [7] a logic 1 written to any of the gcra1[7:0] bits enables gcra1 policing for that particular cell stream. for example, to enable cell rate policing for gcra1 on the user clp=0+1 cell stream, the register configuration would be gcra1[7:0]=11000000. if gcra1[7:0] = 00000000, the first gcra policing instance is globally disabled. note that f5 oam and rm cells are considered user cells when being policed at the f4 level, which occurs if the vc is an f4, or if the vp_police feature is being used. gcra2[7:0] these register bits control upon which cell streams the second gcra instance acts. these register bits are programmed in exactly the same manner as described above. register 0x132: connection policing configuration 3 & 4 register 0x133: connection policing configuration 5 & 6 register 0x134: connection policing configuration 7 & 8
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 246 document id: pmc-1990553, issue 4 register 0x140: phy policing enable 1 bit type function default 31 r/w policephy31 0 30 r/w policephy30 0 29 r/w policephy29 0 28 r/w policephy28 0 27 r/w policephy27 0 26 r/w policephy26 0 25 r/w policephy25 0 24 r/w policephy24 0 23 r/w policephy23 0 22 r/w policephy22 0 21 r/w policephy21 0 20 r/w policephy20 0 19 r/w policephy19 0 18 r/w policephy18 0 17 r/w policephy17 0 16 r/w policephy16 0 15 r/w policephy15 0 14 r/w policephy14 0 13 r/w policephy13 0 12 r/w policephy12 0 11 r/w policephy11 0 10 r/w policephy10 0 9 r/w policephy9 0 8 r/w policephy8 0 7 r/w policephy7 0 6 r/w policephy6 0 5 r/w policephy5 0 4 r/w policephy4 0 3 r/w policephy3 0 2 r/w policephy2 0 1 r/w policephy1 0 0 r/w policephy0 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 247 document id: pmc-1990553, issue 4 policephyx the policephyx bits enable the s/uni-atlas-3200 per-phy policing for phys 0 through 31. if policephyx is logic 1, the per-phy policing is enabled on phyx. all connections associated with phyx may have per-phy policing enabled. the phy police bit in the vc table must also be set to logic 1 for a connection to be per-phy policed as well as policed by the per-connection leaky buckets. if policephyx is logic 0, per-phy policing for phyx is disabled. if per-phy policing is enabled, it is the responsibility of the management software to setup the internal per-phy policing ram.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 248 document id: pmc-1990553, issue 4 register 0x141: phy policing enable 2 bit type function default 31:16 unused x 15 r/w policephy47 0 14 r/w policephy46 0 13 r/w policephy45 0 12 r/w policephy44 0 11 r/w policephy43 0 10 r/w policephy42 0 9 r/w policephy41 0 8 r/w policephy40 0 7 r/w policephy39 0 6 r/w policephy38 0 5 r/w policephy37 0 4 r/w policephy36 0 3 r/w policephy35 0 2 r/w policephy34 0 1 r/w policephy33 0 0 r/w policephy32 0 policephyx the policephyx bits enable the s/uni-atlas-3200 per-phy policing for phys 32 through 47. if policephyx is logic 1, the per-phy policing is enabled on phyx. all connections associated with phyx may have per-phy policing enabled. the phy police bit in the vc table must also be set to logic 1 for a connection to be per-phy policed as well as policed by the per-connection leaky buckets. if policephyx is logic 0, per-phy policing for phyx is disabled. if per-phy policing is enabled, it is the responsibility of the management software to setup the internal per-phy policing ram.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 249 document id: pmc-1990553, issue 4 register 0x142: phy policing configuration bit type function default 31 r/w config4gcra[7] 0 30 r/w config4gcra[6] 0 29 r/w config4gcra[5] 0 28 r/w config4gcra[4] 0 27 r/w config4gcra[3] 0 26 r/w config4gcra[2] 0 25 r/w config4gcra[1] 0 24 r/w config4gcra[0] 0 23 r/w config3gcra[7] 0 22 r/w config3gcra[6] 0 21 r/w config3gcra[5] 0 20 r/w config3gcra[4] 0 19 r/w config3gcra[3] 0 18 r/w config3gcra[2] 0 17 r/w config3gcra[1] 0 16 r/w config3gcra[0] 0 15 r/w config2gcra[7] 0 14 r/w config2gcra[6] 0 13 r/w config2gcra[5] 0 12 r/w config2gcra[4] 0 11 r/w config2gcra[3] 0 10 r/w config2gcra[2] 0 9 r/w config2gcra[1] 0 8 r/w config2gcra[0] 0 7 r/w config1gcra[7] 0 6 r/w config1gcra[6] 0 5 r/w config1gcra[5] 0 4 r/w config1gcra[4] 0 3 r/w config1gcra[3] 0 2 r/w config1gcra[2] 0 1 r/w config1gcra[1] 0 0 r/w config1gcra[0] 0 config1gcra[7:0] the following table indicates upon which cell streams the per-phy policing instance acts (if the phy policing configuration bit in the per-phy policing ram is set to phypoliceconfig[1:0]=00):
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 250 document id: pmc-1990553, issue 4 cell type rm segment oam end-to-end oam user clp bit01010101 reg bit config1 gcra[0] config1 gcra[1] config1 gcra[2] config1 gcra[3] config1 gcra[4] config1 gcra[5] config1 gcra[6] config1 gcra[7] a logic 1 written into any of the config1gcra1[7:0] register bits enables the per-phy policing on that particular cell stream. config2gcra[7:0] these register bits indicate the cell streams upon which the per-phy policing instance acts (if the phy policing configuration bit in the per-phy policing ram is set to phypoliceconfig[1:0]=01). these register bits are programmed in the same manner as listed above. config3gcra[7:0] these register bits indicate the cell streams upon which the per-phy policing instance acts (if the phy policing configuration bit in the per-phy policing ram is set to phypoliceconfig[1:0]=10). these register bits are programmed in the same manner as listed above. config4gcra[7:0] these register bits indicate the cell streams upon which the per-phy policing instance acts (if the phy policing configuration bit in the per-phy policing ram is set to phypoliceconfig[1:0]=11). these register bits are programmed in the same manner as listed above.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 251 document id: pmc-1990553, issue 4 register 0x143: per-phy non-compliant cell counting configuration bit type function default 31:12 unused x 11 r/w phyncount3[3] 0 10 r/w phyncount3[2] 0 9 r/w phyncount3[1] 0 8 r/w phyncount3[0] 0 7 r/w phyncount2[3] 0 6 r/w phyncount2[2] 0 5 r/w phyncount2[1] 0 4 r/w phyncount2[0] 0 3 r/w phyncount1[3] 0 2 r/w phyncount1[2] 0 1 r/w phyncount1[1] 0 0 r/w phyncount1[0] 0 phyncountx[3:0] the phyncountx[3:0] bits determine how the per-phy non-compliant cell counts #1 through #3 of the phy policing ram is defined: phyncountx[3:0] definition 0000 non-compliant clp=0 cells. 0001 non-compliant clp=0+1 cells. 0010 discarded clp=0 cells. 0011 discarded clp=0+1 cells. 0100 tagged clp=0 cells which are not discarded 0101 ? 1001 reserved 1010 total clp=0 aal5 frames received 1011 total clp=0+1 aal5 frames received 1100 total cells non-compliant to gcra1 1101 total cells non-compliant to gcra2 1110 total cells non-compliant to the phy gcra 1111 reserved
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 252 document id: pmc-1990553, issue 4 register 0x144: phy policing ram address and access control bit type function default 31:19 unused x 18 r/w rwb 1 17 r busy x 16 r/w clronrd 0 15 r/w wr_phyconfig 0 14 r/w wr_phynoncomp3 0 13 r/w wr_phynoncomp2 0 12 r/w wr_phynoncomp1 0 11 r/w wr_reserved 0 10 r/w wr_phyi 0 9 r/w wr_phyl 0 8 r/w wr_phytat 0 7 r/w unused 0 6 r/w unused 0 5 r/w phyaddr[5] 0 4 r/w phyaddr[4] 0 3 r/w phyaddr[3] 0 2 r/w phyaddr[2] 0 1 r/w phyaddr[1] 0 0 r/w phyaddr[0] 0 phyaddr[5:0] the phyaddr[5:0] bits indicate which of the per-phy ram locations is going to be accessed. phyaddr[5:0]=000000 holds the policing parameters and non-compliant cell counts for phy 1, and phyaddr[5:0]=101111 holds the policing parameters and non- compliant cell counts for phy48. wr_phytat when wr_phytat is logic 1, then a write access to the phy policing ram will write to the phytat field. when it is logic 0, the contents of phytat will be unchanged after a write access. these bits should be written to zero on setup and left alone thereafter. wr_phyl when wr_phyl is logic 1, then a write access to the phy policing ram will write to the phyl field and the two unused bits contiguous with it. when it is logic 0, the contents of phyl and the unused bits will be unchanged after a write access.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 253 document id: pmc-1990553, issue 4 wr_phyi when wr_phyi is logic 1, then a write access to the phy policing ram will write to the phyi field. when it is logic 0, the contents of phyi will be unchanged after a write access. wr_reserved when wr_reserved is logic 1, then a write access to the phy policing ram will write to the reserved field. when it is logic 0, the contents of the reserved field will be unchanged after a write access. these bits should be written to zero on setup and left alone thereafter. wr_phynoncomp1 when wr_phynoncomp1 is logic 1, then a write access to the phy policing ram will write to the phy non-compliant count 1 field. when it is logic 0, the contents of phy non- compliant count 1 will be unchanged after a write access. wr_phynoncomp2 when wr_phynoncomp2 is logic 1, then a write access to the phy policing ram will write to the phy non-compliant count 2 field. when it is logic 0, the contents of phy non- compliant count 2 will be unchanged after a write access. wr_phynoncomp3 when wr_phynoncomp1 is logic 3, then a write access to the phy policing ram will write to the phy non-compliant count 3 field. when it is logic 0, the contents of phy non- compliant count 3 will be unchanged after a write access. wr_phyconfig when wr_phyconfig is logic 1, then a write access to the phy policing ram will write to the phy action, phy police config, phy vc count, and phy policing rollover fifo enable fields, as well as the 10 unused bits in row 3.. when it is logic 0, the contents of these fields will be unchanged after a write access. clronrd if the clronrd bit is logic 1, then the per-phy non-compliant cell counts are cleared after a read access to a per-phy policing ram location is performed. if clronrd is logic 0, then a clearing write is not performed when the per-phy non-compliant cell counts are accessed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 254 document id: pmc-1990553, issue 4 busy after a read or write access is initiated, the busy bit is asserted until the access has been completed. a read or write access will be completed within 220 sysclk cycles. rwb this bit indicates whether a read or write access is to be performed. if logic 0, a read access is initiated when this register is written to. if logic 1, a write access is initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 255 document id: pmc-1990553, issue 4 register 0x145: phy policing ram data row 0 bit type function default 31 r/w phypolicerow0[31] 0 30 r/w phypolicerow0[30] 0 29 r/w phypolicerow0[29] 0 28 r/w phypolicerow0[28] 0 27 r/w phypolicerow0[27] 0 26 r/w phypolicerow0[26] 0 25 r/w phypolicerow0[25] 0 24 r/w phypolicerow0[24] 0 23 r/w phypolicerow0[23] 0 22 r/w phypolicerow0[22] 0 21 r/w phypolicerow0[21] 0 20 r/w phypolicerow0[20] 0 19 r/w phypolicerow0[19] 0 18 r/w phypolicerow0[18] 0 17 r/w phypolicerow0[17] 0 16 r/w phypolicerow0[16] 0 15 r/w phypolicerow0[15] 0 14 r/w phypolicerow0[14] 0 13 r/w phypolicerow0[13] 0 12 r/w phypolicerow0[12] 0 11 r/w phypolicerow0[11] 0 10 r/w phypolicerow0[10] 0 9 r/w phypolicerow0[9] 0 8 r/w phypolicerow0[8] 0 7 r/w phypolicerow0[7] 0 6 r/w phypolicerow0[6] 0 5 r/w phypolicerow0[5] 0 4 r/w phypolicerow0[4] 0 3 r/w phypolicerow0[3] 0 2 r/w phypolicerow0[2] 0 1 r/w phypolicerow0[1] 0 0 r/w phypolicerow0[0] 0 phypolicerow0[31:0] this is the 32-bits of data to be written into row 0 of the per-phy policing ram, or the data read from row 0 of the ram when a read request has been completed. if data are to be written into the ram, then this register must be written to before the phy policing access and control register is written. if data are to be read, then the busy bit of the phy policing access and control register must be deasserted before these data are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 256 document id: pmc-1990553, issue 4 register 0x146: phy policing ram data row 1 bit type function default 31 r/w phypolicerow1[31] 0 30 r/w phypolicerow1[30] 0 29 r/w phypolicerow1[29] 0 28 r/w phypolicerow1[28] 0 27 r/w phypolicerow1[27] 0 26 r/w phypolicerow1[26] 0 25 r/w phypolicerow1[25] 0 24 r/w phypolicerow1[24] 0 23 r/w phypolicerow1[23] 0 22 r/w phypolicerow1[22] 0 21 r/w phypolicerow1[21] 0 20 r/w phypolicerow1[20] 0 19 r/w phypolicerow1[19] 0 18 r/w phypolicerow1[18] 0 17 r/w phypolicerow1[17] 0 16 r/w phypolicerow1[16] 0 15 r/w phypolicerow1[15] 0 14 r/w phypolicerow1[14] 0 13 r/w phypolicerow1[13] 0 12 r/w phypolicerow1[12] 0 11 r/w phypolicerow1[11] 0 10 r/w phypolicerow1[10] 0 9 r/w phypolicerow1[9] 0 8 r/w phypolicerow1[8] 0 7 r/w phypolicerow1[7] 0 6 r/w phypolicerow1[6] 0 5 r/w phypolicerow1[5] 0 4 r/w phypolicerow1[4] 0 3 r/w phypolicerow1[3] 0 2 r/w phypolicerow1[2] 0 1 r/w phypolicerow1[1] 0 0 r/w phypolicerow1[0] 0 phypolicerow1[31:0] this is the 32-bits of data to be written into row 1 of the per-phy policing ram, or the data read from row 1 of the ram when a read request has been completed. if data are to be written into the ram, then this register must be written to before the phy policing access and control register is written. if data are to be read, then the busy bit of the phy policing access and control register must be deasserted before these data are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 257 document id: pmc-1990553, issue 4 register 0x147: phy policing ram data row 2 bit type function default 31 r/w phypolicerow2[31] 0 30 r/w phypolicerow2[30] 0 29 r/w phypolicerow2[29] 0 28 r/w phypolicerow2[28] 0 27 r/w phypolicerow2[27] 0 26 r/w phypolicerow2[26] 0 25 r/w phypolicerow2[25] 0 24 r/w phypolicerow2[24] 0 23 r/w phypolicerow2[23] 0 22 r/w phypolicerow2[22] 0 21 r/w phypolicerow2[21] 0 20 r/w phypolicerow2[20] 0 19 r/w phypolicerow2[19] 0 18 r/w phypolicerow2[18] 0 17 r/w phypolicerow2[17] 0 16 r/w phypolicerow2[16] 0 15 r/w phypolicerow2[15] 0 14 r/w phypolicerow2[14] 0 13 r/w phypolicerow2[13] 0 12 r/w phypolicerow2[12] 0 11 r/w phypolicerow2[11] 0 10 r/w phypolicerow2[10] 0 9 r/w phypolicerow2[9] 0 8 r/w phypolicerow2[8] 0 7 r/w phypolicerow2[7] 0 6 r/w phypolicerow2[6] 0 5 r/w phypolicerow2[5] 0 4 r/w phypolicerow2[4] 0 3 r/w phypolicerow2[3] 0 2 r/w phypolicerow2[2] 0 1 r/w phypolicerow2[1] 0 0 r/w phypolicerow2[0] 0 phypolicerow2[31:0] this is the 32-bits of data to be written into row 2 of the per-phy policing ram, or the data read from row 2 of the ram when a read request has been completed. if data are to be written into the ram, then this register must be written to before the phy policing access and control register is written. if data are to be read, then the busy bit of the phy policing access and control register must be deasserted before these data are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 258 document id: pmc-1990553, issue 4 register 0x148: phy policing ram data row 3 bit type function default 31 r/w phypolicerow3[31] 0 30 r/w phypolicerow3[30] 0 29 r/w phypolicerow3[29] 0 28 r/w phypolicerow3[28] 0 27 r/w phypolicerow3[27] 0 26 r/w phypolicerow3[26] 0 25 r/w phypolicerow3[25] 0 24 r/w phypolicerow3[24] 0 23 r/w phypolicerow3[23] 0 22 r/w phypolicerow3[22] 0 21 r/w phypolicerow3[21] 0 20 r/w phypolicerow3[20] 0 19 r/w phypolicerow3[19] 0 18 r/w phypolicerow3[18] 0 17 r/w phypolicerow3[17] 0 16 r/w phypolicerow3[16] 0 15 r/w phypolicerow3[15] 0 14 r/w phypolicerow3[14] 0 13 r/w phypolicerow3[13] 0 12 r/w phypolicerow3[12] 0 11 r/w phypolicerow3[11] 0 10 r/w phypolicerow3[10] 0 9 r/w phypolicerow3[9] 0 8 r/w phypolicerow3[8] 0 7 r/w phypolicerow3[7] 0 6 r/w phypolicerow3[6] 0 5 r/w phypolicerow3[5] 0 4 r/w phypolicerow3[4] 0 3 r/w phypolicerow3[3] 0 2 r/w phypolicerow3[2] 0 1 r/w phypolicerow3[1] 0 0 r/w phypolicerow3[0] 0 phypolicerow3[31:0] this is the 32-bits of data to be written into row 3 of the per-phy policing ram, or the data read from row 3 of the ram when a read request has been completed. if data are to be written into the ram, then this register must be written to before the phy policing access and control register is written. if data are to be read, then the busy bit of the phy policing access and control register must be deasserted before these data are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 259 document id: pmc-1990553, issue 4 11.5.5 oam fault management register 0x151: oam defect location octets 3 to 0 bit type function default 31 r/w dl[31] 0 30 r/w dl[30] 1 29 r/w dl[29] 1 28 r/w dl[28] 0 27 r/w dl[27] 1 26 r/w dl [26] 0 25 r/w dl[25] 1 24 r/w dl[24] 0 23 r/w dl[23] 0 22 r/w dl[22] 1 21 r/w dl[21] 1 20 r/w dl[20] 0 19 r/w dl[19] 1 18 r/w dl[18] 0 17 r/w dl[17] 1 16 r/w dl[16] 0 15 r/w dl[15] 0 14 r/w dl[14] 1 13 r/w dl[13] 1 12 r/w dl[12] 0 11 r/w dl[11] 1 10 r/w dl[10] 0 9r/w dl[9] 1 8r/w dl[8] 0 7r/w dl[7] 0 6r/w dl[6] 1 5r/w dl[5] 1 4r/w dl[4] 0 3r/w dl[3] 1 2r/w dl[2] 0 1r/w dl[1] 1 0r/w dl[0] 0 dl[31:0] this register contains the defect location data lsb which is inserted into
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 260 document id: pmc-1990553, issue 4 ais cells generated due to phy ais, send_ais_* and due to declaration of cc alarm. the defect location is also inserted into rdi cells when the phy_rdi, send_rdi_segment or send_rdi_end_to_end register bits are asserted (i.e. forced insertion of rdi cells rather than generation of rdi cells as a -result of auto_rdi) and when rdi cells are generated as a result of the cc_ais_rdi process. this is the least significant 32-bits of the defect location field. note the defect location defaults to 6a6a6a6a6a6a6a6a6a6a6a6a6a6a6a6a hex. register 0x152: defect location octets 7 to 4 register 0x153: defect location octets 11 to 8 register 0x154: defect location octets 15 to 12
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 261 document id: pmc-1990553, issue 4 register 0x155: per-phy ais cell generation control 1 bit type function default 31 r/w ais31 0 30 r/w ais30 0 29 r/w ais29 0 28 r/w ais28 0 27 r/w ais27 0 26 r/w ais26 0 25 r/w ais25 0 24 r/w ais24 0 23 r/w ais23 0 22 r/w ais22 0 21 r/w ais21 0 20 r/w ais20 0 19 r/w ais19 0 18 r/w ais18 0 17 r/w ais17 0 16 r/w ais16 0 15 r/w ais15 0 14 r/w ais14 0 13 r/w ais13 0 12 r/w ais12 0 11 r/w ais11 0 10 r/w ais10 0 9 r/w ais9 0 8 r/w ais8 0 7 r/w ais7 0 6 r/w ais6 0 5 r/w ais5 0 4 r/w ais4 0 3 r/w ais3 0 2 r/w ais2 0 1 r/w ais1 0 0 r/w ais0 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 262 document id: pmc-1990553, issue 4 aisx aisx enables the generation of ais cells for phy x, where x is from 31 to 0. if aisx is a logic 1, ais cells are generated to the output cell interface once per second (nominally) for every connection associated with phyx which is not an end-to-end point. segment ais cells will be generated if the segmentflow bit is logic 1 in the oam configuration field of the vc table; otherwise, end-to-end ais cells are generated. if aisx is a logic 0, ais cell generation on a per-phy basis is disabled. the phyid[5:0] field in the vc table identifies a connection?s associated phy.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 263 document id: pmc-1990553, issue 4 register 0x156: per-phy ais cell generation control 2 bit type function default 31:16 unused x 15 r/w ais47 0 14 r/w ais46 0 13 r/w ais45 0 12 r/w ais44 0 11 r/w ais43 0 10 r/w ais42 0 9 r/w ais41 0 8 r/w ais40 0 7 r/w ais39 0 6 r/w ais38 0 5 r/w ais37 0 4 r/w ais36 0 3 r/w ais35 0 2 r/w ais34 0 1 r/w ais33 0 0 r/w ais32 0 aisx aisx enables the generation of ais cells for phy x, where x is from 47 to 32. if aisx is a logic 1, ais cells are generated to the output cell interface once per second (nominally) for every connection associated with phyx which is not an end-to-end point. segment ais cells will be generated if the segmentflow bit is logic 1 in the oam configuration field of the vc table; otherwise, end-to-end ais cells are generated. if aisx is a logic 0, ais cell generation on a per-phy basis is disabled. the phyid[5:0] field in the vc table identifies a connection?s associated phy.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 264 document id: pmc-1990553, issue 4 register 0x157: per-phy rdi cell generation control 1 bit type function default 31 r/w rdi31 0 30 r/w rdi30 0 29 r/w rdi29 0 28 r/w rdi28 0 27 r/w rdi27 0 26 r/w rdi26 0 25 r/w rdi25 0 24 r/w rdi24 0 23 r/w rdi23 0 22 r/w rdi22 0 21 r/w rdi21 0 20 r/w rdi20 0 19 r/w rdi19 0 18 r/w rdi18 0 17 r/w rdi17 0 16 r/w rdi16 0 15 r/w rdi15 0 14 r/w rdi14 0 13 r/w rdi13 0 12 r/w rdi12 0 11 r/w rdi11 0 10 r/w rdi10 0 9 r/w rdi9 0 8 r/w rdi8 0 7 r/w rdi7 0 6 r/w rdi6 0 5 r/w rdi5 0 4 r/w rdi4 0 3 r/w rdi3 0 2 r/w rdi2 0 1 r/w rdi1 0 0 r/w rdi0 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 265 document id: pmc-1990553, issue 4 rdix rdix enables the generation of rdi cells on a per-phy basis for phy x, where x is from 31 to 0. if rdix is a logic 1, rdi cells for every connection (which is configured as an oam end point) associated with phy x, are generated once per second (nominally) to the backwards direction s/uni-atlas-3200 (through the output backward oam cell interface). segment rdi will be generated at segment end points, and end-to-end rdi at end-to-end points. both kinds of cells will be generated at dual end points. if rdix is a logic 0, rdi cell generation on a per-phy basis is disabled. the phyid[5:0] field in the vc table identifies a connection?s associated phy.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 266 document id: pmc-1990553, issue 4 register 0x158: per-phy rdi cell generation control 2 bit type function default 31:16 unused x 15 r/w rdi47 0 14 r/w rdi46 0 13 r/w rdi45 0 12 r/w rdi44 0 11 r/w rdi43 0 10 r/w rdi42 0 9 r/w rdi41 0 8 r/w rdi40 0 7 r/w rdi39 0 6 r/w rdi38 0 5 r/w rdi37 0 4 r/w rdi36 0 3 r/w rdi35 0 2 r/w rdi34 0 1 r/w rdi33 0 0 r/w rdi32 0 rdix rdix enables the generation of rdi cells on a per-phy basis for phy x, where x is from 47 to 32. if rdix is a logic 1, rdi cells for every connection (which is configured as an oam end point) associated with phy x, are generated once per second (nominally) to the backwards direction s/uni-atlas-3200 via the output backwards cell interface. segment rdi will be generated at segment end points, and end-to-end rdi at end-to-end points. both kinds of cells will be generated at dual end points. if rdix is a logic 0, rdi cell generation on a per-phy basis is disabled. the phyid[5:0] field in the vc table identifies a connection?s associated phy.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 267 document id: pmc-1990553, issue 4 register 0x159: per-phy aps indication 1 bit type function default 31 r/w aps31 1 30 r/w aps30 1 29 r/w aps29 1 28 r/w aps28 1 27 r/w aps27 1 26 r/w aps26 1 25 r/w aps25 1 24 r/w aps24 1 23 r/w aps23 1 22 r/w aps22 1 21 r/w aps21 1 20 r/w aps20 1 19 r/w aps19 1 18 r/w aps18 1 17 r/w aps17 1 16 r/w aps16 1 15 r/w aps15 1 14 r/w aps14 1 13 r/w aps13 1 12 r/w aps12 1 11 r/w aps11 1 10 r/w aps10 1 9 r/w aps9 1 8 r/w aps8 1 7 r/w aps7 1 6 r/w aps6 1 5 r/w aps5 1 4 r/w aps4 1 3 r/w aps3 1 2 r/w aps2 1 1 r/w aps1 1 0 r/w aps0 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 268 document id: pmc-1990553, issue 4 apsx the apsx register bits indicate that automatic protection switching for phy x exists, where x is from 31 to 0. if apsx is logic 1, then when a segment vp-ais cell is terminated, an end- to-end vp-ais cell will not be generated. if apsx is logic 0, then when a segment vp-ais cell is terminated, an end-to-end vp-ais cell will be generated (assuming that end-to-end vpc-ais cells are not being received). the phyid[5:0] field in the vc table identifies the phy device associated with a connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 269 document id: pmc-1990553, issue 4 register 0x15a: per-phy aps indication 2 bit type function default 31:16 unused x 15 r/w aps47 1 14 r/w aps46 1 13 r/w aps45 1 12 r/w aps44 1 11 r/w aps43 1 10 r/w aps42 1 9 r/w aps41 1 8 r/w aps40 1 7 r/w aps39 1 6 r/w aps38 1 5 r/w aps37 1 4 r/w aps36 1 3 r/w aps35 1 2 r/w aps34 1 1 r/w aps33 1 0 r/w aps32 1 apsx the apsx register bits indicate that automatic protection switching for phy x exists, where x is from 47 to 32. if apsx is logic 1, then when a segment vp-ais cell is terminated, an end- to-end vp-ais cell will not be generated. if apsx is logic 0, then when a segment vp-ais cell is terminated, and end-to-end vp-ais cell will be generated. the phyid[5:0] field in the vc table identifies the phy device associated with a connection.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 270 document id: pmc-1990553, issue 4 11.5.6 oam loopback register 0x160: oam loopback location id octets 3 to 0 bit type function default 31 r/w llid[31] 0 30 r/w llid[30] 1 29 r/w llid[29] 1 28 r/w llid[28] 0 27 r/w llid[27] 1 26 r/w llid [26] 0 25 r/w llid[25] 1 24 r/w llid[24] 0 23 r/w llid[23] 0 22 r/w llid[22] 1 21 r/w llid[21] 1 20 r/w llid[20] 0 19 r/w llid[19] 1 18 r/w llid[18] 0 17 r/w llid[17] 1 16 r/w llid[16] 0 15 r/w llid[15] 0 14 r/w llid[14] 1 13 r/w llid[13] 1 12 r/w llid[12] 0 11 r/w llid[11] 1 10 r/w llid[10] 0 9 r/w llid[9] 1 8 r/w llid[8] 0 7 r/w llid[7] 0 6 r/w llid[6] 1 5 r/w llid[5] 1 4 r/w llid[4] 0 3 r/w llid[3] 1 2 r/w llid[2] 0 1 r/w llid[1] 1 0 r/w llid[0] 0
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 271 document id: pmc-1990553, issue 4 llid[31:0] this register contains the lsb of the loopback location id which the s/uni-atlas-3200 will compare against when determining whether to loop back (in the case of outgoing loopback cells) or extract (in the case of returning loopback cells) loopback cells. the default of 6a6a?6a6a hex effectively disables this feature, as cells with this loopback id are not permitted to be looped back. register 0x161: loopback location id octets 7 to 4 register 0x162: loopback location id octets 11 to 8 register 0x163: loopback location id octets 15 to 12
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 272 document id: pmc-1990553, issue 4 11.5.7 oam performance management register 0x170: performance management ram record address, word select and access control bit type function default 31-25 unused x 24 r/w pm bank 0 23 r/w pm addr[7] 0 22 r/w pm addr[6] 0 21 r/w pm addr[5] 0 20 r/w pm addr[4] 0 19 r/w pm addr[3] 0 18 r/w pm addr[2] 0 17 r/w pm addr[1] 0 16 r/w pm addr[0] 0 15 r/w rwb 1 14 r busy x 13 r/w clronrd_row[7] 0 12 r/w clronrd_row[6] 0 11 r/w clronrd_row[5] 0 10 r/w clronrd_row[4] 0 9 r/w clronrd_row[3] 0 8 r/w wr_pm_row[7] 0 7 r/w wr_pm_row[6] 0 6 r/w wr_pm_row[5] 0 5 r/w wr_pm_row[4] 0 4 r/w wr_pm_row[3] 0 3 r/w wr_pm_row[2] 0 2 r/w wr_pm_row[1] 0 1 r/w wr_pm_row[0] 0 0 r/w wr_pm_config 0 pm bank the pm bank bit determines which bank of pm data will be accessed. if this bit is logic 0, the pm addr[7:0] field will access the desired data for the first bank of internal pm ram. if this bit is logic 1, the pm addr[7:0] field will access the desired data for the second bank of internal pm ram.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 273 document id: pmc-1990553, issue 4 pm addr[7:0] this field specifies which of the 256 possible pm sessions to access. the pm bank bit determines whether bank 1 or bank 2 of a particular pm address will be selected. wr_pm_config when this field is logic 1, then when a write operation is requested to the pm internal ram, the pm configuration and status field in row 0 of the pm ram will be written to. when this field is logic 0, then a write operation will not alter the pm configuration and status field in row 0. wr_pm_row[7:0] the pm row mask is used to select which rows of the pm internal ram data will be written during a write operation, or cleared during a read operation. if any of pm row wm[7:0] are ?0? during a write operation, the corresponding row will not be altered by the write operation. all rows for which pm row wm[x] is 1 will be altered by write operations, except for the pm configuration and status register in row 0, which is separately controlled by wr_pm_config. clronrd_row[7:3] when clronrd_row[x] is set to logic 1, then a read access will cause all counts in that row to be cleared to 0, except for those counts (e.g. fwd secbc and bwd secbc) which are naturally rolling counts. rows 0, 1, and 2 contain no clearable counts, so they do not have clronrd bits. if clronrd_row[x] is set to logic 0, then a read will not change the values in that row. busy the busy bit is high while a microprocessor initiated access request to the pm ram data is pending the busy bit is deasserted only after all the access required has been completed. this register should be polled until the busy bit goes low before another microprocessor access request is initiated. a microprocessor access request will be completed within 220 sysclk cycles rwb the rwb bit selects the operation to be performed on the addressed pm ram data: when rwb is set to a logic 1, a read from the internal sram is requested; when rwb is set to a logic 0, a write to the internal sram is requested.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 274 document id: pmc-1990553, issue 4 register 0x171: performance management ram row 0 word 0 (lsw) bit type function default 31 r/w pm_row0[31] 0 30 r/w pm_row0[30] 0 29 r/w pm_row0[29] 0 28 r/w pm_row0[28] 0 27 r/w pm_row0[27] 0 26 r/w pm_row0[26] 0 25 r/w pm_row0[25] 0 24 r/w pm_row0[24] 0 23 r/w pm_row0[23] 0 22 r/w pm_row0[22] 0 21 r/w pm_row0[21] 0 20 r/w pm_row0[20] 0 19 r/w pm_row0[19] 0 18 r/w pm_row0[18] 0 17 r/w pm_row0[17] 0 16 r/w pm_row0[16] 0 15 r/w pm_row0[15] 0 14 r/w pm_row0[14] 0 13 r/w pm_row0[13] 0 12 r/w pm_row0[12] 0 11 r/w pm_row0[11] 0 10 r/w pm_row0[10] 0 9 r/w pm_row0[9] 0 8 r/w pm_row0[8] 0 7 r/w pm_row0[7] 0 6 r/w pm_row0[6] 0 5 r/w pm_row0[5] 0 4 r/w pm_row0[4] 0 3 r/w pm_row0[3] 0 2 r/w pm_row0[2] 0 1 r/w pm_row0[1] 0 0 r/w pm_row0[0] 0 this register contains either the data to be written into the pm ram row 0 word 0 (lsw) or the data read from the internal pm ram when a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written. if data is to be read from the pm ram, this register contains the data from row 0 word 0 (lsw) after the internal sram access is completed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 275 document id: pmc-1990553, issue 4 register 0x172: performance management ram row 0 word 1 bit type function default 31 r/w pm_row0[63] 0 30 r/w pm_row0[62] 0 29 r/w pm_row0[61] 0 28 r/w pm_row0[60] 0 27 r/w pm_row0[59] 0 26 r/w pm_row0[58] 0 25 r/w pm_row0[57] 0 24 r/w pm_row0[56] 0 23 r/w pm_row0[55] 0 22 r/w pm_row0[54] 0 21 r/w pm_row0[53] 0 20 r/w pm_row0[52] 0 19 r/w pm_row0[51] 0 18 r/w pm_row0[50] 0 17 r/w pm_row0[49] 0 16 r/w pm_row0[48] 0 15 r/w pm_row0[47] 0 14 r/w pm_row0[46] 0 13 r/w pm_row0[45] 0 12 r/w pm_row0[44] 0 11 r/w pm_row0[43] 0 10 r/w pm_row0[42] 0 9 r/w pm_row0[41] 0 8 r/w pm_row0[40] 0 7 r/w pm_row0[39] 0 6 r/w pm_row0[38] 0 5 r/w pm_row0[37] 0 4 r/w pm_row0[36] 0 3 r/w pm_row0[35] 0 2 r/w pm_row0[34] 0 1 r/w pm_row0[33] 0 0 r/w pm_row0[32] 0 this register contains either the data to be written into the pm ram row 0 word 1 or the data read from the internal pm ram when a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written. if data is to be read from the pm ram, this register contains the data from row 0 word 1 after the internal sram access is completed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 276 document id: pmc-1990553, issue 4 register 0x173: performance management ram row 0 word 2 (msw) bit type function default 31:16 unused x 15 r/w pm_row0[79] 0 14 r/w pm_row0[78] 0 13 r/w pm_row0[77] 0 12 r/w pm_row0[76] 0 11 r/w pm_row0[75] 0 10 r/w pm_row0[74] 0 9 r/w pm_row0[73] 0 8 r/w pm_row0[72] 0 7 r/w pm_row0[71] 0 6 r/w pm_row0[70] 0 5 r/w pm_row0[69] 0 4 r/w pm_row0[68] 0 3 r/w pm_row0[67] 0 2 r/w pm_row0[66] 0 1 r/w pm_row0[65] 0 0 r/w pm_row0[64] 0 this register contains either the data to be written into the pm ram row 0 word 2 or the data read from the internal pm ram when a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written. if data is to be read from the pm ram, this register contains the data from row 0 word 2 after the internal sram access is completed.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 277 document id: pmc-1990553, issue 4 register 0x174: performance management ram row 1 word 0 (lsw) register 0x175: performance management ram row 1 word 1 register 0x176: performance management ram row 1 word 2 (msw) these registers contain either the data to be written into the pm ram row 1, or contains the data read from the internal pm ram row 1 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 278 document id: pmc-1990553, issue 4 register 0x177: performance management ram row 2 word 0 (lsw) register 0x178: performance management ram row 2 word 1 register 0x179: performance management ram row 2 word 2 (msw) these registers contain either the data to be written into the pm ram row 2, or contains the data read from the internal pm ram row 2 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 279 document id: pmc-1990553, issue 4 register 0x17a: performance management ram row 3 word 0 (lsw) register 0x17b: performance management ram row 3 word 1 register 0x17c: performance management ram row 3 word 2 (msw) these registers contain either the data to be written into the pm ram row 3, or contains the data read from the internal pm ram row 3 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 280 document id: pmc-1990553, issue 4 register 0x17d: performance management ram row 4 word 0 (lsw) register 0x17e: performance management ram row 4 word 1 register 0x17f: performance management ram row 4 word 2 (msw) these registers contain either the data to be written into the pm ram row 4, or contains the data read from the internal pm ram row 4 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 281 document id: pmc-1990553, issue 4 register 0x180: performance management ram row 5 word 0 (lsw) register 0x181: performance management ram row 5 word 1 register 0x182: performance management ram row 5 word 2 (msw) these registers contain either the data to be written into the pm ram row5, or contains the data read from the internal pm ram row 5 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 282 document id: pmc-1990553, issue 4 register 0x183: performance management ram row 6 word 0 (lsw) register 0x184: performance management ram row 6 word 1 register 0x185: performance management ram row 6 word 2 (msw) these registers contain either the data to be written into the pm ram row 6, or contains the data read from the internal pm ram row 6 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 283 document id: pmc-1990553, issue 4 register 0x186: performance management ram row 7 word 0 (lsw) register 0x187: performance management ram row 7 word 1 register 0x188: performance management ram row 7 word 2 (msw) these registers contain either the data to be written into the pm ram row 7, or contains the data read from the internal pm ram row 7 after a read request has been completed. if data is to be written to the pm ram, it must be written to this register before the pm ram select and access control registers are written.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 284 document id: pmc-1990553, issue 4 register 0x189: performance management threshold a bit type function default 31 r/w merror[3] 0 30 r/w merror[2] 0 29 r/w merror[1] 0 28 r/w merror[0] 0 27 unused x 26 unused x 25 r/w mmisins[11] 0 24 r/w mmisins[10] 0 23 r/w mmisins[9] 0 22 r/w mmisins[8] 0 21 r/w mmisins[7] 0 20 r/w mmisins[6] 0 19 r/w mmisins[5] 0 18 r/w mmisins[4] 0 17 r/w mmisins[3] 0 16 r/w mmisins[2] 0 15 r/w mmisins[1] 0 14 r/w mmisins[0] 0 13 unused x 12 unused x 11 r/w mlost[11] 0 10 r/w mlost[10] 0 9r/w mlost[9] 0 8r/w mlost[8] 0 7r/w mlost[7] 0 6r/w mlost[6] 0 5r/w mlost[5] 0 4r/w mlost[4] 0 3r/w mlost[3] 0 2r/w mlost[2] 0 1r/w mlost[1] 0 0r/w mlost[0] 0 this is the first of four threshold registers. these threshold registers are addressed by the threshold_select[1:0] field of the pm configuration field of the pm ram data. note, these thresholds apply to both forward monitoring and backward reporting cells.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 285 document id: pmc-1990553, issue 4 mmisins[11:0] mmisins[11:0] is the binary representation of the threshold of misinserted cells per performance management block required to declare a severely errored cell block of misinserted cells (secb misinserted). the number of misinserted cells is not counted if this threshold is exceeded (the secb misinserted counter will be incremented instead). if mmisins[11:0] is a binary zero, secb misinserted is not declared as a result of excessive misinserted cells. merror[3:0] merror[3:0] is the binary representation of the threshold of bip-16 violations per performance management block required to declare a severely errored cell block for errored cells (secb errored). errored cell counts are not accumulated if this threshold is exceeded (the secb errored count will be incremented instead). if merror[3:0] is a binary zero, the secb errored cell count is not declared as a result of excessive bip-16 violations. mlost[11:0] mlost[11:0] is the binary representation of the threshold of lost cells per performance management block required to declare a severely errored cell block of lost cells (secb lost). the number of lost cells is not counted if this threshold is exceeded (the secb lost counter will be incremented instead). if mlost[11:0] is a binary zero, secb lost is not declared as a result of excessive lost cells. register 0x18a: performance management threshold b register 0x18b: performance management threshold c register 0x18c: performance management threshold d
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 286 document id: pmc-1990553, issue 4 11.5.8 change of connection state fifo register 0x190: vc table change of connection state fifo status bit type function default 31:3 unused x 2 r cosfull x 1 r cosvalid x 0 r cosbusy x the cosvalid and cosbusy register bits indicate whether or not the data in the change of state data register is valid. the cos fifo read pointer is updated when the change of connection state fifo data register is read. cosbusy if cosbusy is logic 1, the cos fifo read-pointer is being updated. when busy is asserted, the cosvalid bit is undefined. when cosbusy is deasserted, the state of the cosvalid bit is defined. cosvalid if this bit is logic 1, the data in the vc table change of connection status data register is valid. the cosvalid bit is defined only when the cosbusy bit is logic 0. cosfull if this register bit is logic 1, the change of state fifo is full, and no more change of connection state data can be written into the fifo. this will suspend the background process which monitors connection for change in connection state. it is the responsibility of the management software to ensure this register is read often enough to ensure the notification of changes in connection state are compliant to bellcore and itu standards.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 287 document id: pmc-1990553, issue 4 register 0x191: vc table change of connection state fifo data bit type function default 31:0 r cosdata[31:0] x the cos fifo read pointer is updated when this register is read. cosdata is valid if the cosvalid bit is logic 1 and busy bit is logic 0. cosdata[28:17] the cosdata[28:17] field contains the end-point information and status field of a connection whose address is identified by the cosdata[15:0] register. the presence of data in this register indicates that the connection has undergone a change in connection state. the formatting of the fifo entries is described in table 34 in section 10.15. cosdata[15:0] this register contains the 16-bit connection id of a connection in the vc table which has undergone a change in connection state. the formatting of the fifo entries is described in table 34 in section 10.15.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 288 document id: pmc-1990553, issue 4 11.5.9 count rollover fifo register 0x198: count rollover fifo status bit type function default 31:3 unused x 2 r crfull x 1 r crvalid x 0 r crbusy x the crvalid and busy register bits indicate whether or not the data in the count rollover data register are valid. the cr fifo read pointer is updated when the count rollover fifo data register is read. crbusy if busy is logic 1, the cr fifo read-pointer is being updated. when busy is asserted, the crvalid bit is undefined. when busy is deasserted, the state of the crvalid bit is defined. crvalid if this bit is logic 1, the data in the count rollover fifo data register is valid. the crvalid bit is defined only when the busy bit is logic 0. crfull if this register bit is logic 1, the count rollover fifo is full, and no more rollover data can be written into the fifo. this will result in those counts which would normally cause entries to be made to saturate rather than rolling over.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 289 document id: pmc-1990553, issue 4 register 0x199: count rollover fifo data bit type function default 31 r source[2] x 30 r source[1] x 29 r source[0] x 28 r crdata[28] x 27 r crdata[27] x 26 r crdata[26] x 25 r crdata[25] x 24 r crdata[24] x 23 r crdata[23] x 22 r crdata[22] x 21 r crdata[21] x 20 r crdata[20] x 19 r crdata[19] x 18 r crdata[18] x 17 r crdata[17] x 16 r crdata[16] x 15 r crdata[15] x 14 r crdata[14] x 13 r crdata[13] x 12 r crdata[12] x 11 r crdata[11] x 10 r crdata[10] x 9 r crdata[9] x 8 r crdata[8] x 7 r crdata[7] x 6 r crdata[6] x 5 r crdata[5] x 4 r crdata[4] x 3 r crdata[3] x 2 r crdata[2] x 1 r crdata[1] x 0 r crdata[0] x the crvalid and crbusy register bits indicate whether or not the data in this register are valid. the cr fifo read pointer is updated when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 290 document id: pmc-1990553, issue 4 source[2:0] the source field identifies which of four possible sources the entry comes from. the source field determines the format of the crdata[26:0]. the source field is encoded as follows: 000 per-vc generic or policing counts 001 per-phy counts 010 pm counts from bank 0 011 pm counts from bank 1 1xx reserved crdata[28:0] the format of the crdata[28:0] depends on the source. see section 11.5.9 for details on the count rollover fifo data.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 291 document id: pmc-1990553, issue 4 11.5.10 per phy statistics register 0x1a0: per-phy counter configuration bit type function default 31:5 unused 4 r/w cnt_nz_gfc 1 3 r/w cnt_efci 0 2 r/w cnt_undef_oam 0 1 r/w cnt_rsvd_vci_pti 0 0 r/w phy rollover_fifo_en 0 phy rollover_fifo_en if this bit is logic 1, all per-phy counts cause entries to be made in the count rollover fifo when their msbs become logic 1. the msb is reset to logic 0 when the fifo entry is successfully made. it is the responsibility of the management software either to ensure the per-phy counts are polled often enough to ensure they do not saturate, or to read the count rollover fifo. if this bit is logic 0, all per-phy counts saturate at all ones. cnt_rsvd_vci_pti the cnt_rsvd_vci_pti controls the counting of f4 cells with vci values of 0 or between 7 and 15, inclusive, and all cells with pti = 7. if cnt_rsvd_vci_pti is a logic 1, these cells are included in the count of invalid vpi/vci/pti cells. if this bit is logic 0, only cells that cannot be searched to a valid, active connection are counted in this count. in any event, cells with an invalid vci or pti cause the invali interrupt to be asserted. cnt_undef_oam if the cnt_undef_oam bit is a logic 1, oam cells with undefined oam type and function type fields are accumulated in the per-phy count of errored oam/rm cells. if cnt_undef_oam is a logic 0, only oam or rm cells with crc-10 errors cause the per- phy errored oam/rm cell count to increment. the oamerri interrupt is also asserted when an oam cell with an undefined oam type function type field is received. cnt_efci if the cnt_efci bit is logic 1, then with a pti of 010 or 011 (which is the explicit forward congestion indication) are accumulated in the per-phy count of efci/non-zero gfc cells. if this bit is logic 0, cells with efci are not accumulated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 292 document id: pmc-1990553, issue 4 cnt_nz_gfc if the cnt_nz_gfc bit is logic 1, then cells which arrive on a uni which have a non-zero gfc field are accumulated in the per-phy count of efci/non-zero gfc cells. if this bit is logic 0, cells with non-zero gfc are not accumulated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 293 document id: pmc-1990553, issue 4 register 0x1a1: per-phy counter control bit type function default 31:18 r unused x 17 r/w rwb 1 16 r busy x 15 r/w clp0_clronrd 0 14 r/w clp1_clronrd 0 13 r/w rm_clronrd 0 12 r/w oam_clronrd 0 11 r/w invoamrm_clronrd 0 10 r/w inval_clronrd 0 9 r/w nzgfc_clronrd 0 8 r/w to_clronrd 0 7:6 r reserved 0 5:0 r/w phyid[5:0] 0 a write to this register initiates an access to the per-phy counting ram. the rwb bit determines if this access is a read or a write. while the transfer is pending, the busy bit will be high. the busy bit will go low when the transfer into the holding registers is complete. phyid[5:0] the phyid field determines which phys counts get read or written. phy id?s greater than 47 will not result in any action and the holding registers will stay unchanged. busy when the busy bit is active it indicates that an access request to the phy counts is pending. while this bit is high the contents of the holding registers is undefined. after writing to this register to initiate an access, the microprocessor should poll this register and wait for the busy to go low before reading the counts from the holding register. an access to the phy counts is typically completed within 22 cycles. clp0_clronrd if clp0_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the clp0 count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 294 document id: pmc-1990553, issue 4 clp1_clronrd if clp1_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the clp1 count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. rm_clronrd if rm_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the valid rm cells count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. oam_clronrd: if oam_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the valid oam cells count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. invoamrm_clronrd if invoamrm_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the invalid oam and rm cells count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. inval_clronrd: if inval_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the invalid vpi/vci/pti count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. nzgfc_clronrd if nzgfc_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the non-zero gfc and efci count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 295 document id: pmc-1990553, issue 4 to_clronrd if to_clronrd is logic 1, then after a read of a set of phy counts, a write is automatically initiated to set the timed out cells count to 0. the writes are done in such a way that no counts are missed. if clronrd = ?0?, no write back to clear the count bits is initiated. rwb the rwb bit selects the operation to be performed on the addressed phy. when rwb is set to a logic 1, a read of the phy counts is requested; when rwb is set to a logic 0, a write to the phy counts is requested.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 296 document id: pmc-1990553, issue 4 register 0x1a8: per-phy clp0 cell count holding register bit type function default 31 r/w clp0[31] x 30 r/w clp0[30] x 29 r/w clp0[29] x 28 r/w clp0[28] x 27 r/w clp0[27] x 26 r/w clp0[26] x 25 r/w clp0[25] x 24 r/w clp0[24] x 23 r/w clp0[23] x 22 r/w clp0[22] x 21 r/w clp0[21] x 20 r/w clp0[20] x 19 r/w clp0[19] x 18 r/w clp0[18] x 17 r/w clp0[17] x 16 r/w clp0[16] x 15 r/w clp0[15] x 14 r/w clp0[14] x 13 r/w clp0[13] x 12 r/w clp0[12] x 11 r/w clp0[11] x 10 r/w clp0[10] x 9r/w clp0[9] x 8r/w clp0[8] x 7r/w clp0[7] x 6r/w clp0[6] x 5r/w clp0[5] x 4r/w clp0[4] x 3r/w clp0[3] x 2r/w clp0[2] x 1r/w clp0[1] x 0r/w clp0[0] x clp0[31:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of clp=0 cells received on the specified phyid. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 297 document id: pmc-1990553, issue 4 a write to the per phy counter control register with rwb = 0 will set the count of clp = 0 cells received on the specified phyid to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 298 document id: pmc-1990553, issue 4 register 0x1a9: per phy clp1 cell count holding register clp1[31:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of clp=1 cells received on the specified phyid. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the count of clp = 1 cells received on the specified phyid to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 299 document id: pmc-1990553, issue 4 register 0x1aa: per phy valid rm cell counts holding register rm[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of rm cells with valid crcs received on the specified phyid. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the count of ?valid rm cells with valid crcs? received on the specified phyid to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 300 document id: pmc-1990553, issue 4 register 0x1ab: per phy valid oam cell counts holding register oam[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of defined oam cells with valid crcs received on the specified phyid. undefined oam cells (i.e. those with a oam and function type not defined by 1.610-1999) are not counted in this register; they may optionally be counted in the per-phy errored oam/rm cell count. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the count of ?oam cells with valid crcs? received on the specified phyid to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 301 document id: pmc-1990553, issue 4 register 0x1ac: per phy errored oam/rm cell counts holding register badoam[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of oam or rm cells with invalid crc?s received on the specified phyid. if the cnt_undef_oam bit is logic 1 in the per-phy counter configuration register, then this count also includes oam cells with an undefined oam type or function type. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the count of ?errored oam or rm? received on the specified phyid to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 302 document id: pmc-1990553, issue 4 register 0x1ad: per phy invalid vpi/vci/pti cell counts holding register badvpivci[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of cells from the specified phyid which did not successfully complete the search, which terminated on an unprovisioned or inactive connection, or which contained an invalid vci or pti. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the count of ?cells from the specified phyid which did not successfully complete the search? to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 303 document id: pmc-1990553, issue 4 register 0x1ae: per-phy efci/non-zero gfc cell count holding register efci_nzgfc[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of cells received at uni connections on the specified phyid with a non-zero gfc field, and/or cells with explicit forward congestion indication set in their pti field, depending on the setting of the cnt_efci and cnt_nz_gfc bits. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the ?efci and/or non-zero gfc uni cells? count of the specified phy to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 304 document id: pmc-1990553, issue 4 register 0x1af: per-phy timed-out cell count holding register timeout [15:0] a write to the per phy counter control register with rwb = 1 will load this register with the count of cells that timed-out of the bcif, mcif, forward pm, or ais/cc processes due to their phy being unable to accept them. if the clronrd bit was set, the internal count will also be reset to zero to start a fresh counting cycle. this transfer and reset will be done in a manner that ensures that no events are lost. a write to the per phy counter control register with rwb = 0 will set the ?timed-out cells? count of the specified phy to the value in this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 305 document id: pmc-1990553, issue 4 register 0x1b0: per phy last unknown vpi & vci holding register bit type function default 31:28 unused x 27 r unk_vpi[11] x 26 r unk_vpi[10] x 25 r unk_vpi[9] x 24 r unk_vpi[8] x 23 r unk_vpi[7] x 22 r unk_vpi[6] x 21 r unk_vpi[5] x 20 r unk_vpi[4] x 19 r unk_vpi[3] x 18 r unk_vpi[2] x 17 r unk_vpi[1] x 16 r unk_vpi[0] x 15 r unk_vci[15] x 14 r unk_vci[14] x 13 r unk_vci[13] x 12 r unk_vci[12] x 11 r unk_vci[11] x 10 r unk_vci[10] x 9 r unk_vci[9] x 8 r unk_vci[8] x 7 r unk_vci[7] x 6 r unk_vci[6] x 5 r unk_vci[5] x 4 r unk_vci[4] x 3 r unk_vci[3] x 2 r unk_vci[2] x 1 r unk_vci [1] x 0 r unk_vci[0] x unk_vci[15:0] a write to the per phy counter control register with rwb = 1 will load this register with the vci of the last cell from the specified phyid which failed the search (due to a search error, an unprovisioned connection, or an inactive connection). the clronrd bit is not relevant for this register and has no effect. a write to the per phy counter control register with rwb = 0 will have no effect on this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 306 document id: pmc-1990553, issue 4 unk_vpi[11:0] a write to the per phy counter control register with rwb = 1 will load this register with the vpi of the last cell from the specified phyid which failed the search. the clronrd bit is not relevant for this register and has no effect. a write to the per phy counter control register with rwb = 0 will have no effect on this register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 307 document id: pmc-1990553, issue 4 register 0x1c0: reserved bit type function default 31:4 unused x 3r/w reserved 0 2r/w reserved 0 1r/w reserved 0 0r/w reserved 1 reserved this register must be programmed to 0x1 for correct operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 308 document id: pmc-1990553, issue 4 11.6 rx link interface the rxlink interface registers should be left in their default state when the rxlink is not being used (i.e. when egress_ingressb is logic 1 in the s/uni-atlas-3200 master configuration register). register 0x200: rxl configuration bit type function default 31:16 unused x 15 unused x 14 unused x 13 unused x 12 unused x 11 unused x 10 unused x 9 r/w postlen[1] 0 8 r/w postlen[0] 0 7 unused x 6 r/w inbandaddr 1 5 r/w prelen[1] 0 4 r/w prelen[0] 0 3 r/w paren 0 2r/w hec 0 1 r/w oddparity 0 0r/w rxlrst 1 rxlrst the rxlrst bit is used to reset the rxlink block circuitry. when rxlrst is set to logic zero, the rxlink block operates normally. when rxlrst is set to logic one, the rxlink block is held in reset, apart from normal mode registers which may be accessed for purposes of initialization. oddparity the oddparity bit is used to set the type of parity that is checked by the rxlink. set this bit to ?1? in order to check odd parity. set this bit to ?0? to check even parity. this bit is global and affects all phy channels. this bit can be changed during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 309 document id: pmc-1990553, issue 4 paren the paren bit is used to indicate whether parity errored cells or packets are marked as errored. when paren is ?1?, parity-errored cells and packets will be marked. when the value is ?0?, errored cells and packets will not be marked. this bit cannot be changed during operation and can only be changed when rxlrst is logic 1. packets marked in error will be marked using rpp_err when they are transmitted. parity errors have no effect on the processing of atm cells. hec the hec bit is used to indicate whether the hec/udf word is included in atm cells. when the value is ?1?, the atm cells contain the hec/udf word. when the value is ?0?, the atm cells do not contain the hec/udf word. in any event, the hec is undefined at the atm layer, and will not be checked by rxlink. this bit cannot be changed during operation and can only be changed when rxlrst is logic one. prelen[1:0] the prelen bits are used to indicate the size of the prepend applied to atm cells. a value of ?00? indicates no prepend word. a value of ?01? indicates 1 prepend word. a value of ?10? indicates 2 prepend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxlrst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed . inbandaddr the inbandaddr bit is used only in pos-phy mode to indicate whether the in band address is expected on the interface. this bit is useful in single phy applications where the in band addressing is optional and the link layer device does not send an address in band since there is only one phy. a setting of ?1? means that the address is expected on rdat when rsx is asserted. a setting of ?0? means that rsx is not used and a phyid of ?000000? is assigned to all traffic on the pos phy interface. this bit cannot be changed during operation and can only be changed when rxlrst is logic one. postlen[1:0] the postlen bits are used to indicate the size of the postpend applied to the atm cells. a value of ?00? indicates no postpend word. a value of ?01? indicates 1 postpend word. a value of ?10? indicates 2 postpend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxlrst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed .
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 310 document id: pmc-1990553, issue 4 register 0x201: rxl interrupt enable bit type function default 31:4 unused x 3 r/w rdtferre 0 2 r/w rerre 0 1 r/w parerre 0 0 r/w fifothe 0 a value of ?0? masks the corresponding interrupt from asserting intb. a setting of ?1? unmasks the interrupt enabling the assertion of intb. the enable bits correspond in bit location to the interrupts described in rxl interrupt register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 311 document id: pmc-1990553, issue 4 register 0x202: rxl interrupt bit type function default 31:4 unused x 3 r rdtferri x 2 r rerri x 1 r parerri x 0 r fifothi x the bits in this register indicate that a given event has occurred since the last time this register was read. the bits are cleared on microprocessor read. fifothi the fifoth (throttling) bit is set when there is cell available from a phy port and no cell space available in the sdq fifo for that port. the rx link must throttle the phy at this point. this is just an indicative interrupt. parerri the parerr bit is set if there is a parity error on the ul3 or pos-phy bus. cells and packets received with parity errors will be marked as errored if the paren bit is logic 1 in the rxl configuration register.. rerri this bit is set if the current pos packet is in error. this bit is set when rerr interface signal is asserted along with reop and rval signals. rdtferri the rdtferri bit is used to indicate that the value of rdat[31:24] during the rsx cycle was not equal to the value of atm_field or pos_field, depending on whether the phy is expected to be an atm or a packet phy. the interrupt is advisory only. this bit is cleared on microprocessor read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 312 document id: pmc-1990553, issue 4 register 0x208: rxl phy indirect address bit type function default 31:16 unused x 15 r busy x 14 r/w config_rwb 1 13 unused x 12 unused x 11 unused x 10 unused x 9 unused x 8 unused x 7 unused x 6 unused 5 r/w phy_addr[5] 0 4 r/w phy_addr[4] 0 3 r/w phy_addr[3] 0 2 r/w phy_addr[2] 0 1 r/w phy_addr[1] 0 0 r/w phy_addr[0] 0 the rxl phy indirect address register is an indirect address register used along with the rxl phy indirect data. phy_addr[5:0] the phy_addr register indicates the indirect address to read or write the rxl phy indirect data, depending on the setting of config_rwb. config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read is to be performed, and the data for phy_addr will be placed in the rxl phy data register. a value of ?0? means that a write of the information in rxl phy data will be performed at address phy_addr. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further access.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 313 document id: pmc-1990553, issue 4 register 0x209: rxl phy indirect data bit type function default 31:8 unused x 7 unused x 6 unused x 5 r/w port_x_map[5] 0 4 r/w port_x_map[4] 0 3 r/w port_x_map[3] 0 2 r/w port_x_map[2] 0 1 r/w port_x_map[1] 0 0 r/w port_x_map[0] 0 the rxl phy indirect data register is used along with the rxl phy indirect address register to program the phy channels. port x map the port_x_map bits are used to translate phy addresses. on powerup, each phy port will map to the corresponding phyid in the fifo. if translation is needed, then the location for the external (ul3 or pos-phy3 bus) phy address must be programmed with the value of the desired internal fifo phyid. the rxlink calendar always refers to the external phyid; the rest of the device will act on the translated phyid. port_x_map must not be written to a value greater than 47.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 314 document id: pmc-1990553, issue 4 register 0x20a: rxl calendar length bit type function default 31:8 unused x 7 unused x 6 r/w calendar_length[6] 0 5 r/w calendar_length[5] 0 4 r/w calendar_length[4] 0 3 r/w calendar_length[3] 0 2 r/w calendar_length[2] 0 1 r/w calendar_length[1] 0 0 r/w calendar_length[0] 0 this register is used in utopia mode for polling and servicing. a description of the calendar is provided in section 10.1.5 calendar_length[6:0] the calendar_length register is provided to program the length of calendar used for polling and servicing up to a maximum of 128 entries. updating the calendar length during cell flow can cause overflows of the sdq or underruns of the attached phy device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 315 document id: pmc-1990553, issue 4 register 0x20b: rxl calendar indirect address and data bit type function default 31:16 unused x 15 r busy x 14 r/w calendar_addr[6] 0 13 r/w calendar_addr[5] 0 12 r/w calendar_addr[4] 0 11 r/w calendar_addr[3] 0 10 r/w calendar_addr[2] 0 9 r/w calendar_addr[1] 0 8 r/w calendar_addr[0] 0 7 r/w config_rwb 1 6 unused x 5 r/w calendar_data[5] 0 4 r/w calendar_data[4] 0 3 r/w calendar_data[3] 0 2 r/w calendar_data[2] 0 1 r/w calendar_data[1] 0 0 r/w calendar_data[0] 0 the rxl calendar indirect address data register is an indirect register used to program the polling and servicing calendar described in section 10.1.5. the rxl block performs polling and servicing in utopia mode only. calendar_data[5:0] the calendar_data register is provided to program the sequence calendar with the phy ids. the calendar consists of a maximum of 128 entries where the calendar_addr is used to access one of the 128 entries to either write or read calendar_data. the length of the calendar is set in the rxl calendar length register. updating the calendar entries during cell flow can cause overflows of the sdq or underruns of the attached phy device. calendar_addr[6:0] the calendar_addr register is an indirect address register that is used with calendar_data register. the two registers together allow indirect address reads and writes to the polling and servicing calendar. the calendar_addr is used with config_rwb and busy to command reads and writes.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 316 document id: pmc-1990553, issue 4 config_rwb the config_rwb register bit specifies whether a read or write is to be performed. a value of ?1? means that a read is to be performed on the data at calendar_addr and will be placed in the calendar_data register. a value of ?0? means that a write of the information in calendar_data will be performed at address calendar_addr. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further accesses.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 317 document id: pmc-1990553, issue 4 register 0x20c: rxl data type field bit type function default 31:16 unused x 15 r/w pos_field[7] 0 14 r/w pos_field[6] 0 13 r/w pos_field[5] 0 12 r/w pos_field[4] 0 11 r/w pos_field[3] 0 10 r/w pos_field[2] 0 9 r/w pos_field[1] 0 8 r/w pos_field[0] 1 7 r/w atm_field[7] 0 6 r/w atm_field[6] 0 5 r/w atm_field[5] 0 4 r/w atm_field[4] 0 3 r/w atm_field[3] 0 2 r/w atm_field[2] 0 1 r/w atm_field[1] 0 0 r/w atm_field[0] 0 the rxl data type field is used in pos mode of operation only and is provided as a means to identify the type of traffic, atm or packet data, being sent over pos-phy. atm_field[7:0] the atm_field register is provided to identify atm cells being transferred over pos-phy. whenever a packet arrives on a phy expected to be an atm phy, rdat[31:24] should match atm_field during the rsx cycle. otherwise, an interrupt (rdtferri) is signaled to indicate pos data type mismatch. these bits can be changed during operation. pos_field[7:0] the pos_field register is provided to identify atm cells being transferred over pos-phy. whenever a packet arrives on a phy expected to be an packet phy, rdat[31:24] should match pos_field during the rsx cycle. otherwise, an interrupt (rdtferri) is signaled to indicate pos data type mismatch. these bits can be changed during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 318 document id: pmc-1990553, issue 4 11.7 tx phy interface the txphy interface registers should be left in their default state when the txphy is not being used (i.e. when egress_ingressb is logic 0 in the s/uni-atlas-3200 master configuration register). register 0x220: txp configuration bit type function default 31:16 unused x 15 unused x 14 unused x 13 unused x 12 unused x 11 unused x 10 unused x 9 r/w postlen[1] 0 8 r/w postlen[0] 0 7 unused x 6 r/w inbandaddr 1 5 r/w prelen[1] 0 4 r/w prelen[0] 0 3 r/w paren 0 2r/whec 0 1 r/w oddparity 0 0r/wtxprst 1 txprst the txprst bit is used to reset the txphy block circuitry. when txprst is set to logic zero, the txphy block operates normally. when txprst is set to logic one, the txphy block circutry is held in reset, except for the normal mode registers which may be accessed for purposes of initialization. oddparity the oddparity bit is used to set the type of parity that is expected on the tpx_dat bus. set this bit to ?1? in order to check for odd parity. set this bit to ?0? to generate even parity. this bit is global and affects all phy channels. this bit can be altered during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 319 document id: pmc-1990553, issue 4 paren the paren bit is used to indicate whether parity errored cells or packets are marked as errored. when paren is ?1?, parity-errored cells and packets will be marked. when the value is ?0?, errored cells and packets will not be marked. this bit cannot be changed during operation and can only be changed when txprst is logic 1. packets marked in error will be marked using tlp_err when they are transmitted. parity errors have no effect on the processing of atm cells. hec the hec bit is used to indicate whether the hec/udf word is included in atm cells. when the value is ?1?, the atm cells contain the hec/udf word. when the value is ?0?, the atm cels do not contain the hec/udf word. in any event, the hec is undefined at the atm layer, and will not be checked by txphy. this bit cannot be changed during operation and can only be changed when txprst is logic one. prelen[1:0] the prelen bits are used to indicate the size of the prepend applied to atm cells. a value of ?00? indicates no prepend word. a value of ?01? indicates 1 prepend word. a value of ?10? indicates 2 prepend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when txprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed . inbandaddr the inbandaddr bit is used only in pos-phy mode to indicate whether the in band address is expected on the interface. this bit is useful in single phy applications where the in band addressing is optional and the link layer device may not send an address in band since there is only one phy. a setting of ?1? means that the address is expected on tpp_dat when tpp_sx is asserted. a setting of ?0? means that tpp_sx is not used and a phyid of ?000000? is assigned to all traffic on the pos phy interface. this bit cannot be changed during operation and can only be changed when txprst is logic one. postlen[1:0] the postlen bits are used to indicate the size of the postpend applied to the atm cells. a value of ?00? indicates no postpend word. a value of ?01? indicates 1 postpend word. a value of ?10? indicates 2 postpend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when txprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed .
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 320 document id: pmc-1990553, issue 4 register 0x221: txp interrupt bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 r tdtferri x 1 r tparerri x 0 r runtcelli x runtcelli runtcelli is set if tpu_enb is deasserted before the end of the cell transfer, resulting in a partial cell transfer. these cells are be marked as errored, and may be discarded or routed to the microprocessor by the cell processor. this error can be caused by incorrectly setting the size of the cell expected by this interface. check that the hec, pre and post word registers are properly set. tparerri the tparerr bit is used to indicate that a parity error was observed on the incoming tpx_dat bus since the last time the interrupt was read. the cell may be marked errored and sent on to the sdq. this bit is cleared on microprocessor read. tdtferri the tdtferri bit is used to indicate that the value of tpp_dat[31:24] during the tpp_sx cycle was not equal to the value of atm_field or pos_field, depending on whether the phy is expected to be an atm or a packet phy. the interrupt is advisory only. this bit is cleared on microprocessor read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 321 document id: pmc-1990553, issue 4 register 0x222: txp interrupt enable bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 r/w tdtferre x 1 r/w tparerre x 0 r/w runtcelle x a value of ?0? masks the corresponding interrupt from asserting intb. a setting of ?1? unmasks the interrupt enabling the assertion of intb. the enable bits correspond in bit location to the interrupts described in rxl interrupt register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 322 document id: pmc-1990553, issue 4 register 0x223: txp data type field bit type function default 31:16 unused x 15 r/w pos_field[7] 0 14 r/w pos_field[6] 0 13 r/w pos_field[5] 0 12 r/w pos_field[4] 0 11 r/w pos_field[3] 0 10 r/w pos_field[2] 0 9 r/w pos_field[1] 0 8 r/w pos_field[0] 1 7 r/w atm_field[7] 0 6 r/w atm_field[6] 0 5 r/w atm_field[5] 0 4 r/w atm_field[4] 0 3 r/w atm_field[3] 0 2 r/w atm_field[2] 0 1 r/w atm_field[1] 0 0 r/w atm_field[0] 0 the txp data type field is used in pos mode of operation only and is provided as a means to identify the type of traffic, atm or packet data, being sent over pos-phy. atm_field[7:0] the atm_field register is provided to identify atm cells being transferred over pos-phy. whenever a packet arrives on a phy expected to be an atm phy, tdat[31:24] should match atm_field during the tsx cycle. otherwise, an interrupt (tdtferri) is signaled to indicate pos data type mismatch. these bits can be changed during operation. pos_field[7:0] the pos_field register is provided to identify atm cells being transferred over pos-phy. whenever a packet arrives on a phy expected to be an packet phy, tdat[31:24] should match pos_field during the tsx cycle. otherwise, an interrupt (tdtferri) is signaled to indicate pos data type mismatch. these bits can be changed during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 323 document id: pmc-1990553, issue 4 11.8 input scalable data queue register 0x240: input sdq control bit type function default 31:2 unused x 1 r tip x 0r/wsdqrst 1 sdqrst this bit is used to reset the sdq. the sdq comes up in reset. it should be taken out of reset by writing a 0 to this bit. the user can reset the sdq at any time by writing a 1 to this bit, and then writing a 0. reset flushes all the data in the fifos, resets the read and write pointers and resets all counters. the configuration information is not changed by reset. tip this bit is asserted after the s/uni-atlas-3200 identity/load counts register or any of the input sdq count registers is written to, and goes low once the per-phy and aggregate counts in the input sdq counting registers are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 324 document id: pmc-1990553, issue 4 register 0x241: input sdq interrupts bit type function default 31:12 unused x 11 undi x 10 eopi x 9sopi x 8ofli x 7: 4 unused x 3 r/w unde 0 2 r/w eope 0 1 r/w sope 0 0r/wofle 0 ofle: when this bit is set to 1, fifo overflows cause intb to be asserted. if this bit is set to 0, fifo overflows do not cause intb to be asserted. eope when this bit is set to 1, bad eop signals cause intb to be asserted. if this bit is set to 0, bad eop signals do not cause intb to be asserted. sope: when this bit is set to 1, bad sop signals cause intb to be asserted. if this bit is set to 0, bad sop signals do not cause intb to be asserted. undrune when this bit is set to 1, fifo under-runs cause intb to be asserted. if this bit is set to 0, fifo under-runs do not cause intb to be asserted. ofli this bit is set when any of the configured fifos overflows. the fifo that caused this interrupt is available in ofl_fifo[5:0] in the fifo overflow id register. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 325 document id: pmc-1990553, issue 4 sopi this bit is set when two sops arrive consecutively on the same fifo without being separated by an eop. the fifo that caused the interrupt is available in sop_fifo[5:0] in the fifo sop error id register. this bit is cleared when this register is read. eopi this bit is set when two eops arrive consecutively on the same fifo without being separated by a sop. the fifo that caused the interrupt is available in eop_fifo[5:0] in the fifo eop error id register. this bit is cleared when this register is read. undi this bit is set when data is requested from an empty fifo, i.e. when the fifo underruns. the fifo that caused this interrupt is available in und_fifo[5:0] in the fifo under-run id register. this bit is cleared when this register is read. this interrupt should never occur, because it would indicate an error internal to the device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 326 document id: pmc-1990553, issue 4 register 0x242: input sdq interrupt id this register identifies the fifos associated with individual interrupts. because reading the interrupts causes them to be cleared, it is preferable to read the interrupt id register first and then the interrupt register. bit type function default 31:30 unused x 29:24 r und_fifo[5:0] x 23:22 unused x 21:16 r eop_fifo[5:0] x 15:14 unused x 13:8 r sop_fifo[5:0] x 7:6 unused x 5:0 r ofl_fifo[5:0] x ofl_fifo[5:0] whenever ofli becomes logic 1, these bits are loaded with the fifo that overflowed. once ofli becomes logic 1, this value will not change until ofli is cleared, and then becomes logic 1 again. sop_fifo[5:0] whenever sopi becomes logic 1, these bits are loaded with the fifo that received two consecutive sops without an intervening eop. once sopi becomes logic 1, this value will not change until sopi is cleared, and then becomes logic 1 again. eop_fifo[5:0] whenever eopi becomes logic 1, these bits are loaded with the fifo that received two consecutive eops without an intervening sop. once eopi becomes logic 1, this value will not change until eopi is cleared, and then becomes logic 1 again. und_fifo[5:0] whenever undi becomes logic 1, these bits are loaded with the fifo that underflowed. once undi becomes logic 1, this value will not change until undi is cleared, and then becomes logic 1 again.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 327 document id: pmc-1990553, issue 4 register 0x244: input sdq indirect address writing to this register initialtes a read or write access (based on rwb) to a set of indirect registers that set up the fifos for each phy: input sdq indirect configuration, input sdq buffer and data available threshold and input sdq indirect cell count. fifos must be configured according to a set of rules defined in section 13.1. in order to change the current setup of a fifo, it is recommended that the user read the existing setup information first, makes any modifications as required, and write back the new configuration . bit type function default 31:16 unused x 15 r busy 0 14 r/w rwb 1 13 r/w flush 1 12 r empty 1 11:6 unused x 5:0 r/w phyid[5:0] 0 phyid[5:0] this is a 6-bit number that is used to describe the current fifo being addressed by the input sdq fifo indirect configuration and indirect cells and packets count register. the range of fifo numbers that can be used is 0 to 47. empty this read-only bit indicates if the requested fifo is empty or not. when this bit is read as 1, the fifo number specified in phyid[5:0] in the fifo indirect address register has no data available to be read out. this bit reflects the read-side perspective and will not react immediately to writes. before reconfiguring a disabled fifo, this bit needs to be sampled at 1, indicating that the fifo is currently empty. a non-empty fifo can be forced empty by writing flush to logic 1. flush flush is an indirect configuration register bit. when rwb = 0, the value written to this bit will be written to the flush bit for the specified phyid. a logic 1 on flush causes the sdq to discard all the current data in the specified fifo; a logic 0 must be written to the fifo in order for it to begin processing data again. flush is typically used when a non- empty fifo needs to be reconfigured.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 328 document id: pmc-1990553, issue 4 rwb this bit is used to indicate whether the user is writing the setup of a fifo, or reading all setup information of a fifo. this bit is used in conjunction with the busy bit. when this bit is set to 1, all the available setup information of the fifo requested in phyid[5:0] will become available in the empty bit, the input sdq indirect configuration register, and the input sdq indirect cell and packet count registers. when this bit is set to 0, the user is writing the configuration of a fifo. the sdq latches in the data in the input sdq indirect configuration and the flush bit into the configuration for the specified fifo. busy this is a read-only bit is used to indicate to the user that the information requested for the fifo specified in bits phyid[5:0] is in the process of being updated. if this bit is sampled to be 1, the update is still in progress. if this bit is sampled 0, the access is complete, the information for the fifo is now available in the empty bit, the input sdq indirect configuration register, and the input sdq cells and packets count register, and another access can be initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 329 document id: pmc-1990553, issue 4 register 0x245: input sdq indirect configuration bit type function default 31:16 unused x 15 r/w fifo_enbl 0 14 r/w fifo_type 0 13:7 r/w fifo_size[6:0] 0000001 6:0 r/w fifo_ptr[6:0] 0000000 fifo_ptr[6:0] this 7-bit pointer specifies where a fifo starts in the 3072-word sram space. it is specified in blocks, where a block is defined as 32 words (128 bytes). the range of this pointer should be 0 to 95; any other values will cause unpredictable effects. this pointer is calculated and programmed based on the number of fifos required by the system and the size of each fifo. the rules governing this calculation are stated in section 13.1. fifo_size[6:0] this 7-bit number denotes the size of a fifo in blocks. the size of a fifo is related to the bandwidth. table 41 shows the suggested fifo size based on the phy bandwidth. since there are altogether 96 blocks in the sram, the legal range for this number is 1 to 96; settings outside this range are reserved and may cause unpredictable effects. table 41 suggested fifo size encoding fifo size (blocks) fifo size (cells) bandwidth 1 2 below sts-1 2 4 sts-1 or less 612sts-3 24 48 sts-12 or sts-48 96 192 sts-48 fifo_type this bit must be set to logic 0 for all fifos in the input sdq to indicate that atm cells are being handled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 330 document id: pmc-1990553, issue 4 fifo_enbl this bit enables individual fifos. writing a ?0? to this bit disables a fifo. if previously enabled, a disabled fifo does not accept any new data into it, but data can be read from it until it is drained completely. in order to reconfigure a fifo during operation, it should be disabled and drained; a fifo can be drained immediately through the use of the flush bit. by default, all the fifos are disabled. only atm phys should be enabled in the input sdq. it is recommended that all fifos that are disabled also have the flush bit set to logic 1. this will tend to eliminate spurious interrupts.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 331 document id: pmc-1990553, issue 4 register 0x246: input sdq cells and packets count this register is used to read the count of the number of cells in the fifo addressed by the input sdq indirect address register. the count reflects the write-side perspective, and will not react immediately to reads. the counts are latched when the s/uni-atlas-3200 identity / load counts register is written to, or when any of the input sdq count registers are written to. while the transfer is in progress, the tip bit is asserted in the input sdq control register and s/uni- atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. once tip goes low, the count for the phy specified in the input sdq address register will be placed in this register. the recommended sequence for using this register is: 1. program the desired phyid in the input sdq address register. typically this would be done while setting rwb = 1. 2. execute a write to this register 3. poll tip in the input sdq control register until it becomes 0. 4. read the value in this register. bit type function default 31:12 unused x 11:0 r count[11:0] 0 count[11:0] this read-only field holds the last sampled count for the fifo requested by phyid[5:0] in the fifo indirect address register. since each fifo can hold up to 3072 pos packets or 192 atm cells, this count does not saturate or roll over.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 332 document id: pmc-1990553, issue 4 register 0x247: input sdq cells accepted aggregate count bit type function default 31:0 r acount[31:0] 0 this read-only field contains the aggregate count of all the atm cells accepted by the input sdq. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or to any of the input sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the input sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. acount[31:0] acount is a 32-bit aggregate counter which records the number of cells or packets accepted by the input sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 333 document id: pmc-1990553, issue 4 register 0x248: input sdq cells dropped aggregate count bit type function default 31:16 unused x 15:0 r dcount[15:0] 0 this read-only field contains the aggregate count of all the atm cells dropped by the input sdq due to overflow or transfer errors. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or to any of the input sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the input sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. dcount[15:0] acount is a 16-bit aggregate counter which records the number of cells or packets dropped by the input sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 334 document id: pmc-1990553, issue 4 11.9 rx phy interface the rxphy interface registers should be left in their default state when the rxphy is not being used (i.e. when egress_ingressb is logic 1 in the s/uni-atlas-3200 master configuration register). register 0x260: rxp configuration bit type function default 31:16 unused x 15 unused x 14 unused x 13 r/w rsxpause[1] 0 12 r/w rsxpause[0] 0 11 unused x 10 unused x 9 r/w postlen[1] 0 8 r/w postlen[0] 0 7 unused x 6 unused x 5 r/w prelen[1] 0 4 r/w prelen[0] 0 3 r/w serveovrd 0 2r/w hec 0 1 r/w oddparity 0 0r/w rxprst 1 rxprst the rxprst bit is used to reset the rxphy block circuitry. when rxprst is set to logic zero, the rxphy block operates normally. when rxprst is set to logic one, the rxphy block is held in reset, apart from normal mode registers which may be accessed for purposes of initialization. oddparity the oddparity bit is used to set the type of parity that is generated by the rxphy. set this bit to ?1? in order to generate odd parity. set this bit to ?0? to generate even parity. this bit is global and affects all phy channels. this bit can be altered during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 335 document id: pmc-1990553, issue 4 hec the hec bit is used to indicate whether the hec/udf word is included in atm cells. when the value is ?1?, the atm cells contain the hec/udf word. when the value is ?0?, the atm cells do not contain the hec/udf word. in any event, the hec is undefined at the atm layer, and will not be calculated by rxphy. this bit cannot be changed during operation and can only be changed when rxprst is logic one. serveovrd the serveovrd bit is used to configure whether servicing override is performed in utopia. normally, the switch or tm device is responsible for polling and servicing the fifos of this interface. the servicing override option allows this interface to appear as a single phy to the switch or tm, with the rxphy block choosing which phy queues to service, using the polling and servicing calendar. when the value is ?1?, the servicing override is engaged. when the value is ?0?, the servicing override is not engaged and expects normal mphy polling and servicing from the switch or tm. this bit cannot be changed during operation and can only be changed when rxprst is logic one. prelen[1:0] the prelen bits are used to indicate the size of the prepend applied to the atm cells to external blocks. a value of ?00? indicates no prepend word. a value of ?01? indicates 1 prepend word. a value of ?10? indicates 2 prepend words a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed . postlen[1:0] the postlen bits are used to indicate the size of the postpend applied to the atm cells. a value of ?00? indicates no postpend word. a value of ?01? indicates 1 postpend word. a value of ?10? indicates 2 postpend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed . rsxpause[1:0] rsxpause bits control the number of clocks to pause between transfers as per pos-phy level 3 specification. these bits are effective in pos mode only. the default setting is ?00? meaning no pause will occur between transfers resulting in maximum bandwidth usage. as setting of ?01? indicates 1 clock between transfers and a setting of ?10? indicates 2 clocks between transfers. a setting of ?11? is reserved. these bits cannot be changed during operation and can only be changed when rxprst is logic one.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 336 document id: pmc-1990553, issue 4 register 0x261: rxp interrupt bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 unused x 1 unused x 0 r runtcelli x runtcelli runtcelli is set if rpu_enb is deasserted before the end of the cell transfer, resulting in a partial cell transfer. if this occurs, the remainder of the cell is discarded. this error can be caused by incorrectly setting the size of the cell expected by this interface. check that the hec, pre and post word registers are properly set.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 337 document id: pmc-1990553, issue 4 register 0x262: rxp interrupt enable bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 unused x 1 unused x 0 r/w runtcelle 0 a value of ?0? masks the corresponding interrupt from asserting intb. a setting of ?1? unmasks the interrupt enabling the assertion of intb. the enable bits correspond in bit location to the interrupts described in rxp interrupt register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 338 document id: pmc-1990553, issue 4 register 0x263: rxp phy indirect address and data bit type function default 31:16 unused x 15 r busy x 14 r/w config_rwb 1 13 r/w phy_addr[5] 0 12 r/w phy_addr[4] 0 11 r/w phy_addr[3] 0 10 r/w phy_addr[2] 0 9 r/w phy_addr[1] 0 8 r/w phy_addr[0] 0 7 unused x 6 unused x 5 unused x 4 unused x 3 r/w burst_size[3] 0 2 r/w burst_size[2] 0 1 r/w burst_size[1] 1 0 r/w burst_size[0] 1 the rxl calendar indirect address and data register is an indirect register used to program the pos-phy burst sizes. burst_size[3:0] the burst_size data register specifies the maximum number of 16-byte blocks allowed to be transferred on a phy in pos-phy mode before the next phy in the calendar is automatically selected. a burst is automatically terminated at the end of a packet, or when the fifo becomes empty. the maximum number of blocks in a burst is burst_size + 1, so that the minimum burst size is 1 block (16 bytes), and the maximum burst size is 16 blocks (256 bytes). for phys carrying atm cells over pos-phy, burst_size must be set to the default 0x3. this register is used only in pos mode, and may be changed during operation. phy_addr[5:0] the phy_addr register specifies the phy for which an indirect read or write of the burst_size field is to occur, depending on the value of config_rwb. the phy_addr is used with config_rwb and busy to command reads and writes.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 339 document id: pmc-1990553, issue 4 config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read is to be performed on the data for phy_addr, which will be placed in the burst_size register. a value of ?0? means that a write of the information in burst_size will be performed at address phy_addr. busy the busy bit is used in indirect addressing to indicate the the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further access.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 340 document id: pmc-1990553, issue 4 register 0x264: rxp calendar length bit type function default 31:8 unused x 6 r/w calendar_length[6] 0 5 r/w calendar_length[5] 0 4 r/w calendar_length[4] 0 3 r/w calendar_length[3] 0 2 r/w calendar_length[2] 0 1 r/w calendar_length[1] 0 0 r/w calendar_length[0] 0 calendar_length[6:0] the calendar_length register is provided to program the length of calendar used for servicing up to a maximum of 128 entries. the length of the calendar is calendar_length[6:0] + 1. for example, a calendar_length[6:0] = ?000000? indicates a calendar length of one. a description of the calendar is provided in section 10.1.5. for maximum efficiency, it is recommended that the rxphy calendar length be set to at least 64, and preferably as close to 128 as is practical. a shorter set of calendar entries can simply be repeated several times to pad out to a greater length.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 341 document id: pmc-1990553, issue 4 register 0x265: rxp calendar indirect address and data bit type function default 31:16 unused x 15 r busy x 14 r/w calendar_addr[6] 0 13 r/w calendar_addr[5] 0 12 r/w calendar_addr[4] 0 11 r/w calendar_addr[3] 0 10 r/w calendar_addr[2] 0 9 r/w calendar_addr[1] 0 8 r/w calendar_addr[0] 0 7 r/w config_rwb 1 6 unused x 5 r/w calendar_data[5] 0 4 r/w calendar_data[4] 0 3 r/w calendar_data[3] 0 2 r/w calendar_data[2] 0 1 r/w calendar_data[1] 0 0 r/w calendar_data[0] 0 the rxp calendar indirect address data register is an indirect register used to program the servicing calendar as described in section 10.1.5. the rxp block performs polling and servicing in utopia mode. calendar_data[5:0] the calendar_data register is provided to program the sequence calendar with phy ids between 0 and 47. the calendar consists of a maximum of 128 entries where the calendar_addr is used to access one of the 128 entries to either write or read calendar_data. the length of the calendar is set in the rxp calendar length register. these bits can be altered during operation. calendar_addr[6:0] the calendar_addr register is an indirect address register that is used with calendar_data register. the two registers together allow indirect address reads and writes using a small amount of external address space. the calendar_addr is used with config_rwb and busy to command reads and writes.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 342 document id: pmc-1990553, issue 4 config_rwb the config_rwb register bit specifies whether a read or write is to be performed. a value of ?1? means that a read is to be performed on the data at calendar_addr and will be placed in the calendar_data register. a value of ?0? means that a write of the information in calendar_data will be performed at address calendar_addr. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further accesses.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 343 document id: pmc-1990553, issue 4 register 0x266: rxp data type field bit type function default 31:16 unused x 15 r/w pos_field[7] 0 14 r/w pos_field[6] 0 13 r/w pos_field[5] 0 12 r/w pos_field[4] 0 11 r/w pos_field[3] 0 10 r/w pos_field[2] 0 9 r/w pos_field[1] 0 8 r/w pos_field[0] 1 7 r/w atm_field[7] 0 6 r/w atm_field[6] 0 5 r/w atm_field[5] 0 4 r/w atm_field[4] 0 3 r/w atm_field[3] 0 2 r/w atm_field[2] 0 1 r/w atm_field[1] 0 0 r/w atm_field[0] 0 the rxp data type field is used in pos mode of operation only and is provided as a means to identify the type of traffic, atm or packet data, being sent over pos-phy. atm_field[7:0] the atm_field register is provided to identify atm cells being transferred over pos_phy. when the outgoing data is of type atm cell, then the atm_field is inserted in rdat[31:24] at the cycle in which the in-band address is inserted in rdat[7:0]. these bits can be changed during operation. pos_field[7:0] the pos_field register is provided to identify packet data in pos_phy. when the outgoing data is of type packet, then the pos_field is inserted in rdat[31:24] at the cycle in which the in-band address is inserted in rdat[7:0]. these bits can be changed during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 344 document id: pmc-1990553, issue 4 11.10 tx link interface the txlink interface registers should be left in their default state when the txlink is not being used (i.e. when egress_ingressb is logic 0 in the s/uni-atlas-3200 master configuration register). register 0x280: txl configuration bit type function default 31:16 unused x 15 unused x 14 unused x 13 unused x 12 unused x 11 unused x 10 unused x 9 r/w postlen[1] 0 8 r/w postlen[0] 0 7 unused x 6 unused x 5 r/w prelen[1] 0 4 r/w prelen[0] 0 3 r/w use_stpa 0 2r/w hec 0 1 r/w oddparity 0 0r/w txlrst 1 txlrst the txlrst bit is used to reset the txlink block circuitry. when txlrst is set to logic zero, the txlink block operates normally. when txlrst is set to logic one, the txlink block circutry is held in reset, except for the normal mode registers which may be accessed for purposes of initialization. oddparity the oddparity bit is used to set the type of parity that is generated by the txlink. set this bit to ?1? in order to generate odd parity. set this bit to ?0? to generate even parity. this bit is global and affects all phy channels. this bit can be changed during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 345 document id: pmc-1990553, issue 4 hec the hec bit is used to indicate whether the hec/udf word is included in atm cells. when the value is ?1?, the atm cells contain the hec/udf word. when the value is ?0?, the atm cells do not contain the hec/udf word. in any event, the hec is undefined at the atm layer, and will not be calculated by rxlink. this bit cannot be changed during operation and can only be changed when rxlrst is logic one. use_stpa the use_stpa bit is used to indicate whether the txlink will recognize transitions on the tlp_stpa pin. when use_stpa is logic 0, tlp_stpa is ignored and transfers are based solely on tlp_ptpa. if use_stpa is logic 1, then on sampling stpa high, the txlink will immediately cease transferring data. the tlp_stpa signal is valid 3 clocks after tsx is driven on the interface by the link device; txlink stops transmitting data three cycles after prelen[1:0] the prelen bits are used to indicate the size of the prepend applied to the atm cells to external blocks. a value of ?00? indicates no prepend word. a value of ?01? indicates 1 prepend word. a value of ?10? indicates 2 prepend words a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed . postlen[1:0] the postlen bits are used to indicate the size of the postpend applied to the atm cells. a value of ?00? indicates no postpend word. a value of ?01? indicates 1 postpend word. a value of ?10? indicates 2 postpend words. a value of ?11? is invalid. these bits cannot be changed during operation and can only be changed when rxprst is logic one. these bits apply to all phy channels. the sum of prelen + postlen must not exceed 2, or correct operation is not guaranteed .
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 346 document id: pmc-1990553, issue 4 register 0x281: txl interrupt enable bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 unused x 1 r/w terre 0 0 r/w tcaerre 0 a value of ?0? masks the corresponding interrupt from asserting intb. a setting of ?1? unmasks the interrupt enabling the assertion of intb. the enable bits correspond in bit location to the interrupts described in rxp interrupt register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 347 document id: pmc-1990553, issue 4 register 0x282: txl interrupt bit type function default 31:8 unused x 7 unused x 6 unused x 5 unused x 4 unused x 3 unused x 2 unused x 1 r terri 0 0 r tcaerri 0 the bits in this register are indicate that the corresponding event has occurred since the last time this register was read. the bits in this register are cleared when the register is read. tcaerri in utopia mode, the tcaerr bit is set if the phy layer device does not respond with asserted tlu_clav after the txlink selects the phy for transfer. because phys are not selected unless they have previously indicated a cell buffer available, this condition indicates an error. if this case occurs, the cell will be transmitted anyway. this bit is not used in pos- phy mode. terri this bit is set if the current pos packet from sdq is in error. this bit is set whenever txlink asserts terr along with teop signal.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 348 document id: pmc-1990553, issue 4 register 0x286: txl data type field bit type function default 31:16 unused x 15 r/w pos_field[7] 0 14 r/w pos_field[6] 0 13 r/w pos_field[5] 0 12 r/w pos_field[4] 0 11 r/w pos_field[3] 0 10 r/w pos_field[2] 0 9 r/w pos_field[1] 0 8 r/w pos_field[0] 1 7 r/w atm_field[7] 0 6 r/w atm_field[6] 0 5 r/w atm_field[5] 0 4 r/w atm_field[4] 0 3 r/w atm_field[3] 0 2 r/w atm_field[2] 0 1 r/w atm_field[1] 0 0 r/w atm_field[0] 0 the txl data type field is used in pos mode of operation only and is provided as a means to identify the type of traffic, atm or packet data, being sent over pos-phy. atm_field[7:0] the atm_field register is provided to identify atm cell being transferred over pos_phy. when the outgoing data is of type atm cell, then the atm_field is inserted in tlp_dat[31:24] at the cycle in which the in-band address is inserted in tlp_dat[5:0]. these bits can be altered during operation. pos_field[7:0] the pos_field register is provided to identify packet data in pos_phy. when the outgoing data is of type packet, then the pos_field is inserted in tlp_dat[31:24] at the cycle in which the in-band address is inserted in tlp_dat[5:0]. these bits can be altered during operation.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 349 document id: pmc-1990553, issue 4 register 0x288: txl phy indirect address bit type function default 31:16 unused x 15 r busy x 14 r/w config_rwb 1 13 unused x 12 unused x 11 unused x 10 unused x 9 unused x 8 unused x 7 unused x 6 unused x 5 r/w phy_addr[5] 0 4 r/w phy_addr[4] 0 3 r/w phy_addr[3] 0 2 r/w phy_addr[2] 0 1 r/w phy_addr[1] 0 0 r/w phy_addr[0] 0 the txl phy indirect address register is an indirect address register used along with the txl phy indirect data. phy_addr[5:0] the phy_addr register specifies the phy for which an indirect read or write on the txl phy indirect data register is to occur, depending on the value of config_rwb. the phy_addr is used with config_rwb and busy to command reads and writes. config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read is to be performed on the data for phy_addr and will be placed in the txl phy indirect data register. a value of ?0? means that a write of the information in txl phy indirect data will be performed at address phy_addr. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further accesses.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 350 document id: pmc-1990553, issue 4 register 0x289: txl phy indirect data bit type function default 31:14 unused x 13 r/w port_x_map[5] 0 12 r/w port_x_map[4] 0 11 r/w port_x_map[3] 0 10 r/w port_x_map[2] 0 9 r/w port_x_map[1] 0 8 r/w port_x_map[0] 0 7 r/w unused 0 6 r/w unused 0 5 r/w unused 0 4 r/w unused 0 3 r/w burst_size[3] 0 2 r/w burst_size[2] 0 1 r/w burst_size[1] 1 0 r/w burst_size[0] 1 the txl phy indirect data register is an indirect access register along with the txl phy indirect address. burst_size[3:0] the burst_size data register specifies the maximum number of 16-byte blocks allowed to be transferred on a phy in pos-phy mode before the next phy in the calendar is automatically selected. a burst is automatically terminated at the end of a packet, or when the fifo becomes empty. the maximum number of blocks in a burst is burst_size + 1, so that the minimum burst size is 1 block (16 bytes), and the maximum burst size is 16 blocks (256 bytes). for phys carrying atm cells over pos-phy, burst_size must be set to the default 0x3. this register is used only in pos mode, and may be changed during operation. port x map the port_x_map bits are used to translate phy addresses. on powerup, each internal fifo phyid will map to the identical phy port. if translation is needed, then the location for the external (ul3 or pos-phy3 bus) phy address must be programmed with the value of the desired internal fifo phyid. the txlink calendar always refers to the external phyid; the rest of the device will act on the internal fifo phyid. if the phyid is written to a value greater then 47, then data on that phy is ignored.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 351 document id: pmc-1990553, issue 4 register 0x28a: txl calendar length bit type function default 31: 7 unused x 6 r/w calendar_length[6] 0 5 r/w calendar_length[5] 0 4 r/w calendar_length[4] 0 3 r/w calendar_length[3] 0 2 r/w calendar_length[2] 0 1 r/w calendar_length[1] 0 0 r/w calendar_length[0] 0 the register is used in both pos and utopia mode of operation to control the weighted round- robin polling and servicing algorithm. . a description of the calendar is provided in section 10.1.5 generally, the calendar should be set up at device initialization and subsequently be left unchanged. when the calendar length, or a calendar entry is updated during cell or packet flow, there may be an impact on polling, which may result in an overrun of the phy device, or a spurious tca error interrupt. the overrun may occur on any phy that is currently transferring data. this impact will be avoided if use_stpa is logic one while the calendar is being updated calendar_length[6:0] the calendar_length register is provided to program the length of calendar used for polling and servicing up to a maximum of 128 entries. . the length of the calendar is calendar_length[6:0] + 1. for example, a calendar_length[6:0] = ?000000? indicates a calendar length of one. (see register 0x28b).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 352 document id: pmc-1990553, issue 4 register 0x28b: txl calendar indirect address and data bit type function default 31:16 unused x 15 r busy x 14 r/w calendar_addr[6] 0 13 r/w calendar_addr[5] 0 12 r/w calendar_addr[4] 0 11 r/w calendar_addr[3] 0 10 r/w calendar_addr[2] 0 9 r/w calendar_addr[1] 0 8 r/w calendar_addr[0] 0 7 r/w config_rwb 1 6 unused x 5 r/w calendar_data[5] 0 4 r/w calendar_data[4] 0 3 r/w calendar_data[3] 0 2 r/w calendar_data[2] 0 1 r/w calendar_data[1] 0 0 r/w calendar_data[0] 0 the txl calendar indirect address data register is an indirect address and data register. the register is used in both pos and utopia mode of operation to control the weighted round-robin polling and servicing algorithm. . a description of the calendar is provided in section 10.1.5. generally, the calendar should be set up at device initialization and subsequently be left unchanged. when the calendar length, or a calendar entry is updated during cell or packet flow, there may be an impact on polling, which may result in an overrun of the phy device, or a spurious tca error interrupt. the overrun may occur on any phy that is currently transferring data. this impact will be avoided if use_stpa is logic one while the calendar is being updated calendar_data[5:0] the calendar_data register is provided to program the sequence calendar with phy ids between 0 and 47. the calendar consists of a maximum of 128 entries where the calendar_addr is used to access one of the 128 entries to either write or read calendar_data. the length of the calendar is set in the txl calendar length register. calendar_addr[6:0] the calendar_addr register is an indirect address register that is used with calendar_data register. the calendar_addr field determines the position in the calendar which is to be written or read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 353 document id: pmc-1990553, issue 4 config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read of the calendar is to be performed at calendar_addr and the data will be placed in the calendar_data register. a value of ?0? means that a write of the information in calendar_data will be performed at address calendar_addr of the calendar. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means an operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further access.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 354 document id: pmc-1990553, issue 4 11.11 output scalable data queue register 0x2a0: output sdq control bit type function default 31:2 unused x 1 r tip x 0r/wsdqrst 1 sdqrst this bit is used to reset the sdq. the sdq comes up in reset. it should be taken out of reset by writing a 0 to this bit. the user can reset the sdq at any time by writing a 1 to this bit, and then writing a 0. reset flushes all the data in the fifos, resets the read and write pointers and resets all counters. the configuration information is not changed by reset. tip this bit is asserted after the s/uni-atlas-3200 identity/load counts register or any of the output sdq count registers is written to, and goes low once the per-phy and aggregate counts in the output sdq counting registers are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 355 document id: pmc-1990553, issue 4 register 0x2a1: output sdq interrupts bit type function default 31:12 unused x 11 undi x 10 eopi x 9sopi x 8ofli x 7: 4 unused x 3 r/w unde 0 2 r/w eope 0 1 r/w sope 0 0r/wofle 0 ofle when this bit is set to 1, fifo overflows cause intb to be asserted. if this bit is set to 0, fifo overflows do not cause intb to be asserted. eope when this bit is set to 1, bad eop signals cause intb to be asserted. if this bit is set to 0, bad eop signals do not cause intb to be asserted. sope when this bit is set to 1, bad sop signals cause intb to be asserted. if this bit is set to 0, bad sop signals do not cause intb to be asserted. undrune when this bit is set to 1, fifo under-runs cause intb to be asserted. if this bit is set to 0, fifo under-runs do not cause intb to be asserted. ofli this bit is set when any of the configured fifos overflows. the fifo that caused this interrupt is available in ofl_fifo[5:0] in the fifo overflow id register. this bit is cleared when this register is read. this interrupt should never occur, since it would indicate an error internal to the device.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 356 document id: pmc-1990553, issue 4 sopi this bit is set when two sops arrive consecutively on the same fifo without being separated by an eop. the fifo that caused the interrupt is available in sop_fifo[5:0] in the fifo sop error id register. this bit is cleared when this register is read. this interrupt should never occur, since it would indicate an error internal to the device. eopi this bit is set when two eops arrive consecutively on the same fifo without being separated by a sop. the fifo that caused the interrupt is available in eop_fifo[5:0] in the fifo eop error id register. this bit is cleared when this register is read. this interrupt should never occur, since it would indicate an error internal to the device. undi this bit is set when data is requested from an empty fifo, i.e. when the fifo underruns. the fifo that caused this interrupt is available in und_fifo[5:0] in the fifo under-run id register. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 357 document id: pmc-1990553, issue 4 register 0x2a2: output sdq interrupt id this register identifies the fifos associated with individual interrupts. because reading the interrupts causes them to be cleared, it is preferable to read the interrupt id register first and then the interrupt register. bit type function default 31:30 unused x 29:24 r und_fifo[5:0] x 23:22 unused x 21:16 r eop_fifo[5:0] x 15:14 unused x 13:8 r sop_fifo[5:0] x 7:6 unused x 5:0 r ofl_fifo[5:0] x ofl_fifo[5:0] whenever ofli becomes logic 1, these bits are loaded with the fifo that overflowed. once ofli becomes logic 1, this value will not change until ofli is cleared, and then becomes logic 1 again. sop_fifo[5:0] whenever sopi becomes logic 1, these bits are loaded with the fifo that received two consecutive sops without an intervening eop. once sopi becomes logic 1, this value will not change until sopi is cleared, and then becomes logic 1 again. eop_fifo[5:0] whenever eopi becomes logic 1, these bits are loaded with the fifo that received two consecutive eops without an intervening sop. once eopi becomes logic 1, this value will not change until eopi is cleared, and then becomes logic 1 again. und_fifo[5:0] whenever undi becomes logic 1, these bits are loaded with the fifo that underflowed. once undi becomes logic 1, this value will not change until undi is cleared, and then becomes logic 1 again.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 358 document id: pmc-1990553, issue 4 register 0x2a4: output sdq indirect address writing to this register initiates a read or write access (based on rwb) to a set of indirect registers that set up the fifos for each phy: output sdq indirect configuration, output sdq buffer and data available threshold and output sdq indirect cell count. fifos must be configured according to a set of rules defined in section 13.1. in order to change the current setup of a fifo, it is recommended that the user read the existing setup information first, makes any modifications as required, and write back the new configuration . bit type function default 31:16 unused x 15 r busy 0 14 r/w rwb 1 13 r/w flush 1 12 r empty 1 11:6 unused x 5:0 r/w phyid[5:0] 0 phyid[5:0] this is a 6-bit number that is used to describe the current fifo being addressed by the output sdq fifo indirect configuration and the output sdq cells and packets count register. the range of fifo numbers that can be used is 0 to 47. empty this read-only bit indicates if the requested fifo is empty or not. when this bit is read as 1, the fifo number specified in phyid[5:0] in the fifo indirect address register has no data available to be read out. this bit reflects the read-side perspective and will not react immediately to writes.. before reconfiguring a disabled fifo, this bit needs to be sampled at 1, indicating that the fifo is currently empty. a non-empty fifo can be forced empty by writing flush to logic 1. flush flush is an indirect configuration register bit. when rwb = 0, the value written to this bit will be written to the flush bit for the specified phyid. a logic 1 on flush causes the sdq to discard all the current data in the specified fifo; a logic 0 must be written to the fifo in order for it to begin processing data again. flush is typically used when a non- empty fifo needs to be reconfigured.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 359 document id: pmc-1990553, issue 4 rwb this bit is used to indicate whether the user is writing the setup of a fifo, or reading all setup information of a fifo. this bit is used in conjunction with the busy bit. when this bit is set to 1, all the available setup information of the fifo requested in phyid[5:0] will become available in the empty bit and the output sdq indirect configuration register. when this bit is set to 0, the user is writing the configuration of a fifo. the sdq latches in the data in the output sdq indirect configuration and the flush bit into the configuration for the specified fifo. busy this is a read-only bit is used to indicate to the user that the information requested for the fifo specified in bits phyid[5:0] is in the process of being updated. if this bit is sampled to be 1, the update is still in progress. if this bit is sampled 0, the access is complete, the information for the fifo is now available in the empty bit and the output sdq indirect configuration register, and another access can be initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 360 document id: pmc-1990553, issue 4 register 0x2a5: output sdq indirect configuration bit type function default 31:16 unused x 15 r/w fifo_enbl 0 14 r/w fifo_type 0 13:7 r/w fifo_size[6:0] 0000001 6:0 r/w fifo_ptr[6:0] 0000000 fifo_ptr[6:0] this 7-bit pointer specifies where a fifo starts in the 3072-word sram space. it is specified in blocks, where a block is defined as 32 words (128 bytes). the range of this pointer should be 0 to 95; any other values will cause unpredictable effects. this pointer is calculated and programmed based on the number of fifos required by the system and the size of each fifo. the rules governing this calculation are stated in section 13.1. fifo_size[6:0] this 7-bit number denotes the size of a fifo in blocks. the size of a fifo is related to the bandwidth. table 42 below shows the suggested fifo size based on the phy bandwidth. since there are altogether 96 blocks in the sram, the legal range for this number is 1 to 96; settings outside this range are reserved and may cause unpredictable effects. table 42 suggested fifo size encoding fifo size (blocks) fifo size (cells) bandwidth 1 2 below sts-1 2 4 sts-1 or less 612sts-3 24 48 sts-12 or sts-48 96 192 sts-48 fifo_type this bit must be set to logic 0 for all fifos in the output sdq to indicate that atm cells are being handled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 361 document id: pmc-1990553, issue 4 fifo_enbl this bit enables individual fifos. writing a ?0? to this bit disables a fifo. if previously enabled, a disabled fifo does not accept any new data into it, but data can be read from it until it is drained completely. in order to reconfigure a fifo during operation, it should be disabled and drained; a fifo can be drained immediately through the use of the flush bit. by default, all the fifos are disabled. only atm phys should be enabled in the output sdq it is recommended that all fifos that are disabled also have the flush bit set to logic 1. this will tend to eliminate spurious interrupts.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 362 document id: pmc-1990553, issue 4 register 0x2a6: output sdq cells and packets count this register is used to read the count of the number of cells in the fifo specified in the output sdq indirect address register. the count reflects the write-side perspective, and will not react immediately to reads. the counts are latched when the s/uni-atlas-3200 identity / load counts register is written to, or when any of the output sdq count registers are written to. while the transfer is in progress, the tip bit is asserted in the output sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. once tip goes low, the count for the phy specified in the output sdq address register will be placed in this register. the recommended sequence for using this register is: 1. program the desired phyid in the output sdq indirect address register. typically this would be done while setting rwb = 1. 2. execute a write to this register 3. poll tip in the output sdq control register until it becomes 0. 4. read the value in this register. bit type function default 31:12 unused x 11:0 r count[11:0] 0 count[11:0] this read-only field holds the last sampled count for the fifo requested by phyid[5:0] in the fifo indirect address register. since each fifo can hold up to 3072 pos packets or 192 atm cells, this count does not saturate or roll over.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 363 document id: pmc-1990553, issue 4 register 0x2a7: output sdq cells accepted aggregate count bit type function default 31:0 r acount[31:0] 0 this read-only field contains the aggregate count of all the atm cells accepted by the output sdq. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or any of the output sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the output sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. acount[31:0] acount is a 32-bit aggregate counter which records the number of cells or packets accepted by the output sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 364 document id: pmc-1990553, issue 4 register 0x2a8: output sdq cells dropped aggregate count bit type function default 31:16 unused x 15:0 r dcount[15:0] 0 this read-only field contains the aggregate count of all the atm cells dropped by the output sdq due to overflow or transfer errors. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or to any of the output sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the output sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. dcount[15:0] acount is a 16-bit aggregate counter which records the number of cells or packets dropped by the output sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 365 document id: pmc-1990553, issue 4 11.12 packet bypass scalable data queue register 0x2c0: bypass sdq control bit type function default 31:2 unused x 1 r tip x 0r/wsdqrst 1 sdqrst this bit is used to reset the sdq. the sdq comes up in reset. it should be taken out of reset by writing a 0 to this bit. the user can reset the sdq at any time by writing a 1 to this bit, and then writing a 0. reset flushes all the data in the fifos, resets the read and write pointers and resets all counters. the configuration information is not changed by reset. tip this bit is asserted after the s/uni-atlas-3200 identity/load counts register or any of the bypass sdq count registers is written to, and goes low once the per-phy and aggregate counts in the bypass sdq counting registers are valid.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 366 document id: pmc-1990553, issue 4 register 0x2c1: bypass sdq interrupts bit type function default 31:12 unused x 11 undi x 10 eopi x 9sopi x 8ofli x 7: 4 unused x 3 r/w unde 0 2 r/w eope 0 1 r/w sope 0 0r/wofle 0 ofle when this bit is set to 1, fifo overflows cause intb to be asserted. if this bit is set to 0, fifo overflows do not cause intb to be asserted. eope when this bit is set to 1, bad eop signals cause intb to be asserted. if this bit is set to 0, bad eop signals do not cause intb to be asserted. sope when this bit is set to 1, bad sop signals cause intb to be asserted. if this bit is set to 0, bad sop signals do not cause intb to be asserted. undrune when this bit is set to 1, fifo under-runs cause intb to be asserted. if this bit is set to 0, fifo under-runs do not cause intb to be asserted. ofli this bit is set when any of the configured fifos overflows. the fifo that caused this interrupt is available in ofl_fifo[5:0] in the fifo overflow id register. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 367 document id: pmc-1990553, issue 4 sopi this bit is set when two sops arrive consecutively on the same fifo without being separated by an eop. the fifo that caused the interrupt is available in sop_fifo[5:0] in the fifo sop error id register. this bit is cleared when this register is read. eopi this bit is set when two eops arrive consecutively on the same fifo without being separated by a sop. the fifo that caused the interrupt is available in eop_fifo[5:0] in the fifo eop error id register. this bit is cleared when this register is read. undi this bit is set when data is requested from an empty fifo, i.e. when the fifo underruns. the fifo that caused this interrupt is available in und_fifo[5:0] in the fifo under-run id register. this bit is cleared when this register is read.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 368 document id: pmc-1990553, issue 4 register 0x2c2: bypass sdq interrupt id this register identifies the fifos associated with individual interrupts. because reading the interrupts causes them to be cleared, it is preferable to read the interrupt id register first and then the interrupt register. bit type function default 31:30 unused x 29:24 r und_fifo[5:0] x 23:22 unused x 21:16 r eop_fifo[5:0] x 15:14 unused x 13:8 r sop_fifo[5:0] x 7:6 unused x 5:0 r ofl_fifo[5:0] x ofl_fifo[5:0] whenever ofli becomes logic 1, these bits are loaded with the fifo that overflowed. once ofli becomes logic 1, this value will not change until ofli is cleared, and then becomes logic 1 again. sop_fifo[5:0] whenever sopi becomes logic 1, these bits are loaded with the fifo that received two consecutive sops without an intervening eop. once sopi becomes logic 1, this value will not change until sopi is cleared, and then becomes logic 1 again. eop_fifo[5:0] whenever eopi becomes logic 1, these bits are loaded with the fifo that received two consecutive eops without an intervening sop. once eopi becomes logic 1, this value will not change until eopi is cleared, and then becomes logic 1 again. und_fifo[5:0] whenever undi becomes logic 1, these bits are loaded with the fifo that underflowed. once undi becomes logic 1, this value will not change until undi is cleared, and then becomes logic 1 again.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 369 document id: pmc-1990553, issue 4 register 0x2c4: bypass sdq indirect address writing to this register initiates a read or write access (based on rwb) to a set of indirect registers that set up the fifos for each phy: bypass sdq indirect configuration, bypass sdq buffer and data available threshold and bypass sdq indirect cell count. fifos must be configured according to a set of rules defined in section 13.1. in order to change the current setup of a fifo, it is recommended that the user read the existing setup information first, makes any modifications as required, and write back the new configuration . bit type function default 31:16 unused x 15 r busy 0 14 r/w rwb 1 13 r/w flush 1 12 r empty 1 11:6 unused x 5:0 r/w phyid[5:0] 0 phyid[5:0] this is a 6-bit number that is used to describe the current fifo being addressed by the bypass sdq fifo indirect configuration and the bypass sdq cells and packets count register. the range of fifo numbers that can be used is 0 to 47. empty this read-only bit indicates if the requested fifo is empty or not. when this bit is read as 1, the fifo number specified in phyid[5:0] in the fifo indirect address register has no data available to be read out. this bit reflects the read-side perspective and will not react immediately to writes. before reconfiguring a disabled fifo, this bit needs to be sampled at 1, indicating that the fifo is currently empty. a non-empty fifo can be forced empty by writing flush to logic 1. flush flush is an indirect configuration register bit. when rwb = 0, the value written to this bit will be written to the flush bit for the specified phyid. a logic 1 on flush causes the sdq to discard all the current data in the specified fifo; a logic 0 must be written to the fifo in order for it to begin processing data again. flush is typically used when a non- empty fifo needs to be reconfigured.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 370 document id: pmc-1990553, issue 4 rwb this bit is used to indicate whether the user is writing the setup of a fifo, or reading all setup information of a fifo. this bit is used in conjunction with the busy bit. when this bit is set to 1, all the available setup information of the fifo requested in phyid[5:0] will become available in the empty bit and the bypass sdq indirect configuration register. when this bit is set to 0, the user is writing the configuration of a fifo. the sdq latches in the data in the bypass sdq indirect configuration and the flush bit into the configuration for the specified fifo. busy this is a read-only bit is used to indicate to the user that the information requested for the fifo specified in bits phyid[5:0] is in the process of being updated. if this bit is sampled to be 1, the update is still in progress. if this bit is sampled 0, the access is complete, the information for the fifo is now available in the empty bit and the bypass sdq indirect configuration register, and another access can be initiated.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 371 document id: pmc-1990553, issue 4 register 0x2c5: bypass sdq indirect configuration bit type function default 31:16 unused x 15 r/w fifo_enbl 0 14 r/w fifo_type 0 13:7 r/w fifo_size[6:0] 0000001 6:0 r/w fifo_ptr[6:0] 0000000 fifo_ptr[6:0] this 7-bit pointer specifies where a fifo starts in the 3072-word sram space. it is specified in blocks, where a block is defined as 32 words (128 bytes). the range of this pointer should be 0 to 95; any other values will cause unpredictable effects. this pointer is calculated and programmed based on the number of fifos required by the system and the size of each fifo. the rules governing this calculation are stated in section 13.1. fifo_size[6:0] this 7-bit number denotes the size of a fifo in blocks. the size of a fifo is related to the bandwidth. table 43 below shows the suggested fifo size based on the phy bandwidth. since there are altogether 96 blocks in the sram, the legal range for this number is 2 to 96; settings outside this range are reserved and may cause unpredictable effects. table 43 suggested fifo size encoding fifo size (blocks) fifo size (bytes) bandwidth 1 128 not supported 2 256 sts-1 or less 6 768 sts-3 24 3072 sts-12 or sts-48 96 12288 sts-48 note that packets occupy a number of bytes equal to their packet length rounded up to the next multiple of 4 bytes. a fifo size of 1 block is not supported. fifo_type this bit must be set to logic 1 for all fifos in the bypass sdq to indicate that packets are being handled.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 372 document id: pmc-1990553, issue 4 fifo_enbl this bit enables individual fifos. writing a ?0? to this bit disables a fifo. if previously enabled, a disabled fifo does not accept any new data into it, but data can be read from it until it is drained completely. in order to reconfigure a fifo during operation, it should be disabled and drained; a fifo can be drained immediately through the use of the flush bit. by default, all the fifos are disabled. only packet phys should be enabled in the bypass sdq. it is recommended that all fifos that are disabled also have the flush bit set to logic 1. this will tend to eliminate spurious interrupts.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 373 document id: pmc-1990553, issue 4 register 0x2c6: bypass sdq cells and packets count this register is used to read the count of the number of packets on the fifo specified in the bypass sdq address register. the count reflects the write-side perspective, and will not react immediately to reads. the counts are latched when the s/uni-atlas-3200 identity / load counts register is written to, or when any of the bypass sdq count registers are written to. while the transfer is in progress, the tip bit is asserted in the bypass sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. once tip goes low, the count for the phy specified in the bypass sdq address register will be placed in this register. the recommended sequence for using this register is: 1. program the desired phyid in the bypass sdq address register. typically this would be done while setting rwb = 1. 2. execute a write to this register 3. poll tip in the bypass sdq control register until it becomes 0. 4. read the value in this register. bit type function default 31:12 unused x 11:0 r count[11:0] 0 count[11:0] this read-only field holds the last sampled count for the fifo requested by phyid[5:0] in the fifo indirect address register, at the time the transfer was initiated. since each fifo can hold up to 3072 pos packets or 192 atm cells, this count does not saturate or roll over.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 374 document id: pmc-1990553, issue 4 register 0x2c7: bypass sdq cells accepted aggregate count bit type function default 31:0 r acount[31:0] 0 this read-only field contains the aggregate count of all the packets accepted by the bypass sdq. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or any of the bypass sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the bypass sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. acount[31:0] acount is a 32-bit aggregate counter which records the number of cells or packets accepted by the bypass sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 375 document id: pmc-1990553, issue 4 register 0x2c8: bypass sdq cells dropped aggregate count bit type function default 31:16 unused x 15:0 r dcount[15:0] 0 this read-only field contains the aggregate count of all the packets dropped by the bypass sdq due to overflow or transfer errors. this register is latched when a write is performed to the s/uni-atlas-3200 identity / load counts register or to any of the bypass sdq counter registers. after the count is latched into the register, the internal counter is reset to 0 and starts counting again. during the latching of this and other counters, the tip bit is asserted in the bypass sdq control register and s/uni-atlas-3200 identity / load counts register, and remains high for the interval of the update. tip goes low once the counts are valid. the update does not cause the counter to lose any events ? the events after the latching are included in the subsequent count value. dcount[15:0] acount is a 16-bit aggregate counter which records the number of cells or packets dropped by the bypass sdq since last read. it saturates at the maximum value.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 376 document id: pmc-1990553, issue 4 12 test features description simultaneously asserting (low) the csb, rdb and wrb inputs causes all digital output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the s/uni-atlas- 3200. test mode registers (as opposed to normal mode registers) are selected when trs (up_addr[11]) is high. test mode registers may also be used for board testing. when all of the blocks within the s/uni- atlas-3200 are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). in addition, the s/uni-atlas-3200 also supports a standard ieee 1149.1 five-signal jtag boundary scan test port for use in board testing. all digital device inputs may be read and all digital device outputs may be forced with the exception of the pout[7:0] bus via the jtag test port. table 44 test mode register memory map address register 0x000-0x7ff normal mode registers 0x800 master test 0x900 cp test register 0 0x901 cp test register 1 0x902 cp test register 2 ? 0xa00-0xfff reserved notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. writable test mode register bits are not initialized upon reset unless otherwise noted.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 377 document id: pmc-1990553, issue 4 register 0x800: master test bit type function default 7 unused x 6 unused x 5 unused x 4w pmctst x 3 w dbctrl x 2r/w reserved 0 1w hizdata x 0r/w hizio 0 this register is used to enable s/uni-atlas-3200 test features. all bits, except pmctst and ds27_53, are reset to zero by a reset of the s/uni-atlas-3200. hizio, hizdata the hizio and hizdata bits control the tri-state modes of the s/uni-atlas-3200 . while the hizio bit is a logic one, all output pins of the s/uni-atlas-3200 except the data bus and output tdo are held tri-state. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. the hizdata bit is overridden by the dbctrl bit. reserved this bit must be programmed to logic 0. dbctrl the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic one and pmctst is logic one, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the s/uni-atlas-3200 to drive the data bus and holding the csb pin low tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. pmctst the pmctst bit is used to configure the s/uni-atlas-3200 for pmc's manufacturing tests. when pmctst is set to logic one, the s/uni-atlas-3200 microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit can be cleared by setting csb to logic one or by writing logic zero to the bit.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 378 document id: pmc-1990553, issue 4 12.1 test mode 0 details in test mode 0, the s/uni-atlas-3200 allows the logic levels on the device inputs to be read through the microprocessor interface and allows the device outputs to be forced to either logic level through the microprocessor interface. to enable test mode 0, the master configuration and reset register is set to 02h, and the pmctst bit in the master test register is set to logic one. the following addresses must be written with 00h as well: 821h, 831h, 839h, 841h, 849h, 851h, 901h, a01h, a21h, a41h, a61h, a81h, aa1h, ac1h. in addition, the following addresses must be written with 10h: 040h, 048h, 050h. clock edges must be provided on inputs sysclk, xclk, bi_clk, bo_clk, iclk, and oclk when these clocks are not being tested. reading the following address locations returns the values being driven on the indicated device inputs: table 45 test mode 0 read map addr bits[x:y] (31:24) bits[x:y] (23:16) bits[x:y] (15:8) bits[x:y] (7:0) 830h bi_dat[15:8] (15:8) bi_dat[7:0] (7:0) 832h bi_soc (0), bi_par (1), bi_rclav_twrenb (4) 840h bo_rdenb (2) 90fh spar[7:0] (7:0) 910h sdat[31:24] (31:24) sdat[23:16] (23:16) sdat[15:8] (15:8) sdat[7:0] (7:0) 911h sdat[63:56] (31:24) sdat[55:48] (23:16) sdat[47:40] (15:8) sdat[39:32] (7:0) a03h icif_err (8), icif_eop(9), icif_mod[1:0] (11:10), icif_sx (12), icif_soc_sop (13), icif_ctrl (15) icif_par (7) a04h icif_dat[15:8] (15:8) icif_dat[7:0] (7:0) a05h icif_dat[31:24] (15:8) icif_dat[23:16] (7:0) a24h icif_err (8), icif_eop (9), icif_mod[1:0] (11:10), icif_sx (12), icif_soc_sop (13), icif_ctrl (0), icif_addr[5:0] (6:1), icif_par (7) a25h icif_dat[15:8] (15:8) icif_dat[7:0] (7:0) a26h icif_dat[31:24] (15:8) icif_dat[23:16] (7:0) a64h ocif_enb_stpa (0), ocif_addr[5:0] (6:1) a83h ocif_enb_stpa (1), ocif_clav_ptpa (2) note: [x:y] are chip pin designations while (a:b) are the corresponding register bits.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 379 document id: pmc-1990553, issue 4 writing the following address locations forces the outputs to the value in the corresponding bit position (zeros should be written to all unused test register locations). some bit may be written from two different locations, and these are designated with a ?*?. when writing to these locations make sure that the mirror location is written to logic 0: table 46 test mode 0 write map addr bits[x:y] (31:24) bits[x:y] (23:16) bits[x:y] (15:8) bits[x:y] (7:0) 822h up_dmareq (0) 832h bi_rrdenb_tclav (6) 838h bo_par (16), bo_soc (17), bo_clav (18) bo_dat[15:8] (15:8) bo_dat[7:0] (7:0) a07h icif_addr[5:0] (5:0) a27h icif_clav_ptpa (11) a84h ocif_addr[5:0] (5:0) a64h ocif_dat[15:8] (15:8) * ocif_dat[7:0] (7:0) * a85h ocif_dat[15:8] (15:8) * ocif_dat[7:0] (7:0) * a65h ocif_dat[31:24] (15:7) * ocif_dat[23:16] (7:0) * a86h ocif_dat[31:24] (15:7) * ocif_dat[23:16] (7:0) * a66h ocif_par (0) *, ocif_err (1) *, ocif_eop (2) *, ocif_mod[1:0] (4:3) *, ocif_sx (5) * a67h ocif_soc_sop (1) * a83h ocif_eop (8) *, ocif_err (9) *, ocif_par (10) *, ocif_soc_sop (11) *, ocif_sx (12) * ocif_mod[1:0] (5:4) *, notes 1. [x:y] are chip pin designations while (a:b) are the corresponding register bits 2. * indicates signals that may be written from two different locations. be careful to have the mirror location written to logic 0. the following outputs can not be controlled with register writes: sdat[63:0], spar[7:0], icif_enb_stpa, ocif_ctrl. 12.2 jtag test port the s/uni-atlas-3200 jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 380 document id: pmc-1990553, issue 4 table 47 instruction register length - 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 table 48 identification register length 32 bits version number 0h part number 7325h manufacturer's identification code 0cdh device identification 073250cdh table 49 boundary scan register length - 514 bits the boundary scan register has an enable register bit for every output and bidirectional register bit. however, in order to integrate the boundary scan chain with the chip core and pad ring it was necessary to select a small number of the boundary scan enables to control all the output and bidirectional pads. for example, the sdat bus is 64 bits wide and therefore has 64 boundary scan enables associated with it. of these 64 enables only one enable is used, the boundary scan enable associated with the 31 st bit of the bus. consequently, a good portion of the scan chain register bits are unused (marked by a - ). the boundary scan chain numbering begins at 0 with the first bit shifted out on tdo and ends at 513 with the last bit shifted out on tdo. pin enable register bit cell type pin enable register bit cell type bi_dat[15] 0 in_cell saddr[11] oeb_ocif_eop 257 out_cell bi_dat[14] 1 in_cell - 258 bi_dat[13] 2 in_cell saddr[12] oeb_ocif_eop 259 out_cell bi_dat[12] 3 in_cell - 260 bi_dat[11] 4 in_cell saddr[13] oeb_ocif_eop 261 out_cell bi_dat[10] 5 in_cell - 262 bi_dat[9] 6 in_cell saddr[14] oeb_ocif_eop 263 out_cell
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 381 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type bi_dat[8] 7 in_cell - 264 bi_dat[7] 8 in_cell saddr[15] oeb_ocif_eop 265 out_cell bi_dat[6] 9 in_cell - 266 bi_dat[5] 10 in_cell saddr[16] oeb_ocif_eop 267 out_cell bi_dat[4] 11 in_cell - 268 bi_dat[3] 12 in_cell saddr[17] oeb_ocif_eop 269 out_cell bi_dat[2] 13 in_cell - 270 bi_dat[1] 14 in_cell srwb oeb_ocif_eop 271 out_cell bi_dat[0] 15 in_cell - 272 bi_par 16 in_cell sceb oeb_ocif_eop 273 out_cell bi_soc 17 in_cell - 274 bi_rrdenb_tcl av oeb_ocif_eop 18 out_cell spar[0] oeb_sdat 275 io_cell - 19 - 276 bi_rclav_twre nb 20 in_cell spar[1] oeb_sdat 277 io_cell bo_rdenb 21 in_cell - 278 bo_clav oeb_ocif_eop 22 out_cell spar[2] oeb_sdat 279 io_cell - 23 - 280 bo_soc oeb_ocif_eop 24 out_cell spar[3] oeb_sdat 281 io_cell - 25 - 282 bo_par oeb_ocif_eop 26 out_cell spar[4] oeb_sdat 283 io_cell - 27 - 284 bo_dat[0] oeb_ocif_eop 28 out_cell spar[5] oeb_sdat 285 io_cell - 29 - 286 bo_dat[1] oeb_ocif_eop 30 out_cell spar[6] oeb_sdat 287 io_cell - 31 - 288 bo_dat[2] oeb_ocif_eop 32 out_cell spar[7] oeb_sdat 289 io_cell - 33 - 290 bo_dat[3] oeb_ocif_eop 34 out_cell sdat[0] oeb_sdat 291 io_cell - 35 - 292 bo_dat[4] oeb_ocif_eop 36 out_cell sdat[1] oeb_sdat 293 io_cell - 37 - 294 bo_dat[5] oeb_ocif_eop 38 out_cell sdat[2] oeb_sdat 295 io_cell - 39 - 296 bo_dat[6] oeb_ocif_eop 40 out_cell sdat[3] oeb_sdat 297 io_cell - 41 - 298 bo_dat[7] oeb_ocif_eop 42 out_cell sdat[4] oeb_sdat 299 io_cell - 43 - 300
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 382 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type bo_dat[8] oeb_ocif_eop 44 out_cell sdat[5] oeb_sdat 301 io_cell - 45 - 302 bo_dat[9] oeb_ocif_eop 46 out_cell sdat[6] oeb_sdat 303 io_cell - 47 - 304 bo_dat[10] oeb_ocif_eop 48 out_cell sdat[7] oeb_sdat 305 io_cell - 49 - 306 bo_dat[11] oeb_ocif_eop 50 out_cell sdat[8] oeb_sdat 307 io_cell - 51 - 308 bo_dat[12] oeb_ocif_eop 52 out_cell sdat[9] oeb_sdat 309 io_cell - 53 - 310 bo_dat[13] oeb_ocif_eop 54 out_cell sdat[10] oeb_sdat 311 io_cell - 55 - 312 bo_dat[14] oeb_ocif_eop 56 out_cell sdat[11] oeb_sdat 313 io_cell - 57 - 314 bo_dat[15] oeb_ocif_eop 58 out_cell sdat[12] oeb_sdat 315 io_cell - 59 - 316 intb oeb_intb 60 out_cell sdat[13] oeb_sdat 317 io_cell oeb_intb 61 enable - 318 up_rstb 62 in_cell sdat[14] oeb_sdat 319 io_cell up_wrb 63 in_cell - 320 up_rdb 64 in_cell sdat[15] oeb_sdat 321 io_cell up_ale 65 in_cell - 322 up_csb 66 in_cell sdat[16] oeb_sdat 323 io_cell up_dmareq oeb_ocif_eop 67 out_cell - 324 - 68 sdat[17] oeb_sdat 325 io_cell up_busyb oeb_ocif_eop 69 out_cell - 326 - 70 sdat[18] oeb_sdat 327 io_cell up_addr[0] 71 in_cell - 328 up_addr[1] 72 in_cell sdat[19] oeb_sdat 329 io_cell up_addr[2] 73 in_cell - 330 up_addr[3] 74 in_cell sdat[20] oeb_sdat 331 io_cell up_addr[4] 75 in_cell - 332 up_addr[5] 76 in_cell sdat[21] oeb_sdat 333 io_cell up_addr[6] 77 in_cell - 334 up_addr[7] 78 in_cell sdat[22] oeb_sdat 335 io_cell up_addr[8] 79 in_cell - 336 up_addr[9] 80 in_cell sdat[23] oeb_sdat 337 io_cell up_addr[10] 81 in_cell - 338
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 383 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type up_addr[11] 82 in_cell sdat[24] oeb_sdat 339 io_cell up_dat[0] oeb_up_dat 83 io_cell - 340 - 84 sdat[25] oeb_sdat 341 io_cell up_dat[1] oeb_up_dat 85 io_cell - 342 - 86 sdat[26] oeb_sdat 343 io_cell up_dat[2] oeb_up_dat 87 io_cell - 344 - 88 sdat[27] oeb_sdat 345 io_cell up_dat[3] oeb_up_dat 89 io_cell - 346 - 90 sdat[28] oeb_sdat 347 io_cell up_dat[4] oeb_up_dat 91 io_cell - 348 - 92 sdat[29] oeb_sdat 349 io_cell up_dat[5] oeb_up_dat 93 io_cell - 350 - 94 sdat[30] oeb_sdat 351 io_cell up_dat[6] oeb_up_dat 95 io_cell - 352 - 96 sdat[31] 353 io_cell up_dat[7] oeb_up_dat 97 io_cell oeb_sdat 354 enable - 98 sdat[32] oeb_sdat 355 io_cell up_dat[8] oeb_up_dat 99 io_cell - 356 - 100 sdat[33] oeb_sdat 357 io_cell up_dat[9] oeb_up_dat 101 io_cell - 358 - 102 sdat[34] oeb_sdat 359 io_cell up_dat[10] oeb_up_dat 103 io_cell - 360 - 104 sdat[35] oeb_sdat 361 io_cell up_dat[11] oeb_up_dat 105 io_cell - 362 - 106 sdat[36] oeb_sdat 363 io_cell up_dat[12] oeb_up_dat 107 io_cell - 364 - 108 sdat[37] oeb_sdat 365 io_cell up_dat[13] oeb_up_dat 109 io_cell - 366 - 110 sdat[38] oeb_sdat 367 io_cell up_dat[14] oeb_up_dat 111 io_cell - 368 - 112 sdat[39] oeb_sdat 369 io_cell up_dat[15] 113 io_cell - 370 oeb_up_dat 114 enable sdat[40] oeb_sdat 371 io_cell up_dat[16] oeb_up_dat 115 io_cell - 372 - 116 sdat[41] oeb_sdat 373 io_cell up_dat[17] oeb_up_dat 117 io_cell - 374 - 118 sdat[42] oeb_sdat 375 io_cell up_dat[18] oeb_up_dat 119 io_cell - 376
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 384 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type - 120 sdat[43] oeb_sdat 377 io_cell up_dat[19] oeb_up_dat 121 io_cell - 378 - 122 sdat[44] oeb_sdat 379 io_cell up_dat[20] oeb_up_dat 123 io_cell - 380 - 124 sdat[45] oeb_sdat 381 io_cell up_dat[21] oeb_up_dat 125 io_cell - 382 - 126 sdat[46] oeb_sdat 383 io_cell up_dat[22] oeb_up_dat 127 io_cell - 384 - 128 sdat[47] oeb_sdat 385 io_cell up_dat[23] oeb_up_dat 129 io_cell - 386 - 130 sdat[48] oeb_sdat 387 io_cell up_dat[24] oeb_up_dat 131 io_cell - 388 - 132 sdat[49] oeb_sdat 389 io_cell up_dat[25] oeb_up_dat 133 io_cell - 390 - 134 sdat[50] oeb_sdat 391 io_cell up_dat[26] oeb_up_dat 135 io_cell - 392 - 136 sdat[51] oeb_sdat 393 io_cell up_dat[27] oeb_up_dat 137 io_cell - 394 - 138 sdat[52] oeb_sdat 395 io_cell up_dat[28] oeb_up_dat 139 io_cell - 396 - 140 sdat[53] oeb_sdat 397 io_cell up_dat[29] oeb_up_dat 141 io_cell - 398 - 142 sdat[54] oeb_sdat 399 io_cell up_dat[30] oeb_up_dat 143 io_cell - 400 - 144 sdat[55] oeb_sdat 401 io_cell up_dat[31] oeb_up_dat 145 io_cell - 402 - 146 sdat[56] oeb_sdat 403 io_cell icif_dat[31] oeb_icif_dat 147 io_cell - 404 - 148 sdat[57] oeb_sdat 405 io_cell icif_dat[30] oeb_icif_dat 149 io_cell - 406 - 150 sdat[58] oeb_sdat 407 io_cell icif_dat[29] oeb_icif_dat 151 io_cell - 408 - 152 sdat[59] oeb_sdat 409 io_cell icif_dat[28] oeb_icif_dat 153 io_cell - 410 - 154 sdat[60] oeb_sdat 411 io_cell icif_dat[27] oeb_icif_dat 155 io_cell - 412 - 156 sdat[61] oeb_sdat 413 io_cell icif_dat[26] oeb_icif_dat 157 io_cell - 414
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 385 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type - 158 sdat[62] oeb_sdat 415 io_cell icif_dat[25] oeb_icif_dat 159 io_cell - 416 - 160 sdat[63] oeb_sdat 417 io_cell icif_dat[24] oeb_icif_dat 161 io_cell - 418 - 162 ocif_dat[31] oeb_ocif_dat 419 io_cell icif_dat[23] oeb_icif_dat 163 io_cell - 420 - 164 ocif_dat[30] oeb_ocif_dat 421 io_cell icif_dat[22] oeb_icif_dat 165 io_cell - 422 - 166 ocif_dat[29] oeb_ocif_dat 423 io_cell icif_dat[21] oeb_icif_dat 167 io_cell - 424 - 168 ocif_dat[28] oeb_ocif_dat 425 io_cell icif_dat[20] oeb_icif_dat 169 io_cell - 426 - 170 ocif_dat[27] oeb_ocif_dat 427 io_cell icif_dat[19] oeb_icif_dat 171 io_cell - 428 - 172 ocif_dat[26] oeb_ocif_dat 429 io_cell icif_dat[18] oeb_icif_dat 173 io_cell - 430 - 174 ocif_dat[25] oeb_ocif_dat 431 io_cell icif_dat[17] oeb_icif_dat 175 io_cell - 432 - 176 ocif_dat[24] oeb_ocif_dat 433 io_cell icif_dat[16] oeb_icif_dat 177 io_cell - 434 - 178 ocif_dat[23] oeb_ocif_dat 435 io_cell icif_dat[15] oeb_icif_dat 179 io_cell - 436 - 180 ocif_dat[22] oeb_ocif_dat 437 io_cell icif_dat[14] oeb_icif_dat 181 io_cell - 438 - 182 ocif_dat[21] oeb_ocif_dat 439 io_cell icif_dat[13] oeb_icif_dat 183 io_cell - 440 - 184 ocif_dat[20] oeb_ocif_dat 441 io_cell icif_dat[12] oeb_icif_dat 185 io_cell - 442 - 186 ocif_dat[19] oeb_ocif_dat 443 io_cell icif_dat[11] oeb_icif_dat 187 io_cell - 444 - 188 ocif_dat[18] oeb_ocif_dat 445 io_cell icif_dat[10] oeb_icif_dat 189 io_cell - 446 - 190 ocif_dat[17] oeb_ocif_dat 447 io_cell icif_dat[9] oeb_icif_dat 191 io_cell - 448 - 192 ocif_dat[16] oeb_ocif_dat 449 io_cell icif_dat[8] oeb_icif_dat 193 io_cell - 450 - 194 ocif_dat[15] oeb_ocif_dat 451 io_cell icif_dat[7] oeb_icif_dat 195 io_cell - 452
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 386 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type - 196 ocif_dat[14] oeb_ocif_dat 453 io_cell icif_dat[6] oeb_icif_dat 197 io_cell - 454 - 198 ocif_dat[13] oeb_ocif_dat 455 io_cell icif_dat[5] oeb_icif_dat 199 io_cell - 456 - 200 ocif_dat[12] oeb_ocif_dat 457 io_cell icif_dat[4] oeb_icif_dat 201 io_cell - 458 - 202 ocif_dat[11] oeb_ocif_dat 459 io_cell icif_dat[3] oeb_icif_dat 203 io_cell - 460 - 204 ocif_dat[10] oeb_ocif_dat 461 io_cell icif_dat[2] oeb_icif_dat 205 io_cell - 462 - 206 ocif_dat[9] oeb_ocif_dat 463 io_cell icif_dat[1] oeb_icif_dat 207 io_cell - 464 - 208 ocif_dat[8] oeb_ocif_dat 465 io_cell icif_dat[0] 209 io_cell - 466 oeb_icif_dat 210 enable ocif_dat[7] oeb_ocif_dat 467 io_cell icif_par 211 in_cell - 468 icif_eop 212 in_cell ocif_dat[6] oeb_ocif_dat 469 io_cell icif_soc_sop 213 in_cell - 470 icif_sx 214 in_cell ocif_dat[5] oeb_ocif_dat 471 io_cell icif_err 215 in_cell - 472 icif_mod[1] 216 in_cell ocif_dat[4] oeb_ocif_dat 473 io_cell icif_mod[0] 217 in_cell - 474 icif_ctrl 218 in_cell ocif_dat[3] oeb_ocif_dat 475 io_cell icif_addr[5] icif_addr_oeb 219 io_cell - 476 - 220 ocif_dat[2] oeb_ocif_dat 477 io_cell icif_addr[4] icif_addr_oeb 221 io_cell - 478 - 222 ocif_dat[1] oeb_ocif_dat 479 io_cell icif_addr[3] icif_addr_oeb 223 io_cell - 480 - 224 ocif_dat[0] 481 io_cell icif_addr[2] icif_addr_oeb 225 io_cell oeb_ocif_dat 482 enable - 226 ocif_par oeb_ocif_eop 483 out_cell icif_addr[1] icif_addr_oeb 227 io_cell - 484 - 228 ocif_eop 485 out_cell icif_addr[0] 229 io_cell oeb_ocif_eop 486 enable icif_addr_oeb 230 enable ocif_soc_sop oeb_ocif_eop 487 out_cell icif_clav_ptpa oeb_ocif_eop 231 out_cell - 488 - 232 ocif_sx oeb_ocif_eop 489 out_cell icif_enb_stpa oeb_ocif_eop 233 out_cell - 490
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 387 document id: pmc-1990553, issue 4 pin enable register bit cell type pin enable register bit cell type - 234 ocif_err oeb_ocif_eop 491 out_cell saddr[0] oeb_ocif_eop 235 out_cell - 492 - 236 ocif_mod[1] oeb_ocif_eop 493 out_cell saddr[1] oeb_ocif_eop 237 out_cell - 494 - 238 ocif_mod[0] oeb_ocif_eop 495 out_cell saddr[2] oeb_ocif_eop 239 out_cell - 496 - 240 ocif_clav_ptp a 497 in_cell saddr[3] oeb_ocif_eop 241 out_cell ocif_enb_stpa 498 in_cell - 242 ocif_addr[5] oeb_ocif_add r 499 io_cell saddr[4] oeb_ocif_eop 243 out_cell - 500 - 244 ocif_addr[4] oeb_ocif_add r 501 io_cell saddr[5] oeb_ocif_eop 245 out_cell - 502 - 246 ocif_addr[3] oeb_ocif_add r 503 io_cell saddr[6] oeb_ocif_eop 247 out_cell - 504 - 248 ocif_addr[2] oeb_ocif_add r 505 io_cell saddr[7] oeb_ocif_eop 249 out_cell - 506 - 250 ocif_addr[1] oeb_ocif_add r 507 io_cell saddr[8] oeb_ocif_eop 251 out_cell - 508 - 252 ocif_addr[0] 509 io_cell saddr[9] oeb_ocif_eop 253 out_cell oeb_ocif_add r 510 enable - 254 ocif_ctrl oeb_ocif_eop 511 out_cell saddr[10] oeb_ocif_eop 255 out_cell - 512 - 256 halfsecclk 513 in_cell notes: 1. oenb is the active low output enable for d[7:0]. 2. rdatenb is the active low output enable for rsoc, rdat[15:0], and rxprty[1:0]. 3. when set high, intb will be set to high impedance. 4. hiz is the active low output enable for all out_cell types except d[7:0], rxprty[1:0], rdat[15:0], and intb 5. a[7] is the first bit of the boundary scan chain.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 388 document id: pmc-1990553, issue 4 boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table located above. figure 21 input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 22 output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 389 document id: pmc-1990553, issue 4 figure 23 bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 24 layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 390 document id: pmc-1990553, issue 4 13 operations 13.1 configuring the scalable data queue the sdq supports a number of fifo sizes, from 128 bytes (equal to 2 atm cells) to 12,288 bytes (equal to 192 atm cells). the 12,288-byte total storage can be carved up into a maximum of 48 fifos. in order to configure the sdq-atlas, the user first determines the size of each fifo in blocks (1 block = 128 bytes) based on the phys in the system, and adds them all up. the total number of blocks should be less than or equal to 96. the user then needs to program four things for a given phy: fifo pointer ? this is the starting block number, which is an integer from 0 to 95. since there are 96 blocks in total, this is a 7-bit number, as specified in the fifo indirect configuration register (fifo_ptr[6:0] field). there is no restriction on where a phy?s fifo may start, so long as no fifos overlap. fifo size ? this is the size of a fifo measured in blocks. refer to the suggested fifo size encoding table below for the values used to specify the fifo sizes, and a guide to sizing the fifo based on the bandwidth of the associated phy. it is up to the discretion of the user to apply this guide to each specific case. room permitting, it is always acceptable to increase the amount of space for a fifo. this number is specified in the fifo indirect configuration register (fifo_size[6:0] field). packets occupy a number of bytes equal to their length, rounded up to the next multiple of 4 bytes; atm cells occupy 64 bytes apiece, regardless of prepends or postpends. table 50 suggested fifo size encoding fifo size (blocks) fifo size (cells) fifo size (bytes) bandwidth 1 2 128 below sts-1 2 4 256 sts-1 or less 6 12 768 sts-3 24 48 3072 sts-12 or sts-48 96 192 12288 sts-48 fifo type ? this is a single bit which sets the fifo in either pos mode (1) or atm mode (0). this bit must be set to logic 0 for all phys in the input and output sdqs, and to logic 1 for all phys in the packet bypass sdq. this bit is specified in the fifo indirect configuration register (fifo_type field).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 391 document id: pmc-1990553, issue 4 fifo enable ? this is a single bit which enables the fifo (1) or disables the fifo (0). when the fifo is disabled, it refuses to accept any data, but data can still be read from it. this bit is specified in the fifo indirect configuration register (fifo_enbl field). unused phys should be left disabled, and should have their flush bit set. only atm phys should be enabled in the input and output sdqs, and only packet phys should be enabled in the bypass sdq. a fifo should be disabled and emptied if it is to be reconfigured. starting from the fifo pointer, a fifo occupies the number of blocks specified by its fifo size. the user should not configure the fifo pointers such that two fifos overlap. the user can, however, have gaps between consecutive fifos. this is useful when the fifo size needs to be adjusted dynamically. the following table illustrates the configuration for a typical case. this example involves 3 phys that have a bandwidth of sts-12, and are allocated 24 blocks each. in addition, there are 1 sts-3 phy with a fifo size of 6 blocks, 6 sts-1 phys each with a fifo size of 2 blocks, and 3 t1 phys each with a fifo size of 1 block. the sum of all the blocks used in this example is 93, which is less than the total number of blocks available, 96. table 51 sdq-atlas configuration example phyid bandwidth fifo pointer fifo size (blocks) fifo size (cells) 0 sts-12 0 24 48 1sts-1224 24 48 3sts-348 6 12 4sts-154 2 4 5sts-156 2 4 2sts-1258 24 48 6sts-182 2 4 7sts-184 2 4 8sts-186 2 4 9sts-188 2 4 12 t1 90 1 2 10 t1 91 1 2 15 t1 92 1 2 blocks 93 to 95 are not used in this example. potentially, users can configure three more 1-block fifos, or one more 1-block fifo and one more 2-block fifo, or to enlarge phy #15 to 4 blocks, and so on. note that the fifos are not required to be adjacent to each other; gaps are allowed between fifos. for example, phy #10 could start at block 93. the sdq cannot detect errors due to user misconfiguration. if the user sets up fifos that overlap each other, or start at an illegal fifo position (e.g. a number greater than 95) or with an illegal fifo size (i.e. 0, 97-127), the results will be unpredictable. in terms of the actual programming sequence for a given fifo, the recommended sequence is as follows:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 392 document id: pmc-1990553, issue 4 1. read the indirect address register until busy = 0 2. write the desired values into the indirect configuration register 3. write to the indirect address register with rwb = 0, phyid = desired phy, and flush = 1 4. poll the indirect address register until busy = 0 5. write to the indirect address register with rwb = 0, phyid = desired phy, and flush = 0 when reconfiguring the sdq while traffic is passing through, all fifos that are being affected by the reconfiguration should be disabled and flushed, and held that way until the reconfiguration is complete. fifos unaffected by the reconfiguration will continue to carry traffic normally. 13.2 jtag support the s/uni-atlas-3200 supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown:
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 393 document id: pmc-1990553, issue 4 figure 25 boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 394 document id: pmc-1990553, issue 4 13.2.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described: figure 26 tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 395 document id: pmc-1990553, issue 4 test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 396 document id: pmc-1990553, issue 4 boundary scan instructions the following is an description of the standard instructions. each instruction selects an serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out output, tdo using the shift-dr state. 13.3 board design recommendations recommendations for board design are contained in the s/uni-atlas-3200 with mach-48 reference design, pmc-2000718.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 397 document id: pmc-1990553, issue 4 14 functional timing 14.1 pos-phy level 3 14.1.1 ingress packet interface when the s/uni-atlas-3200 is required to carry a mix of cells and packets, a pos-phy level 3 interface is used. in the ingress direction, the s/uni-atlas-3200 provides an rx phy interface on the system side, and an rx link interface on the phy side. selection of ingress vs. egress mode and pos vs ul3 signalling must be performed at startup. figure 27 illustrates the operation of the interface. the figure is valid for both the rxlink and rxphy blocks (on input and output, respectively), with the ?x? in the signal names replaced with ?l? for the rxlink and ?p? for rxphy. the pos-phy receive interface is controlled by the phy layer. it is presumed that the link layer device can accept data at full line rate, so backpressure is limited to a single rxp_enb signal. at the beginning of a transfer, rxp_sx is asserted to indicate that the phy address is on rxp_dat. in the subsequent cycle, rxp_sop is asserted to mark the first word of the packet. at any time, the phy layer may pause the transfer by deasserting rxp_val. at the end of a packet, rxp_mod becomes valid to indicate how many of the final 4 bytes (between 1 and 4) are valid. rxp_err may be asserted in this cycle to indicate that the packet is in error. phy devices generally assert rerr to indicate that hdlc abort flags rather than normal hdlc flags were received at the end of a packet; s/uni-atlas-3200 will assert rpp_rerr when transmitting packets if rlp_rerr was asserted when the packet was received or, configurably, if an interface error such as a parity error was detected.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 398 document id: pmc-1990553, issue 4 figure 27 pos-phy level 3 ingress logical timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 d0 d1 d2 d14 d15 d16 d17 0001 d1 ....... ...... 0 0 2 0 rpp_clk rpp_sx rpp_sop rpp_eop rpp_err rpp_enb rpp_dat[31:0] rpp_mod[1:0] rpp_par rpp_val on the rxlink interface, the s/uni-atlas-3200 will deassert rlp_rdenb to pause a transaction if any of the per-phy queues backs up. however, so long as s/uni-atlas-3200 is properly provisioned, and rpp_rdenb is never asserted to s/uni-atlas-3200 by the switch or tm, then this will not occur. on the rxphy interface, the s/uni-atlas-3200 will not update its outputs when it samples rpp_enb deasserted. transferring cells over this interface is just like transferring packets. the length of the cells is programmed into the rxphy and rxlink blocks so that they can correctly generate and interpret the packet, but as far as the interface is concerned, atm cells are simply 52, 56, 60, or 64-byte packets. there exists an option, using the atm_field and pos_field bits in the rxphy and rxlink blocks, to insert and check an identifier in the top 8 bits of rdat during the rlp_sx cycle, which identifies atm vs packet data. this feature is useful in detecting misconfigurations in the selection of packet vs. atm phys. rxlink pos-phy logical timing in the ingress direction, the s/uni-atlas-3200 input cell/packet interface acts as a receive link layer device, and the upstream device acts as a phy layer device, for the purposes of pos- phy level 3 transfers.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 399 document id: pmc-1990553, issue 4 figure 28 rxlink pos-phy packet transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 h1 d0 d1 d3 d4 d6 d7 0001 d1 d2 0 0 2 0 rlp_clk rlp_sx rlp_sop rl p_ eop rl p_ err rl p_ enb rlp_da t[31:0] rl p_ pa r rlp_mod[1:0] rlp_v a l figure 28 is an example of a multi-port phy device with at least two channels. the phy informs the s/uni-atlas-3200 of the port address of the selected fifo by asserting rlp_sx with the port address on the rlp_dat bus in cycle 2. the link layer may pause the receive interface at any time by deasserting the rlp_enb signal. the end of the packet is indicated with the rlp_eop signal. the next transfer starts by asserting rlp_sx in cycle 14. if an error occurred during the reception of the packet, the rlp_err would be asserted with rlp_eop.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 400 document id: pmc-1990553, issue 4 figure 29 rxlink back to back pos-phy packet transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 h1 d0 d1 d3 d4 d6 d7 h1 d1 d2 0 0 2 0 rlp_clk rlp_sx rlp_sop rl p_ eop rl p_ err rl p_ enb rlp_da t[31:0] rl p_ pa r rlp_mod[1:0] rlp_v a l figure 29 is an example of a multi-port phy device performing a back to back packet transfer. the phy informs the s/uni-atlas-3200 of the port address of the selected fifo by asserting rlp_sx with the port address on the rlp_dat bus. the link layer may pause the receive interface at any time by deasserting the rlp_enb signal. the end of the packet is indicated with the rlp_eop signal. thus, the next subsequent fifo transfer for this port would be the start of the next packet. if an error occurred during the reception of the packet, the rlp_err would be asserted with rlp_eop.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 401 document id: pmc-1990553, issue 4 figure 30 rxlink pos-phy atm cell transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 h1 d0 d11 0008 h1 d0 d1 d2 0 d1 rlp_clk rlp_sx rlp_sop rl p_ eop rl p_ err rl p_ enb rlp_da t[31:0] rl p_ pa r rlp_mod[1:0] rlp_v a l figure 30 is an example of atm cells being transferred over the pos-phy interface. the transfer is initiated with rlp_sx and the address insertion on the rlp_dat bus. after 3 clocks, the link layer decides to pause the transfer with the deassertion rlp_enb. the phy layer must discontinue transfer immediately as shown, holding d2 on the rlp_dat bus. transfer commences when the rlp_enb signal is asserted. cell traffic continues to flow until the phy layer has run out of data, at which time it deasserts rlp_val. s/uni-atlas-3200 may pause a transfer via rlp_enb in the middle of a cell or packet; however, generally speaking s/uni- atlas-3200 will not need to do so as long as no backpressure is applied at the output of the device, and the device is properly configured. cells and packets may be interleaved, but must be on separate phys. rxphy pos-phy logical timing in the ingress direction, the s/uni-atlas-3200 output cell/packet interface acts as a receive phy layer device, and the downstream device acts as a link layer device, for the purposes of pos-phy level 3 cell transfer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 402 document id: pmc-1990553, issue 4 the pos-phy receive interface is controlled by the s/uni-atlas-3200 phy layer device. all signals must be updated and sampled using rpp_clk. the rpp_dat bus, rpp_par, rpp_mod, rpp_sop, rpp_eop and rpp_err signals are valid in cycles for which rpp_val is high. outputs will not be updated by the pos-phy receive phy interface when it samples rpp_enb deasserted. in the example below, rpp_enb is deasserted by the link layer in cycle 4. the s/uni-atlas-3200 interface samples it in cycle 5, and does not update the interface in cycle 6. when transferring data, rpp_val is asserted and remains high until the internal fifo of the phy layer device is empty, or a complete burst is transferred. a burst always ends at an eop. the rpp_sx signal is valid in the cycle for which rpp_val is low and rpp_enb was low in the previous cycle. figure 31 rxphy pos-phy packet transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 d0 d1 d2 d14 d15 d16 d17 0001 d1 ....... ...... 0 0 2 0 rpp_clk rpp_sx rpp_sop rpp_eop rpp_err rpp_enb rpp_dat[31:0] rpp_mod[1:0] rpp_par rpp_val figure 31 is an example of a multi-port phy device with at least two channels. the phy informs the link layer device of the port address of the selected fifo by asserting rpp_sx with the port address on the rpp_dat bus. the link layer may pause the receive interface at any time by deasserting the rpp_enb signal. the end of the packet is indicated with the rpp_eop signal, along with any error condition on rpp_err. the receive pos-phy interface bursts data in 16 word bursts. a burst always ends at an eop, and rsx is always asserted before the start of another burst. the receive phy interface selects phy 1 for the next burst, which starts at cycle 15.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 403 document id: pmc-1990553, issue 4 figure 32 rxphy pos-phy atm cell transfer 1 2 3 4 5 6 7 8 9 1 0 0000 h1 d0 d11 ....... ...... d1 d2 0 rpp_clk rpp_sx rpp_sop rpp_eop rpp_err rpp_enb rpp_dat[31:0] rpp_mod[1:0] rpp_par rpp_val figure 32 is an example of 52-byte atm cells being transferred over the pos-phy interface. the transfer is initiated with rpp_sx and the address insertion on the rpp_dat bus. after 3 clocks, the link layer decides to pause the transfer by deasserting rpp_enb. the s/uni- atlas-3200 discontinues the transfer immediately as shown, holding d2 on the rpp_dat bus. unless paused by rpp_enb, the s/uni-atlas-3200 always transfers entire cells, ending with an rpp_eop. a new rpp_sx selection cycle will occur before another cell or packet is transferred.. cells and packets may be interleaved, but must be on separate phys. 14.1.2 egress packet interface when the s/uni-atlas-3200 is required to carry a mix of cells and packets, a pos-phy level 3 interface is used. in the egress direction, the s/uni-atlas-3200 provides a tx phy interface on the input (system) side, and a tx link interface on the output (phy) side. selection of ingress vs. egress mode and pos vs ul3 signaling must be performed at startup. the pos-phy egress transmit interface is controlled by the link layer device. figure 33 is an example of the txlink block of s/uni-atlas-3200 polling and transmitting to a multi-port phy device with several channels. the egress input interface (the txphy block) works exactly the same way, except that the signals have a tpp (transmit phy pos) prefix, and the s/uni- atlas-3200 plays the role of the phy rather than the link layer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 404 document id: pmc-1990553, issue 4 all signals must be updated and sampled using the rising edge of the transmit fifo clock, tlp_clk (tpp_clk on the input side). at the beginning of a transfer, tlp_sx is asserted to indicate that the phy address is on the data bus tlp_dat. in the subsequent cycle, tlp_sop is asserted to show that the first word is present on tlp_dat, and tlp_enb is asserted low to indicate valid data. the transfer may be paused at any time by the link layer by deasserting tlp_enb. s/uni-atlas-3200 will typically move on to another phy by asserting tlp_sx at this point, but it is not required to. the phy layer may indicate the that the phy being transferred to is near-full by deasserting tlp_stpa. the link layer must then stop the transfer; it may pause the transfer and resume it once tlp_stpa is reasserted, or it may move on to a different phy. at the end of a packet, tlp_eop is asserted. tlp_mod is valid during the cycle, and indicates how many bytes (between 1 and 4) are valid at the end of the packet. tlp_err is also valid during this cycle, and indicates that a packet is errored in some way. s/uni-atlas-3200 will assert terr if the traffic manager indicated the packet was in error, or (configurably) if an interface error such as a parity error was detected. figure 33 pos-phy level 3 egress logical timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 0000 d0 d47 d48 d49 d50 0001 d16 ....... ...... d1 d2 ...... p1 p1 p2 p4 p0 p1 p4 p0 p2 p4 p0 p1 p2 p2 p4 p4 p2 p4 p0 p1 p0 ...... 0 0 0 1 0 .... .... .... p1 p0 p1 ...... tlp_clk tlp_sx tlp_sop tlp_eop tlp_err tlp_enb tlp_dat[31:0] tlp_mod[1:0] tlp_par tlp_stpa tlp_addr[5:0] tlp_ptpa transferring cells over this interface is just like transferring packets. the length of the cells is programmed into the txphy and txlink blocks so that they can correctly generate and interpret the packet, but as far as the interface is concerned, atm cells are simply 52, 56, 60, or 64-byte packets. there exists an option, using the atm_field and pos_field bits in the txphy and txlink blocks, to insert and check an identifier in the top 8 bits of tdat during the tlp_sx cycle, which identifies atm vs packet data. this feature is useful in detecting misconfigurations in the selection of packet vs. atm phys.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 405 document id: pmc-1990553, issue 4 txphy pos-phy logical timing the s/uni-atlas-3200 input interface in the egress direction acts as a tx phy layer device. this interface is controlled by the attached link layer device using the tpp_tenb signal. figure 34 is an example of polling and transmission to a multi-port phy device with several channels. the s/uni-atlas-3200 indicates that a fifo has at least 16 32-bit words or more of space available by asserting tpp_ptpa when it is polled by the link layer. polling is accomplished with the tpp_addr[5:0] signal. after selection, packet available status is indicated by asserting the selected transmit packet available signal tpp_stpa. tpp_stpa remains asserted while the phy is selected and until the transmit fifo is almost full. when tpp_stpa transitions low, it indicates that there are less than 16 32-bit words available in the transmit fifo. the latency on this signal is no more than 8 cycles. if stpa is being used, the source must take this latency into account in using stpa to avoid overflow. the use of stpa is optional; the source may safely rely solely on ptpa figure 34 txphy pos-phy packet transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 0000 d0 d47 d48 d49 d50 0001 d16 ....... ...... d1 d2 ...... p1 p1 p2 p4 p0 p1 p4 p0 p2 p4 p0 p2 p4 p4 p2 p1 p0 ...... 0 0 0 1 0 .... .... .... p0 p1 ...... tpp _clk tpp _sx tpp _sop tpp _eop tpp _err tpp _enb tpp_dat[31:0] tpp _mod[1:0] tpp _pa r tpp_stpa tpp_addr[5:0] tpp_ptpa figure 35 is an example of the link layer device polling and sending atm cells across the pos interface to the s/uni-atlas-3200 transmit phy interface. the link layer device is not restricted in its polling order. cells and packets may be interleaved, but they must belong to separate fifos.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 406 document id: pmc-1990553, issue 4 figure 35 transmit pos-phy atm cell transfer 1 2 3 4 5 6 7 8 9 10 11 12 0000 h1 d0 h1 ...... d12 d1 d2 ...... ...... d12 ...... ...... ...... p1 p2 p3 p0 p1 p0 p1 p3 p0 p1 p2 p3 p2 ...... p1 ...... ...... ...... h1 0 0 0 0 0 p0 p1 ...... ...... p3 p0 0001 tpp _clk tpp _sx tpp _sop tpp _eop tpp _err tpp _enb tpp_dat[31:0] tpp _mod[1:0] tpp _pa r tpp_stpa tpp_addr[5:0] tpp_ptpa txlink pos-phy logical timing the s/uni-atlas-3200 output interface in the egress direction acts as a tx link layer device. this interface controls the attached phy layer device using the tlp_enb signal.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 407 document id: pmc-1990553, issue 4 figure 36 txlink pos-phy logical timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d15 p1 d4 p2 d5 d1 d2 p0 p1 p2 p4 p0 p1 p4 p1 p2 p4 p0 p1 p2 p2 p4 p4 p2 p4 p0 p0 p1 030 d14 p1 p1 d32 d33 3 d0 d3 p2 p2 30 p1 tlp_clk tlp_sx tlp_sop tlp_eop tlp_err tlp_enb t lp_dat[31:0] tlp_par tlp_mod[1:0] tlp_stpa t lp_addr[5:0] tlp_ptpa figure 36 is an example of polling and transmission to a multi-port phy device with several channels. the phy layer device indicates that a fifo is not full by asserting tlp_ptpa when it is polled by the s/uni-atlas-3200. polling is accomplished with the tlp_addr[5:0] signal. after selection, packet available status is indicated by asserting the selected transmit packet available signal tlp_stpa. tlp_stpa remains asserted while the phy is selected and until the transmit fifo is almost full. the s/uni-atlas-3200 will halt data transfer three clocks after tlp_stpa is driven low on the bus, if the use_stpa register bit is logic 1. the s/uni- atlas-3200 will then select the next phyid in the calendar which has a positive ptpa response and for which data is available in the s/uni-atlas-3200. the s/uni-atlas-3200 will transmit packets in 16 word bursts. in cycle 1 and 2, a 16 word burst is completing for a packet. in cycle 3, phy p1 is selected for transfer and the phy device indicates the selected phy is nearly full by deasserting tlp_stpa in cycle 6. the atm layer device halts data transfer in cycle 9. phy p1 is again polled in cycle 9, and the phy device indicates that it has space for additional data. the atm layer device selects phy p1 in cycle 14, and continues the packet transfer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 408 document id: pmc-1990553, issue 4 figure 37 txlink pos-phy atm cell transfer timing 1 2 3 4 5 6 7 8 9 10 11 12 13 p1 d0 d1 d13 d14 d15 d2 d8 d9 d0 3 0 p1 d10 3 p1 tlp_clk tlp_sx tlp_sop tlp_eop tlp_err tlp_enb tlp_dat[31:0] tlp_pa r1 tlp_mod[1:0] tlu_a ddr[5:0] tl p_ ptpa figure 37 is an example of the link layer device sending atm cells across the pos interface. the status of a given phy port may be determined by setting the polling address tlu_addr bus to the port address. the polled transmit packet available signal tlp_ptpa is updated with the transmit fifo status in a pipelined manner. the link layer device is not restricted in its polling order. the selected transmit packet available tlp_stpa signal allows monitoring the selected phy status and halting data transfer once the fifo is full. in this case, phy p1 is being polled continuously on tlu_addr. the phy device indicates that there is no space for the next burst by driving tlp_ptpa low in cycle 5. note that the atm link layer device will ignore tlp_ptpa for the selected phy until 3 clocks after selection. later on in cycle 6 of the diagram during the transfer of word d8, the phy indicates that there actually is space in the transmit fifo for an additional cell. for back to back atm cells on the pos interface, the phy device must indicate tlp_ptpa asserted no less then five clocks before the last word of the transfer. cells and packets may be interleaved, but they will belong to different fifos. 14.2 utopia level 3 the s/uni-atlas-3200 features utopia level 3 compliant interfaces to the phy side and the system side. the s/uni-atlas-3200 acts as a master to the phy side (like any other ul3 atm layer device), and appears as a 48-phy device to the system side. to accommodate system side devices which may not support multi-phy queues in the ingress direction, the output cell interface supports a ?self-polled? mode in which it will ignore the presented utopia address and appear as a single phy.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 409 document id: pmc-1990553, issue 4 14.2.1 ingress ul3 interface in the ingress direction, the s/uni-atlas-3200 provides an rx link interface on the input (phy) side, and an rx phy interface on the output (system) side. selection of ingress vs. egress mode and pos vs ul3 signalling must be performed at startup. figure 38 shows the format of an rx utopia transfer. on the input (rxlink) side the ?x? in the signals is a ?l?; on the output (rxphy) side the ?x? is a ?p?. the rx interface in ul3 is controlled by the downstream atm layer (aka link layer) device, which polls the phy layer device, and uses rxp_rdenb to select phys for transfer, and enable the transfer. once a transfer has been initiated, it must be completed. figure 38 ingress utopia logical timing 1 2 3 4 5 6 7 8 91 0 phy 07 phy 08 phy 09 phy 00 phy 02 phy 03 phy 04 da t12 da t11 da t10 da t9 phy 05 phy 06 phy 06 h1 da t0 da t1 da t2 da t3 phy 08 phy 07 phy 06 rxp_clk rxp_addr[5:0] rxp_clav rxp_rdenb rxp_dat[31:0] rxp_soc rxp_par the receive link layer interface is a regular ul3 mphy interface. the receive phy layer interface, however, can operate either as a mphy interface, or as a single-phy interface. the single-phy interface, selected via the servicing override bit in the rxp configuration register, allows the s/uni-atlas-3200 to interface to a mphy device on its input, and to an non-phy- aware, single-phy switch fabric on the other. in this case, cells will be drawn from the internal phy queues as determined by the rxp calendar. this operation is transparent to the switch, which sees a single-phy interface. rxlink utopia logical timing in the ingress direction, the s/uni-atlas-3200 input cell/packet interface acts as a receive atm layer device, and the upstream device acts as a phy layer device, for the purposes of utopia level 3 cell transfer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 410 document id: pmc-1990553, issue 4 figure 39 rxlink utopia cell transfer 1 2 3 4 5 6 7 8 9 phy4 phy7 phy8 phy5 phy1 phy1 3 phy11 phy0 d12 d11 d10 h1 d0 d1 d2 d9 phy 4 phy7 phy8 rlu_clk rlu_a ddr[5:0] rlu_cla v rlu_rdenb rlu_da t[31:0] rlu_pa r rlu_rsoc the utopia receive interface is controlled by the atm layer device. figure 39 shows the s/uni-atlas-3200 polling the phy layer device with the address bus in order to gather cell available status. the phy layer device can send a cell to an atm port only when phy port has indicated that it has at least one complete atm cell available and when the atm port has indicated to the phy layer device that it is ready to receive a cell. the s/uni-atlas-3200 will indicate this by asserting the rlu_rdenb in response to a receive cell available (rlu_clav) signal from the phy device. once the rlu_clav signal has been asserted, the phy layer is committed to a cell transfer. figure 39 shows that phy 8 is engaged for transfer with the selection cycle in cycle 4. phy 8 has two clocks to respond and does so with data in cycle 6. figure 40 rxlink back-to-back utopia cell transfers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d7 d6 d5 d9 d10 d11 d12 phy 8 d8 h1 d4 rlu_clk rlu_a ddr[5:0] rlu_cla v rlu_rdenb rl_dat[31:0] rlu_pa r rlu_rsoc
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 411 document id: pmc-1990553, issue 4 figure 40 shows the rxlink i/o datapath signals for utopia back to back transfer. two cells are shown being transferred from the same phy address (phy 8) with a dead cycle in between. in order for full bandwidth support, rlu_clav must be asserted at least 8 clock cycles before the end of the current transfer. see cycle 2. note also that the rxlink squelches rlu_clav up to rlu_rsoc+1 cycles if the phyid being serviced is identical to the one being polled. this is to guarantee that the rlu_clav sent to the rxlink is not for the current cell being serviced, but for the next cell transfer. s/uni-atlas-3200 always reselects the phy by temporarily deasserting rlu_rdenb between cell transfers. rxphy utopia timing in the ingress direction the s/uni-atlas-3200 output cell/packet interface acts as a receive phy layer device, and the downstream device acts as an atm layer device, for the purposes of utopia level 3 cell transfer. figure 41 rxphy utopia cell transfer 1 2 3 4 5 6 7 8 9 10 1 1 phy07 phy08 phy09 phy00 phy02 phy03 phy04 d12 d11 d10 d9 phy05 phy06 phy06 h1 d0 d1 d2 d3 phy08 phy07 phy06 rpu_clk rpu_addr[5:0] rpu_clav rpu_rdenb rpu_dat[31:0] rpu_soc rpu_par the s/uni-atlas-3200 utopia receive phy interface is controlled by the attached atm layer device. figure 41 shows the atm layer polling the s/uni-atlas-3200 device with the address bus in order to gather cell available status. the s/uni-atlas-3200 will assert rpu_clav only when it can transfer an entire cell. the atm layer device will read the cell by asserting the rpu_rdenb in response to a receive cell available (rpu_clav) signal from the s/uni-atlas-3200 device. figure 41 shows that phy08 is engaged for transfer with the selection cycle in clock number 4. phy08 has two clocks to respond and does so with data in cycle 6. the rxphy is capable of appearing as a single-phy device, removing the need for polling. in this case the rxphy will use an internal calendar to determine the order in which the phy queues are serviced. single-phy operation is controlled via the servicing override bit in the rxp configuration register.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 412 document id: pmc-1990553, issue 4 14.2.2 egress ul3 interface in the egress direction, the s/uni-atlas-3200 provides a tx phy interface on the input (system) side, and a tx link interface on the output (phy) side. selection of ingress vs. egress mode and pos vs ul3 signalling must be performed at startup. figure 42 shows the egress txlink interface that interfaces to the phy side; the txphy interface operates in the same way, but the signal names start with tpu, and the s/uni-atlas-3200 plays the role of the phy. figure 42 egress utopia logical timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 ...... p5 p3 p4 p5 p0 p1 p3 p4 p0 p1 p2 ...... p4 p3 p5 p3 p0 p5 p4 ...... h1 d10 d11 h1 d1 ...... d11 ....... ...... d1 d2 ...... ...... ...... p4 d0 d0 ...... p0 p1 ...... p1 p2 tlu_clk tlu_addr[5:0] tlu_clav tlu_wrenb tlu_soc tlu_dat[31:0] tlu_par the s/uni-atlas-3200 can send a cell to a phy port only when the phy port has indicated to the atm layer device that it is ready to receive at least one cell. the phy device will indicate this by asserting the transmit cell available (tlu_clav). the phy device must deassert the txclav 2 cycles after sampling tlu_soc high if it cannot accept the immediate transfer of a subsequent cell. txphy utopia logical timing in the egress direction the s/uni-atlas-3200 input cell/packet interface acts as a transmit phy layer device, and the upstream device acts as an atm layer device, for the purposes of utopia level 3 cell transfer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 413 document id: pmc-1990553, issue 4 figure 43 txphy utopia cell transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 p3 h1 d11 d12 h1 d1 ...... d12 ....... ...... d1 d2 ...... ...... d0 d0 ...... p3 tpu_clk tpu_addr[5:0] tpu_clav tpu_w renb tpu_soc tpu_dat[31:0] tpu_pa r the atm layer device can send a cell to the s/uni-atlas-3200 transmit phy port only when the s/uni-atlas-3200 has indicated to the atm layer device that it is ready to receive at least one cell. the s/uni-atlas-3200 will indicate this by asserting the transmit cell available (tpu_clav). in this case, the atm layer is only polling a single phy. the s/uni-atlas- 3200 will deassert tpu_clav one cycle after tpu_soc if it cannot accept the immediate transfer of a subsequent cell. once tpu_clav has been asserted, it will have to stay asserted until the clock edge after the start of cell (tpu_soc). figure 43 shows the case in which cells are transferred back-to-back, utilizing the full bandwidth of the bus. this can be achieved in the case where the s/uni-atlas-3200 indicates 1 cycle after tpu_soc that it can accept at least one complete cell in addition to the current cell (tpu_clav asserted) and the atm device has a cell ready for transfer. txlink utopia logical timing in the egress direction the s/uni-atlas-3200 output cell/packet interface acts as a transmit atm layer device, and the downstream device acts as a phy layer device, for the purposes of utopia level 3 cell transfer.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 414 document id: pmc-1990553, issue 4 figure 44 txlink utopia transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ...... p3 p4 p3 p0 p1 p4 p3 p1 p2 ...... p4 p3 p4 ...... h1 d10 d11 d1 ...... d11 ....... d1 d2 ...... ...... p4 d0 d0 ..... ..... ..... p5 p5 tlu_clk tlu_addr tlu_clav tlu_wren b tlu_soc t lu_dat[31:0] tlu_par the utopia transmit interface is controlled by the s/uni-atlas-3200. figure 44 shows the s/uni-atlas-3200 polling the phy layer device with the address bus (tlu_addr) to gather transmit cell available status (tlu_clav). the s/uni-atlas-3200 can send a cell to a phy port only when the phy port has indicated to the s/uni-atlas-3200 device that it is ready to receive at least one cell. the phy device will indicate this via tlu_clav. the tlu_clav in response to the phy selection (i.e. the value of tlu_clav in cycle 4) is ignored by the link device. once tlu_clav has been asserted for a particular phy queue, it will have to stay asserted for that phy until a cell is transmitted to the phy layer device on that phy queue. figure 44 shows that a cell is engaged for transfer to phy 3 with the selection cycle in cycle 2. figure 45 txlink back-to-back utopia transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d5 d10 d11 d1 d1 d8 d6 d0 p8 d9 d7 d4 d3 d2 tlu_clk tlu_a ddr tlu_cla v tlu_wrenb tlu_soc tlu_da t[31:0] tlu_pa r
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 415 document id: pmc-1990553, issue 4 figure 45 shows the s/uni-atlas-3200 performing a back to back transfer. two cells are shown being transferred to the same phy address (phy 8) with a selection cycle in between. s/uni-atlas-3200 will always perform this selection between cells. in order for full bandwidth support, tlu_clav must be asserted at least 5 clock cycles before the end of the current transfer. see cycle 6. note also that the atm layer device ignores tlu_clav responses from the phy up until cycle 14, for the purposes of deciding whether to transfer yet another cell on the same phy. the cycle after selection, cycle 12, is the first cycle it is valid for the atm layer device to poll the selected phy to determine if it has space for the next cell transfer. this is to guarantee that the tlu_clav sent to the atm layer is not for the current cell being serviced, but for the next cell transfer. 14.3 sram interface the s/uni-atlas-3200 stores the search and linkage tables in up to 16m of external sram. the sram may be in two 256kx36 or one 256kx72 units, and must be pipelined zbt sram?s rated for at least a 7ns cycle time. only 8m of external sram (e.g. two 128kx36) is required to support 64k connections. however, up to 16m of ram may be provisioned if the additional search depth is desired. 18 address bits are provided, to support up to a 256kx72 external sram. if less sram is provisioned, the msb of the ram address should still be connected to saddr[17]; saddr[16] may be left unconnected if only 8m of external sram is needed, saddr[16:15] if only 4m, and so on. to facilitate timing from s/uni-atlas-3200 to the srams, the device drives the sram clock (sramclk_o) along with the address, data, and control signals. to facilitate timing from the sram to the s/uni-atlas-3200, a copy of sramclk_o , called sysclk_o, must be fed back into the device on the sysclk pin. this arrangement is illustrated in figure 46.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 416 document id: pmc-1990553, issue 4 figure 46 interface between s/uni-atlas-3200 and external ram 128 k x 36 pipelined zbt sram s/uni-atlas-3200 scsb srwb saddr[17:0] spar[7:0] sdat[63:0] sramclk_o sysclk 128 k x 36 pipelined zbt sram spar[3:0] spar[7:4] sdat[31:0] sdat[63:32] clock source 125 mhz xclk sysclk_o figure 47 illustrates the operation of the sram interface. the majority of accesses to the external srams are reads, with the occasional write initiated by the microprocessor. as as a result, the csb signal is used to insert dead cycles between reads and writes, to facilitate easy board design. figure 47 sram interface functional timing 1 rd 2 rd 3 r d no p 4 wr no p 5 rd 6 rd 1 r d 2 rd 3 rd 4 w 5 rd 6 rd sramclk_o sa ddr srwb scsb sdat,spar sysclk
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 417 document id: pmc-1990553, issue 4 14.4 backwards cell interface figure 48 normal bcif functional timing x x x xx w1 w2 w27 w28 w29 w30 w31 w32 xx w1 bi_clk / bo_clk bo_clav -> bi_rclav_twrenb bo_soc -> bi_soc bi_rrenb_tclav -> bo_rdenb bo_par -> bi_par bo_dat[15:0] -> bi_dat[15:0] in a typical implementation, the bcifs of two s/uni-atlas-3200 devices are wired directly to each other. in this case, the ibcif is an rx master, and the obcif is an rx slave. bi_rclav_twrenb is acting as bi_rclav. figure 48 shows a cell transfer, 64 bytes in length, and the start of a second transfer. figure 49 ibcif as tx slave functional timing calevl0 = 0 (4 cycles early) x x xx w1 w2 w3 w32 w1 w2 w27 w2 8 w29 w30 w31 w32 xx w1 w2 bi_clk bi_rrenb_tclav bi_soc bi_rclav_twrenb bi_par bi_dat[15:0] in some implementations, such as when connecting a tester or another device to the interface, it may be desirable to set the ibcif_txslave bit to logic 1. in this case, the bcif as a whole appears like a phy device, i.e. with one tx slave and one rx slave. bi_rclav_twrenb is actiing as bi_twrenb. in this configuration, back-to-back cells may be transferred.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 418 document id: pmc-1990553, issue 4 15 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 52 absolute maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage (vdd33) -0.3v to +3.9v supply voltage (vdd25, vddq25) -0.3v to 3.5v supply voltage (vddq15) -0.3v to +3.0v supply voltage (vdd15) -0.3v to +3.0v voltage on any 3.3v i/o pin -0.3v to vdd33 + 0.3v voltage on any 2.5v i/o pin (i.e. the sram interface) -0.3 to vdd25 + 0.3 v static discharge voltage 1000 v latch-up current 100 ma dc input current 10 ma lead temperature +230c absolute maximum junction temperature +125c
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 419 document id: pmc-1990553, issue 4 16 d.c. characteristics tj = 0c to tj=100c, vdd33 = 3.3 v 0. 165v, vddq25 = 2.5 0.125v, vdd25 = 2.5 0.125v, vddq15 = 1.5 v 0.075v, vdd15 = 1.5 v 0.075v (typical conditions: tc = 25c, vdd = 3.3 v, vdd25 = vddq25 = 2.5v, vddq15 = vdd15 = 1.5v ) table 53 dc characteristics symbol parameter min typ max units conditions vdd33 3.3v power supply 3.135 3.3 3.465 volts vdd25 2.5v power supply 2.375 2.5 2.625 volts vddq25 2.5v power supply 2.375 2.5 2.625 volts vddq15 1.5v power supply 1.425 1.5 1.575 volts vdd15 1.5v power supply 1.425 1.5 1.575 volts vil33 input low voltage (3.3v ttl only) -0.3 0.8 volts guaranteed input low voltage vil25 input low voltage (2.5v i/o) -0.3 0.7 vih33 input high voltage (3.3v ttl only) 2.0 vdd33 +0.3 volts guaranteed input high voltage vih25 input high voltage (2.5v i/o) 1.7 vdd25 + 0.3 0.1 0.4 volts vdd33 = min, iol = -2 ma minimum. note 2 vol output or bidirectional low voltage 0.2 0.4 volts vdd33 = min, iol = -8 ma minimum. note 2 vdd33 ? 0.6v 3.0 volts vdd33 = min, ioh = 2 ma minimum. note 2 voh33 output or bidirectional high voltage (3.3v only) vdd33 ? 0.6v volts vdd33=min, ioh = 8ma minimum. note 2. vdd25 ? 0.6v voh25 output or bidirectional high voltage (2.5v only) vdd25 ? 0.6v volts vdd25 = min, ioh = 8ma minimum vt+ reset input high voltage 2.0 volts ttl schmitt
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 420 document id: pmc-1990553, issue 4 symbol parameter min typ max units conditions vt- reset input low voltage 0.8 volts ttl schmitt vth reset input hysteresis voltage 0.4 volts ttl schmitt iilpu input low current +10 +200 a vil = gnd. notes 1, 2 iihpu33 input high current (3.3v i/o) -15 +650 a vih = vdd33. notes 1, 2 iihpu25 input high current (2.5v i/o) -10 +10 a vih = vdd25. notes 1, 2 cin input capacitance 5 pf excluding package, package typically 2 pf cout output capacitance 5pf excluding package, package typically 2 pf cio bidirectional capacitance 5pf excluding package, package typically 2 pf iddop unloaded operating current processing cells ma vdd33 = 3.60 v, vdd15 = 1.575 outputs unloaded, sysclk = 125 mhz interface clocks = 104 mhz bcif clock = 52 mhz iddop loaded total operating current processing cells ma vdd33 = 3.60 v, vdd15 = 1.575 outputs loaded with 50 pf, sysclk = 125 mhz interface clocks = 104 mhz mhz bcif clock = 52 mhz notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 421 document id: pmc-1990553, issue 4 17 a.c. timing characteristics 17.1 conditions tj = 0c to tj=100c, vdd33 = 3.3 v 0.165v, vdd25 = 2.5 0.125v, vddq25 = 2.5 0.125v, vddq15 = 1.5 v 0.075v, vdd15 = 1.5 v 0.075v (typical conditions: tc = 25c, vdd = 3.3 v, vdd25 = vddq25 = 2.5v, vddq15 = vdd15 = 1.5v ) 17.2 reset timing table 54 rtsb ac timing symbol description min max units tv rstb rstb pulse width 100 ns figure 50 rstb ac timing rstb tv rstb 17.3 half-second clock timing table 55 half-second clock ac timing symbol description min max units tv halfsec halfsecclk pulse width 100 ns figure 51 half-second clock ac timing tvhalfsecclk tvhalfsecclk ha lfsecclk 17.4 microprocessor interface read timing table 56 microprocessor interface read access ac timing symbol parameter min max units ts ar address to valid read set-up time 5 ns th ar address to valid read hold time 2.5 ns
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 422 document id: pmc-1990553, issue 4 symbol parameter min max units ts alr address to latch set-up time 5 ns th alr address to latch hold time 5 ns t vl valid latch pulse width 10 ns ts lr latch to read set-up 0 ns th lr latch to read hold 2.5 ns tp rd valid read to valid data propagation delay 30 ns tz rd valid read negated to output tri-state 13 ns tz inth valid read negated to output tri-state 20 ns figure 52 microprocessor interface read access ac timing intb tz int (csb+rdb) valid data d[31:0] tp r tz r ts a r th a r valid address a [11:0] a le ts a l tv l ts lr th a l th lr
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 423 document id: pmc-1990553, issue 4 notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point o\ the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[31:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalr, thalr, tvl, and tslr are not applicable. 5. parameter thar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 17.5 microprocessor interface write timing table 57 microprocessor interface write access ac timing symbol parameter min max units ts aw address to valid write set-up time 5ns ts dw data to valid write set-up time 10 ns ts alw address to latch set-up time 5ns th alw address to latch hold time 5ns t vl valid latch pulse width 10 ns ts lw latch to write set- up 0ns th lw latch to write hold 2.5 ns th dw data to valid write hold time 3.0 ns th aw address to valid write hold time 2.5 ns
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 424 document id: pmc-1990553, issue 4 figure 53 microprocessor interface write ac timing th dw valid data d[31:0] tv wr ts a w th a w ts dw (csb+wrb) a [11:0] valid address a le tv l ts a lw ts lw th a lw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalw, thalw, tvl, and tslw are not applicable. 3. parameter thaw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 17.6 ul3/pl3 interface timing table 58 utopia level 3 / pos-phy level 3 ac timing symbol description min max units f ul3pl3clk ul3/pl3 clock frequency (1) 75 104 mhz pw ul3pl3clk ul3/pl3 clock pulse width (high or low) 4.0 ns ts ul3pl3 ul3/pl3 input setup to clock high 2.0 ns th ul3pl3 ul3/pl3 clock high to input hold 0.5 ns
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 425 document id: pmc-1990553, issue 4 symbol description min max units tp ul3pl3 ul3/pl3 clock to output propagation delay (2) 1.5 6.0 ns notes: 1. throughput is not guaranteed below 104 mhz. 2. 30 pf load. figure 54 utopia level 3 / pos-phy level 3 ac timing max tpul3pl3 min tpul3pl3 thul3pl3 tsul3pl3 ul3/pl3 clock all ul3/pl3 inputs all ul3/pl3 outputs 17.7 bcif interface timing table 59 bcif interface ac timing symbol description min max units f bcifclk bi_clk or bo_clk frequency 52 mhz tpw bcifclk bi_clk or bo_clk high or low pulse width 7.6 ns ts bcif all ibcif inputs valid to bi_clk high setup. all obcif inputs valid to bo_clk high setup 4.0 ns th bcif bi_clk high to ibcif input hold. bo_clk high to obcif input hold 1.0 ns tp bcif bi_clk high to ibcif outputs valid bo_clk high to obcif outputs valid 2.0 12.0 ns figure 55 bcif interface ac timing ma x t p b c i f min tpbcif thbcif tsbcif bcif clock a ll bcif inputs all bcifoutputs
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 426 document id: pmc-1990553, issue 4 17.8 sram interface timing table 60 sram interface ac timing symbol description min max units f xclk xclk frequency (1) 100 125 mhz tpw xclk xclk high or low pulse width 3.2 ns tp sramclk_o xclk to sramclk_o or sysclk_o delay (unconstrained) -- -- ns td sysclk required external delay from sysclk_o to sysclk input 01.0ns tp sram sramclk_o to sdout, spar, sceb, srwb propagation delay 1.0 5.5 ns tz sram sramclk_o to sdout, spar high- impedance 1.0 6.0 ns tv sram sramclk_o to sdout, spar low- impedance 1.0 5.5 ns ts sram sdat, spar setup to sysclk 3.0 ts sram sdat, spar hold to sysclk 1.0 figure 56 sram interface ac timing tpsram tvsram tzsram tpsram thsram tssram tdsysclk tpsramclk_o xclk sysclk_o, sramclk_o sysclk sdat, spar sceb, srwb, saddr notes: 1. min xclk reflects min frequency for correct operation. throughput is not guaranteed for frequencies other than 125 mhz. 17.9 jtag interface timing table 61 jtag port interface timing symbol description min max units tck frequency 1 mhz
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 427 document id: pmc-1990553, issue 4 symbol description min max units tck duty cycle4060% ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns tp tdo tck low to tdo valid 250ns tv trstb trstb pulse width 100 ns
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 428 document id: pmc-1990553, issue 4 figure 57 jtag port interface ac timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. output propagation delays are measured with a 30 pf load on the outputs.
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 429 document id: pmc-1990553, issue 4 18 ordering and thermal information 18.1 ordering information table 62 ordering information part no. description PM7325-tc 768 tbga 18.2 thermal information this product is designed to operate over a wide temperature range and is suited for commercial applications such as central office equipment. maximum long-term operating junction temperature to ensure adequate long-term life 100 0 c maximum junction temperature for short-term excursions with guaranteed continued functional performance. 1 this condition will typically be reached when local ambient reaches 70 deg c. 100 0 c minimum ambient temperature -5 0 c thermal resistance vs air flow 2 airflow natural convection 200 lfm 400 lfm ja ( 0 c/w) 10.7 7.9 6.2 device compact model 3 jt ( 0 c/w) 1.2 jb ( 0 c/w) 4.0 operating power dissipated in package (watts) at worst case power supply, worst case traffic power (watts) 3.0 w notes 1. short-term is understood as the definition stated in bellcore generic requirements gr-63-core. 2. ja , the total junction to ambient thermal resistance as measured according to jedec standard jesd51 (2s2p) 3. jb , the junction-to-board thermal resistance and jt, the residual junction to ambient thermal resistance are obtained by simulating conditions described in jedec standard, jesd 15-8. junction board ambient device compact model jt jb
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 430 document id: pmc-1990553, issue 4 19 mechanical information figure 58 768 tape ball grid array (tbga)
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 431 document id: pmc-1990553, issue 4
downloaded by vinve fu of olivetti on thursday, 19 september, 2002 11:57:41 pm s/uni?-atlas-3200 telecom standard product data sheet preliminary proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 432 document id: pmc-1990553, issue 4 notes

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