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| ics for communications atm oam processor aop pxb 4340 e version 1.1 data sheet 04.2000 ds 1
3;%( 5hylvlrq+lvwru\ &xuuhqw9huvlrq previous version: preliminary data sheet 09.98 (ds 2) page (in previous version) page (in current version) subjects (major changes since last revision) the data sheet has been reorganized. i om ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of infineon technologies ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , digitape ? are trademarks of infineon technologies ag. all other brand or product names, hardware or software names are trademarks or registered trademarks of their respective companies or organizations. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com. (glwlrq this edition was realized using the software system framemaker a . 3xeolvkhge\ ,qilqhrq7hfkqrorjlhv$* 6& %dodqvwud?h 0?qfkhq ? infineon technologies ag 2000. all rights reserved. $wwhqwlrqsohdvh as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for ap- plications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the infineon technologies companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. 3dfnlqj please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &rpsrqhqwvxvhglqolihvxssruwghylfhvruv\vwhpvpxvwehh[suhvvo\dxwkrul]hgiruvxfksxusrvh critical components 1 of infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be ex- pected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or main- tain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. 3;%( 7deohri&rqwhqwv 3djh data sheet 0-3 04.2000 2yhuylhz 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 layer point concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 )xqfwlrqdo'hvfulswlrq 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 cell handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 cell buffering and oam cell insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 addressing of external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.6 oam functions overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7 alarm oam functions (ais/rdi/cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7.1 transmission line failures (ais/rdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7.2 atm layer failures (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8 network connectivity check (lb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.1.1 f4/f5 end-to-end loopback processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.8.1.2 f4/f5 segment loopback processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.1.3 f4/f5 end point loopback processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.1.4 vpci consistency check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.9 connection quality measurement (pm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.9.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.9.2 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.9.3 pm data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.9.4 simultaneous pm flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.9.5 adjacent pm segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.10 activation and deactivation cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.11 interactions between oam functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.12 cell filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.12.1 special oam cell filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.12.2 general purpose cell filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.13 microprocessor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.14 access to internal and external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.15 scan mechanism with oam and/or dma function . . . . . . . . . . . . . . . . . . . . . . 48 2.16 receive and transmit buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5hjlvwhu'hvfulswlrq 3.1 transfer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.1 write transfer registers (wdr0l..wdr13h) . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.2 read transfer registers (rdr0l..rdr13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1.3 mask data registers (mdr0l..mdr6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1.4 write mask register (wmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.1.5 read-modify-write control register (rmwc) . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.1.6 read-modify-write address register (rmwadr) . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 registers for celltype recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 location / source identifier registers (lsidr0..7) . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.2 special oam cell filter (ctr0, ctr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3;%( 7deohri&rqwhqwv 3djh data sheet 0-4 04.2000 3.2.3 cell filter 1 and 2 registers (ctrxy, mrxy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3 transmit / receive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3.1 transmit cell header registers (txr0..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3.2 transmit cell payload registers (txr3..txr26) . . . . . . . . . . . . . . . . . . . . . . 68 3.3.3 transmission command register (tmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.3.4 receive cell buffer read register (rxrcel) . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4 performance monitoring configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.1 upstream maximum lost cells (umlost) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.2 upstream maximum misinserted cells (ummisins) . . . . . . . . . . . . . . . . . . . . 71 3.4.3 upstream maximum lost clp0 cells (umlost0) . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.4 upstream maximum errors (umerr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.4.5 downstream maximum lost cells (dmlost) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.4.6 downstream maximum misinserted cells (dmmisins) . . . . . . . . . . . . . . . . . . . 72 3.4.7 downstream maximum lost clp0 cells (dmlost0) . . . . . . . . . . . . . . . . . . . . 72 3.4.8 downstream maximum errors (dmerr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.5 scan registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5.1 dma write register 15..0 (dwdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.2 dma write register 31..16 (dwdrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5.3 dma mask register 15..0 (dmrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.5.4 dma mask register high 31..16 (dmrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.5.5 phy error indication 15..0 (phyerrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.6 phy error indication 23..16 (phyerrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.7 dma read register (dmar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.8 dma configuration register (dconf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.9 time constant register 0 (scconf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.10 time constant register 1 (scconf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.5.11 time constant register 2 (scconf2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.5.12 scan command register (scconf3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.5.13 lower boundary of lci range (scconf4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.5.14 upper boundary of lci range (scconf5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.5.15 scan status register (scstat0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.5.16 currently processed lci (scstat1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6 interrupt and interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6.1 interrupt status register 0 (isr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.6.2 interrupt status register 1 (isr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.6.3 interrupt mask register 0 (imr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.6.4 interrupt mask register 1 (imr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.6.5 cell insertion fault register low and high (cifl and cifh) . . . . . . . . . . . . . . . 85 3.7 utopia interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.1 utopia configuration register 0 (utconf0) . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.2 utopia configuration register 1 (utconf1) . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.7.3 upstream port enable low and high (uprtenl and uprtenh) . . . . . . . . . . . 89 3.7.4 downstream port enable low and high (dprtenl and dprtenh) . . . . . . . . . 89 3.7.5 oam cell insertion threshold upstream (oamthru) . . . . . . . . . . . . . . . . . . . 90 3.7.6 oam cell insertion threshold downstream (oamthrd) . . . . . . . . . . . . . . . . . 91 3.7.7 backpressure threshold downstream (bpthrd) . . . . . . . . . . . . . . . . . . . . . . . 91 3.8 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.8.1 ram type select register (misc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3;%( 7deohri&rqwhqwv 3djh data sheet 0-5 04.2000 3.8.2 test register 1 (testr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.8.3 test register 2 (testr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8.4 version register low and high (verl and verh) . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.5 bist mode register low (bistml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.8.6 bist mode register high (bistmh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.8.7 bist done register (bistdn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.8.8 bist error register (bisterr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.9 external and internal ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.1 upstream external ram f5 entry: dwords 0..3 . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.1.1 upstream f5 oam entry: dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.1.2 upstream f5 oam entry: dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.1.3 upstream f5 oam entry: dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.1.4 upstream f5 oam entry: dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.9.2 upstream external ram f4 entry: dwords 4..7 . . . . . . . . . . . . . . . . . . . . . . . . 104 3.9.2.1 upstream f4 oam entry: dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.9.2.2 upstream f4 oam entry: dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.9.2.3 upstream f4 oam entry : dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.9.2.4 upstream f4 oam entry: dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.9.3 downstream external ram f5 entry: dwords 0..3 . . . . . . . . . . . . . . . . . . . . 110 3.9.3.1 downstream f5 oam entry: dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.9.3.2 downstream f5 oam entry: dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.9.3.3 downstream f5 oam entry: dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.9.3.4 downstream f5 oam entry: dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.9.4 downstream external ram f4 entry: dwords 4..7 . . . . . . . . . . . . . . . . . . . . 116 3.9.4.1 downstream f4 oam entry: dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.9.4.2 downstream f4 oam entry: dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.9.4.3 downstream f4 oam entry: dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.9.4.4 downstream f4 oam entry: dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.9.5 internal pm main ram entry: dwords 0..2 . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.9.5.1 internal pm main ram entry: dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.9.5.2 internal pm main ram entry: dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.9.5.3 internal pm main ram entry: dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.9.6 internal pm data collection ram entry: dwords 0..13 . . . . . . . . . . . . . . . . . 123 3.9.6.1 internal pm data collection ram entry: dword 0 . . . . . . . . . . . . . . . . . . . . . 123 3.9.6.2 internal pm data collection ram entry: dword 1 . . . . . . . . . . . . . . . . . . . . . 123 3.9.6.3 internal pm data collection ram entry: dword 2 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.4 internal pm data collection ram entry: dword 3 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.5 internal pm data collection ram entry: dword 4 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.6 internal pm data collection ram entry: dword 5 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.7 internal pm data collection ram entry: dword 6 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.8 internal pm data collection ram entry: dword 7 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.9 internal pm data collection ram entry: dword 8 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.10 internal pm data collection ram entry: dword 9 . . . . . . . . . . . . . . . . . . . . . 124 3.9.6.11 internal pm data collection ram entry: dword 10 . . . . . . . . . . . . . . . . . . . . 124 3.9.6.12 internal pm data collection ram entry: dword 11 . . . . . . . . . . . . . . . . . . . . 125 3.9.6.13 internal pm data collection ram entry: dword 12 . . . . . . . . . . . . . . . . . . . . 125 3.9.6.14 internal pm data collection ram entry: dword 13 . . . . . . . . . . . . . . . . . . . . 125 3;%( 7deohri&rqwhqwv 3djh data sheet 0-6 04.2000 2shudwlrq 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.1.1 guidelines for microprocessor actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.1.1.1 write-modify-read-access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.1.1.2 cell insertion by the microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.1.1.3 reading of arrived cells by the microprocessor . . . . . . . . . . . . . . . . . . . . . . . . 127 4.1.1.4 scan usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.1.2 initialization and test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.4 setup/ cleardown of connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.5 enable/ disable of pm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.6 normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.6.1 scan process trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.6.2 pm threshold check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.7 events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.7.1 transmission line failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.7.2 lb cell transmission/ reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.7.3 pm activation/ deactivation cell transmission . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.7.4 pm activation/ deactivation cell reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.2 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.2.1 pm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ,qwhuidfhv 5.1 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.1.1 utopia multi-phy support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.2 ram interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.4 jtag/boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.5 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.6 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 (ohfwulfdo&kdudfwhulvwlfv 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.4.1 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.4.1.1 microprocessor write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.4.1.2 microprocessor read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.4.1.3 dma request timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.4.2 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.4.3 ssram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.4.4 cell filter detector timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.4.5 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.4.6 boundary-scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 3dfndjh2xwolqhv 3;%( 7deohri&rqwhqwv 3djh data sheet 0-7 04.2000 2yhuylhz/lvwv 8.1 layer point configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8.2 oam cell formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.2.1 oam cell header coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8.2.2 ais cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 8.2.3 rdi cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 8.2.4 cc cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 8.2.5 lb cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.2.6 fm cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.2.7 br cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.2.8 pm/cc activation/deactivation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.3 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 8.4 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 3;%( /lvwri)ljxuhv 3djh data sheet 0-8 04.2000 figure 1: chipset configuration for main atm layer functionality . . . . . . . . . . . . . . . . . . . 11 figure 2: chipset configuration for main atm layer functionality plus full oam . . . . . . . . 12 figure 3: chipset configuration for main atm layer functionality plus full oam and arbitrary header translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4: miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5: line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6: logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7: location of pxb 4340 e aop on a switch port . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8: symbol for switch with aops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9: vp level oam functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10: vc level oam functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11: vc endpoint inside the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12: cell buffers in pxb 4340 aop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13: thresholds in utopia cell buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14: pointer structure of up- and downstream oam tables . . . . . . . . . . . . . . . . . . . 26 figure 15: example for line failure notification via ais cells . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16: vp-ais/rdi-flow (f4-ais/rdi-flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17: ais state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18: rdi state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19: example for misrouting failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20: f4 segment cc flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21: continuity check cell generation state diagram . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22: continuity check evaluation state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23: example of f4 end-to-end loopback processing . . . . . . . . . . . . . . . . . . . . . . . 36 figure 24: example of f5 segment loopback processing . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 25: example of f4 end point loopback processing . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26: pm configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 27: pm data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28: example for adjacent pm segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29: effect of cc cells on ais recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 30: access to internal or external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 31: scan mechanism with oam and/or dma function . . . . . . . . . . . . . . . . . . . . . . 49 figure 32: read-modify-write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 33: performance monitoring example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 34: utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 35: standardized utopia cell format (16-bit) all fields according to standards, unused octets shaded . . . . . . . . . . . . . . . . . 136 figure 36: proprietary utopia cell format (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 37: upstream receive utopia example for 4 x 6 phys . . . . . . . . . . . . . . . . . . . . 137 figure 38: upstream or downstream ram interface using 2 mbits rams . . . . . . . . . . . . 139 figure 39: upstream or downstream ram interface using 1 mbit rams . . . . . . . . . . . . . 140 figure 40: example of execution timing for read cycles (burst mode) . . . . . . . . . . . . . . 141 figure 41: microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 42: jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 43: input/output waveform for ac measurements . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 44: microprocessor interface write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 45: microprocessor interface read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 46: microprocessor dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3;%( /lvwri)ljxuhv 3djh data sheet 0-9 04.2000 figure 47: setup and hold time definition (single- and multi-phy) . . . . . . . . . . . . . . . . . 158 figure 48: tristate timing (multi-phy, multiple devices only) . . . . . . . . . . . . . . . . . . . . . 159 figure 49: interface naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 50: ssram interface generic timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 51: cell filter detector timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 52: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 53: boundary-scan test interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 170 3;%( /lvwri7deohv 3djh data sheet 0-10 04.2000 table 1: oam functionality determined by layer point configuration . . . . . . . . . . . . . . 19 table 2: aop register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 3: internal and external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 4: cell filter detector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 5: scan periods for a core clock of 51.84 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 6: bit mapping for "compressed" dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 7: utopia polling modes. the numbers indicate the offset which is added to the phy number. . . . . . . . 138 table 8: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 9: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 10: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 11: clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 12: microprocessor interface write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 13: microprocessor interface read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 14: microprocessor dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 15: transmit timing upstream (16-bit data bus, 50 mhz at cell interface, single phy) . . . . . . . . . . . . . . . . . 161 table 16: receive timing upstream (16-bit data bus, 50 mhz at cell interface, single phy) . . . . . . . . . . . . . . . . . 161 table 17: transmit timing downstream (16-bit data bus, 50 mhz at cell interface, singel phy) . . . . . . . . . . . . . . . . . 162 table 18: receive timing downstream (16-bit data bus, 50 mhz at cell interface, single phy) . . . . . . . . . . . . . . . . . 162 table 19: transmit timing upstream (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . 163 table 20: receive timing upstream (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . 164 table 21: transmit timing downstream (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . 165 table 22: receive timing downstream (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . 166 table 23: ssram interface ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 24: cell filter detecor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 25: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 26: boundary-scan test interface ac timing characteristics . . . . . . . . . . . . . . . . 170 table 27: capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 28: thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 29: thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 30: layer point configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 3;%( data sheet 1-11 04.2000 2yhuylhz 2yhuylhz the pxb 4340 e atm oam processor is a member of the infineon atm622 chip set. the whole chip set consists of: ? pxb 4330 e atm buffer manager abm ? pxb 4340 e atm oam processor aop ? pxb 4350 e atm layer processor alp ? pxb 4360 f content addressable memory element came main atm layer functionality is achieved with only two chips, alp and abm. the combination of these two devices provides elementary atm functionality like header translation, policing, oam support, multicast and traffic management (fig.1). the functionality is upgradeable to full oam support by the aop (fig.2) and to arbitrary header translation by came (fig.3). )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\ utopia pol. ram pointer ram cell ram phys conn. ram conn. ram cell ram utopia utopia switch (loop) pxb 4350 e alp pxb 4330 e abm 3;%( data sheet 1-12 04.2000 2yhuylhz )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\soxvixoo2$0 )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\soxvixoo2$0dqgdu elwudu\khdghuwudqvodwlrq utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram came conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop 3;%( data sheet 1-13 04.2000 2yhuylhz the atm 622 layer devices can be used as .... ...a full switch in: adsl concentrators / multiplexers (dslam) access multiplexers access concentrators multiservice switches ...line card in: workgroup switches edge switches core switches )ljxuh 0lqlvzlwfkfrqiljxudwlrq $/3 $23 utopia utopia $%0 utopia 3;%( data sheet 1-14 04.2000 2yhuylhz )ljxuh /lqhfdugfrqiljxudwlrq due to their most flexible scaling facilities, feature set and throughput the infineon atm622 layer chips are the ideal devices for almost any atm system. $/3 $23 utopia utopia $%0 utopia 6zlwfk data sheet 1-15 04.2000 $702$03urfhvvru $23 3;%( 9huvlrq &026 7\sh 3dfndjh pxb 4340 e p-bga-352-2 xqghufrqvwuxfwlrq p-bga-352 )hdwxuhv 3huirupdqfh ? performance up to stm-4/oc-12 equivalent atm layer processing ? flexibel throughput from1 .. 687 mbit/s bi-directional ? up to 16384 connections in both directions (vpc/ vcc) ? temperature range from 0c to 70c ? multiport utopia level 2 interface in up- and downstream direction according to atm forum, utopia level 1 and 2 specifications [ ] ? 16-bit microprocessor interface, e.g. 386ex ? cell insert/extract function ? 32 cell fifo buffer at utopia upstream receive interface ? 96 cell shared buffer for up to 24 phys at utopia downstream transmit interface ? boundary scan support according to jtag [ ] ? internal data stream loop at atm and at phy side ([whuqdo5$0v ? two external ssrams for connection related data, one for upstream and one for downstream direction, 2 x 4 mbit for 16k connections ? dma for fast data transfer between external ram and microprocessor ? all entries parity protected 2$0)xqfwlrqv ? oam levels and flows (f4/f5) according to itu-t/i.610 [ ] and bellcore gr-1248 [ ] ? all oam cell types hard-wired ? generation, discard, extraction and insertion of oam cells ? programmable oam cell types for future standardization $,65',&&)xqfwlrqv ? ais/rdi/cc function for all connections permanently active ? automatic generation of vp/vc-ais cells at line failures p-bga-352 3;%( data sheet 1-16 04.2000 2yhuylhz ? automatic generation of vc-ais cells for all vccs of a vpc at the endpoint including automatic backward emission of vp-rdi cells ? automatic generation of vp/vc-cc cells to detect atm layer failures ? optional internal cc function for switch test (proprietary) ? programmable guard times and cell insertion intervals ? support of cc activation/deactivation cells /rrsedfn ? automatic loop of cells for all connections with lb id inversion ? programmable port id for on the fly comparison with location id or source id of lb cells ? insertion/extraction of lb cells via microprocessor 3huirupdqfh0rqlwrulqj ? 128 simultaneous pm generation/ evaluation processors shared for up- and downstream direction ? full hw evaluation of fm cells and generation of br cells ? full hw support of data collection according to bellcore gr-1248 for 128 connections ? support of pm activation/deactivation cells ? support of simultaneous pm flows of f4 and f5 level ? support of adjacent pm segments in one pxb 4340 aop ? 128 pm data collection processors shared for up- and downstream direction ? collection of the following data: C severely errored cell blocks C errored cells C lost high priority cells (clp0) C total lost cells (clp0+1) C transmitted high priority cells (clp0) C total transmitted cells (clp0+1) C misinserted cells C impaired blocks 0lfursurfhvvru&rqwuro ? intel 386ex microprocessor interface ? low external processing power required 7hfkqrorj\ ? 0.35 cmos, 3.3v ? plastic bga-352 package ? extended temperature range from -40c to +85c ? power dissipation 2.2 w 2$0)xqfwlrqvzklfkduhqrwvxssruwhg ? combined monitoring and reporting oam cells for performance monitoring ? time stamp in forward monitoring oam cells ? defect type and defect location fields in ais/rdi cells ? segment ais/rdi ? simultaneous generation of end-to-end and segment fm cells 3;%( data sheet 1-17 04.2000 2yhuylhz /rjlf6\pero )ljxuh /rjlf6\pero 3;%( $23 0lfursurfhvvru ,qwhuidfhelw 7hvw-7$* ,qwhuidfh 8723,$ 5hfhlyh ,qwhuidfh &orfndqg 5hvhw ,qwhuidfh 8723,$ 7udqvplw ,qwhuidfh 8svwuhdp &rqqhfwlrq 5$0,qwhuidfh 8723,$ 5hfhlyh ,qwhuidfh 8723,$ 7udqvplw ,qwhuidfh vodyh 'rzqvwuhdp &rqqhfwlrq 5$0,qwhuidfh pdvwhu 00665$0 00665$0 3;%( data sheet 1-18 04.2000 2yhuylhz 6\vwhp,qwhjudwlrq the pxb 4340 aop is located at the ports of a switch so that each atm cell passes two pxb 4340 aop devices, one at the ingress port and one at the egress port. the pxb 4340 aop assumes that all connections are set-up bi-directional with the same local connection identifier lci in both directions. in the infineon technologies atm chip set environment ( vhh iljxuhv dqg iljxuh ) the lci is provided by the pxb 4350 alp and contains vpi, vci and phy information. the pxb 4340 aop uses pointers to define a connection as vpc or vcc ( vhhiljxuh ); the phy number is not evaluated. if the pxb 4340 aop is not used together with the pxb 4350 alp it can operate on vpi or vci identifiers only. in these cases the oam functionality is reduced accordingly. )ljxuh /rfdwlrqri3;% ($23rqd6zlwfk3ruw utopia utopia pol. ram phys conn. ram arc conn. ram conn. ram conn. ram conn. ram = connection data ram pol. ram = policing data ram arc = address reduction circuit upstream: address reduction policing downstream: header translation e.g. pxb 4350 e alp (optional) (optional) (optional) (mandatory) (mandatory) (mandatory) aop pxb 4340 e utopia atm switch core 3;%( data sheet 1-19 04.2000 2yhuylhz /d\hu3rlqw&rqfhsw this concept is introduced to enable the automatic execution of oam functions by the aop. for each connection, vpc or vcc the layer point is configured at connection setup. then the oam functions required for this layer point are executed automatically by the aop. there are 3 different layer points: ? end point ep ? segment end point sp ? intermediate point ip end points and segment end points can be originating or terminating and can belong to a vpc or a vcc; they are referenced as e.g. vpc originating end point vp-oep or vcc terminating segment point vc-tsp. as an example a (terminating) segment end point would ignore arriving ais cells, as ais cells have always the end-to-end identification. the same layer point would loop arriving forward segment lb cells. 7deoh gives a coarse overview over the oam functions executed by the aop at each layer point. monitoring functions can be enabled optionally. the details are described with the upstream and downstream external ram entries. 7deoh 2$0)xqfwlrqdolw\'hwhuplqhge\/d\hu3rlqw&rqiljxudwlrq $,6&hoo ,qvhuwlrq )ruzdug qrq lqfoxvlyh 0rqlwrulqj 5',&hoo ,qvhuwlrq %dfnzdug qrq lqfoxvlyh 0rqlwrulq j 30 *hqhudwh /rrs (ydoxdwh 'h $fwlydwlrq /%&hoo ,qvhuw /rrsedfn &&&hoo *hqhudwh 7huplqdwh 'h $fwlydwh )xwxuh 2$0 )xqfwlrqv 1) via 2 programmable oam cell filters with discard/drop/monitor/ignore options ,3 yes no monitor only evaluate only intra-domain lb only no yes 63 yes no monitor only yes segment cells only yes segment cells only yes segment cells only yes (3 yes (f4 to f5 error propagation) yes yes yes yes yes 3;%( data sheet 1-20 04.2000 2yhuylhz in the following scenarios examples for four layer point configurations are shown. in these figures a switch with its incoming and outgoing port is represented by the symbol shown in iljxuh . )ljxuh 6\peroiru6zlwfkzlwk$23v the pxb 4340 aop can be configured according to its location in the network as shown in the following examples. within a pure atm network vpcs may be originated or terminated. in addition vp segments can be originated or terminated as shown in iljxuh . )ljxuh 93/hyho2$0)xqfwlrqv as vpcs are always terminated at an ingress port and originated at an egress port, the functionality of the pxb 4340 aop is restricted accordingly. for example it is not possible to terminate vp-ais cells at the egress port of a switch. 7deoh shows an overview over all possible layer points. vccs are not originated or terminated within a pure atm network, but only vc segments ( iljxuh ). v\perori6zlwfklqj )deulf v\perorirxwjrlqj sruwzlwk$23 v\perorilqfrplqj sruwzlwk$23 wudqvplvvlrqolqhv 3+ 3;%( data sheet 2-22 04.2000 )xqfwlrqdo'hvfulswlrq )xqfwlrqdo'hvfulswlrq 2yhuylhz the pxb 4340 aop provides full standardized oam functionality of the atm layer in one device, covering the functions fault management (ais, rdi, cc, lb) and performance monitoring (fm flow, br flow, data collection). it has stm-4/oc-12 equivalent throughput in upstream and downstream direction. the ais, rdi, cc mechanism can be applied to a range of up to 16k (=16384) connections. performance monitoring can be done for 128 connections simultaneously with each connection selectable from up- or downstream direction. loopback functionality can be applied to the full range of up to 16k connections (see vhfwlrq page 27 and vhfwlrq page 34). data cells are transferred via industry standard level 2, single-port/ multi-port utopia interfaces based on cell level handshake. they can be adjusted for 8-bit or 16-bit data transfer. the atm side utopia interface is operating in slave mode, the phy side utopia interface in master mode. the phy number of a cell is transported transparently through the chip, i.e. a cell input at an utopia receive interface with the phy number p is output at the corresponding utopia transmit interface with the same phy number p. note that the phy number is not the utopia address, but contains address and handshake line pair information (see vhfwlrq ) two 32 bit external ssram blocks are provided for oam data storage for each connection. their size is depending on the number of supported connections (see vhfwlrq page 139). chip control is performed by a standard 16-bit asynchronous microprocessor interface (e.g. for 80386ex). the microprocessor can access the external rams any time during operation. this is necessary for connection set up/release, data read/modify/write and configuration adjustment. the external ram is not memory mapped into the microprocessor address range. accesses occur via a transfer register set using transfer commands or via dma (see vhfwlrq page 141). all functions are supported to a great extent in hw, so that sw effort is minimized. 7kurxjksxw data throughput is depending on the chip operating clock sysclk, which is used for the chip core and the external ssrams. the pxb 4340 aop needs 32 cycles of the sysclk to process one atm cell. thus in 32 cycles 64 octets are transported through the chip for a 53 octet atm cell, giving a penalty of 53/64. hence the atm cell throughput is: atm cell throughput[mbit/s] = sysclk[mhz] x 16 x 53/64 = sysclk[mhz] x 13.25 for a frequency of 51.84 mhz the throughput is 686.88 mbit/s. the 51.84 mhz are easy to generate, as this is 1/3 of 155.52 mhz, the generic sdh/sonet frequency. the clock of the utopia interfaces is independent of sysclk. it should be less or equal to the sysclk frequency. this is not a restriction, as the transfer time for a cell in the utopia interface is only 27 clock cycles. 3;%( data sheet 2-23 04.2000 )xqfwlrqdo'hvfulswlrq &hoo+dqgolqj each cell entering the pxb 4340 aop via the upstream/downstream receive utopia interface is identified either as user cell or as oam cell. the chip recognizes all standardized oam cells and has two programmable comparators for possible new oam cell types. data stored on a connection basis in the external rams determines if a connection is enabled and which layer point is configured (see wdeoh for all possible configurations). accordingly the respective function is performed. ? for example a vp-ais cell would be ignored at a vp segment endpoint. ? as an other example a user cell belonging to a vpc for which end-to-end performance monitoring is enabled is counted and its checksum (bip-16) is added to the checksum in the aop located at the vp endpoint. in the respective oam processing block new status information is calculated, for example alarm indication bits, bip-16 checksums, cell counts etc. whereas user cells are never modified and are always forwarded, oam cells can be ? generated and inserted into the cell stream in up- or downstream direction ? extracted from the cell stream and discarded or dropped to the receive cell buffer of the p ? forwarded with or without modification ? looped back with modification. for oam cell generation the pxb 4340 aop uses the configuration bits of the respective connection to determine the oam cell type. therefore it distinguishes between f4 and f5 flow and between segment and end-to-end flow. when detecting oam cells the pxb 4340 aop recognizes f4 or f5 oam cells for end-to-end or segment. according to the configuration the required actions are performed. &hoo%xiihulqjdqg2$0&hoo,qvhuwlrq the pxb 4340 aop has four cell buffers located close to the two utopia interfaces in each direction ( iljxuh ): ? utopia upstream receive interface: 32 cells, single queue ? utopia upstream transmit interface: 4 cells, single queue ? utopia downstream receive interface: 4 cells, single queue ? utopia downstream transmit interface: 96 cells, shared buffer with 24 queues. the 4-cell buffers satisfy the needs of the utopia slave handshake at the upstream transmit and downstream receive interface. the 32 cells wide upstream receive buffer stores incoming user cells during the insertion of oam cells. oam cells can be generated or looped from the opposite direction. the pxb 4340 aop uses forced insertion for all oam cells. forced insertion is disabled beyond a buffer filling level which is programmable for upstream direction via register oamthru (see vhfwlrq page 90 and iljxuh , part a). the oam cells to be inserted are lost in this case. also see wdeoh for illustration of the cell handling at the utpoia upstream receive interface. when the receive buffer filling level is lower then the threshold the oam and user cells are processed with the shown priority. 3;%( data sheet 2-24 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh &hoo%xiihuvlq3;% $23 the downstream transmit buffer also does forced oam cell insertion by back-pressuring user cells to the downstream receive interface and possibly to the previous chip. it is realized as shared buffer of up to 24 queues, associated to the respective phys. the back-pressured user cells are released in bursts of up to 687 mbit/s when no other cells with higher priority according to wdeoh are present. these bursts must be stored by the downstream transmit buffer and released to the phys according to their respective speed. 7deoh 8723,$sulrulw\olvw xsvwuhdp grzqvwuhdp uhfhlyh),)2ilooohyho wkuhvkrog uhfhlyh),)2iloo ohyho 3 wkuhvkrog xwrsldwudqvplw),)2qrw ixoo xwrsldwudqvplw ),)2ixoo 1 br cell from downstream 1 utopia 1 fm cell insertion backpressure to adjacent device 2 lb cell from downstream 2 br cell from upstream 3 fm cell from downstream 3 lb cell from upstream 4 scan poll 4 scan poll 5 scan oam insertion 5 scan oam insertion 6 p cell insertion 6 p cell insertion 7 p ram access (rmw) 7 p ram access (rmw) 8 utopia 8 utopia 1) 1 = highest priority, 8 = lowest priority xsvwuhdpgluhfwlrqwrvzlwfklqjqhwzrun grzqvwuhdpgluhfwlrqwr3+< ?3,qwhuidfh 8wrsld0dvwhu,qwhuidfh 2$0 3urfhvvruv 8wrsld6odyh,qwhuidfh fhooexiihuiru 8723,$kdqgvkdnh fhooexiihuiru 8723,$kdqgvkdnh fhoovkduhgexiihu irufhooghpxowlsoh[lqj fhooexiihu iruedfnsuhvvxuh irufhglqvhuwlrq ri2$0fhoov xvhufhoov 2$0fhoov xvhufhoov 3;%( data sheet 2-25 04.2000 )xqfwlrqdo'hvfulswlrq the downstream transmit buffer has 2 thresholds for each queue: ? the utopia backpressure threshold: beyond this threshold the backpressure signal is given to the downstream receive interface for this phy (see vhfwlrq page 91) ? the oam cell insertion threshold: beyond this threshold the insertion of oam cells is disabled (see vhfwlrq page 91). as with the upstream receive buffer in this state oam cells to be inserted are lost. the two thresholds are identical for all queues. the utopia backpressure threshold should be programmed to a value lower than the oam cell insertion threshold, this difference guarantees a cell storage space for oam cells (see iljxuh , part b). )ljxuh 7kuhvkrogvlq8723,$fhooexiihuv the atm cell load should be selected by the user in a way that the probability to loosing oam cells is almost zero (e.g. 10 -11 ). this is done by reserving bandwidth for the inserted oam cells. oam cell bandwidth is mainly depending on the selected pm block size (128, 256, 512, 1024). in worst case, when f4 and f5 level pm cell streams are generated, the overhead is still less than 2%. lost oam cells do not lead to system malfunction. if e.g. an fm cell is lost the pm processor continues to count user cells and bip-16 checksums. the correct values will be sent out with the next block. thus block size would be e.g. 256 instead of 128 in case of a lost cell. the insertion of ais/rdi/cc cells will only be halted temporarily during the (very unlikely) case of a buffer overflow. an lb cell to be looped, however, will be lost. here only the repeat function would help. &hoolqvhuwlrqwkuhvkrog xsvwuhdp 2$07+58 txhxhlvhpsw\ cell buffer user cells if a queue exceeds this threshold : no more oam cells are inserted. they are lost. fhoolqvhuwlrqwkuhvkrog grzqvwuhdp 2$07+5' edfnsuhvvxuhwkuhvkrog grzqvwuhdp %37+5' txhxhlvhpsw\ cell buffer oam cells user cells if a queue exceeds this threshold : no more user cells are accepted if a queue exceeds this threshold : no more oam cells are inserted d xsvwuhdpuhfhlyh),)2 e grzqvwuhdpwudqvplw),)2 3;%( data sheet 2-26 04.2000 )xqfwlrqdo'hvfulswlrq $gguhvvlqjrih[whuqdo5$0v the external rams for the storage of connection related oam data are symmetrical in up- and downstream direction. also the addressing is symmetrical as the lci values for forward and backward connection are identical. note that according to the standards each atm connection is set-up bi-directional, but not necessarily with the same bit rate in both directions. both external rams are divided into an f4 and an f5 oam table. each connection entry has 4 dwords. with the lci of the cell first the vc-specific table is addressed. therein an f4 pointer is contained pointing to a vp-specific entry. there are two cases, both depicted in the circle of iljxuh . . )ljxuh 3rlqwhu6wuxfwxuhrixsdqggrzqvwuhdp2$07deohv 1. a vpc intermediate point in this case the f5 entry is "dont care", except some common fields. see e.g. vpc i in iljxuh . the vp-specific entry contains the oam data for the vpc. 2. a terminated vpc decomposed into vccs in this case each vcc has an f5 entry with identical f4 pointers pointing all to the same f4 entry. see e.g. vcc a and vcc b of vpc t in iljxuh . 16383 16382 16381 : : 2 1 0 16383 16382 16381 : : 2 1 0 : : : : : : : : connections: f4 pointer: lci2(vpct) lci (vcca) lci (vccb) lci (vpci) f4 oam table f5 oam table f5 entry f5 entry don't care f4 entry f4 entry f4 pointer: lci2=lci vpct vpci vcca vccb 3;%( data sheet 2-27 04.2000 )xqfwlrqdo'hvfulswlrq 2$0)xqfwlrqv2yhuylhz there are two groups of applications for oam functions: alarms and measurements. alarm functions inform users and network operators about network failures. these include the oam functions ? alarm indication signal (ais) ? remote defect indication (rdi) ? continuity check (cc). ais and rdi are used to convey transmission line failure information to subscriber and network operator; cc detects atm layer failures. as failure events are unpredictable the alarm supervising hw is always running. when a failure occurs the notification process starts automatically. measurements are initiated for diagnosis purposes by the network operator. therefore these functions do not need to be active permanently for all connections. the respective oam functions are: ? loopback lb ? performance monitoring pm lb checks the connectivity of a connection by sending a single cell which is looped back at predefined points. lb is used e.g. immediately after connection set-up or periodically to check all permanent connections of a network using end-to-end or segment lb. a network operator could also use intra-domain lb to localize a failed link. another option for loopback are subscriber initiated loops either end-to-end to the partner or access line lb to the first node in the network. pm is a more precise tool than lb. it checks not only the connectivity, but the real performance of a connection in terms of bit failures and cell losses. as it requires complex hw support and sw performance pm will not be activated permanently for all connections. e.g. vpcs or permanent vccs could be monitored if a subscriber pays for this service. also a network operator would use pm to check the quality of a connection if a subscriber complains about it. $odup2$0)xqfwlrqv $,65',&& there are two types of failures detected by the alarm functions: transmission line failures and atm layer failures. transmission line failures are e.g. line brakes, failures of lasers or failures of reception diodes. typical atm layer failures are the misrouting of cells in the switching fabric or a falsified entry in a routing table. in this case all cells of a connection are forwarded to a wrong destination. 7udqvplvvlrq/lqh)dloxuhv $,65', transmission line failures are recognized by the receiving phy and conveyed to the pxb 4340 aop by the on-board control processor. it is sufficient to set one single bit for the respective phy to initiate the periodic insertion of ais cells for all affected connections. in the external ram entry a bit carien exists for f5-ais and a bit parien for f4-ais ( for carien see vhfwlrq page 100, for upstream and vhfwlrq page 112, for downstream; for parien see vhfwlrq page 107, for upstream and vhfwlrq page 118, for downstream). when these bits are set to 1, the insertion of ais cells is enabled. note, that no f4 oam/user-flow is supported if the lci-mode "10" in register utconf1 is selected (see vhfwlrq page 88). further the bit disf4 and disf5 in the external ram entries have to be set to 0 to enable the 3;%( data sheet 2-28 04.2000 )xqfwlrqdo'hvfulswlrq f4/f5 processing (see vhfwlrq page 98, vhfwlrq page 110, for disf5 in up- and downstream direction; vhfwlrq page 105, vhfwlrq page 116, for disf4 in up- and downstream direction). otherwise all f4/f5 cells are discarded at the receiving point. the pxb 4340 aop automatically inserts vp-ais cells for vpcs and vc-ais cells for vccs. )ljxuh shows that this case occurs at the incoming port of a switch. )ljxuh ([dpsohiru/lqh)dloxuh1rwlilfdwlrqyld$,6fhoov the generated vc-ais cells travel up to the endpoint of the connection, which normally is the user terminal. thus within a very short time delay - determined by the control processors response time, the pxb 4340 aop insertion delay and the cell transfer time - the user is informed about the failure. the generated vp-ais cells travel up to the vp terminating endpoint which normally is within the network. at the vp terminating endpoint - which is always at the incoming port of a switch - vc- ais cells must be generated for all vccs contained in the vpc. again, all affected user terminals are informed. the pxb 4340 aop automatically performs the following actions when receiving vp-ais cells at a vp terminating endpoint (see iljxuh ): aop 6zlwfk )deulf 3ruwd 3ruwe ?3 olqhidlo lqglfdwlrq $,6fhoov 3ruwf $,6fhoov vhw3+< huuru /lqh&dug 3;%( data sheet 2-29 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 93$,65',)orz )$,65',)orz ? discard of vp-ais cells (see iljxuh , marker ? ) ? execution of the (vp-)ais state diagram shown in iljxuh for the respective vpc. ? insertion of vp-rdi cells in backward direction. this informs the originating endpoint of the vpc about the failure. rdi makes sense in cases where the failure of the line affects only one direction. the automatic rdi generation in backward direction assumes bi-directional connections with the same identifier (lci) in both directions (see iljxuh , marker ). ? insertion of vc-ais cells in forward direction for each vcc of this vpc. this informs all users sharing this vpc about the failure in the network (see iljxuh , marker ). ? declaration of ais/rdi idloxuh states after 3.5 seconds (standard) persistence of ais defect state. the cell insertions continue unaffected. at the originating endpoint of the vpc the following actions are perfomed: ? discard of vp-rdi cells (see iljxuh , marker ? ) ? execution of the rdi state diagram shown in iljxuh . ? declaration of rdi failure state after 3.5 seconds (standard) duration of rdi defect state. the ais state diagram executed at the sink endpoint of a connection is shown in iljxuh . note that in accordance for the anomaly-defect-failure mechanism only transitions to and from failure state are notified to the microprocessor. this avoids unnecessary interrupts. aope aope aope aope configured as an f4 originating end point configured as an f4 intermediate point configured as an f4 terminating end point configured as an f5 terminating end point end of the oam flow configured as an f4 terminating end point configured as an f4 intermediate point configured as an f4 originating end point configured as an f5 originating end point begin of the oam flow for all vccs in one vpc: f5 ais cells are sent line broken f4 ais cell f5 ais cell f5 ais cell f5 rdi cell f5 rdi cell f4 rdi cell discard f4 ais cell f5 f5 4 3 2 1 discard f4 rdi cell 3;%( data sheet 2-30 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh $,66wdwh'ldjudp )ljxuh 5',6wdwh'ldjudp normal operation ais-defect one valid user cell or one cc cell if terminating cc is disabled and no ais cell is received for a certain time (programmable <= 3,5 sec, default 2,5 sec) first ais cell detected ais-failure receiving of ais cell for a certain time (programmable <= 7,5 sec, default 3.5 sec) transmit periodically (1 cell/s) ais cells respectively rdi cells. first ais cell within 0.5 s. transmit periodically (1 cell/s) ais cells respectively rdi cells. setup of a new connection notification to up notification to up one valid user cell or one cc cell or if terminating cc is disabled: no ais cell is received for a certain time (programmable <= 3,5 sec, default 2,5 sec) normal operation rdi-defect rdi-failure notification to up notification to up setup of new connection no rdi cell received for a certain time (programmable <= 3,5 sec, default 2,5 sec) no rdi cell received for a certain time (programmable <= 3,5 sec, default 2,5 sec) first rdi cell detected receiving rdi cells for a certain time (programmable <= 7,5 sec, default 3,5 sec) 3;%( data sheet 2-31 04.2000 )xqfwlrqdo'hvfulswlrq the actual f5-ais/rdi state is indicated by bits 14..19 in dword2 of the downstream external ram entry ( vhfwlrq page 114) and the upstream external ram entry ( vhfwlrq page 102). for the actual f4-ais/rdi state information use bits 22..27 in dword4 of the downstream external ram entry ( vhfwlrq page 116) and the upstream external ram entry ( vhfwlrq page 105 ). the p is informed by the interrupts dcsttr for downstream f5, ucsttr for upstream f5, dpsttr for downstream f4 and upsttr for upstream f4 state transitions ( vhfwlrq page 83). both forward and backward cell insertions are initiated by the scan mechanism (see vhfwlrq ). all delay times given are default values, recommended by [ ]. the pxb 4340 aop allows to program these values in multiples of the 0.5 second scan period given by the microprocessor. therefore consider the register description of scconf1 (see vhfwlrq page 79). the 0.5 second scan period determines the insertion delay for oam cells. if the scan mechanism has passed a connection entry just before an ais condition became true the maximum waiting time for the next scan access is about 0.5 second. $70/d\hu)dloxuhv && the mechanism to detect failures like misrouting is the continuity check (cc). its idea is to insert dummy cells in a connection if it is inactive, i.e. if the user is not sending data cells. the dummy cells are called cc oam cells and are inserted at the originating end/segment point of a connection after a one second absence of user cells. the repetition interval is also one second. at the connection/segment endpoint the cc cells are discarded. if no user or oam cells are received within 3.5 seconds the loss of continuity (loc) defect state is declared. like ais state loc causes the automatic insertion of vp-ais or vc-ais cells for the affected connections. if loc is detected at a terminating endpoint rdi cells are generated in backward direction. )ljxuh shows an example for the operation of cc: two vccs entering a switch at ports a and b should both be forwarded to port c. due to misrouting within the switching fabric the cells of vcc b are forwarded to an unconnected switch output, where they are lost without being notified. the cc detection function at port c, however, detects the absence of user cells after the 3.5 seconds time-out and inserts vc-ais cells for connection b. the time values given are values recommended in [6]. the pxb 4340 aop allows to progam them in a wide range. the pxb 4340 aop supports the cc function for all 16384 connections in both up- and downstream direction. setting one bit in the respective connection ram is sufficient to activate the origination or the termination of a cc flow. this is bit 11 in dword1 (up-/downstream) for originating f5 segment cc, bit 10 in dword1 (up-/downstream) for originating f5 end-to-end cc and bit 11 in dword4 (up-/downstream) for originating f4 segment cc (see vhfwlrq page 98). all other actions are automatic: at the cc origination point (see iljxuh and iljxuh ): ? continuous supervision of user cell stream (see iljxuh , marker ? ) ? periodic insertion of cc cells in one second intervals after one second (standard) time-out (see iljxuh , marker ? ) 3;%( data sheet 2-32 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh ([dpsohiru0lvurxwlqj)dloxuh'hwhfwlrq )ljxuh )vhjphqw&&)orz aop vcca vcca ? vccb port b port a switch fabric misrouting port c vc-ais(b) timeout 3.5 s user cells & vc-cc cells of vccb aope aope aope aope configured as an f4 intermediate point and originating segment point configured as an f4 intermediate point and terminating segment point configured as an f4 terminating end point configured as an f5 terminating end point end of the oam flow configured as an f4 intermediate point and terminating segment point configured as an f4 intermediate point and originating segment point configured as an f4 originating end point configured as an f5 originating end point begin of the oam flow for all vccs in one vpc: f5 ais cells are sent connection broken f4 ais cell f5 ais cell f5 ais cell f5 rdi cell f5 rdi cell f4 rdi cell f4 segment cc f4 segment cc timeout (no user or cc cells) f4 user cells discard received cc cells 3 2 1 1 3;%( data sheet 2-33 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh &rqwlqxlw\&khfn&hoo*hqhudwlrq6wdwh'ldjudp at the cc termination point (see iljxuh ): ? discard of cc cells (see iljxuh , marker ) ? declaration of loc ghihfw state and insertion of ais cells in one second intervals after 3.5 seconds absence of user or oam cells (see iljxuh , marker ) ? declaration of loc idloxuh state if loc defect state persists for 2.5 seconds. )ljxuh &rqwlqxlw\&khfn(ydoxdwlrq6wdwh'ldjudp the loc failure state is notified to the control processor, while still ais cells are automatically generated. this additional filtering according to the standards avoids frequent notifications to the microprocessor due to sporadic errors (see bits 3..0 of register isr0, vhfwlrq ). all cell insertions are initiated by the scan mechanism (see vhfwlrq ). the delay times given are default values, recommended by i.610 [ ]. the pxb 4340 aop allows to program these values in multiples of the scan frequency which in turn is given by the microprocessor. the corresponding register is named scconf0 (see vhfwlrq page 78). cc active cc inactive setup of new connection cc activated for vpc/vcc by up cc deactivated for vpc/vcc by up insert cc cell if no user cell transmitted for programmable ts (<= 1.5 sec, default 1 sec) cc active notification to up notification to up cc inactive loss of continuity failure send periodically ais/rdi every 1 second loss of continuity defect setup of new connetion cc activated for vpc/vcc by up cc deactivated for vpc/vcc by up first valid atm cell for vpc/vcc received no valid atm cell for vpc/vcc received for programmable tr (<= 7.5 sec, default: 3.5 sec) first valid atm cell for vpc/vcc received no valid atm cell for vpc/vcc received for programmable tdef (<= 7.5 sec, default: 2.5 sec) send periodically ais/rdi every 1 second 3;%( data sheet 2-34 04.2000 )xqfwlrqdo'hvfulswlrq to further limit the load for the microprocessor the dma function is provided which transfers relevant status bits for all connections to the control processor memory in the background (see fkdswhu ). the insertion of ais cells occurs as in the ais state ( fkdswhu ), i.e. with periodic insertion of vp-ais or vc-ais cells and vp-rdi cells in backward direction. no additional ais cells are inserted if ais and loc state are declared simultaneously. additionally to the standardized cc an internal continuity check icc is provided as proprietary function. it uses cc cells with a specially marked header (see vhfwlrq ) between incoming and outgoing port. if no aope continuity check is active a network element icc can be activated in order to check the connectivity across the switching network between aope upstream and aope downstream. the functionality of icc does not differ from the aope cc since a received icc cell is treated like a cc cell, i.e. the same checkers/generators which otherwise do cc processing are used for icc with the following consequences : ? insertion of icc cells in the upstream direction of the aope (originating point) if no valid user cell has been received for a specified time interval of one second. ? supervision of arrived user cells or icc cells at downstream direction of the aope (terminating point) within a specific time interval of 3.5 +/- 0.5 seconds. ? loss of icc cells in downstream direction of the aope will result in ais/rdi generation as described in vhfwlrq . the ais/rdi generation is adjustable via vpc/vcc. icc can be activated by software for each valid vpc/vcc. icc cells are distinguished from cc cells by the hk bits (hk=100) in the utopia cell header (udf1 field). for icc segment cc cell format is used. if evaluation of the udf1 field is not enabled, icc is not supported. for icc the vp/vc segment configuration flags are not relevant. therefore 3 atm layer configuration cases for upstream cell generation are remaining : ? generation of vp icc cells at vp intermediate points ? geneartion of vc icc cells at vc originating end points ? generation of vc icc cells at vc intermediate points for downstream evaluation are remaining : ? evaluation of vp icc cells at vp intermediate points ? evaluation of vc icc cells at vc terminating end points ? evaluation of vc icc cells at vc intermediate points icc cells never leave a switch while icc is intended for connection supervision within a switch. 1hwzrun&rqqhfwlylw\&khfn /% *hqhudo the loopback (lb) oam function is intended for checking the connectivity of a virtual connection by sending a single lb cell along the connection. the lb cell is extracted at well defined points of the network and sent back to the source via the backward connection. note that each atm connection has an associated connection in backward direction with the same connection identifiers. 3;%( data sheet 2-35 04.2000 )xqfwlrqdo'hvfulswlrq there are three possibilities for specifying the loopback point of an lb cell: ? end-to-end lb processing ? segment lb processing ? end point lb processing the loopback function determines which loopback activities are executed dependent on atm layer configuration of the network element (originating segment/end point, terminating segment/ end point, intermediate point) and the received f4/f5 lb cell at the aope (upstream, downstream). loop of lb cells including reset of the lb indication bit in the cell is done without microprocessor interaction at the respective segment or connection end points. the vpc consistency flag (see vhfwlrq page 39) indicates the availability of the vpc to the microprocessor at the loopback port. the loopback processing selects the loopback actions dependent on the loopback state and the loopback location/source id flag of the f4/f5 flow and the content of the received f4/f5 lb cell payload (lb indication, lb location id, lb source id) at the aope (upstream or downstream). the evaluation of the lb location/source id of the lb cell payload is switchable via the lb location/source id flag. the correlation tag of the lb cell payload is supported by sw. if the connection is in loopback state (lb state = 1) then an lb cell can be copied or dropped from cellstream into the cell buffer of the p. if the lb location/source id flag is set a compare has to be done between the lb location/source id and the network element id (see vhfwlrq page 98). at the originating segment/end point, the f4/f5-lb cell can be inserted into the cellstream in upstream or downstream direction. the insertion of the lb cell is done by sw via the transmit cell buffer of the p (see marker ? in iljxuh , iljxuh and iljxuh ). if a looped f4/f5 lb cell arrived at the originating segment/end point, this cell is dropped to the cell receive buffer of the p (see marker ? in iljxuh , iljxuh and iljxuh ). cell insertion and extraction functions are described in vhfwlrq page 49. the atm layer configuration, the loopback state of a connection and the lb location/source id flag are vp and vc connection specific data. this data is located in external rams for upstream and downstream direction (see vhfwlrq page 98). note that the automatic loop function assumes identical connection identifiers for both forward and backward connections. ))(qgwr(qg/rrsedfn3urfhvvlqj if the lb indication bit of an lb cell is equal to 1 the lb cell is forwarded to the terminating end point. at the terminating end point the lb indication flag is set to 0 and the lb cell is looped back (loopback point, see iljxuh , marker ). if the lb indication is equal to 0 (lb cell already looped) and the connection is in lb state (lb state = 1) and the lb source id of the lb cell is equal the network element id (lb source id match) then the lb cell is copied to the receive cell buffer of the p and the lb cell is also forwarded to the terminating end point (see iljxuh , marker ). if the lb source id flag of this connection is disabled the same loopback actions are done. if the connection isnt in lb state (lb state = 0) or an lb source id mismatch occurs the lb cell is forwarded to the terminating end point (see iljxuh , marker ? ). 3;%( data sheet 2-36 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh ([dpsohri)(qgwr(qg/rrsedfn3urfhvvlqj ))6hjphqw/rrsedfn3urfhvvlqj if the lb indication bit of an lb cell is equal to 1 and an lb location id of the lb cell is equal to the network element id (lb location id match) the loopback indication flag is set to 0 and the lb cell is looped back (loopback point, see iljxuh , marker ). additionally the unchanged lb cell is forwarded to the terminating segment point. this cell is looped back at the terminating segment point (see iljxuh , marker ). if the lb location id flag is disabled or an lb location id mismatch occurs the lb cell is forwarded to the terminating segment point (see iljxuh , marker ) 7deoh (qgwr(qg/rrsedfn3urfhvvlqj /% lqglfdwlrq /%vwdwh /%/rfdwlrq 6rxufh,')odj /%/rfdwlrq 6rxufh,' /rrsedfn$fwlrq 1 dont care dont care dont care forward lb cell to terminating end point 0 0 dont care dont care forward lb cell to terminating end point 1 disabled dont care ? copy of lb cell to p receive cell buffer ? forward lb cell to terminating end point enabled match enabled mismatch forward lb cell to terminating end point aope lb status = 1 aope lb status = 0 aope lb status = 1 aope insertion of f4 lb cell drop lb cell to p receive cell buffer copy lb cell to p receive cell buffer when lb status and lb source id match and lb cell is allready looped aope configured as an f5 orginating end point configured as an f4 originating end point and f5 originating segment point configured as an f4 intermediate point configured as an f5 terminating end point configured as an f4 terminating end point and f5 terminating segment point configured as an f4 intermediate point configured as an f4 terminating end point and f5 intermediate point configured as an f4 originating end point and f5 intermediate point aope configured as an f5 terminating segment and f5 terminating end point configured as an f5 originating segment and f5 originating end point lb cell looped back configured as an f4 intermediate point configured as an f4 intermediate point set lb indication flag to 0 set lb indication flag to 0 1 2 3 4 5 3;%( data sheet 2-37 04.2000 )xqfwlrqdo'hvfulswlrq . )ljxuh ([dpsohri)6hjphqw/rrsedfn3urfhvvlqj if the lb indication of an lb cell is equal to 0 (lb cell already looped) and the connection is in lb state (lb state = 1) and the lb source id of the lb cell is equal to the network element id (lb source id match) the lb cell is copied into the receive cell buffer of the p and the lb cell is forwarded to the terminating segment point. if the lb source id flag of a connection is disabled the lb cell is also copied into the receive cell buffer of the p and the lb cell is forwarded to the terminating segment point. 7deoh 6hjphqw/rrsedfn3urfhvvlqj /% ,qglfdwlrq /%6wdwh /%/rfdwlrq 6rxufh,')odj /%/rfdwlrq 6rxufh,' /rrsedfn$fwlrq 1 dont care enabled match ? set lb indication to 0 ? lb cell is looped back ? forward of lb cell to terminating segment point enabled mismatch forward of lb cell to terminating segment point disabled dont care 0 0 dont care dont care forward of lb cell to terminating segment point 1 disabled dont care ? copy of lb cell to p receive cell buffer ? forward of lb cell to terminating segment point enabled match enabled mismatch forward of lb cell to terminating segment point aope lb status = 1 aope lb status = 0 aope lb status = 1 aope lb status = 0 insertion of f5 lb cell drop lb cell to p receive cell buffer aope configured as an f5 orginating end point configured as an f4 originating end point and f5 originating segment point configured as an f4 intermediate point configured as an f5 terminating end point configured as an f4 terminating end point and f5 terminating segment point configured as an f4 intermediate point configured as an f4 terminating end point and f5 intermediate point configured as an f4 originating end point and f5 intermediate point aope configured as an f5 terminating segment and f5 terminating end point configured as an f5 originating segment and f5 originating end point lb cell looped back configured as an f4 intermediate point configured as an f4 intermediate point f5 segment lb set lb indication flag to 0 lb cell looped back 1 2 3 4 5 set lb indication flag to 0 4 3;%( data sheet 2-38 04.2000 )xqfwlrqdo'hvfulswlrq ))(qg3rlqw/rrsedfn3urfhvvlqj if the lb indication of an lb cell is equal to 1 and an lb location id of the lb cell is equal to the network element id (lb location id match) the lb indication flag is set to 0 and the lb cell is looped back (loopback point, see iljxuh , marker ). this means that the aope asic sends the lb cell to the opposite direction of aope (from upstream direction to downstream direction and in opposite direction). in case of an lb location id mismatch the lb cell is discarded. additionally the loopback processing sets a consistency flag for the p only at the vp terminating end point (aope upstream) in order to support the vpci consistency check. the consistency flag is reset by sw. if the lb indication of an lb cell is equal to 0 (lb cell already looped) and the connection is in lb state (lb state = 1) and the source id of the lb cell is equal the network element id (lb source id match) the lb cell is dropped into the receive cell buffer of the p (see iljxuh , marker ). if the lb source id flag of a connection is disabled or an lb source id mismatch occurs then the lb cell is discarded. if the connection isnt in lb state (lb state = 0) the lb cell is discarded. )ljxuh ([dpsohri)(qg3rlqw/rrsedfn3urfhvvlqj aope aope aope lb status = 1 aope lb status = 0 aope lb status = 1 aope insertion of f4 lb cell drop lb cell to p receive cell buffer configured as an f5 orginating end point configured as an f4 originating end point and f5 originating segment point configured as an f4 intermediate point configured as an f5 terminating end point configured as an f4 terminating end point and f5 terminating segment point configured as an f4 intermediate point configured as an f4 terminating end point and f5 intermediate point configured as an f4 originating end point and f5 intermediate point configured as an f5 terminating segment and f5 terminating end point configured as an f5 originating segment and f5 originating end point lb cell looped back configured as an f4 intermediate point configured as an f4 intermediate point set flag for vpci consistency check 3 1 2 vpci consistency flag 3;%( data sheet 2-39 04.2000 )xqfwlrqdo'hvfulswlrq 93&,&rqvlvwhqf\&khfn vpci consistency check is supported by the lb function at the vpc terminating end point. the loopback function of aope (upstream) indicates vpci consistency by setting a flag, if an f4 end-to-end lb cell is received and successfully looped back at vpc terminating end point. this flag is reset by sw. the bit vpcchk in dword4 of the external ram entry is the corresponding to this flag (see vhfwlrq page 105, and vhfwlrq page 116). &rqqhfwlrq4xdolw\0hdvxuhphqw 30 *hqhudo to make measurement of connection quality possible, the aope provides a number of counters. the performance monitoring (pm) flow allows the use and evaluation of these counters. the counter values are stored in the internal pm main ram (see vhfwlrq page 121). the aope can process 128 bidirectional pm flows configurable for the upstream or downstream direction on a connection basis (see vhfwlrq page 98). pm flows can be applied to the f4/ f5 layer as a segment flow or end-to-end flow. in the pm flow, forward error detection information (e.g. the error detection code) is communicated by the pm end points using forward monitoring (fm) cells. the performance monitoring results are received on the reverse direction using backward reporting (br) cells. after a block of user cells has been received, the related fm cell can be inserted directly within the next cell cycle. the blocksize is defined in vhfwlrq page 122. the first fm cell sent from the pm originating point is used to initialize the pm terminating point. after an fm cell has been received at a pm terminating point, the corresponding br cell is generated (if enabled) and sent back via the opposite direction, i.e. if it is received upstream it is sent downstream and if it is received downstream it is sent upstream. 7deoh (qg3rlqw/rrsedfn3urfhvvlqj /% lqglfdwlrq /%vwdwh /%/rfdwlrq 6rxufh,')odj /%/rfdwlrq 6rxufh,' /rrsedfn$fwlrq 1 dont care dont care match ? set lb indication flag to 0 ? lb cell looped back ? set a flag for vpci consistency check mismatch discard lb cell 0 0 dont care dont care discard lb cell 1 disable dont care drop of lb cell to receive cell buffer of the p enabled match enable mismatch discard lb cell 3;%( data sheet 2-40 04.2000 )xqfwlrqdo'hvfulswlrq the first br cell is generated when the first fm cell for this pm flow has been received. this br cell carries valid data to initialize the br data collection point, but no valid data for data collection. only the following br cells contain valid data for data collection. the pm function is split into three different parts: ? pm generation ? pm analysis and loop ? pm data collection. pm generation includes ? calculation of total user cell count for all cells and for high priority cells (clp=0) ? calculation of a bip-16 checksum over user cell payload ? generation of fm cells containing the calculated results. the fm cells are coded as f4 or f5 automatically for vpcs and vccs, respectively, end-end or segment as specified. fm cell sequence number and crc-10 checksum are also generated. the blocksize can be selected between 2 and 65536. the optional time stamp of the fm cell is not generated. forced oam cell insertion is used for both up- and downstream fm cell insertion. during insertion of fm cells the user cell stream is stored in the respective buffers (see vhfwlrq ). pm analysis and loop include ? calculation of total user cell count for all cells and for high priority cells (clp=0) ? extraction of fm cells ? appending of calculation results to the end of the cell ? conversion of the cell into a br cell ? re-insertion of the br cell in opposite direction. pm analysis uses the same pm processor circuits as the generation process. in total 128 pm processor circuits are shared by up- and downstream direction. for pm data collection 128 circuits are provided, which are independent of the pm processor circuits. both pm and data collection processors have their respective entries in the internal pm/ data collection rams. the assignment of pm and data collection processors to connections in up- or downstream direction is arbitrary. vpcs and vccs can be assigned by programming pointers in the f4 and f5 entries, respectively (see vhfwlrq page 121, and vhfwlrq page 123). ([dpsoh a typical pm scenario is shown in iljxuh in case of vp end-to-end monitoring. two nodes are involved, node a where the vpc a-b is created and node b where vpc a-b is terminated. in backward direction the associated vpc b-a is created in node b and terminated in node a. creation of a vpc allways occurs at an outgoing port of a node and termination at an incoming port. hence the originating end point (oep) of vpc a-b is located in the downstream part of the pxb 4340 aop in node a, and the terminating end point (tep) of vpc a-b is located in the upstream part of the pxb 4340 aop in node b. for vpc b-a the situation is mirrored according to iljxuh . 3;%( data sheet 2-41 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 30&rqiljxudwlrq([dpsoh note that between nodes a and b a number of intermediate nodes can be located. all pxb 4340 aop chips on these nodes must be configured either as originating or terminating segment points (osp, tsp) or as intermediate points (ip). one of the 128 pm processors in the pxb 4340 aop upstream part of node a is configured in generate mode, i.e. it monitors all user cells of vpc a-b , computes pm data and inserts it after blocks of user cells into the cell stream as forward monitoring (fm) cells. at the terminating pxb 4340 aop one of the 128 pm processors is configured in analyze mode, i.e. it monitors all user cells of vpc a-b , computes pm data and adds it to the pm data contained in the fm cells. the fm cells are extracted from the cell stream, converted into backward reporting (br) cells and re-inserted in backward direction in vpc b-a . the conversion into br cells includes the calculation of the differences between measured pm data and the pm data contained in the fm cells. the differences are written into the br cells. back at the originating node a, the br cells are discarded after evaluation. note that the re-insertion of br cells in backward direction assumes the same identifier (lci) of the backward direction connection. ? ? plfursurfhvvru plfursurfhvvru 93&2(3 93&7(3 30gdwd froohfwlrq 93%5 fhoov 30gdwd froohfwlrq 30surfhvvru dqdo\]hprgh 93%5 fhoov 30surfhvvru jhqhudwhprgh 93%5 fhoov 93)0 fhoov 93)0 fhoov xvhu fhoov xvhu fhoov switch 1rghd 1rghe aop aop vpc oep vpc tep 93& de 93& ed switch 3;%( data sheet 2-42 04.2000 )xqfwlrqdo'hvfulswlrq 30'dwd&roohfwlrq the data collection procedure is independent of the fm/br cell mechanism. it uses one of the 128 data collection processors contained in the pxb 4340 aop. each of them can evaluate the br data flow from upstream or downstream direction. data collection can be done at any node along the way of the br cells. in the example of iljxuh nodes a or b could be selected for data collection. it can be done concerning the data of an incoming br cell or after a bler0+1 calculation concerning the data of an incoming fm cell. the tucdiff/tucdiff0 calculation has to be done before the data collection can be started. in the data collection processing it is first proved whether tucdiff/tucdiff0 is zero. if it is zero, the bler0+1 is checked. if tucdiff/ tucdiff0 is not zero, it is not reasonable to prove the bler0+1. according to the defined thresholds certain counters have to be updated. 7deoh is a summery of counters, which are updated for data collection (see vhfwlrq page 123). the counters secb, secberr, secbmis and tlostc0 are updated if a related threshold value is reached. the threshold values are set in several p registers (see vhfwlrq page 71). tucdiff is the difference between the transmitted cells of the pm originating point and the received cells of the pm terminating point. tucdiff is calculated for the clp-0+1 flow and tucdiff0 for the clp=0 flow. the bler-0+1 counts the bip16 errors of a block of user cells if no user cells are lost or misinserted, i.e. tucdiff = 0. 7deoh 8sgdwhgfrxqwhuviru'dwd&roohfwlrq $furq\pv whup impb impaired blocks secb severely errored cell blocks secberr severely errored cell block errored counter errc errored cells lostc lost cells misc misinserted cells tlost0 total lost cells secbmis severely errored cell blocks of misinserted cells lostc0 lost cells of the clp=0 flow tlostc0 total lost cells of the clp=0 flow transuc0 transmitted user cells of clp=0 flow transuc transmitted user cells of clp-0+1 flow 3;%( data sheet 2-43 04.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 30'dwd&roohfwlrq 1rwh 7kh wkuhvkrogv 0/267 dqg 00,6,16 dqg 0(55 fdq eh surjudpphg iru xs dqg grzqvwuhdp gluhfwlrqvhsdudwho\7kh\dsso\irudoofrqqhfwlrqv 6lpxowdqhrxv30iorzv the pxb 4340 aop contains 128 pm processors which may be used to generate an fm flow or to terminate an fm flow. terminating an fm flow means analyzing and looping of the fm cells as br cells. during one cell cycle irxu pm processors can be executed arbitrary for f4 and f5 level. it may happen that a user cell belongs to a vcc for which f5 segment pm is done. e.g. in the example of iljxuh node b could be a vcc originating segment point (osp) in addition to the vpc tep. in this case the arrival of a vcc user cell triggers two pm processors in the upstream part of the pxb 4340 aop. in case of f4 and f5 segments e.g. the downstream part of a pxb 4340 aop could be configured as vpc osp and vcc osp ( uhihu wr wdeoh ). in this case a user cell not only triggers two pm processors simultaneously, but might also complete two pm blocks. then two fm cells have to be generated simultaneously. in this case the pxb 4340 aop first inserts the vp-fm cell and then the vc-fm cell. (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6) (0,16) .... (+1,x) (+2,x) (+3,x) (-1,x) (-2,x) (-3,x) (-4,x) .... .... add 1 to secb add bipv to errc mmisins = 2 mlost = 3 merr = 3 add tucdiff to misc add 1 to secb add 1 to secb add |tucdiff| to lostc add 1 to impb add 1 to impb add 1 to secberr tucdiff add |tucdiff| to tlostc add 1 to secbmis (-2,x) tucdiff bler0+1 x = not defined secb = severely errored cell block common flow (clp = 0+1) add 1 to impb bler0+1 3;%( data sheet 2-44 04.2000 )xqfwlrqdo'hvfulswlrq $gmdfhqw306hjphqwv the arbitrary assignment of pm processors to connections also allows e.g. to terminate a segment pm flow and generate a new segment pm flow for the same connection within one pxb 4340 aop as shown in iljxuh . )ljxuh ([dpsohirudgmdfhqw306hjphqwv $fwlydwlrqdqg'hdfwlydwlrq&hoov these cell types are generated by the microprocessor and transmitted via the cell insertion function ( vhfwlrq ) of the pxb 4340 aop. the detection and extraction of activation/deactivation cells is done automatically at the respective segment or end-to-end points if the pxb 4340 aop is configured correctly and the function is enabled (which is possible per connection). extracted cells are stored in the receive buffer ( vhfwlrq ). ,qwhudfwlrqvehwzhhq2$0)xqfwlrqv the pxb 4340 aop does failure propagation automatically, e.g. a received vp-ais cell automatically leads to the generation of vc-ais and vp-rdi cells at the vp endpoint. also the generation of ais/rdi as a consequence of loc state is done automatically. failure propagation from degraded performance, detected with the pm function, to ais/rdi insertion, however is not done automatically, but must be initiated by the microprocessor. to enforce vp-level ais/rdi insertion command bits are available per connection. if enabled the pxb 4340 aop automatically inserts vc-ais cells for all vccs of a vpc. connection specific ais state is left when user or cc cells are detected. only end-to-end cells may react in this way with ais because "shorter" cc flows such as segment cc or icc may cause a mixture of ais and scc/icc cells which would corrupt ais recognition in the cases a) [ \ ] segment fm flow segment br flow x, y, z independent, any value between 0 and 127 pm = performance monitoring dc = data collection segment fm flow segment br flow '& surfhvvru] 30 surfhvvru\ lqjhqhudwh prgh 30 surfhvvru[ lqdqdo\]h prgh 305$0 '&5$0 pm entry pm entry dc entry 3;%( data sheet 2-45 04.2000 )xqfwlrqdo'hvfulswlrq and b) outlined in figure x. consequently the ais analyser implementation totally ignores scc/ icc cells. neither the occurrence of scc/icc cells causes return to ais normal state nor the setup for activation of the cc checker disables return to ais normal state by a timeout criterion. )ljxuh (iihfwri&&fhoovrq$,6uhfrjqlwlrq user cells oep osp tsp tep ais cells ais monitoring corrupted if ais state is left with scc occurence user cells oep osp tsp+tep ais cells cc flow active scc cells cc flow active scc cells rdi generating corrupted if ais state is left with scc occurence e2e-cc cells oep osp tsp+tep ais cells cc flow broken undisturbed monitoring and tep processing a) b) c) aope defect e2e = end-to-end scc = segment cc 3;%( data sheet 2-46 04.2000 )xqfwlrqdo'hvfulswlrq &hoo)lowhuv the pxb 4340 aop provides two types of cell filters: ? filters for special oam cells ? filters for general purpose atm cells for both filter types two filters are provided. 6shfldo2$0&hoo)lowhuv for these filters only the first payload byte of the desired oam cell (oam type and function type field) has to be programmed. the other criteria of oam cells, vci or pt coding are hard-wired in the chip. all oam cells, f4 and f5, segment and end-to-end are detected. the filters are working for up- and downstream direction. for each filter the action upon the detection of an oam cell of the programmed type can be programmed: ? ignore cell (default) ? discard cell ? extract to receive buffer ? copy to receive buffer and forward. applications for this filter function are e.g. proprietary oam functions using the standardized system oam cell coding or the treatment of future oam cell types. *hqhudosxusrvh&hoo)lowhuv these filters consist of 3 programmable words for the comparison of all 5 cell header bytes plus the first payload byte. the utopia cell format described in vhfwlrq is compared. each bit can be individually masked with the mask pattern defined in 3 programmable mask registers. a masked bit matches always when the pattern is compared to the atm cells. cells from both up- and downstream direction are compared. upon match the following actions can be selected: ? ignore cell (default); e.g. forward cell ? discard cell ? extract to receive buffer ? copy to receive buffer and forward. see vhfwlrq for the receive buffer description. in addition to the these actions the match signals of both comparators and for up- and downstream direction are output at four pins as a short pulse. the pulses can be further processed by external logic. this feature could be used for measurements. other applications for the general purpose cell filters are e.g. communication channels within a switch or the filtering of rm cells. 0lfursurfhvvru&rqwuro a 16-bit microprocessor interface for embedded controllers like e.g. the 386ex is provided for configuration and operation of the pxb 4340 aop. 8 address lines allow to address 172 registers (non-contiguous addresses). interrupts are provided for the notification of unexpected events. dma support is provided for fast data transfer to and from the external rams. 3;%( data sheet 2-47 04.2000 )xqfwlrqdo'hvfulswlrq $ffhvvwrlqwhuqdodqgh[whuqdo5$0v the microprocessor can not access these rams directly, but uses a transfer register set. it consists of three blocks: ? read register block ? write register block ? mask register block. in addition an address register specifying the entry to be accessed and a command register to specify the ram and to start the transfer are defined. the pxb 4340 aop uses one single access type, the read-modify-write transfer, where the old data is transferred from the specified ram entry to the read transfer registers and the contents of the write transfer registers are written to the ram entry for those bits which are unmasked. in addition to the read-modify-write access executed upon microprocessor command for a single entry, there are two other access types to the external ram (figure 30): ? the access initiated by the passing atm cell ? the scan access for oam and/or dma. )ljxuh $ffhvvwrlqwhuqdoruh[whuqdo5$0v $235hjlvwhuv cmr register address register write transfer registers read transfer registers internal or external ram ?3 data address address = k ram entry 0 ram entry n ram entry k transfer command r ea d mask registers m m u u x x write write select select 3;%( data sheet 2-48 04.2000 )xqfwlrqdo'hvfulswlrq 6&$10hfkdqlvpzlwk2$0dqgru'0$)xqfwlrq this mechanism has to be triggered by the microprocessor. it is recommended to trigger it in a 0.5 s time frame, as all time-out values are determined based on this time interval. during a scan all entries within the specified range of the external rams are accessed sequentially using the read-modify-write access described in vhfwlrq . the scan must be programmed in a way that it covers all used ram entries in a little less than 0.5 s. to initialize the scan mechanism use register scconf2 (see vhfwlrq page 79). the scan is processed for all connections inside the range selected by register scconf4 (see vhfwlrq page 80) and register scconf5 (see vhfwlrq page 81). to initiate the scan bit startsc in register scconf3 has to be set (see vhfwlrq page 80). the following equation can be used to calculate the scan cycle period (scp) : with : scanperiod + tolerance < 500 ms ! example : the aop needs 32 cycles per cell. at a core frequency of 51.84 mhz the aop can process 1.62 m cells per second. if scan has to process e.g. 8192 connections within 350 ms (scanperiod + tolerance) the scp is calculated as : here scp is equal to the time the aop needs to process 69.21 cells. the values of the register entry scp is of type integer. so the scp is rounded to 69. if the result of the scp calculation is 40 or less scan operation is no more guaranteed at full traffic load because scan operation requires a number of empty cycles. with each scan trigger two functions can be enabled independently for up- and downstream direction: oam function and dma transfers. oam functions include all the necessary actions for ais/rdi/cc processing, i.e. update of counters, check for time-out values and execution of state transitions, oam cell insertions and interrupts. the dma function allows to transfer data to and from the external ram during the scan. the dma function has two modes, the normal dma function and the compressed dma. in the normal dma mode a specified dword of each external ram entry is transferred to a range of the microprocessor main memory. each bit of the specified dword can be overwritten by a specified value for all entries. so the normal dma can be used to initialize the whole external ram to common values or also to verify entries of all connections. in compressed dma mode one dword with pre-defined bits collected from several dwords of the external ram is transferred to a microprocessor memory range. the pre-defined bits are status bits and status transition bits. the status transition bits must be reset with each scan, which can be achieved with appropriate settings of write and mask registers. the compressed dma is typically used in-service together with the oam function (see vhfwlrq ). scp scanperiod tolerance C () f core cycles per cell ------------------------------------- lci max lci min C 1 + ------------------------------------------------------------------------------------------------------------------ - = scp 350ms 1.62 m cells s ------------ - 8192 ------------------------------------------------------------- 6 9 . 2 1 c e l l s = = 3;%( data sheet 2-49 04.2000 )xqfwlrqdo'hvfulswlrq for the dma data transfers a 32 word fifo is provided on-chip for dma read (figure 31). it is emptied by the microprocessor via consecutive reads of the dma register. the dma request pin of the pxb 4340 aop is asserted when the fifo is occupied and deasserted when it is empty. the dma transfer itself must be executed by an external dma controller. )ljxuh 6fdq0hfkdqlvpzlwk2$0dqgru'0$)xqfwlrq 5hfhlyhdqg7udqvplw%xiihu the pxb 4340 aop provides a 12-cell receive buffer and a 1-cell transmit buffer. they are used for insertion and extraction of lb cells, activation and deactivation cells and special cells defined with the cell filters (see vhfwlrq ). the buffers are realized differently. the transmit buffer consists of 27 words, directly addressable by the microprocessor for read and write. when the cell is assembled it can be inserted by setting a command bit. the command bit is reset after complete insertion of the cell into the data stream. the insertion direction, up- or downstream can be selected and also if the crc-10 should be computed automatically by the chip or not. the receive buffer is realized as fifo with word-wise access via a single register. a cell is read with 27 consecutive read accesses to this register. reception of a cell is signalled to the microprocessor via an interrupt bit. the interrupt bit is reset by the chip automatically after the last read access if no more cell is in the buffer. the receive buffer collects cells from up- and downstream direction, they are distinguished with a bit in the udf2 octet. cell format for both receive and transmit buffer is the 16-bit utopia format as described in vhfwlrq . external aop ram up or down entry k cell access scan / oam p access transfer registers p - i/f aop 32 x 16 bit words fifo dma-option dmar register 3;%( data sheet 3-50 04.2000 5hjlvwhu'hvfulswlrq 5hjlvwhu'hvfulswlrq 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 5hdg0dvn:ulwh5hjlvwhuv 00 wdr0l write data register 0 (15.. 0) r rw 0000 h 59 01 wdr0h write data register 0 (31..16) r rw 0000 h 59 02 wdr1l write data register 1 (15.. 0) r rw 0000 h 59 03 wdr1h write data register 1 (31..16) r rw 0000 h 59 04 wdr2l write data register 2 (15.. 0) r rw 0000 h 59 05 wdr2h write data register 2 (31..16) r rw 0000 h 59 06 wdr3l write data register 3 (15.. 0) r rw 0000 h 59 07 wdr3h write data register 3 (31..16) r rw 0000 h 59 08 wdr4l write data register 4 (15.. 0) r rw 0000 h 59 09 wdr4h write data register 4 (31..16) r rw 0000 h 59 0a wdr5l write data register 5 (15.. 0) r rw 0000 h 59 0b wdr5h write data register 5 (31..16) r rw 0000 h 59 0c wdr6l write data register 6 (15.. 0) r rw 0000 h 59 0d wdr6h write data register 6 (31..16) r rw 0000 h 59 0e wdr7l write data register 7 (15.. 0) r rw 0000 h 59 0f wdr7h write data register 7 (31..16) r rw 0000 h 59 10 wdr8l write data register 8 (15.. 0) r rw 0000 h 59 11 wdr8h write data register 8 (31..16) r rw 0000 h 59 12 wdr9l write data register 9 (15.. 0) r rw 0000 h 59 13 wdr9h write data register 9 (31..16) r rw 0000 h 59 14 wdr10l write data register 10 (15.. 0) r rw 0000 h 59 15 wdr10h write data register 10 (31..16) r rw 0000 h 59 16 wdr11l write data register 11 (15.. 0) r rw 0000 h 59 17 wdr11h write data register 11 (31..16) r rw 0000 h 59 18 wdr12l write data register 12 (15.. 0) r rw 0000 h 59 19 wdr12h write data register 12 (31..16) r rw 0000 h 59 1a wdr13l write data register 13 (15..0) r rw 0000 h 59 3;%( data sheet 3-51 04.2000 5hjlvwhu'hvfulswlrq 1b wdr13h write data register 13 (31..16) r rw 0000 h 59 1c rdr0l read data register 0 (15.. 0) rw r 0000 h 60 1d rdr0h read data register 0 (31..16) rw r 0000 h 60 1e rdr1l read data register 1 (15.. 0) rw r 0000 h 60 1f rdr1h read data register 1 (31..16) rw r 0000 h 60 20 rdr2l read data register 2 (15.. 0) rw r 0000 h 60 21 rdr2h read data register 2 (31..16) rw r 0000 h 60 22 rdr3l read data register 3 (15.. 0) rw r 0000 h 60 23 rdr3h read data register 3 (31..16) rw r 0000 h 60 24 rdr4l read data register 4 (15.. 0) rw r 0000 h 60 25 rdr4h read data register 4 (31..16) rw r 0000 h 60 26 rdr5l read data register 5 (15.. 0) rw r 0000 h 60 27 rdr5h read data register 5 (31..16) rw r 0000 h 60 28 rdr6l read data register 6 (15.. 0) rw r 0000 h 60 29 rdr6h read data register 6 (31..16) rw r 0000 h 60 2a rdr7l read data register 7 (15.. 0) rw r 0000 h 60 2b rdr7h read data register 7 (31..16) rw r 0000 h 60 2c rdr8l read data register 8 (15.. 0) rw r 0000 h 60 2d rdr8h read data register 8 (31..16) rw r 0000 h 60 2e rdr9l read data register 9 (15.. 0) rw r 0000 h 60 2f rdr9h read data register 9 (31..16) rw r 0000 h 60 30 rdr10l read data register 10 (15.. 0) rw r 0000 h 60 31 rdr10h read data register 10 (31..16) rw r 0000 h 60 32 rdr11l read data register 11 (15.. 0) rw r 0000 h 60 33 rdr11h read data register 11 (31..16) rw r 0000 h 60 34 rdr12l read data register 12 (15.. 0) rw r 0000 h 60 35 rdr12h read data register 12 (31..16) rw r 0000 h 60 36 rdr13l read data register 13 (15.. 0) rw r 0000 h 60 37 rdr13h read data register 13 (31..16) rw r 0000 h 60 38 mdr0l mask data register 0 (15.. 0) r rw 0000 h 60 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-52 04.2000 5hjlvwhu'hvfulswlrq 39 mdr0h mask data register 0 (31..16) r rw 0000 h 60 3a mdr1l mask data register 1 (15.. 0) r rw 0000 h 60 3b mdr1h mask data register 1 (31..16) r rw 0000 h 60 3c mdr2l mask data register 2 (15.. 0) r rw 0000 h 60 3d mdr2h mask data register 2 (31..16) r rw 0000 h 60 3e mdr3l mask data register 3 (15.. 0) r rw 0000 h 60 3f mdr3h mask data register 3 (31..16) r rw 0000 h 60 40 mdr4l mask data register 4 (15.. 0) r rw 0000 h 60 41 mdr4h mask data register 4 (31..16) r rw 0000 h 60 42 mdr5l mask data register 5 (15.. 0) r rw 0000 h 60 43 mdr5h mask data register 5 (31..16) r rw 0000 h 60 44 mdr6l mask data register 6 (15.. 0) r rw 0000 h 60 45 mdr6h mask data register 6 (31..16) r rw 0000 h 60 46 wmask mask for word 7-13 r rw 0000 h 61 47 rmwc rmw control register rw rw 0000 h 62 48 rmwadr lci/pm pointer for rmw r rw 0000 h 63 &hoow\sh5hfrjqlwlrq5hjlvwhuv 60 lsidr0 lb location/source identifier r rw 0000 h 64 61 lsidr1 lb location/source identifier r rw 0000 h 64 62 lsidr2 lb location/source identifier r rw 0000 h 64 63 lsidr3 lb location/source identifier r rw 0000 h 64 64 lsidr4 lb location/source identifier r rw 0000 h 64 65 lsidr5 lb location/source identifier r rw 0000 h 64 66 lsidr6 lb location/source identifier r rw 0000 h 64 67 lsidr7 lb location/source identifier r rw 0000 h 64 68 ctr0 special oam cell filter 0 r rw 0000 h 64 69 ctr1 special oam cell filter 1 r rw 0000 h 64 6a ctr10 cell filter1 r rw 0000 h 65 6b ctr11 cell filter1 r rw 0000 h 65 6c ctr12 cell filter1 r rw 0000 h 65 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-53 04.2000 5hjlvwhu'hvfulswlrq 6d ctr20 cell filter2 r rw 0000 h 65 6e ctr21 cell filter2 r rw 0000 h 65 6f ctr22 cell filter2 r rw 0000 h 65 70 mr10 mask for cell filter 1 r rw 0000 h 65 71 mr11 mask for cell filter 1 r rw 0000 h 65 72 mr12 mask for cell filter 1 r rw 0000 h 65 73 mr20 mask for cell filter 2 r rw 0000 h 65 74 mr21 mask for cell filter 2 r rw 0000 h 65 75 mr22 mask for cell filter 2 r rw 0000 h 65 7udqvplw5hfhlyh5hjlvwhuv 80 txr0 transmit cell register 0 (header) r rw 0000 h 67 81 txr1 transmit cell register 1 (header) r rw 0000 h 67 82 txr2 transmit cell register 2 (header) r rw 0000 h 67 83 txr3 transmit cell register 3 (payload) r rw 0000 h 68 : : : : : : : : : : : : : : 9a txr26 transmit cell register 26 (payload) rrw0000 h 68 9c tmcr tx command register rw rw 0000 h 69 9d rxrcel receive cell buffer w r 0000 h 70 3huirupdqfh0rqlwrulqj5hjlvwhuv a0 umlost upstream max. lost cells r rw 0000 h 71 a1 ummisins upstream max. misinserted cells r rw 0000 h 71 a2 umlost0 upstream max. lost clp0 cells r rw 0000 h 71 a3 umerr upstream max. errors r rw 0000 h 71 a4 dmlost downstream max. lost cells r rw 0000 h 72 a5 dmmisins downstream max. misinserted cells rrw0000 h 72 a6 dmlost0 downstream max. lost clp0 cells r rw 0000 h 72 a7 dmerr downstream max. errors r rw 0000 h 72 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-54 04.2000 5hjlvwhu'hvfulswlrq 6fdq5hjlvwhuv b0 dwdrl dma write-register (15..0) r rw 0000 h 74 b1 dwdrh dma write-register (31..16) r rw 0000 h 74 b2 dmrl dma mask-register (15.. 0) r rw 0000 h 75 b3 dmrh dma mask-register (31..16) r rw 0000 h 75 b4 phyerrl port 15..0 upstream only r rw 0000 h 76 b5 phyerrh port 23..16 upstream only r rw 0000 h 76 b6 dmar dma-register of dma-fifo rw r 0000 h 77 b7 dconf dma configuration register r rw 0000 h 77 b8 scconf0 oam timeout values r rw 0275 h 78 b9 scconf1 oam timeout values r rw 0057 h 79 ba scconf2 scan cycle period/tolerance r rw 002d h 79 bb scconf3 scan command register r rw 0000 h 80 bc scconf4 scan start lci r rw 0000 h 80 bd scconf5 scan end lci r rw 0000 h 81 be scstat0 scan status register 0 rw r 0000 h 81 bf scstat1 scan status register 1 rw r 8000 h 82 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-55 04.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw5hjlvwhuv d0 isr0 interrupt status register 0 rw rw 0000 h 83 d1 isr1 interrupt status register 1 rw rw 0000 h 84 d2 imr0 interrupt mask register 0 r rw 0000 h 85 d3 imr1 interrupt mask register 1 r rw 0000 h 85 d4 cifl cell insertion fault port bit map (downstream) rw r 0000 h 85 d5 cifh rw r 0000 h 85 8wrsld&rqiljxudwlrq5hjlvwhuv e0 utconf0 config. utopia atm side r rw 0000 h 87 e1 utconf1 config. utopia phy side r rw 0000 h 88 e2 uprtenl utopia port 23..0 enable upstream rrw0000 h 89 e3 uprtenh r rw 0000 h 89 e4 dprtenl utopia port 23..0 enable downstream rrw0000 h 89 e5 dprtenh r rw 0000 h 90 e6 oamthru threshold for forced oam cell insertion upstream rrw001e h 90 e7 oamthrd threshold for cell insertion downstream rrw0060 h 91 e8 bpthrd queue backpressure level downstream rrw0060 h 91 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-56 04.2000 5hjlvwhu'hvfulswlrq 0lvfhoodqhrxv5hjlvwhuv f0 misc sw reset, 1mbit/2mbit ram rw, r rw 0000 h 92 f1 testr1 test register 1 r rw 0000 h 92 f2 testr2 test register 2 r rw 0000 h 93 f3 verl version register (15.. 0) - r a06d h 94 f4 verh version register (31..16) - r 523b h 94 f5 bistml bist mode low register r rw 0000 h 95 f6 bistmh bist mode high register r rw 0000 h 95 f7 bistdon bist done rw r 0000 h 96 f8 bisterr bist error rw r 0000 h 97 7deoh $235hjlvwhu2yhuylhz dgu kh[ uhjlvwhu ghvfulswlrq $6,& fruh ?3 uhvhw ydoxh vhhsdjh 3;%( data sheet 3-57 04.2000 5hjlvwhu'hvfulswlrq 7udqvihu5hjlvwhuv these registers are provided for data transfer to and from the external connection rams or the internal rams.two internal rams are provided, one for pm data processing and one for the collection of analysed pm results. both pm rams are shared for up- and downstream direction. the entries in each ram have different sizes as shown in 7deoh . * depending on external ram size there is only one single ram access type, the read-modify-write transfer shown in iljxuh . it consists of two steps: in the first step all data from the specified ram entry is transferred into the read register set rdr. in the second step the data is written back again. it can be either the original data or new data specified in the write register set wdr. the decision if original or new data is written to the ram entry is done via the mask register set mdr and the mask register wmask. for the lower 7 dwords of an entry the source of each single bit can be individually selected by the corresponding bit of the respective mdr register (bit-by-bit basis), for the upper 7 dwords one single bit of wmask selects the source for a whole dword. 7deoh ,qwhuqdodqgh[whuqdo5$0v 5$0w\sh /rfdwlrq 1xpehurihqwulhv 'zrugvshu hqwu\ upstream connection ram external 4 - 16k* 8 downstream connection ram external 4 - 16k* 8 pm processing data on-chip 128 3 pm data collection on-chip 128 14 3;%( data sheet 3-58 04.2000 5hjlvwhu'hvfulswlrq )ljxuh 5hdgprgli\zulwh7udqvihu the address of the selected entry is given in register rmwadr. register bits for specifying the target ram and initiating the transfer are contained in the read-modify-write control register rmwc. this register also contains command bits for setting or clearing all mask register bits. read and write register sets rdr and wdr contain 14 dwords in 28 registers. for simplification the mask register set is slightly different: mdr0..6 have a one-to-one bit mapping with rdr0..6 and wdr0..6. for rdr7..13 and wdr7..13 one single mask bit for each dword is provided in the wmask register, bits 0..6. when accessing ram entries with less than 14 dwords (see 7deoh ) only the lower registers of rdr, wdr and mdr are involved, e.g. for accesses to the 8-dword size entries of the external connection tables rdr0..7, wdr0..7, mdr0..6 and bit 0 of wmask are involved. for accesses to the different rams the rdr and wdr register bits have different meaning. this is described for each target ram in the mapping tables (see vhfwlrq ). hl 0 13 write transfer registers wdr hl 0 13 0 1 mask registers mdr hl 0 6 7 13 wmask bit 0..6 0 6 select 32 32 32 1 read transfer 2 write transfer 1 2 3 ram entry k read transfer registers rdr 3;%( data sheet 3-59 04.2000 5hjlvwhu'hvfulswlrq :ulwh7udqvihu5hjlvwhuv :'5/:'5+ read/write address 00 h ..1b h value after reset 0000 h the write transfer registers are shown below with their mapping to the 32-bit dwords 0..13. when accessing the external ram bit 31 of each dword controls the parity bit of the entry. if bit 31=0 the correct parity bit is generated. if bit 31=1 the parity bit is inverted. dword 13 register wdr13h / address 1b h register wdr13l / address 1a h 12 register wdr12h / address 19 h register wdr12l / address 18 h 11 register wdr11h / address 17 h register wdr11l / address 16 h 10 register wdr10h / address 15 h register wdr10l / address 14 h 9 register wdr9h / address 13 h register wdr9l / address 12 h 8 register wdr8h / address 11 h register wdr8l / address 10 h 7 register wdr7h / address 0f h register wdr7l / address 0e h 6 register wdr6h / address 0d h register wdr6l / address 0c h 5 register wdr5h / address 0b h register wdr5l / address 0a h 4 register wdr4h / address 09 h register wdr4l / address 08 h 3 register wdr3h / address 07 h register wdr3l / address 06 h 2 register wdr2h / address 05 h register wdr2l / address 04 h 1 register wdr1h / address03 h register wdr1l / address 02 h 0 register wdr0h / address 01 h register wdr0l / address 00 h 3;%( data sheet 3-60 04.2000 5hjlvwhu'hvfulswlrq 5hdg7udqvihu5hjlvwhuv 5'5/5'5+ read address 1c h ..37 h value after reset 0000 h the read transfer registers are shown below with their mapping to the 32-bit dwords 0..13. when reading the external ram bit 31 contains the result of the parity check. bit 31=0 indicates that the external parity bit stored in bit 31 was correct, bit 31=1 indicates a wrong parity bit. 0dvn'dwd5hjlvwhuv 0'5/0'5+ read/write address 38 h ..45 h value after reset 0000 h these registers have a bit-to-bit correspondence to the 7 lower read and write transfer registers rdr0..rdr6 and wdr0..wdr6. if a bit in mdr0l..mdr6h is cleared, the corresponding bit of the ram entry remains unchanged, if set the ram entry bit is overwritten by the value contained in the corresponding write register bit. the upper 7 transfer registers are masked globally with one bit each. these bits are contained in the wmask register. dword 13 register rdr13h / address 37 h register rdr13l / address 36 h 12 register rdr12h / address 35 h register rdr12l / address 34 h 11 register rdr11h / address 33 h register rdr11l / address 32 h 10 register rdr10h / address 31 h register rdr10l / address 30 h 9 register rdr9h / address 2f h register rdr9l / address 2e h 8 register rdr8h / address 2d h register rdr8l / address 2c h 7 register rdr7h / address 2b h register rdr7l / address 2a h 6 register rdr6h / address 29 h register rdr6l / address 28 h 5 register rdr5h / address 27 h register rdr5l / address 26 h 4 register rdr4h / address 25 h register rdr4l / address 24 h 3 register rdr3h / address 23 h register rdr3l / address 22 h 2 register rdr2h / address 21 h register rdr2l / address 20 h 1 register rdr1h / address 1f h register rdr1l / address 1e h 0 register rdr0h / address 1d h register rdr0l / address 1c h 3;%( data sheet 3-61 04.2000 5hjlvwhu'hvfulswlrq the mask data registers are shown below with their mapping to the 32-bit dwords 0..6. :ulwh0dvn5hjlvwhu :0$6. read/write address 46 h value after reset 0000 h dword 6 register mdr6h / address 45 h register mdr6l / address 44 h 5 register mdr5h / address 43 h register mdr5l / address 42 h 4 register mdr4h / address 41 h register mdr4l / address 40 h 3 register mdr3h / address 3f h register mdr3l / address 3e h 2 register mdr2h / address 3d h register mdr2l / address 3c h 1 register mdr1h / address 3b h register mdr1l / address 3a h 0 register mdr0h / address 39 h register mdr0l / address 38 h unused unused bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 6 mask for dword 13. bit 5 mask for dword 12. bit 4 mask for dword 11. bit 3 mask for dword 10. bit 2 mask for dword 9. bit 1 mask for dword 8. bit 0 mask for dword 7. 3;%( data sheet 3-62 04.2000 5hjlvwhu'hvfulswlrq 5hdg0rgli\:ulwh&rqwuro5hjlvwhu 50:& read/write address 47 h value after reset 0000 h 1rwh 7khvhohfwelwv5$06(/ up/dn dqg5'$ru:5$fdqehvhwwrjhwkhuzlwkwkh 67$57elwlqwkhvdphzulwhdffhvv 1rwh 5'$dqg:5$pxvwqrwehvhwvlpxowdqhrxvo\ 1rwh 5hjlvwhu50:&lvzulwhsurwhfwhgdvorqjdv67$57lvvhw unused unused ramsel(1:0) start up/dn wra rda ramsel(1:0) select ram for rmw access 00 pm data processing ram 01 external ram (up- or downstream selected with bit 2). 1x pm data collection ram start command bit. set =1 to start the rmw-access specified with bits 2, 4 and 5. bit 3 is reset after execution of the command. rdr registers should not be read before, otherwise it will result in unexpected values. up/dn selection of external ram for rmw-access: 0 downstream-ram. 1 upstream-ram. wra write all. setting this bit together with the start bit sets all mask register bits to one ehiruh the rmw access. this results in a write access of the whole entry. all dwords of the specified entry are overwritten. the mask bits remain cleared after the access. wra is reset to zero after execution of the rmw access. rda read all. setting this bit together with the start bit sets all mask register bits to zero ehiruh the rmw access. this results in a read only access. no data in the specified entry is modified. the mask bits remain set after the access. rda is reset to zero after execution of the rmw access. 3;%( data sheet 3-63 04.2000 5hjlvwhu'hvfulswlrq 5hdg0rgli\:ulwh$gguhvv5hjlvwhu 50:$'5 read/write address 48 h value after reset 0000 h 1rwh 5hjlvwhu50:$'5lvzulwhsurwhfwhgdvorqjdvwkh67$57elwri50:&lvvhw unused adr(13:8) adr(7:0) adr(13:0) specifies the base address for the rmw access. in 4x1m mode the bits 13..12 selects the ram, the bits 11..0 defines the address. in 2x2m mode the bit 13 selects the ram and the bits 12..0 defines the address. should not be outside the physical range of the respective ram (see 7deoh ). 3;%( data sheet 3-64 04.2000 5hjlvwhu'hvfulswlrq 5hjlvwhuviru&hoow\sh5hfrjqlwlrq /rfdwlrq6rxufh,ghqwlilhu5hjlvwhuv /6,'5 read/write address 60 h ..67 h value after reset 0000 h the 16-octet port id defines a unique identifier for the switch port. it is used for intra-domain lb cells. depending on layer point configuration and settings the port id is compared with location or source id of the lb cell. 6shfldo2$0&hoo)lowhu &75&75 read/write address 68 h ..69 h value after reset 0000 h both ctr0 and ctr1 have the same mapping: using these registers two oam cell types can be defined. oam cells in the cell stream which match a programmed pattern are treated according to the four options defined in the corresponding action(1:0) bits. the action is executed for all matching cells in up- and downstream direction. this function is provided to support new or proprietary oam cell types. these could be dropped to the microprocessor and handled by sw. recognized as oam cells are: all cells with either pti=100 or 101 or vci=3 or 4 and which have the correct crc-10. oam cells with incorrect crc-10 are discarded anyway with notification in interrupt status register isr0 and additionally an indication in the external connection ram entry for the respective connection (lci). $ggu 1dph 60 lsidr0 port id byte #15 port id byte #14 61 lsidr1 port id byte #13 port id byte #12 62 lsidr2 port id byte #11 port id byte #10 63 lsidr3 port id byte #9 port id byte #8 64 lsidr4 port id byte #7 port id byte #6 65 lsidr5 port id byte #5 port id byte #4 66 lsidr6 port id byte #3 port id byte #2 67 lsidr7 port id byte #1 port id byte #0 unused action(1:0) oamtyp(3:0) functyp(3:0) 3;%( data sheet 3-65 04.2000 5hjlvwhu'hvfulswlrq &hoo)lowhudqg5hjlvwhuv &75[\05[\ read/write address 6a h ..75 h value after reset 0000 h using these 12 registers two free programmable cell types can be filtered. the complete utopia cell header (including 5 bits of the udf1 octet but without the udf2 octet) and the first payload octet are compared. each bit within these six octets can be individually masked by setting the corresponding mask bit to one. masked bits match anyway, unmasked bits must match with the corresponding bit in the passing cells. the programmed patterns are compared to all cells in up- and downstream direction. if all unmasked bits match one of the four actions defined in the action bits (8 and 9 of words ctrx2) is executed for the cell. this function can be used to treat selected cells by sw, e.g. by extracting them from the cell stream and processing them by sw. this could be oam cells or any other type of cells, e.g. rm cells or internal message cells. in addition four pins are provided to indicate the match of filter 1 or 2 in up- and downstream direction. these detector pins are activated upon match if not disabled via action(1:0)=00. the match signals of the indication pins fpctxy can be used e.g. to determine the cdv of a certain connection with external evaluation circuitry. action(1:0) action in case of cell filter match 00 ignore cell. use this selection to disable the function. 01 discard cell. 10 drop cell; the cell is extracted from the cell stream and stored in the receive buffer. 11 monitor cell; the cell is copied into the receive buffer. oamtyp(3:0) defines the oam type bits of the oam cell to be filtered. functyp(3:0) defines the function type bits of the oam cell to be filtered. 7deoh &hoo)lowhu'hwhfwru2xwsxwv 0dwfkri&hoo)lowhu 'luhfwlrq $fwlydwhg3lq 1upstreamfpct1u 1 downstream fpct1d 2upstreamfpct2u 2 downstream fpct2d 3;%( data sheet 3-66 04.2000 5hjlvwhu'hvfulswlrq programming of the two cell filters is identical: only the 5 msbs of the udf1 octet are compared. the 3 lsbs are treated like masked and match always. in case of the proprietary cell format udf1(7:3) contains the two msbs of the lci and the housekeeping bits. see )ljxuhv and for cell formats. cell type vpi/lci vci pt c lci hk 1st payload udf1 1 mr10 mr11 mr12 1 ctr10 ctr11 ctr12 2 mr20 mr21 mr22 2 ctr20 ctr21 ctr22 ctrxy, mrxy meaning of the indices x, y: x selects filter 1 or filter 2. y selects one of the three registers for each filter. bit 10 of ctrx2 unused bit 9,8 of ctrx2 define the action to be done in case of match: 00 ignore cell. use this selection to disable the function. 01 discard cell. 10 drop cell; the cell is extracted from the cell stream and stored in the receive buffer. 11 monitor cell; the cell is copied into the receive buffer. 3;%( data sheet 3-67 04.2000 5hjlvwhu'hvfulswlrq 7udqvplw5hfhlyh5hjlvwhuv these registers are used to insert atm cells into the cell stream and to extract or copy cells from the cell stream. for the insertion one set of 27 registers (txr0...txr26) is provided capable of storing a complete atm cell in utopia cell format. when assembled the atm cell is inserted into either up- or downstream data stream via the command register tmcr. for cell extraction/ copy an internal 12-cell receive buffer is provided. a non-empty receive buffer is signalled via bit 9 of interrupt status register isr0. cells are read from the internal receive buffer by repeated reading of the rxrcel register. 7udqvplw&hoo+hdghu5hjlvwhuv 7;5 read/write address 80 h ...82 h value after reset 0000 h (for all) header octets 1..4 as well as udf1 and udf2 octets are mapped transparently to the cell. the only field which is interpreted by the aop is pn(4:0); it selects the (internal) phy port number the cell is destined to. for the determination of the utopia port number and header formats see vhfwlrq . in case of 8-bit utopia pn(4:0) is evaluated but not transferred to the data stream. $ggu 1dph 80 txr0 header octet 1 header octet 2 81 txr1 header octet 3 header octet 4 82 txr2 udf1(7:0) udf2(7:5) pn(4:0) 3;%( data sheet 3-68 04.2000 5hjlvwhu'hvfulswlrq 7udqvplw&hoo3d\ordg5hjlvwhuv 7;57;5 read/write address 83 h ...9a h value after reset 0000 h (for all) 1rwh $gguhvv % + lvxqxvhg all octets are mapped transparently into the transmitted cell. in case the automatic crc-10 generation is enabled the two lsbs of octet 47 and octet 48 will be overwritten. the 6 msbs of octet 47 are mapped transparently into the cell. hence to be conform to the standardized oam cell format these bits must be programmed to zero before inserting an oam cell. $ggu 1dph 83 txr3 payload octet 1 payload octet 2 84 txr4 payload octet 3 payload octet 4 85 txr5 payload octet 5 payload octet 6 86 txr6 payload octet 7 payload octet 8 87 txr7 payload octet 9 payload octet 10 88 txr8 payload octet 11 payload octet 12 89 txr9 payload octet 13 payload octet 14 8a txr10 payload octet 15 payload octet 16 8b txr11 payload octet 17 payload octet 18 8c txr12 payload octet 19 payload octet 20 8d txr13 payload octet 21 payload octet 22 8e txr14 payload octet 23 payload octet 24 8f txr15 payload octet 25 payload octet 26 90 txr16 payload octet 27 payload octet 28 91 txr17 payload octet 29 payload octet 30 92 txr18 payload octet 31 payload octet 32 93 txr19 payload octet 33 payload octet 34 94 txr20 payload octet 35 payload octet 36 95 txr21 payload octet 37 payload octet 38 96 txr22 payload octet 39 payload octet 40 97 txr23 payload octet 41 payload octet 42 98 txr24 payload octet 43 payload octet 44 99 txr25 payload octet 45 payload octet 46 9a txr26 payload octet 47 payload octet 48 3;%( data sheet 3-69 04.2000 5hjlvwhu'hvfulswlrq 7udqvplvvlrq&rppdqg5hjlvwhu 70&5 read/write address 9c h value after reset 0000 h 1rwh ,wlvqrwsrvvleohwrvhwerwk7;83dqg7;'1vlpxowdqhrxvo\ 7;83zlooehvhw 1rwh 7khfhoowudqvplwuhjlvwhuv7;5dqgwkhwudqvplwfrppdqguhjlvwhu70&5lwvhoiduh zulwhsurwhfwhgdvorqjdvrqhriwkhlqvhuwlrqfrppdqgelwv7;83ru7;'1lvvhw7klv dyrlgvhuurqhrxvprglilfdwlrqriwkhfhoogxulqjwkhwudqvplvvlrqskdvh unused unused encrc txup txdn encrc enable automatic crc-10 generation of inserted cell 0 no automatic crc10. must be provided by p. 1 crc10 automatically generated by aop. it is inserted into payload octets 47 and 48 (see vhfwlrq ). txup writing this bit to 1 initiates insertion of the cell specified in registers 80...9a into upstream data path. insertion is done with the next available free cell cycle. after completed insertion txup is reset. txdn writing this bit to 1 initiates insertion of the cell specified in registers 80 h ...9a h into the downstream data path. insertion is done with the next available free cell cycle. after completed insertion txdn is reset. 3;%( data sheet 3-70 04.2000 5hjlvwhu'hvfulswlrq 5hfhlyh&hoo%xiihu5hdg5hjlvwhu 5;5&(/ read address 9d h value after reset 0000 h cell format of the extracted cell is: the cell format is identical to the insertion cell format except the udf2 octet: rxrcel(15:8) rxrcel(7:0) rxrcel(15:0) receive cell buffer access. a cell extracted or copied from the data stream is transferred from the internal receive buffer to the microprocessor by 27 read accesses of rxrcel. the accesses need not be consecutive; it is allowed to access other registers in between. received cell(s) are indicated with bit 9 of isr0 set. after read-out of the last cell isr0(9) is reset by the aop. 5hdg$ffhvv 1st access header octet 1 header octet 2 2nd access header octet 3 header octet 4 3rd access udf1(7:0) 7 6 udf2(5:0) 4th access payload octet 1 payload octet 2 : : : : : : 27th access payload octet 47 payload octet 48 bit 7 udf2(7) of the extracted cell (dont care in case of 8-bit utopia) bit 6 source of the received cell (overwrites udf2(6) of extracted/copied cell) : 0 cell from downstream direction 1 cell from upstream direction udf2(5:0) 6 lsbs of the udf2 octet of the extracted cell (dont care in case of 8- bit utopia). 3;%( data sheet 3-71 04.2000 5hjlvwhu'hvfulswlrq 3huirupdqfh0rqlwrulqj&rqiljxudwlrq5hjlvwhuv these registers define the thresholds in the pm data collection algorithm described in iljxuh 26. the referenced counters are located in the pm data collection ram (see vhfwlrq 3.9.6). 8svwuhdp0d[lpxp/rvwfhoov 80/267 read/write address a0 h value after reset 0000 h recommended value 0003 h . umlost(15:0) holds the global mlost threshold (clp0+1 cells) for the pm data collection in upstream direction. a pm block with more than mlost lost cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mlost cells are missing the lost cell counters are incremented. 8svwuhdp0d[lpxp0lvlqvhuwhgfhoov 800,6,16 read/write address a1 h value after reset 0000 h recommended value 0002 h . umisins(15:0) holds the global mmisins threshold for the pm data collection in upstream direction. a pm block with more than mmisins misinserted cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mmisins cells are misinserted the misinserted cell counters are incremented. 8svwuhdp0d[lpxp/rvw&/3fhoov 80/267 read/write address a2 h value after reset 0000 h recommended value 0003 h . umlost0(15:0) holds the global mlost0 threshold (clp0 cells only) for the pm data collection in upstream direction. a pm block with more than mlost0 lost cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mlost0 cells are missing the lost cell counters are incremented. 8svwuhdp0d[lpxp(uuruv 80(55 read/write address a3 h value after reset 0000 h recommended value 0003 h . umerr(15:0) holds the global merr threshold for the pm data collection in upstream direction. a br cell carrying a block error result bler value greater than merr denotes a severely errored block. accordingly the secb counter is incremented. if bler is less or equal merr the bler value is added to the error counter errc. 3;%( data sheet 3-72 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp0d[lpxp/rvwfhoov '0/267 read/write address a4 h value after reset 0000 h recommended value 0003 h . dmlost(15:0) holds the global mlost threshold (clp0+1 cells) for the pm data collection in downstream direction. a pm block with more than mlost lost cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mlost cells are missing the lost cell counters are incremented. 'rzqvwuhdp0d[lpxp0lvlqvhuwhgfhoov '00,6,16 read/write address a5 h value after reset 0000 h recommended value 0002 h . dmmisins(15:0) holds the global mmisins threshold for the pm data collection in downstream direction. a pm block with more than mmisins misinserted cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mmisins cells are misinserted the misinserted cell counters are incremented. 'rzqvwuhdp0d[lpxp/rvw&/3fhoov '0/267 read/write address a6 h value after reset 0000 h recommended value 0003 h . dmlost0(15:0) holds the global mlost0 threshold (clp0 cells only) for the pm data collection in downstream direction. a pm block with more than mlost0 lost cells is considered severely errored by the data collection algorithm. accordingly the secb counter is incremented. if less or equal mlost0 cells are missing the lost cell counters are incremented. 'rzqvwuhdp0d[lpxp(uuruv '0(55 read/write address a7 h value after reset 0000 h recommended value 0003 h . dmerr(15:0) holds the global merr threshold for the pm data collection in downstream direction. a br cell carrying a block error result bler value greater than merr denotes a severely errored block. accordingly the secb counter is incremented. if bler is less or equal merr the bler value is added to the error counter errc. 3;%( data sheet 3-73 04.2000 5hjlvwhu'hvfulswlrq 6fdq5hjlvwhuv the scan performs the oam functions ais, rdi and cc for all connections. it must be triggered by the microprocessor in 500 ms intervals. the scan procedure goes through all requested entries of the external connection memory, reads the data and writes back updated information. e.g. the scan checks if user cells has been received, increments counters and accordingly performs transitions in the ais/rdi/cc state diagrams. also ais/rdi/cc cell insertion is done by the scan. the scan starts with the lower lci bound programmed by the user and ends at the higher lci bound. if for a connection a cell is to be inserted the scan halts the user cell stream for one cell cycle. the user cells are buffered intermediately (see iljxuh 12). a scan cycle of one lci lasts 32 clock cycles like a cell access. it uses idle times, i.e. it is initiated if no complete cell is available in the input utopia buffer. hence a certain number of idle cell cycles is needed by the scan to do its work. the idle cell cycles can be calculated from the difference between the sum of phy payload rates and the maximum cell processing rate of the pxb 4340 aop. 7deoh shows some example values for scan period times as a function of phy payload rates. it can be seen that 673 mbit/s is the highest possible aggregate phy payload rate if 16 k connections are used. the scan periods in 7deoh are minimum values, as additional idle cycles occur if the phys user cell rate is below 100%. a typical link load value is <100%. the spare bandwidth is used for oam cell insertion and microprocessor accesses to the external rams. while the scan mechanism processes the entries of all connections the dma function can be activated. the read value of one specified dword of each entry can be transferred to the microprocessor via a 32-entry dma buffer. the occupied dma buffer is signalled to the microprocessor via the mpdreq pin. also selected bits of the specified dma entry can be overwritten during the dma process, e.g. to clear state transition flags. with the compressed dma option a special dword with a collection of state transition and status flags is transferred to the dma buffer during the scan. this option allows to check the status of all connections rapidly. 1rwh 7kh 6&$1 uhjlvwhuv duh zulwh surwhfwhg gxulqj wkh 6&$1 phfkdqlvp lv uxqqlqj 6&67$76&$1b$&7 ?? 7deoh 6&$1shulrgvirudfruhforfnri0+] 6xpri3+<sd\ordg udwhv &hoof\fohvxvhgiru xvhufhoov &hoof\fohvdydlodeoh iru6&$1 0lqlpxp6&$1 shulrgiru frqqhfwlrqv 600 mbit/s 1.415 mcells/s 204 906 cycles/s 80 ms 625 mbit/s 1.474 mcells/s 145 943 cycles/s 112 ms 650 mbit/s 1.533 mcells/s 86 981 cycles/s 188 ms 673 mbit/s 1.587 mcells/s 32 768 cycles/s 500 ms 687 mbit/s 1.620 mcells/s 0 not possible 3;%( data sheet 3-74 04.2000 5hjlvwhu'hvfulswlrq '0$:ulwh5hjlvwhu ':'5/ read/write address b0 h value after reset 0000 h '0$:ulwh5hjlvwhu ':'5+ read/write address b1 h value after reset 0000 h dwdrl(15:8) dwdrl(7:0) dwdrl(15:0) dma write register(15:0), specifies the lower 16-bit of the dword to be written into the external connection ram via dma. the bit positions to be overwritten in the connection ram dword are specified with the associated mask register dmrl, the dword of the ram entry is selected by dconf.index. sp dwdrh(14:8) dwdrh(7:0) sp select parity: if sp=0 the correct parity is generated when the dword is transferred to the external ram; if sp=1 a false parity bit is generated. dwdrh(14:0) dma write register(31:16), specifies the upper 16-bit of the dword to be written into the external connection ram via dma. the bit positions to be overwritten in the connection ram dword are specified with the associated mask register dmrl, the dword of the ram entry is selected by dconf.index. 3;%( data sheet 3-75 04.2000 5hjlvwhu'hvfulswlrq '0$0dvn5hjlvwhu '05/ read/write address b2 h value after reset 0000 h '0$0dvn5hjlvwhu+ljk '05+ read/write address b3 h value after reset 0000 h dmrl(15:8) dmrl(7:0) dmrl(15:0) dma mask register(15:0): 0 bit is unchanged. 1 bit is replaced by corresponding dwdr-bit, used for rmw operation on external ram word selected by dconf.index. dmrh(15:8) dmrh(7:0) dmrh(15:0) dma mask register(31:16): 0 bit is unchanged. 1 bit is replaced by corresponding dwdr-bit, used for rmw operation on external ram word selected by dconf.index. 3;%( data sheet 3-76 04.2000 5hjlvwhu'hvfulswlrq 3+<(uuru,qglfdwlrq 3+<(55/ read/write address b4 h value after reset 0000 h 3+<(uuru,qglfdwlrq 3+<(55+ read/write address b5 h value after reset 0000 h phyerrl(15:8) phyerrl(7:0) phyerrl(15:0) these bits have a one-to-one correspondence with the phys that are connected to the switch port. in case of an interruption of the physical transmission (e.g. laser failure) the microprocessor sets the respective phyerr bit. the scan mechanism uses this indication together with the phy number stored in each connection entry of the upstream external ram (see vhfwlrq ) to generate ais cells. phyerr bits are used in upstream direction only. unused phyerrl(23:16) phyerrh(23:16) these bits have a one-to-one correspondence with the phys that are connected to the switch port. in case of an interruption of the physical transmission (e.g. laser failure) the microprocessor sets the respective phyerr bit. the scan mechanism uses this indication together with the phy number stored in each connection entry of the upstream external ram (see vhfwlrq ) to generate ais cells. phyerr bits are used in upstream direction only. 3;%( data sheet 3-77 04.2000 5hjlvwhu'hvfulswlrq '0$5hdg5hjlvwhu '0$5 read address b6 h value after reset 0000 h 1rwh 2xwsxwvhtxhqfhri'0$gdwd elwiurpwkhh[whuqdo5$0duhdozd\vrxwsxwdvfrqvhfxwlyhelwzrugv %lwvduhdozd\vorfdwhglqwkhiluvwzruglqwkhvhfrqgzrug +huhe\elwdozd\vlqglfdwhvwkhvrxufh iurpgrzqvwuhdp5$0 iurp8svwuhdp5$0 '0$&rqiljxudwlrq5hjlvwhu '&21) read/write address b7 h value after reset 0000 h dmar(15:8) dmar(7:0) dmar(15:0) dma read register of dma-fifo (32 words deep). the external dma controller has to be programmed to read this address. unused unused dmaen mode index(2:0) 3;%( data sheet 3-78 04.2000 5hjlvwhu'hvfulswlrq 7lph&rqvwdqw5hjlvwhu 6&&21) read/write address b8 h value after reset 0275 h dmaen enable mpdreq output signal: 0 mpdreq is always tristate and mpdack is not evaluated. 1 mpdreq gets low impedance if dma is requested, otherwise tristate. mpdreq is mpdack controlled. mode selects standard dma or compressed dma 0 standard dma: 32 bit rmw operation on dword of lci entry selected with index(2:0) using dwdr and dmr. 1 compressed dma: 32 bit rmw operation on all interrupt relevant flags in lci entry, no influence of dwdr, for bit mapping see vhfwlrq 4.1.6.1. index(2:0) selects which word (0..7) in the lci table is object of the rmw operation of standard dma. index is dont care in compressed mode (mode=1). unused maxts(1:0) maxtr(3:0) ccdefmax(3:0) maxts(1:0) time for generation of cc cells if no user cell has arrived in the cc generation. counted in multiples of scan cycles (typ. 500 ms). maxtr(3:0) time for transition from normal operation to loc defect state in the cc evaluation. counted in multiples of scan cycles (typ. 500 ms). ccdefmax(3:0) time for transition from loc defect to loc failure state in the cc evaluation. counted in multiples of scan cycles (typ. 500 ms). 3;%( data sheet 3-79 04.2000 5hjlvwhu'hvfulswlrq 7lph&rqvwdqw5hjlvwhu 6&&21) read/write address b9 h value after reset 0057 h 1rwh 7khw\slfdoydoxhiruwkh6&$1f\fohshulrglvpv 7lph&rqvwdqw5hjlvwhu 6&&21) read/write address ba h value after reset 002d h f4f5 prop unused unused idlemax(2:0) ardefmax(3:0) f4f5prop control forced ais/rdi cell generation (arins bit in external ram) behaviour at f4tep: 0 generate f4rdi only if arins is set. 1 generate f4rdi and f5ais for all included vccs if arins is set. idlemax(2:0) time for transition from ais defect/failure to normal operation or from rdi defect/failure to normal operation. counted in multiples of scan cycles. ardefmax(3:0) time for transition from ais defect to ais failure state or rdi defect to rdi failure state. counted in multiples of scan cycles. scptol(5:0) scp(9:8) scp(7:0) scptol(5:0) scan cycle tolerance: (maximum time - minimum time) for complete processing of 1 lci counted in cell cycles). 1rwh 6&3pxvweh!iru6&372/xvdjh scp(9:0) scan cycle period: minimum time for processing of 1 lci counted in cell cycles; necessary for equal distribution of oam cells over 1 scan cycle, avoids oam bursts generated by scan). 0 disables scan. 3;%( data sheet 3-80 04.2000 5hjlvwhu'hvfulswlrq 6&$1&rppdqg5hjlvwhu 6&&21) read/write address bb h value after reset 0000 h /rzhu%rxqgdu\ri/&,5dqjh 6&&21) read/write address bc h value after reset 0000 h unused dma up oam up unused unused dma dn oam dn start sc dmaup select scan with dma transfer upstream. oamup select scan with oam processing upstream. dmadn select scan with dma transfer downstream. oamdn select scan with oam processing downstream. startsc start scan up- and downstream with the selected processing. this bit is set by the microprocessor every 500 ms. as soon as the scan mechanism is started, this bit is reset to 0. the select bits can be defined with the same write access. the select bits are modified only by the microprocessor. the scan start bit is set by the microprocessor and reset by the aop immediately after the start of the scan. to determine the termination of the scan refer to the scan status register below. unused lcimin(13:8) lcimin(7:0) lcimin(13:0) lower boundary of lci range processed by scan (up- and downstream). 3;%( data sheet 3-81 04.2000 5hjlvwhu'hvfulswlrq 8sshu%rxqgdu\ri/&,5dqjh 6&&21) read/write address bd h value after reset 0000 h 6&$16wdwxv5hjlvwhu 6&67$7 read only address be h value after reset 0000 h unused lcimax(13:8) lcimax(7:0) lcimax(13:0) upper boundary of lci range processed by scan (up- and downstream). unused cgenp dmad oamd utog unused unused cgenp dmad oamd dtog scan act 1 cgenp upstream cell generation pending, internal state for debugging. dmad upstream dma done, internal state for debugging. oamd upstream oam done, internal state for debugging. utog upstream toggle flag, used for vp processing once in a scan cycle. cgenp downstream cell generation pending, internal state for debugging. dmad downstream dma done, internal state for debugging. oamd downstream oam done, internal state for debugging. dtog downstream toggle flag, used for vp processing once in a scan cycle. scanact 1 scan mechanism was started and has not yet finished. 1rwh 7kh?vfdqilqlvkhg?frqglwlrqlv 6&$1$&7 ??dqg6&&2167$576& ?? 3;%( data sheet 3-82 04.2000 5hjlvwhu'hvfulswlrq &xuuhqwo\3urfhvvhg/&, 6&67$7 read only address bf h value after reset 8000 h 1rwh ,qdssolfdwlrqv6&$1kdvwrehvwduwhge\wkh?3hyhu\pvwkhwlphvjlyhqkhuhduh edvhgrqwklvwlplqj,qwkh+:wkhvhwwlqjvderyhuhsuhvhqw?1xpehuri6&$1f\fohv? )ruwhvw6&$1pd\ehvwduwhglqduelwudu\wlphshulrgv ,qwhuuxswdqg,qwhuuxsw0dvn5hjlvwhuv interrupt bits signal unpredictable events to the controlling microprocessor, e.g. errors. each interrupt bit signals a different event. events which are associated to a certain connection, as e.g. the misinserted oam cell interrupt are stored additionally also in the external connection ram under the respective lci entry. if one of these interrupt indications is set the corresponding error might have occured for at least one or more connections. thus the microprocessor has to check all entries of the connection ram dedicated to the respective direction for the indicated error. to clear interrupt bits the microprocessor must write a 1 to the respective bit. writing a 0 has no effect. this behaviour simplifies interrupt management by separate interrupt routines. after a hw interrupt more than one interrupt bit might be set. then each interrupt routine can clear the respective bit separately after having checked or corrected the interrupt cause. de df lcis(13:8) lcis(7:0) de dma buffer empty = 0 words in fifo. df dma buffer full 3 32 words in fifo. lcis(13:0) currently processed lci up- and downstream. internal state for debugging. 3;%( data sheet 3-83 04.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw6wdwxv5hjlvwhu ,65 read/write address d0 h value after reset 0000 h bit 15 uuped utopia parity error detected upstream. bit 14 duped utopia parity error detected downstream. bit 13 uusoce utopia start of cell or cell length error detected upstream. bit 12 dusoce utopia start of cell or cell length error detected downstream. bit 11 uedcer crc-10 error detected in oam cell in upstream direction. this error indication is also stored in dword2, bit 13 in the upstream connection ram entry of the respective lci (see vhfwlrq 3.9.1.3). bit 10 dedcer crc-10 error detected in oam cell in downstream direction. this error indication is also stored in dword2, bit 13 in the downstream connection ram entry of the respective lci (see vhfwlrq 3.9.3.3). bit 9 rxcel indicates a non-empty receive buffer. it is cleared automatically after 27 read accesses of the rxrcel register, i.e. after read-out of a complete cell. if further cells are in the receive buffer this bit is set again immediately. bit 8 rxov indicates an overflow of the receive buffer; is set if at least one cell has been discarded due to a full receive cell buffer. bit 7 ocif bit ocif is set if ? an oam cell generated by the scan could not be inserted in downstream direction; ? br or fm cells could not be inserted in downstream direction; ? "central control" loopback of lb cells could not be performed because insertion in downstream direction was not possible; ? fm cells transformed to br cells could not be inserted in downstream direction; this bit is the or function result of all bits of cifl and cifh registers. 1rwh :ulwlqjd??wrelw2&,)zloodovruhvhwuhjlvwhuv&,)/dqg&,)+ bit 6 is set if an oam cell generated by the scan could not be inserted in upstream direction. this occurs if during the insertion window defined in register scconf2 the upstream internal 32-cell buffer filling was constantly beyond the insertion threshold defined in register oamthru. bit 5 dutbo utopia transmit-buffer overflow downstream. 3;%( data sheet 3-84 04.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw6wdwxv5hjlvwhu ,65 read/write address d1 h value after reset 0000 h bit 4 dberr dma buffer overflow or underflow. (bit 3..0) these bits indicate important transitions of ais, rdi or cc state diagrams (see )ljxuhv 17, 18 and 22) for any connection with the respective functionality enabled. these are collection interrupts of the respective connection specific flags in the external ram: bit 3 dcsttr downstream vc-related state transition occurred, i.e. one of the bits 14..19 of dword2 in downstream external ram entry set (see vhfwlrq 3.9.3.3). bit 2 ucsttr upstream vc-related state transition occurred, i.e. one of the bits 14..19 of dword2 in upstream external ram set (see vhfwlrq 3.9.1.3). bit 1 dpsttr downstream vp-related state transition occurred, i.e. one of the bits 22..27 of dword4 in downstream external ram set (see vhfwlrq 3.9.4.1). bit 0 upsttr upstream vp-related state transition occurred, i.e. one of the bits 22..27 of dword4 in upstream external ram set (see vhfwlrq 3.9.2.1). bit 15:9 unused bit 8 sctout time-out for scan processing within scp. bit 7 upstream loopback cell discarded. bit 6 downstream loopback cell discarded. bit 5 cell received for an invalid connection (vcon=0) upstream. vcon is bit19 in dword0 of upstream ram (see vhfwlrq 3.9.1.1). bit 4 cell received for an invalid connection (vcon=0) downstream. vcon is bit19 in dword0 of downstream ram (see vhfwlrq 3.9.3.1). bit 3 ram-parity error occurred upstream. bit 2 ram-parity error occurred downstream. bit 1 uoamis mis-inserted oam cell detected upstream. this indication is also stored per connection in bit 12 of dword2 in the upstream external ram. bit 0 doamis mis-inserted oam cell detected downstream. this indication is also stored per connection in bit 12 of dword2 in the downstream external ram. 3;%( data sheet 3-85 04.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw0dvn5hjlvwhu ,05 read/write address d2 h value after reset 0000 h ,qwhuuxsw0dvn5hjlvwhu ,05 read/write address d3 h value after reset 0000 h &hoo,qvhuwlrq)dxow5hjlvwhuorzdqgkljk &,)/dqg&,)+ /rz read address d4 h value after reset 0000 h imr0(15:8) imr0(7:0) imr0(15:0) interrupt mask register for isr0: 0 setting of corresponding bit in isr0 does not activate the interrupt pin mpint . 1 setting of corresponding bit in isr0 activates mpint . unused imr1(8) imr1(7:0) imr1(8:0) interrupt mask register for isr1: 0 setting of corresponding bit in isr1 does not activate the interrupt pin mpint . 1 setting of corresponding bit in isr1 activates mpint . cif(15:8) cif(7:0) 3;%( data sheet 3-86 04.2000 5hjlvwhu'hvfulswlrq +ljk read address d5 h value after reset 0000 h unused cif(23:16) cif(23:0) for the respective port 15..0 in downstream direction an oam cell could not be inserted. this occurs during the scan process if between consecutive lcis there is no opportunity to insert the required oam cell. oam cells are not inserted if the filling level of the respective qeue exceeds the threshold specified in the oamthrd register. the indication may also be generated for any of the following reasons: ? br or fm cells could not be inserted in downstream direction; ? "central control" loopback of lb cells could not be performed because insertion in downstream direction was not possible; ? fm cells transformed to br cells could not be inserted in downstream direction; bit ocif in register isr0 is the or function result of all bits of cifl and cifh registers. 1rwh :ulwlqjd??wrelw2&,)lquhjlvwhu,65zloodovruhvhwuhjlvwhuv &,)/dqg&,)+ 3;%( data sheet 3-87 04.2000 5hjlvwhu'hvfulswlrq 8723,$,qwhuidfh5hjlvwhuv 8723,$&rqiljxudwlrq5hjlvwhu 87&21) read/write address e0 h value after reset 0000 h this register configures the atm side utopia interfaces. unused unused uta16 utapar unused utaconf(1:0) bit (15:5) unused uta16 select 8- or 16-bit utopia data bus 0 8 bit data bus at atm side. 1 16 bit data bus at atm side. utapar enables/disables parity check 0 dont check parity of atm receive data. 1 check parity of atm receive data. bit (2) unused utaconf(1:0) configuration of mode at atm side : 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 utopia level 1 (4 x 1 port) 3;%( data sheet 3-88 04.2000 5hjlvwhu'hvfulswlrq 8723,$&rqiljxudwlrq5hjlvwhu 87&21) read/write address e1 h value after reset 0000 h this register configures the phy side utopia interfaces and the defines the lci location. unused lcimod(1:0) unused utp16 unused utppar utpconf(1:0) bit(15:10) unused lcimod(1:0) position of lci up/downstream: 00 lci(13:12) = udf(7:6), lci(11:0) = vpi(11:0) 01 lci(13:12) = 00, lci(11:0) = vpi in this mode no icc possible. 10 lci(13:0) = vci(13:0) f4-oam/user-flow not supported. 11 is not allowed, will be handled as 10. bit(7:5) unused utp16 select 8- or 16-bit utopia data bus 0 8 bit data bus at phy side. 1 16 bit data bus at phy side. bit(3) unused utppar enables/disables parity check 0 dont check parity of phy receive data. 1 check parity of phy receive data. utpconf(1:0) configuration of mode at phy side : 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 utopia level 1 (4 x 1 port) 3;%( data sheet 3-89 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp3ruw(qdeohorzdqgkljk 8357(1/dqg8357(1+ /rz read/write address e2 h value after reset 0000 h +ljk read/write address e3 h value after reset 0000 h 'rzqvwuhdp3ruw(qdeohorzdqgkljk '357(1/dqg'357(1+ /rz read/write address e4 h value after reset 0000 h uporten(15:8) uporten(7:0) unused uprten(23:16) bit(15:8) unused uprten(23:16) 0 disables utopia port upstream. 1 enables utopia port upstream. dprten(15:8) dprten(7:0) 3;%( data sheet 3-90 04.2000 5hjlvwhu'hvfulswlrq +ljk read/write address e5 h value after reset 0000 h 2$0&hoo,qvhuwlrq7kuhvkrog8svwuhdp 2$07+58 read/write address e6 h value after reset 001e h unused dprten(23:16) bit(15:0) unused in high word only dprten(23:0) 0 disables utopia port downstream. 1 enables utopia port downstream. unused unused oamthru(5:0) oamthru(5:0) threshold for forced oam cell insertion in upstream direction. if the upstream 32-cell buffer is filled beyond this level oam cells are inserted with lower priority than user cells. recommended value 30 (1e h ). 0 oam cell insertion upstream only possible if no cell from utopia is received. 1..31 cell insertion has higher priority until filling level of upstream 32-cell buffer reaches this threshold. >31 oam cells are always inserted with higher priority (in case of 32-cell buffer overflow backpressure to phy). 3;%( data sheet 3-91 04.2000 5hjlvwhu'hvfulswlrq 2$0&hoo,qvhuwlrq7kuhvkrog'rzqvwuhdp 2$07+5' read/write address e7 h value after reset 0060 h %dfnsuhvvxuh7kuhvkrog'rzqvwuhdp %37+5' read/write address e8 h value after reset 0060 h unused unused oamthrd(6:0) oamthrd(6:0) threshold for forced oam cell insertion in downstream direction. if a queue of the downstream shared buffer is filled beyond this level oam cells destined to the respective phy are not inserted. 0 no cell insertion downstream possible. 1...95 cell insertion is possible until queue filling level reaches threshold. >95 cell insertion downstream only limited by buffer overflow condition. unused unused bpthrd(6:0) bpthrd(6:0) queue backpressure level in downstream direction. if a queue exceeds this threshold the downstream receive utopia interface does not accept any more cell: 0 always backpressure to downstream receive utopia interface for all ports. 1...95 backpressure to the respective phy of the downstream receive utopia interface if queue filling level reaches threshold. >95 queue specific backpressure disabled, backpressure controlled by shared buffer overflow only. (recommended value is 65.) 3;%( data sheet 3-92 04.2000 5hjlvwhu'hvfulswlrq 0lvfhoodqhrxv5hjlvwhuv 5$07\sh6hohfw5hjlvwhu 0,6& read/write address f0 h value after reset 0000 h 7hvw5hjlvwhu 7(675 read/write address f1 h value after reset 0000 h unused unused ramsel(1:0) swres ramsel(1:0) selects the type of ram used for upstream and downstream external connection ram. 00 1 mbit external ram. 01 2 mbit external ram. swres sw-reset. if set to one the internal reset cycle is executed. unused unused tint loopud loopdu 3;%( data sheet 3-93 04.2000 5hjlvwhu'hvfulswlrq 7hvw5hjlvwhu 7(675 read/write address f2 h value after reset 0000 h reserved for device test only. dont write. unused(15:3) tint test of interrupt. 0 normal operation, test of interrupts is disabled. 1 interrupt generation test mode: normal interrupt generation is disabled; interrupt test procedure is controlled by consecutive write accesses to register rxrcel (offset address: 9d h ): 1. write: will set bit isr0(0) 2. write: will set bit isr0(1) ... ... 10. write: will 127 set bit isr0(9) 1rwh 7klvlqwhuuxswvwdwxvelwlvdqh[fhswlrqdqgfdqqrw ehwhvwhge\wklvsurfhgxuh 11. write: will set bit isr0(10) ... ... 16. write: will set bit isr0(15) 17. write: will set bit isr1(0) ... ... 32. write: will set bit isr1(15) bit tint has to be set to 0 to re-enter normal operation. loopud 1 enable testloop up-to-downstream. loopdu 1 enable testloop down-to-upstream. 3;%( data sheet 3-94 04.2000 5hjlvwhu'hvfulswlrq 9huvlrq5hjlvwhuorzdqgkljk 9(5/dqg9(5+ /rz read address f3 h value after reset a06d h +ljk read address f4 h value after reset 523b h 1rwh 7khvhduhwkh,'elwvriwkherxqgdu\vfdqvhtxhqfh 01010010001110111010000001101101 verh verl 3;%( data sheet 3-95 04.2000 5hjlvwhu'hvfulswlrq %,670rgh5hjlvwhu/rz %,670/ read/write address f5 h value after reset 0000 h %,670rgh5hjlvwhu+ljk %,670+ read/write address f6 h value after reset 0000 h rxr ncp uttxd3 uttxd2 uttxd1 utrxd uttxu utrxu bit coding(1:0) selects the bist function. 00 bist inactive, normal operation mode. 01 test of bist circuit. 10 start bist. 11 diagnose mode (not used). rxr select bist function for receive buffer ncp select bist function for cell processing ram uttxd1..3 select bist function for utopia downstream transmit (shared) buffer 1..3 utrxd select bist function for utopia downstream receive buffer uttxu select bist function for utopia upstream transmit buffer utrxu select bist function for utopia upstream receive buffer pmdc6 pmdc5 pmdc4 pmdc3 pmdc2 pmdc1 pmdc0 pmain 3;%( data sheet 3-96 04.2000 5hjlvwhu'hvfulswlrq %,67'rqh5hjlvwhu %,67'1 read address f7 h value after reset 0000 h the 16 bits of this register have a one-to-one correspondence with internal ram blocks. these bits are set by the aop if the respective bist is completed. all bits are reset by any write to the bisterr register. after completion of a bist the aop must be reset. bit coding(1:0) selects the bist function. 00 bist inactive, normal operation mode. 01 test of bist circuit. 10 start bist. 11 diagnosis mode (not used). pmdc6..0 select bist function for pm data collection ram part 6..0 pmain select bist function for pm main ram bit 15..9 bist of pmdc6..0 ram block is completed bit 8 bist of pmain ram is completed bit 7 bist of rxr buffer is completed bit 6 bist of ncp ram is completed bit 5..3 bist of utopia downstream ram block 3..1 is completed bit 2 bist of utopia downstream receive buffer is completed bit 1 bist of utopia upstream transmit buffer is completed bit 0 bist of utopia receive upstream buffer is completed 3;%( data sheet 3-97 04.2000 5hjlvwhu'hvfulswlrq %,67(uuru5hjlvwhu %,67(55 read address f8 h value after reset 0000 h the 16 bits of this register have a one-to-one correspondence with internal ram blocks. these bits are set if during bist execution an error occured in the respective ram block. bit 15..9 bist of pmdc6..0 ram block is faulty bit 8 bist of pmain ram is faulty bit 7 bist of rxr buffer is faulty bit 6 bist of ncp ram is faulty bit 5..3 bist of utopia downstream ram block 3..1 is faulty bit 2 bist of utopia downstream receive buffer is faulty bit 1 bist of utopia upstream transmit buffer is faulty bit 0 bist of utopia receive upstream buffer is faulty 3;%( data sheet 3-98 04.2000 5hjlvwhu'hvfulswlrq ([whuqdodqg,qwhuqdo5$0 8svwuhdp([whuqdo5$0)(qwu\ 'zrugv 8svwuhdp)2$0(qwu\ 'zrug dword 3 31 30 29 28 cedcid(6:0) csdcid(6:0) cpmtid(6:0) cpmoid(6:0) 2 31 ctsdcid(6:0) 19 18 17 16 15 14 13 12 11..7 6 5 4 3..0 131 30..15 14131211109876543210 0 31302928272625242322212019 lci2(13:0) pn(4:0) bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 cpmten enable a terminating f5 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier cpmtid in dword3. bit 29 cpmoen enable an originating f5 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier cpmoid in dword3. bit 28 clbs f5 loopback state according to i.610. should be set before inserting a lb cell, cleared after reception of the looped cell. bit 27 csrciden loopback of f5 lb cells using lb source id 1 enabled. normally this bit is =0 as the location id is used to detect intra-domain lb cells. bit 26 clociden loopback of f5 lb cells using lb location id 1 enabled. normally this bit is =1 as according to the standard the location id is used to detect intra-domain lb cells bit 25 acdeac treatment of activation/deactivation cells at their destination points: 0 discard (if activation/ deactivation function is not used) 1 extract to receive buffer (if activation/ deactivation is supported) 3;%( data sheet 3-99 04.2000 5hjlvwhu'hvfulswlrq bit 24 disf5 0 enable f5 processing, default. 1 disable f5 processing. all f5 oam cells are discarded. bit 23 ctsp 0 no f5 terminating segment point. 1 f5 terminating segment point. do not adjust at f5 oep. bit 22 cosp 0 no f5 originating segment point. 1 f5 originating segment point. bit 21 unused it is recommended to initialize with 0. bit 20 cip 0 f5 originating end point (oep). 1 f5 intermediate point. bit 19 vcon 0 connection not activated, cells for this lci are discarded. 1 connection activated. lci2(13:0)18..5 pointer to the vp connection data of the actual vcc. f4 pointer in iljxuh . meaning of bits 18..5 depends on bit field lcimod in register utconf1. pn(4:0)4..0 phy number associated with this lci. used for phy specific ais generation (see p register phyerr). 3;%( data sheet 3-100 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0(qwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30..15 initialize to 0 at connection setup. do not change by p in normal operation. bit 14 ciccen 1 enable internal continuity check, originating icc in upstream direction. set to 0 if icc is not used. bit 13 csccten 1 terminate a f5 segment continuity check. should only be enabled at a f5 tsp (ctsp=1). bit 12 reserved, set to 0. bit 11 csccoen 1 originate a f5 segment continuity check flow. should only be enabled at a f5 osp (cosp=1). bit 10 ceccoen 1 originate a f5 end-to-end continuity check flow. should only be enabled at a f5 oep (cip=0). bit 9 crdimen 0 f5 rdi monitoring disabled. 1 f5 rdi monitoring enabled. state transition to rdi failure state and out of rdi failure state is reported by use of the p interrupt ucsttr. bit 8 caismen 0 f5 ais monitoring disabled. 1 f5 ais monitoring enabled. state transition to ais failure state and out of ais failure state is reported by use of the p interrupt ucsttr. bit 7 cccmen 0 f5 cc monitoring disabled. 1 f5 cc monitoring enabled. state transition to loc failure state and out of loc failure state is reported by use of the p interrupt ucsttr. 3;%( data sheet 3-101 04.2000 5hjlvwhu'hvfulswlrq bit 6 carien 0 f5 ais cell insertion disabled. 1 f5 ais cell insertion enabled. independent on the reason for cell generation (forced insertion by arins, physical error by p register phyerr, detected loc or ais state) ais/rdi cell generation is always controlled by this flag. used e.g. to suppress rdi at endpoints of multicast connections. bit 5 clocfai f5 loc failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 4 clocdef f5 loc defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 3 crdifai f5 rdi failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 2 crdidef f5 rdi defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 1 caisfai f5 ais failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 0 caisdef f5 ais defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. 3;%( data sheet 3-102 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0(qwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. 30..27 unused it is recommended to initialize with 0. ctsdcid(6:0) identifier for data collection on terminated / intermediate segment f5 br cells. related enable ctsdcen in dword3. bit 19 clocf2n 1 indication for a state transition from f5 loc failure state to f5 loc normal state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with cccmen=1 (dword1). bit 18 clocd2f 1 indication for a state transition from f5 loc defect state to f5 loc failure state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with cccmen=1 (dword1). bit 17 crdif2n 1 indication for a state transition from f5 rdi failure state to f5 rdi normal state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with crdimen=1 (dword1). bit 16 crdid2f 1 indication for a state transition from f5 rdi defect state to f5 rdi failure state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with crdimen=1 (dword1). bit 15 caisf2n 1 indication for a state transition from f5 ais failure state to f5 ais normal state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with caismen=1 (dword1). bit 14 caisd2f 1 indication for a state transition from f5 ais defect state to f5 ais failure state. set by aop, must be cleared by the p. reported with interrupt ucsttr if enabled with caismen=1 (dword1). 3;%( data sheet 3-103 04.2000 5hjlvwhu'hvfulswlrq bit 13 edcerr 1 wrong edc (crc10) in an oam cell detected on this connection. reported with interrupt uedcer. bit 12 oammis 1 mis-inserted oam cell discarded on this connection. reported with interrupt uoamis. bit 11..7 initialize to 0 at connection setup. do not change by p in normal operation. bit 6 cccins 0 default; normal cc cell insertion 1 force insertion of f5 cc cells for all activated cc flows; period determined by maxts in register scconf1. bit 5 initialize to 0 at connection setup. do not change by p in normal operation. bit 4 carins: 1 force insertion of f5 ais cells upstream. cells are generated with every 2nd scan. used e.g. for ais insertion due to vcc performance degrade (determined by pm function). bit 3..0 initialize to 0 at connection setup. do not change by p in normal operation. 3;%( data sheet 3-104 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0(qwu\ 'zrug 8svwuhdp([whuqdo5$0)(qwu\ 'zrugv bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 cedcen enable data collection on f5 end-to-end br cells. related identifier cedcid. bit 29 csdcen enable data collection on f5 segment br cells directly generated from f5 segment fm cells. related identifier csdcid. bit 28 ctsdcen enable data collection on terminated / intermediate f5 segment br cells, related identifier ctspmdcid is in dword2. cedcid(6:0) identifier for data collection on f5 end-to-end br cells. related enable cedcen. csdcid(6:0) identifier for data collection on f5 segment br cells directly generated from f5 segment fm cells. related enable csdcen. cpmtid(6:0) identifier for a terminating f5 segment or end-to-end fm flow. related enable cpmten in dword0. cpmoid(6:0) identifier for an originating f5 segment or end-to-end fm flow. related enable cpmoen in dword0. dword 7 31 ptsdcid(6:0) 6 31 30 29 28 pedcid(6:0) psdcid(6:0) ppmtid(6:0) ppmoid(6:0) 531 30..15 14131211109876543210 4 3130292827262524232221201918171615 13 12..9 8 7 6 5 4..0 3;%( data sheet 3-105 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0hqwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 ppmten enable a terminating f4 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier ppmtid in dword6. bit 29 ppmoen enable an originating f4 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier ppmoid in dword6. bit 28 initialize to 0 at a connection setup. do not change by p in normal operation. bit 27 plocf2n 1 indication for a state transition from loc failure state to loc normal state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with pccmen=1 in dword5. bit 26 plocd2f 1 indication for a state transition from loc defect to loc failure state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with pccmen=1 in dword5. bit 25 prdif2n 1 indication for a state transition from ais failure to ais normal state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with prdimen=1 in dword5. bit 24 prdid2f 1 indication for a state transition from ais defect to ais failure state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with prdimen=1 in dword5. bit 23 paisf2n 1 indication for a state transition from ais failure to ais normal state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with paismen=1 in dword5. 3;%( data sheet 3-106 04.2000 5hjlvwhu'hvfulswlrq bit 22 paisd2f 1 indication for a state transition from ais defect to ais failure state. set by aop, must be cleared by the p. reported with interrupt upsttr if enabled with paismen=1 in dword5. bit 21 plbs f4 loopback state according to i.610. should be set before inserting a lb cell, cleared after reception of the looped cell. bit 20 vpcchk vpci consistency check. if set indicates that a lb cell has been looped. bit 19 psrciden loopback of f4 lb cells using lb source id 1 enabled. normally this bit is =0 as the location id is used to detect intra-domain lb cells. bit 18 plociden loopback of f4 lb cells using lb location id 1 enabled. normally this bit is =1 as according to the standard the location id is used to detect intra-domain lb cells. bit 17 disf4 0 enable f4 processing, default. 1 disable f4 processing. all f4 oam cells are discarded. option selected e.g. at aal interworking point. bit 16 ptsp 0 no f4 terminating segment point. 1 f4 terminating segment point. bit 15 posp 0 no f4 originating segment point. 1 f4 originating segment point. do not adjust at f4 tep. bit 13 pip 0 f4 terminating end point (tep). 1 f4 intermediate point. bit 12..9 initialize to 0 at connection setup. do not change by p in normal operation. bit 8 pccins 1 force insertion of f4 cc cells for all activated cc flows; period determined by maxts in register scconf1. 3;%( data sheet 3-107 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0(qwu\ 'zrug bit 7 initialize to 0 at connection setup. do not change by p in normal operation. bit 6 parins 1 force insertion of f4 ais cells upstream. used e.g. for ais insertion due to vpc performance degrade (determined by pm function). bit 5 initialize to 1 at connection setup. do not change by p in normal operation. bit 4..0 initialize to 0 at connection setup. do not change by p in normal operation. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30..15 initialize to 0 at connection setup. do not change by p in normal operation. bit 14 piccen 1 enable internal continuity check, in upstream direction originating icc is enabled. bit 13 psccten 1 terminate a f4 segment continuity check. should only be enabled at a f4 tsp (ptsp=0). bit 12 peccten 1 terminate a f4 end-to-end continuity check. should only be enabled at a f4 tep (pip=0). bit 11 psccoen 1 originate a f4 segment continuity check. should only be enabled at a f4 osp (posp=1). bit 10 reserved, set to 0. bit 9 prdimen 0 f4 rdi monitoring disabled. 1 f4 rdi monitoring enabled. state transition to rdi failure state and out of rdi failure state is reported by use of the interrupt upsttr. 3;%( data sheet 3-108 04.2000 5hjlvwhu'hvfulswlrq bit 8 paismen 0 f4 ais monitoring disabled. 1 f4 ais monitoring enabled. state transition to ais-failure state and out of ais-failure state is reported by use of the p interrupt upsttr. bit 7 pccmen 0 f4 cc monitoring disabled. 1 f4 cc monitoring enabled. state transition to loc failure state and out of loc failure state is reported by use of the p interrupt upsttr. bit 6 parien 0 f4 ais/rdi cell insertion disabled. 1 f4 ais/rdi cell insertion enabled. independent of the reason for cell generation (forced insertion by arins, physical error by p register phyerr, detected loc or ais state) ais/rdi cell generation is always enabled with this flag. used e.g. to suppress rdi at endpoints of multicast connections. bit 5 plocfai 1 f4 loc failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 4 plocdef 1 f4 loc defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 3 prdifai 1 f4 rdi failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 2 prdidef 1 f4 rdi defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 1 paisfai 1 f4 ais failure state indication. initialize to 0 at connection setup. do not change by p in normal operation. bit 0 paisdef 1 f4 ais defect state indication. initialize to 0 at connection setup. do not change by p in normal operation. 3;%( data sheet 3-109 04.2000 5hjlvwhu'hvfulswlrq 8svwuhdp)2$0(qwu\ 'zrug 8svwuhdp)2$0(qwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 pedcen enable data collection on f4 end-to-end br cells. related identifier pedcid. bit 29 psdcen enable data collection on f4 segment br cells directly generated from f4 segment fm cells. related identifier psdcid. bit 28 ptsdcen enable data collection on terminated / intermediate f4 segment br cells, related identifier ptsdcid in dword7. pedcid(6:0) identifier for data collection on f4 end-to-end br cells. related enable pedcen. psdcid(6:0) identifier for data collection on f4 segment br cells directly generated from f4 segment fm cells. related enable psdcen. ppmtid(6:0) identifier for a terminating f4 segment or end-to-end fm flow. related enable ppmten in dword4. ppmoid(6:0) identifier for an originating f4 segment or end-to-end fm flow. related enable ppmoen in dword4. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30..7 unused it is recommended to initialize with 0. ptsdcid(6:0) identifier for data collection on terminated / intermediate f4 segment br cells. related enable ptsdcen in dword6. 3;%( data sheet 3-110 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp([whuqdo5$0)(qwu\ 'zrugv 'rzqvwuhdp)2$0(qwu\ 'zrug dword 3 31 30 29 28 cedcid(6:0) csdcid(6:0) cpmtid(6:0) cpmoid(6:0) 2 31 ctsdcid(6:0) 1918171615141312 11..7 6 5 4 3..0 131 30..15 14131211109876543210 0 31302928272625242322 2019 lci2(13:0) pn(4:0) bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 cpmten enable a terminating f5 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier cpmtid in dword3. bit 29 cpmoen enable an originating f5 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier cpmoid in dword3. bit 28 clbs f5 loopback state according to i.610. should be set before inserting a lb cell, cleared after reception of the looped cell. bit 27 csrciden loopback of lb cells using lb source id 1 enabled. normally this bit is =0 as the location id is used to detect intra-domain lb cells. bit 26 clociden loopback of lb cells using lb location id 1 enabled. normally this bit is =1 as according to the standard the location id is used to detect intra-domain lb cells. bit 25 acdeac treatment of activation/deactivation cells at their destination points: 0 discard (if activation / deactivation function is not used) 1 extract to receive buffer (if activation / deactivation is supported) 3;%( data sheet 3-111 04.2000 5hjlvwhu'hvfulswlrq bit 24 disf5 0 enable f5 processing, default. 1 disable f5 processing. all f5 oam cells are discarded. bit 23 ctsp 0 no f5 terminating segment point. 1 f5 terminating segment point. bit 22 cos 0 no f5 originating segment point. 1 f5 originating segment point. do not adjust at f5 tep. bit 20 cip 0 f5 terminating end point (tep). 1 f5 intermediate point. bit 19 vcon 0 connection not activated, cells for this lci are discarded. 1 connection activated. lci2(13:0) pointer to the vp connection data of the actual vcc. f4 pointer in iljxuh ). meaning of bits 18..5 depends on bit field lcimod in register utconf1. pn(4:0) phy number associated with this lci. used for phy specific rdi cell generation. 3;%( data sheet 3-112 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp)2$0(qwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30..15 initialize to 0 at connection setup. do not change by p in normal operation. bit 14 ciccen 1 enable internal continuity check, terminating icc in downstream direction. set to 0 if icc is not used. bit 13 csccten 1 terminate a f5 segment continuity check. should only be enabled at a f5 tsp (ctsp=1). bit 12 ceccten 1 terminate a f5 end-to-end continuity check flow. should only be enabled at a f5 tep (cip=0). bit 11 csccoen 1 originate a f5 segment continuity check flow. should only be enabled at a f5 osp (cosp=1). bit 10 reserved, set to 0. bit 9 crdimen 0 f5 rdi monitoring disabled. 1 f5 rdi monitoring enabled. state transition to asi failure state and out of asi failure state is reported by use of the p interrupt dcsttr. bit 8 caismen 0 f5 ais monitoring disabled. 1 f5 ais monitoring enabled. state transition to ais failure state and out of ais failure state is reported by use of the p interrupt dcsttr. 3;%( data sheet 3-113 04.2000 5hjlvwhu'hvfulswlrq bit 7 cccmen 0 f5 cc monitoring disabled. 1 f5 cc monitoring enabled. state transition to loc failure state and out of loc failure state is reported by use of the p interrupt dcsttr. bit 6 carien 0 f5 ais or rdi cell insertion disabled. 1 f5 ais or rdi cell insertion enabled. independent of the reason for cell generation (forced insertion by arins, detected loc or ais state) ais/rdi cell generation is always controlled by this flag. necessary e.g. to suppress rdi at endpoints of multicast or unidirectional connections. bit 5 clocfai f5 loc failure state. initialize to 0 at connection setup. do not change by p in normal operation. bit 4 clocdef f5 loc defect state. initialize to 0 at connection setup. do not change by p in normal operation. bit 3 crdifai f5 rdi failure state. initialize to 0 at connection setup. do not change by p in normal operation. bit 2 crdidef f5 rdi defect state. initialize to 0 at connection setup. do not change by p in normal operation. bit 1 caisfai f5 ais failure state. initialize to 0 at connection setup. do not change by p in normal operation. bit 0 caisdef f5 ais defect state. initialize to 0 at connection setup. do not change by p in normal operation. 3;%( data sheet 3-114 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp)2$0(qwu\ 'zrug bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. ctsdcid(6:0) identifier for data collection on terminated / intermediate f5 segment br cells. related enable is ctsdcen in dword3. bit 19 clocf2n 1 indication for a state transition from f5 loc failure state to f5 loc normal state. set by aop, reset by the p. reported with interrupt dcsttr if enabled with caismen=1 (dword1). bit 18 clocd2f 1 indication for a state transition from f5 loc defect state to f5 loc failure state. set by aop, reset by the p. reported with interrupt dcsttr if enabled with cccmen=1 (dword1). bit 17 crdif2n 1 indication for a state transition from f5 rdi failure state to f5 rdi normal state. set by aop, reset by the p. reported with interrupt dcsttr if enabled with crdimen (dword1). bit 16 crdid2f 1 indication for a state transition from f5 rdi defect state to f5 rdi failure state. set by aop, reset by the p. reported with interrupt dcsttr if enabled with crdimen=1. (dword1. bit 15 caisf2n 1 indication for a state transition from f5 ais failure state to f5 ais normal state. set by aop, reset by the p.reported with interrupt dcsttr if enabled with caismen=1 (dword1). bit 14 caisd2f 1 indication for a state transition from f5 ais defect state to f5 ais failure state. set by aop, reset by the p. reported with interrupt dcstr if enabled with caismen=1 (dword1). bit 13 edcerr 1 wrong edc (crc10) in an oam cell detected. reported with interrupt dedcer. 3;%( data sheet 3-115 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp)2$0(qwu\ 'zrug bit 12 oammis 1 miss inserted oam cell discarded. reported with interrupt doamis. bit 11..7 initialize to 0 at connection setup. do not change by p in normal operation. bit 6 cccins 0 default, normal cc cell insertion. 1 force insertion of f5 cc cells for all activated cc flows; period determined by maxts in register scconf1. bit 5 initialize to 0 at connection setup. do not change by p in normal operation. bit 4 carins 1 force insertion of f5 ais cells downstream (cip=1). bit 3..0 initialize to 0 at connection setup. do not change by p in normal operation. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 cedcen enable data collection on f5 end-to-end br cells. related identifier cedcid. bit 29 csdcen enable data collection on f5 segment br cells directly generated from f5 segment fm cells. related identifier csdcid. bit 28 ctsdcen enable data collection on terminated / intermediate f5 segment br cells, related identifier ctsdcid in dword2. cedcid(6:0) identifier for data collection on f5 segment br cells. related enable cedcen. csdcid(6:0) identifier for data collection on f5 segment br cells directly generated from f5 segment fm cells. related enable csdcen. cpmtid(6:0) identifier for a terminating f5 segment or end-to-end fm flow. related enable cpmten in dword0. cpmoid(6:0) identifier for an originating f5 segment or end-to-end fm flow. related enable cpmoen in dword0. 3;%( data sheet 3-116 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp([whuqdo5$0)(qwu\ 'zrugv 'rzqvwuhdp)2$0(qwu\ 'zrug dword 7 31 ptsdcid(6:0) 6 31 30 29 28 pedcid(6:0) psdcid(6:0) ppmtid(6:0) ppmoid(6:0) 531 30..15 14131211109876543210 43130292827262524232221201918171615 13 12..9 8765 4..0 bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 ppmten enable a terminating f4 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier ppmtid in dword6. bit 29 ppmoen enable an originating f4 segment or end-to-end fm flow. flow type selected with pmft in pm ram entry. related identifier ppmoid in dword6. bit 28 initialize to 0 at a connection setup. do not change by p in normal operation. bit 27 plocf2n 1 indication for a state transition from loc failure state to loc normal state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with pccmen=1 (dword5). bit 26 plocd2f 1 indication for a state transition from loc defect state to loc failure state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with pccmen=1 (dword5). bit 25 prdif2n 1 indication for a state transition from ais failure state to ais normal state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with prdimen=1 (dword5). 3;%( data sheet 3-117 04.2000 5hjlvwhu'hvfulswlrq bit 24 prdid2f 1 indication for a state transition from ais defect state to ais failure state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with prdimen=1 (dword5). bit 23 paisf2n 1 indication for a state transition from ais failure state to ais normal state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with paismen=1 (dword5). bit 22 paisd2f 1 indication for a state transition from ais defect state to ais failure state. set by aop, reset by the p. reported with interrupt dpsttr if enabled with paismen=1 (dword5). bit 21 plbs f4 loopback state according to i.610. should be set before inserting a lb cell, cleared after reception of the looped cell. bit 20 reserved , set to 0. bit 19 psrciden loopback of lb cells using lb source id: 1 enabled. normally this bit is =0 as the location id is used to detect intra-domain lb cells. bit 18 plociden loopback of lb cells using lb location id 1 enabled. normally this bit is =1 as according to the standard the location id is used to detect intra-domain lb cells. bit 17 disf4 0 enable f4 processing, default. 1 disable f4 processing. all f4 oam cells are discarded. option selected e.g. at aal interworking point. bit 16 ptsp 0 no f4 terminating segment point. 1 f4 terminating segment point. do not adjust at f4 oep. bit 15 posp 0 no f4 originating segment point. 1 f4 originating segment point. 3;%( data sheet 3-118 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp)2$0(qwu\ 'zrug bit 13 pip 0 f4 originating end point (oep). 1 f4 intermediate point. bit 12..9 initialize to 0 at connection setup. do not change by p in normal operation. bit 8 pccins 1 insertion of f4 cc cells for all activated cc flows; period determined by maxts in register scconf1. bit 7 initialize to 0 at connection setup. do not change by p in normal operation. bit 6 parins 1 force insertion of f4 ais cell downstream. bit 5 initialize to 1 at connection setup. do not change by p in normal operation. bit 4..0 initialize to 0 at connection setup. do not change by p in normal operation. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30..15 initialize to 0 at connection setup. do not change by p in normal operation. bit 14 piccen 1 enable internal continuity check, terminating icc in downstream direction. set to 0 if icc is not used. bit 13 psccten 1 terminate a f4 segment continuity check. should only be enabled at a f4 tsp (ptsp=1). bit 12 reserved, set to 0. bit 11 psccoen 1 originate a f4 segment continuity check. should only be enabled at a f4 osp (posp=1). bit 10 peccoen 1 originate a f4 end-to-end continuity check. should only be enabled at a f4 oep (pip=0). 3;%( data sheet 3-119 04.2000 5hjlvwhu'hvfulswlrq bit 9 prdimen 0 f4 rdi monitoring disabled. 1 f4 rdi monitoring enabled. state transition to rdi failure state and out of rdi failure state is reported by use of the p interrupt dpsttr. bit 8 paismen 0 f4 ais monitoring disabled. 1 f4 ais monitoring enabled. state transition to ais failure state and out of ais failure state is reported by use of the p interrupt dpsttr. bit 7 pccmen 0 f4 cc monitoring disabled. 1 f4 cc monitoring enabled. state transition to loc failure state and out of loc failure state is reported by use of the p interrupt dpsttr. bit 6 parien 0 f4 ais/rdi cell insertion disabled. 1 f4 ais/rdi cell insertion enabled. independent of the reason for cell generation (forced insertion by arins, detected loc or ais state) ais cell generation is always controlled by this flag. bit 5 plocfai 1 f4 loc failure state indication. initialize to 0. do not change by p in normal operation. bit 4 plocdef: 1 f4 loc defect state indication. initialize to 0. do not change by p in normal operation. bit 3 prdifai: 1 f4 rdi failure state indication. initialize to 0. do not change by p in normal operation. bit 2 prdidef: 1 f4 rdi defect state indication. initialize to 0. do not change by p in normal operation. bit 1 paisfai: 1 f4 ais failure state indication. initialize to 0. do not change by p in normal operation. 3;%( data sheet 3-120 04.2000 5hjlvwhu'hvfulswlrq 'rzqvwuhdp)2$0(qwu\ 'zrug 'rzqvwuhdp)2$0(qwu\ 'zrug bit 0 paisdef: 1 f4 ais defect state indication. initialize to 0. do not change by p in normal operation. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. bit 30 pedcen enable data collection on f4 end-to-end br cells. related identifier pedcid. bit 29 psdcen enable data collection on f4 segment br cells directly generated from f4 segment fm cells. related identifier psdcid. bit 28 ptsdcen enable data collection on terminated / intermediate f4 segment br cells, related identifier ptsdcid in dword7. pedcid(6:0) identifier for data collection on f4 end-to-end br cells. related enable pedcen. psdcid(6:0) identifier for data collection on f4 segment br cells directly generated from f4 segment fm cells. related enable psdcen. ppmtid(6:0) identifier for a terminating f4 segment or end-to-end fm flow. related enable ppmten in dword4. ppmoid(6:0) identifier for an originating f4 segment or end-to-end fm flow. related enable ppmoen in dword4. bit 31 par dword parity protection. in normal operation write to 0. should always read as 0. ptsdcid(6:0) identifier for data collection on terminated/intermediate f4 segment br cells, related to ptsdcen in dword6. 3;%( data sheet 3-121 04.2000 5hjlvwhu'hvfulswlrq ,qwhuqdo300dlq5$0(qwu\ 'zrugv ,qwhuqdo300dlq5$0(qwu\ 'zrug ,qwhuqdo300dlq5$0(qwu\ 'zrug dword 2 fmdiff(15:0) bl(3:0) ft 8 unused 1 bip16(15:0) mcsnup(7:0) mcsn(7:0) 0 tuc(15:0) tuc0(15:0) bit 31:16 tuc(15:0) total user cell count high and low priority cells (clp0+1). used at originating and terminating point. initialized to all 0 at pm set-up. bit 15:0 tuc0(15:0) total user cell count high priority cells only (clp=0). used at originating and terminating point. initialized to all 0 at pm set-up. bit 31:16 bip16(15:0) bit interleaved parity accumulated over block of user cells. used at originating and terminating point. initialized to all 0 at pm set-up. bit 15:8 mcsnup(7:0) monitoring cell sequence number updated by the last fm cell. used at terminating point only. initialized to all 0 at pm set-up. bit 7:0 mcsn(7:0) monitoring cell sequence number running counter. used at originating and terminating point. initialized to all 0 at pm set-up. 3;%( data sheet 3-122 04.2000 5hjlvwhu'hvfulswlrq ,qwhuqdo300dlq5$0(qwu\ 'zrug bit 31:16 fmdiff(15:0) local tuc minus tuc from incoming fm cell at fm terminating point. fmdiff is not used at fm originating point. initialized to all 0 at pm set- up. bit 15:12 block length encoding. programmed by the microprocessor, read by the aop. bl(3:0) block length 0000 2 0001 4 0010 8 0011 16 0100 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192 1101 16384 1110 32768 1111 65536 bit(11:10) ft(1:0) flow type 00 f4 segment 01 f4 end-to-end 10 f5 segment 11 f5 end-to-end 3;%( data sheet 3-123 04.2000 5hjlvwhu'hvfulswlrq ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrugv ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug bit 9 unused bit 8 bridis 0 backward reporting cell insertion enabled 1 backward reporting cell insertion disabled bit(7:0) unused dword 13 secbmis(31:0) 12 secberr(31:0) 11 tlostc0(31:0) 10 tlostc(31:0) 9impb(31:0) 8 misc(31:0) 7 transuc0(31:0) 6 transuc(31:0) 5 lostc0(31:0) 4lostc(31:0) 3 errc(31:0) 2 31 secb(30:0) 1 tucold(15:0) tuc0old(15:0) 0 trccold(15:0) trcc0old(15:0) trccold(15:0) offset values : used for tucdiff calculation. trcc0old(15:0) offset values : used for tucdiff0 calculation. tucold(15:0) offset values : used for tucdiff/transuc calculation. tuc0old(15:0) offset values : used for tucdiff0/transuc0 calculation. 3;%( data sheet 3-124 04.2000 5hjlvwhu'hvfulswlrq ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug bit 31 fbr set after the 1. br cell, no data collection is done for 1. br cell. secb(30:0) total severely errored cell blocks. errc(31:0) total errored cells. lostc(31:0) total lost cells (clp = 0+1). lostc0(31:0) total lost cells (clp = 0). transuc(31:0) total transmitted user cells (clp = 0+1). transuc0(31:0) total transmitted user cells (clp = 0). misc(31:0) total misinserted cells. impb(31:0) total impaired blocks. tlostc(31:0) total lost cells (clp = 0+1). 3;%( data sheet 3-125 04.2000 5hjlvwhu'hvfulswlrq ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug ,qwhuqdo30'dwd&roohfwlrq5$0(qwu\ 'zrug tlostc0(31:0) total lost cells (clp = 0). secberr(31:0) total severely errored cell blocks due to bit errors. secbmis(31:0) total severely errored cell blocks due to misinserted cells. 3;%( data sheet 4-126 04.2000 2shudwlrq 2shudwlrq 2yhuylhz this section describes the actions to be done by the microprocessor. for this purpose the following network scenario is assumed (see also )ljxuhv dqg for reference): ? the oam functions ais/rdi/cc are always enabled for all connections (although the aop also supports enabling on a per-connection basis). activating the cc function by default avoids use of cc activation/deactivation cells. ? for all time-out values the recommended values of the standard [ ] are used. ? performance monitoring is always initiated by the generating port ( vhh)ljxuh ) using pm activation cells. the respective endpoint loops a cell with activation request confirmed back if a pm processor is available. if all 128 pm processors are in use the activation request denied cell is sent back. the deactivation cell is always confirmed. ? pm data collection is always done on the port where the fm cells are generated, i.e. the br cells are evaluated and discarded there (the aop supports pm data collection on any point along the backward pm cell path). ? segment borders are fixed to transmission lines (although the aop supports the per- connection definition of segment points). ? at originating segment points ais/rdi monitoring for vpcs is enabled, i.e. at the entrance of the network of an operator it is detected if a vpc is received fault-free or not. so the network operator knows at any time the availability of his vpcs. monitoring is not activated for vccs, as these are set-up only temporary. all these assumptions facilitate oam management by reducing the number of parameters to be handled. *xlgholqhviruplfursurfhvvrudfwlrqv :ulwh0rgli\5hdg$ffhvv for a normal read-modify-write access to a ram, the following actions have to be done by the microprocessor : 1. write the data to the write transfer registers wdr0l..wdr13h (see vhfwlrq page 59). 2. set the mask bits in the mask data registers mdr0l..mdr6h and wmask (see vhfwlrq page 60 and vhfwlrq page 61). note that ram words 0..6 are bitwise masked with the mdr registers, ram words 7..13 are masked completely by setting the corresponding bit in register wmask). 3. write the lci to the address register rmwadr (see vhfwlrq page 63). 4. set the following bits in the read-modify-write control register rmwc (see vhfwlrq page 62) : bits 5..4 (e.g. to 01 for external ram), bit 2 equal to 1 for upstream or equal to 0 for downstream and bit 3 epual to 1, i.e. start of rmw. 5. the rmw is done when bit 3 of rmwc is set to 0 by the aop. 6. read the read transfer registers rdr0l..rdr13h (see vhfwlrq page 60). rmw access on pm or dc ram is the same as for the external ram, besides that rmwadr should have a value between 0 and 127 and for pmmain only registers wdr0l..wdr2h, rdr0l..rdr2h, mdr0l..mdr2h are used. the entries 0..3 will be written to address lci defined by register rmwadr, the entries 4..7 to address lci2 defined in entry 0. note, that read 3;%( data sheet 4-127 04.2000 2shudwlrq data from a former rmw cycle is lost during write-only-access (bit 0 of register rmwc equal to 1). during read or modify the external ram parity-check will be done. while rmw is active, the registers rmwc and rmwadr are writeprotected. &hoolqvhuwlrqe\wkhplfursurfhvvru when the microprocessor should insert cells, e.g. pm or cc, follow this guideline : 1. write the cell data into the transmit cell payload registers txr0..26 (see vhfwlrq page 67 and vhfwlrq page 68). 2. if the cell is to be inserted in downstream direction set bit 0 of the transmission command register tmcr (see vhfwlrq page 69). otherwise set bit 1 (for upstream direction). if both bits are set to 1, the aop reacts in the same way as if only bit 1 is set. 3. after the insertion of the microprocessor cell into the datastream, the choosen bit in register tmcr will be reset by the aop. 5hdglqjriduulyhgfhoove\wkhplfursurfhvvru if a cell arrives at the aop, the microprocessor must perform the following operations : 1. the aop signals the availability of arrived cells by setting bit 9 of the interrupt register isr0 (see vhfwlrq page 83). 2. the microprocessor has to read the receive cell register rxrcel for 27 times. 3. bit 6 of the udf2 octed will indicate the source of the arrived cell (0 = downstream). 4. after the 27th read access the aop will reset bit 9 of isr0. the cell will be read in the same order as the transmit cell, i.e. address 80 to 9c. 6&$1xvdjh here is an example for the usage of the scan. 1. setup the connections in the external ram using rmw. 2. for general adjustement of the scan procedure, the microprocessor has to write the first lci to be processed into register scconf4 (see vhfwlrq page 80) and the last lci to be processed into register scconf5 (see vhfwlrq page 81). write the values for scp and scptol into register scconf2 (see vhfwlrq page 79 and vhfwlrq page 48). further some adjustments for dma are needed when use of dma is intended. set bit 3 of the dma configuration register dconf (see vhfwlrq page 77) to the respective value for normal or compressed mode. additionally write the index value to the same register (bit 2..0). write dma data to registers dwdrl and dwdrh (see vhfwlrq page 74 and vhfwlrq page 74) and the rmw mask to registers dmrl and dmrh (see vhfwlrq page 75 and vhfwlrq page 75). at last adjustments for the oam are needed when use of oam is intended. herefore setup the counter limits for state transitions in the registers scconf0 and scconf1 (see vhfwlrq page 78 and vhfwlrq page 79). 3. the scan mechanism is started by the following actions. write respective settings to the scan command register scconf3 (see vhfwlrq page 80). the scan is started by setting bit 0. this bit is reset as soon as the scan mechanism is started internally. 4. the scan is finished when the start bit is reset and bit 0 of the scan status register is equal to 0 (see vhfwlrq page 81). the registers in the scan block are write protected during the scan operation. 3;%( data sheet 4-128 04.2000 2shudwlrq ,qlwldol]dwlrqdqg7hvw these are the actions to be performed after reset to prepare the aop for operation. ? check reset values of all registers ? set hw configuration (ram type, utopia configuration) ? initialize internal and external rams for this purpose the dma feature of the chip could be used. ? test parity detectors ? check data path (via adjacent atm devices) &rqiljxudwlrq the following parameters must be known by the microprocessor for the operation of the aop: ? number of phys ? edge-of-the-network or intra-network point for each phy ? switch port id for intra-network loopback ? number of supported connections ? thresholds for pm data collection values ? use of internal cc function or not. 6hwxs &ohdugrzqri&rqqhfwlrqv for a connection setup the following parameters are required: ? local connection identifier lci ? vpc or vcc ? if vcc the lci2 value of the associated vp-entry (vp-pointer) ? vcc endpoint indication (at aal function) ? phy number all further programming is done using the edge-of-the-network or intra-network configuration of the phy (for the abbreviations see 6hfwlrq ): ? in case of a vcc the upstream part of the aop is configured as vp-tep and the downstream part as vp-oep. if in addition the phy is configured as edge of a network the upstream part is configured as vc-osp and the downstream part as vc-tsp. ? in case of a vpc without a segment border both up- and downstream parts are configured as intermediate point (vp-ip). if the phy is configured as edge of the network the upstream part is configured as vp-osp and the downstream part as vp-tsp. 1rwh ,id3+<lvdwwkhhgjhridqhwzrunlwvwudqvplvvlrqolqhlvfrqqhfwhgwrwkhqhwzrunridqrwkhurshudwru +hqfhdoovhjphqwvwuhdpvduhwhuplqdwhgehiruhwkh$70fhoovohdyhwkhqrgh qrqryhuodsslqjprgh ? at oeps the cc flow generation is enabled (vpc or vcc, segment or end-to-end). 3;%( data sheet 4-129 04.2000 2shudwlrq (qdeoh 'lvdeohri30 this command is issued by the microprocessor either on request from the system controller or in the course of a activation/deactivation cell received for this connection. the following parameters are needed: ? lci of the connection or lci2 of the vp-pointer ? block size 128, 256, 512 or 1024 ? mode select: 1) generate and collect data or 2) analyze and loop. 1rupdo2shudwlrq 6fdq3urfhvv7uljjhu in fault free state the main task of the microprocessor is to trigger the scan function in 500 ms intervals. this is done by setting one single bit in a register. an internal logic checks all requested entries (from lci min. to lci max) of both up- and downstream external rams. according to the actual state of the connection (ais state, phy failure, cc state etc.) and the programmed time- out values the respective state transitions are performed automatically by the aop. in addition an interrupt bit is set if a state transition to or from failure state occurred. as long as no state transition occurs nothing else has to be done by the microprocessor than to trigger the scan in 500 ms intervals. in case of an interrupt the microprocessor must determine the connection which triggered the (common) interrupt. for this purpose the compressed dma function is enabled together with the next scan, which transfers the status dword of all connections from both up- and downstream external ram to the microprocessor memory. the status dword contains: ? vp/vc ais/rdi/loc defect/failure state ? transition events between these states and fault-free state ? error indication bits ? direction bit. the compressed dma can be programmed to clear the transition event bits after read within the same scan/dma process ( vhh)ljxuh ). the microprocessor is informed by the aop about transitions to failure states and back to fault- free states via interrupt. according to the standards transitions to defect states are not reported. scan and dma completion is indicated by flags. with one 32-bit dword transferred per connection and per direction, in total up to 32 k dwords are transferred to the microprocessor memory. the dwords are stored in the designated ram area with ascending lci values from lower to upper lci limit. upstream and downstream dword of a lci are adjacent, but their order is undetermined. the direction bit must be evaluated for each dword. 3;%( data sheet 4-130 04.2000 2shudwlrq %lw0dsslqjiru&rpsuhvvhg'0$0rgh dword 0 31302928272625242322212019181716 0 0 13 12 11 10 9 8 0 0 5 4 3 2 1 0 7deoh %lw0dsslqjiru&rpsuhvvhg'0$0rgh %lw 1dph )) 'zrug %lw ,qglfdwlrq 31 1 : up 0 : down - - - indicates upstream or downstream external ram. 30 parity error - - - if =1 at least one dword of the lci entry a parity error was detected. 29 plocf2n f4 4 27 indication for a state transition from loc failure state to loc normal state. 28 plocd2f f4 4 26 indication for a state transition from loc defect to loc failure state. 27 prdif2n f4 4 25 indication for a state transition from ais failure to ais normal state. 26 prdid2f f4 4 24 indication for a state transition from ais defect to ais failure state. 25 paisf2n f4 4 23 indication for a state transition from ais failure to ais normal state. 24 paisd2f f4 4 22 indication for a state transition from ais defect to ais failure state. 23 edcerr f4 2 13 wrong edc (crc10) in an oam cell detected. 22 oammis f4 2 12 misinserted oam cell discarded. 21 plocfai f4 5 5 f4 loc failure state indication. 20 plocdef f4 5 4 f4 loc defect state indication. 19 prdifai f4 5 3 f4 rdi failure state indication. 18 prdidef f4 5 2 f4 rdi defect state indication. 17 paisfai f4 5 1 f4 ais failure state indication. 16 paisdef f4 5 0 f4 ais defect state indication. 15 0 always - - - 14 0 always - - - 13 clocf2n f5 2 19 indication for a state transition from f5 loc failure state to f5 loc normal state. 12 clocd2f f5 2 18 indication for a state transition from f5 loc defect state to f5 loc failure state. 3;%( data sheet 4-131 04.2000 2shudwlrq 307kuhvkrog&khfn also in normal operation the local controller checks all data collection entries, compares the values with the given thresholds and if these are exceeded ? activates ais/rdi insertion and ? informs network management optionally records of the e.g. last 15 minutes could be collected on-board for the last 24 hours. (yhqwv events are unpredictable for the peripheral controller. these may be interrupts from the hw or command messages received from the system controller . 7udqvplvvlrq/lqh)dloxuh such failures are e.g. line breaks or transmitter/receiver failure. they are detected by the phy device and usually signalled to the local controller by interrupt. if the failure is confirmed the local controller ? sets the corresponding phy error bit in a aop register to signal the failure to the atm layer. all ensuing actions as generation of vp-ais or vc-ais cells in forward direction as well as the insertion of vp-rdi or vc-rdi cells in backward direction are done automatically by the scan mechanism. 11 crdif2n f5 2 17 indication for a state transition from f5 rdi failure state to f5 rdi normal state. 10 crdid2f f5 2 16 indication for a state transition from f5 rdi defect state to f5 rdi failure state. 9 caisf2n f5 2 15 indication for a state transition from f5 ais failure state to f5 ais normal state. 8 caisd2f f5 2 14 indication for a state transition from f5 ais defect state to f5 ais failure state. 7 0 always - - - 6 0 always - - - 5 clocfai f5 1 5 f5 loc failure state. 4 clocdef f5 1 4 f5 loc defect state. 3 crdifai f5 1 3 f5 rdi failure state. 2 crdidef f5 1 2 f5 rdi defect state. 1 caisfai f5 1 1 f5 ais failure state. 0 caisdef f5 1 0 f5 ais defect state. 1) refer to the external ram (identical for up- and downstream ram). 2) for detailed explanation see section 3.9.1, page 98, section 3.9.2, page 104, section 3.9.3, page 110 and section 3.9.4, page 116. 7deoh %lw0dsslqjiru&rpsuhvvhg'0$0rgh %lw 1dph )) 'zrug %lw ,qglfdwlrq 3;%( data sheet 4-132 04.2000 2shudwlrq /%&hoo7udqvplvvlrq 5hfhswlrq the transmission of a lb cell is usually initiated by the system controller. the parameters ?lci ? segment or end-to-end or intra-domain lb ? the location identifier in case of intra-domain lb must be given by the system controller. note that in case of a segment or end-to-end lb the location and source id are set to all ones. the microprocessor assembles the lb cell and transmits it via the aop. a timer is started for time-out supervision. prior to transmission the lb state bit is set for this connection. this bit causes the returning lb cell to be copied to the receive buffer. if it is not set the backward lb cell is discarded without notice. by comparing the correlation tag the peripheral controller makes sure that the cell was the one sent out before. 1rwh 7khfruuhodwlrqwdjlvqrwjhqhudwhge\wkh$23,wl vuhfrpphqghgwrj hqhudwhdudqgrpqxpehue\wkh shulskhudofrqwuroohu 30$fwlydwlrq 'hdfwlydwlrq&hoo7udqvplvvlrq the request to do performance monitoring over a given vpc or vcc connection or segment is initiated by the system controller and sent to the originating point microprocessor. the parameters ? lci or lci2 (for f4 pm) ? block size (128, 256, 512, 1024) must be given. similar to the lb procedure the microprocessor generates an appropriate activation cell for either segment or end-to-end, depending on the given configuration. after reception of the confirmation cell ( 6hfwlrq ) the fm generation processor is assigned as well as a data collection processor in the opposite direction. there are two restrictions to be checked: ? there are at most 128 processors for fm generation or analysis and 128 processors for data collection ? not more than 2 processors can be invoked for one user cell, one for f4 and one for f5 ( 6hfwlrq ). 30$fwlydwlrq 'hdfwlydwlrq&hoo5hfhswlrq an activation/ deactivation cell may be received at any time at the receive buffer of the aop. in such a case the peripheral controller looks for a free pm processor and assigns it to the connection. the pm processor is initialized in analyzing mode. then a confirmation cell is sent back to the originating port. the pm endpoint is now ready for reception of the first fm cell. 3;%( data sheet 4-133 04.2000 2shudwlrq ([dpsohv 30&rqiljxudwlrq in this example a vpc containing a vcc is terminated. a number of pm measurements are performed: ? end-to-end pm at f4 (vpc) level bi-directional ? segment pm termination and creation of a new segment at f5 (vcc) level uni-directional in total 4 pm processors and 2 data collection processors are involved. their associated ram entries are shown in )ljxuh . the two connections involved, vpca and vccb are represented by 2 entries in each up- and downstream ram, a f4 and a f5 entry with the f5 entry pointing to the f4 entry. each entry has 4 pointer + enable pairs to define: ? the origination point of a pm flow ? the endpoint of a pm flow ? a data collection point for a end-to-end flow ? a data collection point for a segment flow. for origination and termination points the selection between end-to-end and segment flows is done in the pm main ram by setting the flow type (ft) bits. at termination points the generation of br cells can be enabled by setting brdis=0. a further parameter to specify is the block length bl. in the example of )ljxuh two different block sizes are used, 1024 (coding 1001) at the f4 level and 256 (coding 0111) at the f5 level. the data collection function evaluates the contents of br cells. it can be enabled at any point along the path of the br cells, including the analyzing point where the br cells are generated. in the present example the evaluation occurs at the end point of the br cells. the scenario shown in )ljxuh can only occur at an ingress port of a switch, where vpcs are terminated. hence the origination of a end-to-end f4 flow should not be programmed in upstream direction. conversely in downstream direction a f4 end-to-end flow must not be enabled. 3;%( data sheet 4-134 04.2000 2shudwlrq )ljxuh 3huirupdqfh0rqlwrulqj([dpsoh upstream connection ram 0 127 0 16383 downstream connection ram pm result data (14 dwords) 0 127 0 16383 vpca vccb f4 end-end pm flow f5 segment pm flow analyze loop report back f5 segment pm flow segment border generate collect data analyze loop report back f4 end-end pm flow generate collect data pm result data (14 dwords) terminate end-end or segment flow (ppmten + ppmtid) originate end-end or segment flow (ppmoen + ppmoid) data collect end-end (pedcen + pedcid) data collect segment (psdcid + psdcen) terminate end-end or segment flow (cpmten + cpmtid) originate end-end or segment flow (cpmoen + cpmoid) data collect end-end (cedcen + cedcid) data collect segment (csdcid + csdcen) terminate end-end or segment flow (ppmten + ppmtid) originate end-end or segment flow (ppmoen + ppmoid) data collect end-end (pedcen + pedcid) data collect segment (psdcid + psdcen) terminate end-end or segment flow (cpmten + cpmtid) originate end-end or segment flow (cpmoen + cpmoid) data collect end-end (cedcen + cedcid) data collect segment (csdcid + csdcen) f5 entry of vccb f5 entry of vccb f4 entry of vpca f4 entry of vpca performance monitoring main ram performance monitoring data collection ram ft=01 | brdis=0 | bl=1001 | pm data... ft=10 | brdis=0 | bl=0111 | pm data... ft=10 | brdis=1 | bl=0111 | pm data... ft=01 | brdis=1 | bl=1001 | pm data... 3;%( data sheet 5-135 04.2000 ,qwhuidfhv ,qwhuidfhv 8723,$,qwhuidfhv the aop has one utopia receive interface and one utopia transmit interface with master capability at the phy side and one receive and transmit interface with slave capability at the atm side ( iljxuh ). the interfaces are compliant to the utopia level 1 and 2 specification [ ], i.e.: ? bus width is selectable either 8 or 16 bit ? single-phy or multi-phy configurations ? phy number enhancement option, see specification utopia level 2 appendix 1. )ljxuh 8723,$,qwhuidfhv $23 receive upstream master transmit downstream master transmit upstream slave receive downstream slave 8svwuhdp&hoo)orz 'rzqvwuhdp&hoo)orz atm (a) phy (p) phy (p) atm (a) 3+< 6lgh $70 6lgh rxdatu(15:0) rxsocu rxprtyu rxclavu(3:0) rxenbu(3:0) rxadru(3:0) utphyclk txdatd(15:0) txsocd txprtyd txclavd(3:0) txenbd(3:0) txadrd(3:0) utatmclk rxdatd(15:0) rxsocd rxprtyd rxclavd(3:0) rxenbd(3:0) rxadrd(3:0) txdatu(15:0) txsocu txprtyu txclavu(3:0) txenbu(3:0) txadru(3:0) 3;%( data sheet 5-136 04.2000 ,qwhuidfhv receive and transmit side of atm and phy side utopia interface operate each from one clock which may be completely independent from the main chip clock sysclk. the utopia clock frequency must be less than or equal to the main chip clock sysclk. the utopia interface has an 8-bit and a 16-bit option. the 16-bit option has the 54 octet cell format shown in iljxuh for the standardized format and in iljxuh for the proprietary format. the 8-bit format has 53 octet without the udf2 octet. atm side and phy side utopia interface can be configured independently in 8-bit or 16-bit mode. )ljxuh 6wdqgdugl]hg8723,$fhooirupdw elw dooilhogvdffruglqjwrvwdqgdugvxqxvhgrfwhwvvkdghg )ljxuh 3ursulhwdu\8723,$fhooirupdw elw with pn(2:0) = port number for pxb 4220 iwe8 (dont care for aop) hk(2:0) = housekeeping bits (only for internal continuity check icc) lci(13:0) = logical connection identifier all other fields according to standards, unused octets shaded. 8723,$0xowl3+<vxssruw to support multi-phy configurations with and without use of the utopia phy address the infineon technologies atm switching chip set supports the direct status polling option of the utopia level 2 standard [ ]. it allows the simultaneous polling of up to 4 groups of phys by using 4 clavx/enx signal pairs (x=0..3). during the transfer of a cell the master utopia interface polls 12 phy addresses. the 27 clock cycles time for the transfer of a cell in 16-bit utopia format allows to poll 12 phy addresses and to select one of them for the next cell transfer. receive and transmit utopia interfaces always poll separately. to allow the support of more than 12 phys 4 pairs of clavx/enx lines are provided in all infineon technologies atm switching chips with utopia interfaces. bit:1514131211109876543210 0 vpi(11:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 udf1 udf2 3 payload octet 1 payload octet 2 4 payload octet 3 payload octet 4 :: : 26 payload octet 47 payload octet 48 word bit:1514131211109876543210 0 lci(11:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 /&, hk(2:0) pn(2:0) udf2 3 payload octet 1 payload octet 2 4 payload octet 3 payload octet 4 :: : 26 payload octet 47 payload octet 48 word 3;%( data sheet 5-137 04.2000 ,qwhuidfhv however, although 48 phys could be polled by this configuration only up to 24 phy are supported. 1rwh wkhqxpehuriolqhlqwhuidfhv 3+ 3;%( data sheet 5-139 04.2000 ,qwhuidfhv 5$0,qwhuidfhv the aop uses external, synchronous, static ram (ssram) for the storage of connection related oam data. two identical ssram interfaces are provided, one for each direction. the ssram chips are operated with the system clock of up to 52 mhz. all memory entries are protected with a parity bit at the msb location. the size of the ssram is depending on the number of supported connections: 8 dwords of 32- bit are required per connection. using ssram devices of 1 mbit or 2 mbit size, i.e. 32 k x 32 bit and 64 k x 32 bit, respectively, the possible memory configurations are: ? 2 x 2 mbit or 4 x 1 mbit ssram for 16384 connections ? 1 x 2 mbit or 2 x 1 mbit ssram for 8192 connections ? 1 x 1 mbit ssram for 4096 connections these are the values for one direction. both up- and downstream external memory should always be configured symmetrical. the selection 1 mbit or 2 mbit ssram chips is done via register bits. )ljxuh shows an example of maximum ram size with two 2 mbit devices, iljxuh shows an example of maximum ram size with four 1 mbit devices. )ljxuh 8svwuhdprugrzqvwuhdp5$0lqwhuidfhxvlqj0elwv5$0v rdatx(31:0) . [ elw 665$0 1 x = u for upstream, d for downstream ram sysclk gnd +3.3 v gnd +3.3 v +3.3 v 0 3;% ( $23 rce3x roex radvx radrx(14:0) 2x2m configuration 10 k w 10 k w 10 k w 1k w 226 w io(31:0) a( 15) a(14:0) adv oe gw clk adsc adsp bwe ce2 ce2 bw1 bw2 bw3 bw4 mode zz ce of ram no. 1 ce of ram no. 0 rgwx rce1x rce0x rscx 3;%( data sheet 5-140 04.2000 ,qwhuidfhv )ljxuh 8svwuhdprugrzqvwuhdp5$0,qwhuidfhxvlqj 0elw5$0v note that rcex2 is unused and rcex3 is used as additional address pin adr(15) when using 2 mbit rams.the aop uses 4-bursts to access the external rams. )ljxuh shows an example for the read access. during each cell cycle two 4-burst read and two 4-burst write accesses are made at both up- and downstream ram. if no cell is to be processed at one of the interfaces a scan/dma access or microprocessor access is executed. rdatx(31:0) radrx(14:0) radvx . [ elw 665$0 1 2 3 x = u for upstream, d for downstream ram sysclk gnd +3.3 v gnd +3.3 v +3.3 v 0 3;% ( $23 10 k w 10 k w 10 k w 1k w 226 w zz mode bw4 bw3 bw2 bw1 ce2 ce2 bwe adsp adsc ce of ram no. 1 ce of ram no. 2 ce of ram no. 3 clk gw oe adv a(14:0) io(31:0) ce of ram no. 0 roex rgwx rce3x rce2x rce1x rce0x rscx 3;%( data sheet 5-141 04.2000 ,qwhuidfhv )ljxuh ([dpsohri([hfxwlrq7lplqjiru5hdg&\fohv %xuvw0rgh 0lfursurfhvvru,qwhuidfh the aop has a 16-bit microprocessor interface for control and operation. it is identical for all devices of the infineon technologies atm switching chip set . a possible microprocessor could be the 386ex embedded controller as shown in iljxuh . a(17:0) 12 3456789 sysclk adsc adv gw ce oe rdatx input burst read a1 a2 10 11 d1 d2 d3 d4 d8 d7 d6 d5 d1..d8 dwords 1..8 from external ram a1 address from rmw address register a2 address lci2 from external ram entry (a1) (a1) (a1) (a1) (a2) (a2) (a2) (a2) 3;%( data sheet 5-142 04.2000 ,qwhuidfhv )ljxuh 0lfursurfhvvru,qwhuidfh the interface is operating completely asynchronous to the system clock sysclk. -7$*%rxqgdu\6fdq,qwhuidfh this interface contains the boundary scan of all signal pins according to the standard [ ]. it consists of the pins shown in iljxuh . )ljxuh -7$*,qwhuidfh 7hvw,qwhuidfh there are several additional test pins provided for board test. please let them unconnected or connected to ground as described in section 5.6, part "additional testpins". mpdat(15:0) mpadr(7:0) mpwr mprd mpcs mpint mprdy * mpdreq mpdack 1rwh 6wdwhpdfklqhvirujoxhorjlfdydlodeohxsrquhtxhvw 3;%( $23 plfursurfhvvru (; tdo 3;%( $23 tms tdi tck trst 3;%( data sheet 5-143 04.2000 3lq'hvfulswlrq 3lq'hilqlwlrqvdqg)xqfwlrqv the following explanations applies for all pins of a field in the table respectively: ? pins with a 1) attached are connected with an internal pull up resistor. ? pins with a 2) attached are connected with an internal pull down resistor. ? pins with a 3) attached are 5v compatible. pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq &orfndqguhvhw slqv ac26 reset i chip reset b12 sysclk i main chip clock a13 utphyclk i utopia clock at phy side (master). ae14 utatmclk i utopia clock at atm side (slave). 8wrsld,qwhuidfh uhfhlyhxsvwuhdppdvwhu slqv b20, a20, c20, b19, d18, a19, c19, b18, a18, b17, c18, a17, d17, b16, c17, a16 2) rxdatu (15:0) i receive data bus from phy side. c23, a23, b22, d22 rxadru (3:0) o address outputs to phy side. a21 2) rxprtyu i odd parity of rxdatu(15:0) from phy side. a25, b24, a24, b23 rxenbu (3:0) o enable signal to phy side. a22, b21, d20, c21 2) rxclavu (3:0) i cell available signal from phy side. c22 2) rxsocu i start of cell signal from phy side. 3;%( data sheet 5-144 04.2000 3lq'hvfulswlrq 8wrsld,qwhuidfh wudqvplwgrzqvwuhdppdvwhu slqv d12, b10, c11, a10, d10, b9, c10, a9, b8, a8, c9, b7, d8, a7, c8, b6 txdatd (15:0) o transmit data bus to phy side. d13, a12, b11, c12 txadrd (3:0) o address to phy side. a11 txprtyd o odd parity to phy side. a15, c16, b14, d15 txenbd (3:0) o enable signal to phy side. d7, a6, c7, b5 2) txclavd (3:0) i cell available signal from phy side. b15 txsocd o start of cell signal to phy side. 8wrsld,qwhuidfh uhfhlyhgrzqvwuhdpvodyh slqv af9, ae9, ad8, af8, ac9, ae8, ad7, af7, ae7, af6, ad6, ac7, ae6, af5, ad5, ac5 2) rxdatd (15:0) i receive data bus from atm side. ad11, af12, ae12, af11 2) rxadrd (3:0) i address from atm side. ae5 2) rxprtyd i odd parity of rxdatd(15:0) from atm side. ad12, af13, ac12, ae13 1) rxenbd (3:0) i enable signals from atm side. ae11, ac10, af10, ad9 rxclavd (3:0) o cell available signal to atm side. ad10 2) rxsocd i start of cell signal from atm side. pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 5-145 04.2000 3lq'hvfulswlrq 8wrsld,qwhuidfh wudqvplwxsvwuhdpvodyh slqv ad18, af19, ae19, af18, ad17, ae18, ac17, af17, ad16, ae17, ac15, af16, ad15, ae16, af15, ad14 txdatu (15:0) o transmit data bus to atm side. ae23, ad21, af22, ae21 2) txadru (3:0) i address from atm side. ae15 txprtyu o odd parity of rxdatu(15:0) to atm side. ad23, ae24, ad22, af23 1) txenbu (3:0) i enable signal from atm side. ad19, af20, ac19, ae20 txclavu (3:0) o cell available signal to atm side. ad13 txsocu o start of cell signal to atm side. 0lfursurfhvvru,qwhuidfh slqv e2, e4, e3, e1, f2, g4, f3, f1, g2, g1, g3, h2, j4, h1, h3, j2 mpdat (15:0) i/o microprocessor data bus c4, b3, c5, a4, d5, b4, c6, a5 mpadr (7:0) i address from microprocessor b1 mpwr i write enable from microprocessor. c2 mprd i read enable from microprocessor. a3 mpcs i chip select from microprocessor. d1 3) mpint o interrupt request to microprocessor. d3 mpdreq o dma request to microprocessor. d2 mprdy o ready output to microprocessor for read and write accesses. c1 mpdack i m p dma acknowledgment pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 5-146 04.2000 3lq'hvfulswlrq &rqqhfwlrq'dwd665$08svwuhdp slqv l25, m24, l26, m23, k25, l24, k26, k23, j25, k24, j26, h25, h26, j24, g25, h23, g26, h24, f25, g23, f26, g24, e25, e26, f24, d25, e23, d26, e24, c25, d24, c26 2) rdatu (31:0) i/o databus of upstream connection ram r25, t26, u24, t25, m26, n24, m25, t24, r26, v25, v26, u25, v24, u26, u23 radru (14:0) o addressbus of upstream connection ram p24 radvu o address advance input n23 roeu o output enable n25 rgwu o global write p25 rce0u o chip enable ram 0 r23 rce1u o chip enable ram 1 p26 rce2u o chip enable ram 2, not used in 2x2m mode r24 rce3u o chip enable ram 3 or adr(15) in 2x2m mode n26 rscu o status controller ram pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 5-147 04.2000 3lq'hvfulswlrq &rqqhfwlrq'dwd665$0'rzqvwuhdp slqv t3, u1, u4, v2, u3, v1, w2, w1, v3, y2, w4, y1, w3, aa2, y4, aa1, y3, ab2, ab1, ac2, ab4, ac1, ab3, ad2, ac3, ad1, af2, ae3, af3, ae4, ad4, af4 2) rdatd (31:0) i/o databus of downstream connection ram n2, l3, m1, l1, k3, u2, r4, n1, m4, j1, k2, j3, k1, k4, l2 radrd (14:0) o address bus of downstream connection ram t1 radvd o address advance input t2 roed o output enable r1 rgwd o global write p1 rce0d o chip enable ram 0 n3 rce1d o chip enable ram 1 r2 rce2d o chip enable ram 2, not used in 2x2m mode p3 rce3d o chip enable ram 3 or adr(15) in 2x2m mode r3 rscd o status controller ram pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 5-148 04.2000 3lq'hvfulswlrq 'hwhfwru,qwhuidfh slqv w25 fpct2d o cell filter 2 detector output downstream. in case of match a high pulse of 30 sysclk cycles is output. minimum low period between 2 pulses is 2 sysclk cycles. v23 fpct1d o cell filter 1 detector output downstream. in case of match a high pulse of 30 sysclk cycles is output. minimum low period between 2 pulses is 2 sysclk cycles. w26 fpct2u o cell filter 2 detector output upstream. in case of match a high pulse of 30 sysclk cycles is output. minimum low period between 2 pulses is 2 sysclk cycles. w24 fpct1u o cell filter 1 detector output upstream. in case of match a high pulse of 30 sysclk cycles is output. minimum low period between 2 pulses is 2 sysclk cycles. 7hvw-7$*%rxqgdu\6fdq slqv af24 1) tdi i test data input; this pin has an internal pull-up resistor and need not to be connected for normal operation. ac14 1) tck i test clock; this pin has an internal pull-up resistor and need not to be connected for normal operation. ad25 1) tms i test mode select this pin has an internal pull-up resistor and need not to be connected for normal operation. ad26 1) trst i tap controller reset this pin has an internal pull-down resistor and need not to be connected for normal operation. if connected it must be driven to v ss for normal operation. ae26 tdo o test data output; need not to be connected for normal operation. pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 5-149 04.2000 3lq'hvfulswlrq $gglwlrqdo7hvwslqv slqv ac25 1) outtri i for test only, do not connect ac24 1) uttri i for test only, do not connect y23 2) stest i for test only, do not connect ab25 aopiidd i has to be connected to ground. aa24 ndtro o for test only, do not connect ab23, ab24, ab26, aa25 tstbusi i testbus in for test only, dont connect. aa26, y25, y26, y24 tstbuso o testbus out for test only, dont connect. 6xsso\ slqv d6, d11, d16, d21, f4, f23, l4, l23, t4, t23, aa4, aa23, ac6, ac11, ac16, ac21 vdd, chip 3.3 v supply a1, a2, a26, b2, b25, b26, c3, c24, d4, d9, d14, d19, d23, h4, j23, n4, p23, v4, w23, ac4, ac8, ac13, ac18, ac23, ad3, ad24, ae1, ae2, ae25, af1, af25, af26 vss, chip ground 8qfrqqhfwhg3lqv slqv a14, b13, c13, c14, c15, m2, m3, p2, p4, aa3, ac20, ac22, ad20, ae10, ae22, af14, af21 not connected pins pin definitions and functions 3lq1r 6\pero ,qsxw , 2xwsxw 2 )xqfwlrq 3;%( data sheet 6-150 04.2000 (ohfwulfdo&kdudfwhulvwlfv (ohfwulfdo&kdudfwhulvwlfv $evroxwh0d[lpxp5dwlqjv 7deoh $evroxwh0d[lpxp5dwlqjv 1rwh 6wuhvvhv deryh wkrvh olvwhg khuh pd\ fdxvh shupdqhqw gdpdjh wr wkh ghylfh ([srvxuh wr devroxwh pd[lpxpudwlqjfrqglwlrqviruh[whqghgshulrgvpd\diihfwghylfhuholdelolw\ 2shudwlqj5dqjh 1rwh ,qwkhrshudwlqjudqjhwkhixqfwlrqvjlyhqlqwkhflufxlwghvfulswlrqduhixoiloohg 1rwh 7khqrplqdovxsso\yrowdjh 9 '' vkrxogqrwh[fhhg9wrnhhswkhghylfhzlwklqwkhvshflilhgfxuuhqw dqgsrzhuglvvlsdwlrqudqjhv 3dudphwhu 6\pero /lplw9doxhv 8qlw ambient temperature under biaspxb 7 a -40 to 85 c storage temperature 7 stg -40 to 125 c ic supply voltage with respect to ground 9 dd -0.3 to 3.6 v voltage on any pin with respect to ground 9 s -0.4 to 9 dd + 0.4 v esd robustness 1) hbm: 1.5 k w , 100 pf 1) according to mil-std 883d, method 3015.7 and esd association standard eos/esd-5.1-1993. the rf pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 v (versus 9 s or gnd). the high frequency performance prohibits the use of adequate protective structures. v esd,hbm 2500 v 7deoh 2shudwlqj5dqjh 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq pd[ ambient temperature under bias 7 a -40 85 c junction temperature 7 j 125 c supply voltage 9 dd 3.15 3.45 v ground 9 ss 00v power dissipation 3 1.9 w 3;%( data sheet 6-151 04.2000 (ohfwulfdo&kdudfwhulvwlfv '&&kdudfwhulvwlfv 7deoh '&&kdudfwhulvwlfv 3dudphwhu 6\pero /lplw9doxhv 8qlw 1rwhv plq w\s pd[ *hqhudo,qwhuidfh/hyhov (does not apply to boundary scan interface): input low voltage 9 il C0.4 0.8 v input high voltage 9 ih 2.0 2.1 for pin trst 9 dd + 0.3 v lvttl (3.3v) output low voltage 9 ol 0.2 0.4 v , ol =4ma ( , ol = 6 ma for txclav/ rxclav signals) output high voltage(s) 9 oh 2.4 9 dd v , oh =C4ma ( , oh =C6ma for txclav/ rxclav signals) average power supply current , cc (av) 395 550 ma 9 dd = 3.45 v, sysclk = 52mhz; utphyclk = 52mhz; utatmclk = 52mhz; average power up supply current (n sysclk cycles after reset) , ccpu (av) 550 ma 9 dd =3.45v, sysclk = 52mhz; utphyclk = 52mhz; utatmclk = 52mhz; average power dissipation 3 (av) 1.3 1.9 w 9 dd = 3.45 v, sysclk = 52mhz; utphyclk = 52mhz; utatmclk = 52mhz; 3;%( data sheet 6-152 04.2000 (ohfwulfdo&kdudfwhulvwlfv input current , iin -1 1 ma 9 in = 9 dd or 9 ss 50 150 ma 9 in = 9 dd for inputs with internal pull- down resistor -50 -200 ma 9 in = 9 ss for inputs with internal pull-up resistor output leakage current , oz -1 1 ma 9 dd =3.3v, gnd = 0 v, 9 in = 9 dd or 9 ss, 9 out in tristate 3dudphwhu 6\pero /lplw9doxhv 8qlw 1rwhv plq w\s pd[ 3;%( data sheet 6-153 04.2000 (ohfwulfdo&kdudfwhulvwlfv $&&kdudfwhulvwlfv 7 a = -40 to 85 c, 9 cc = 3.15 v .. 3.45 v, 9 ss = 0 v all inputs are driven to 9 ih = 2.4 v for a logical 1 and to 9 il = 0.4 v for a logical 0 all outputs are measured at 9 h = 2.0 v for a logical 1 and at 9 l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown below. )ljxuh ,qsxw2xwsxw:dyhirupiru$&0hdvxuhphqwv 7deoh &orfn)uhtxhqflhv 3dudphwhu 6\pero /lplw9doxhv 8qlw plq pd[ core clock sysclk2552mhz utopia clock at phy-side utphyclk i sysclk/2 i sysclk mhz utopia clock at atm-side utatmclk i sysclk/2 i sysclk mhz m p clock 1) 1) supplied only to external microprocessor; 25 i sysclk mhz test points ac_int.ds4 v h device under test c load = 50 pf max v h v l v l 3;%( data sheet 6-154 04.2000 (ohfwulfdo&kdudfwhulvwlfv 0lfursurfhvvru,qwhuidfh7lplqj 0lfursurfhvvru:ulwh&\foh7lplqj )ljxuh 0lfursurfhvvru,qwhuidfh:ulwh&\foh7lplqj 7deoh 0lfursurfhvvru,qwhuidfh:ulwh&\foh7lplqj 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 mpadr setup time before mpcs low 0 ns 2 mpcs setup time before mpwr low 0 ns 3 mprdy low delay after mpwr low 1 15 ns 4 mpdat setup time before mpwr high 5 ns 5 pulse width mprdy low 3 sysclk cycles 4 sysclk cycles 6 mprdy high to mpwr high 5 ns 7 mpdat hold time after mpwr high 5 ns 8 mpcs hold time after mpwr high 5 ns 9 mpadr hold time after mpwr high 5 ns 10 mpcs low to mprdy low impedance 1 10 ns 11 mpcs high to mprdy high impedance 15 ns 1 3 4 56 7 8 9 mpadr mpcs mpwr mprdy mpdat 2 11 10 3;%( data sheet 6-155 04.2000 (ohfwulfdo&kdudfwhulvwlfv 0lfursurfhvvru5hdg&\foh7lplqj )ljxuh 0lfursurfhvvru,qwhuidfh5hdg&\foh7lplqj 7deoh 0lfursurfhvvru,qwhuidfh5hdg&\foh7lplqj 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 21 mpadr setup time before mpcs low 0 ns 22 mpcs setup time before mprd low 0 ns 23 mprdy low delay after mprd low 1 15 ns 24 pulse width mprdy low 4 sysclk cycles 5 sysclk cycles 24 pulse width mprdy low (mpadr = 9d h ) 6 sysclk cycles 7 sysclk cycles 24 pulse width mprdy low (mpadr = b6 h ) 7 sysclk cycles 8 sysclk cycles 25 mpdat valid before mprdy high 5 ns 26 mprdy high to mprd high 5 ns 27 mpdat hold time after mprd high 2 ns 28 mpcs hold time after mprd high 5 ns 29 mpadr hold time after mprd high 5 ns 30 mprd low to mpdat low impedance 1 15 ns 31 mprd high to mpdat high impedance 2 15 ns 21 23 25 24 26 27 28 29 mpadr mpcs mprd mprdy mpdat 22 30 31 33 32 3;%( data sheet 6-156 04.2000 (ohfwulfdo&kdudfwhulvwlfv '0$5htxhvw7lplqj for dma operation the mpdreq signal is necessary. it indicates that at least one more word is available within the aop dma buffer. when the microprocessor reads the last word in the buffer (dmar register) it must be ensured that the mpdreq signal is updated early enough to prohibit another read to the dmar register. with asynchronous sampling of the microprocessor mpdreq input, mpdreq has to be updated at least 1 clkout cycle before the mprdy gets active (386ex user manual, "12.2.5 ending dma transfers", page 12-11). in aop mpdreq update is done 5 sysclk cycles (= 96ns at 51.84 mhz) before mprdy. with 25 mhz microprocessor clock (clk2) the clkout period (twice the clk2 period) of 80 ns is satisfied. less than 25 mhz microprocessor clock frequency may cause problems. if mpdreq gets inactive the aop waits for mpdack = 'high', afterwards additional 20 sysclk cycles (about 400ns) are spent until mpdreq will become active again. this minimum gap was introduced to ensure co-operation with the 80386ex internal dma controller. for distinction of 2 successive read cycles the read signal must be '1' for at least 1 sysclk cycle, the chip select signal may remain active. this 'command inactive time' is necessary for all adjacent microprocessor read and write accesses. 32 mpcs low to mprdy low impedance 1 10 ns 33 mpcs high to mprdy high impedance 15 ns 7deoh 0lfursurfhvvru,qwhuidfh5hdg&\foh7lplqj 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 3;%( data sheet 6-157 04.2000 (ohfwulfdo&kdudfwhulvwlfv )ljxuh 0lfursurfhvvru'0$,qwhuidfh 7deoh 0lfursurfhvvru'0$lqwhuidfh 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 40 rising edge of mpdreq after mprd low 1 3 sysclk cycles 41 mpdreq driven high before high impedance 1 1 sysclk cycles 42 interval between mpdreq active phases (in case of successive accesses) 20 sysclk cycles 43 interval between mpdack inactive and subsequent mpdreq active 20 sysclk cycles 44 mpdreq inactive before mprdy active (in case the dma fifo gets empty during the current read access) 5 5 sysclk cycles ph2 ph1 ph2 ph1 ph2 ph1 ph2 80ns t1 t2 t2 asic not ready => one more t2 asic ready +30ns rd output delay +40ns synchronisation in asic +20ns dre output delay -80ns async dre sampling before ready 200ns 386ex:clk2 386ex:clkout 386ex:rd 386ex:dre 386ex:dack note: time values given in this figure are example values and not tested in production. 3;%( data sheet 6-158 04.2000 (ohfwulfdo&kdudfwhulvwlfv 8723,$,qwhuidfh the ac characteristics of the utopia interface fulfill the standard of [1] and [2]. setup and hold times of the 50 mhz utopia specification are valid. according to the utopia specification, the ac characteristics are based on the timing specification for the receiver side of a signal. the setup and the hold times are defined with regards to a positive clock edge, see )ljxuh . taking into account the actual clock frequency (up to the maximum frequency), the corresponding (min. and max.) transmit side "clock to output" propagation delay specifications can be derived. the timing references (tt5 to tt12) are according to the data found in 7deoh to 7deoh . )ljxuh 6hwxsdqg+rog7lph'hilqlwlrq 6lqjohdqg0xowl3+< &orfn 6ljqdo 84, 86 85, 87 input setup to clock input hold from clock 3;%( data sheet 6-159 04.2000 (ohfwulfdo&kdudfwhulvwlfv )ljxuh shows the tristate timing for the multi-phy application (multiple phy devices, multiple output signals are multiplexed together). )ljxuh 7ulvwdwh7lplqj 0xowl3+<0xowlsoh'hylfhv2qo\ &orfn 6ljqdo 90 91 signal going low impedance from clock 88 89 signal going low impedance to clock signal going high impedance from clock signal going high impedance to clock 3;%( data sheet 6-160 04.2000 (ohfwulfdo&kdudfwhulvwlfv ,qwhuidfhdqgvljqdoqdplqjfrqyhqwlrqv )ljxuh ,qwhuidfh1dplqj&rqyhqwlrqv in the following tables, a t p (column dir, direction) defines a signal from the atm layer (transmitter, driver) to the phy layer (receiver), a p defines a signal from the phy layer (transmitter, driver) to the atm layer (receiver). $23 receive upstream master transmit downstream master transmit upstream slave receive downstream slave 8svwuhdp&hoo)orz 'rzqvwuhdp&hoo)orz atm (a) phy (p) phy (p) atm (a) 3+< 6lgh $70 6lgh rxdatu(15:0) rxsocu rxprtyu rxclavu(3:0) rxenbu(3:0) rxadru(3:0) utphyclk txdatd(15:0) txsocd txprtyd txclavd(3:0) txenbd(3:0) txadrd(3:0) utatmclk rxdatd(15:0) rxsocd rxprtyd rxclavd(3:0) rxenbd(3:0) rxadrd(3:0) txdatu(15:0) txsocu txprtyu txclavu(3:0) txenbu(3:0) txadru(3:0) 3;%( data sheet 6-161 04.2000 (ohfwulfdo&kdudfwhulvwlfv all timings also apply to utopia level 1 8-bit data bus operation. the direction notification in the following tables apply to the utopia master interface (aop to phy) 7deoh 7udqvplw7lplqj8svwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh6lqjoh 3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utatmclk atm clk frequency (nominal) i sysclk /2 52 mhz 81 atm clk duty cycle 40 60 % 82 atm clk peak-to-peak jitter - 5 % 83 atm clk rise/fall time - 2 ns 84 txdatu [15:0], txsocu a p input setup to atm clk 4 - ns 87 input hold from atm clk 1 - ns 7deoh 5hfhlyh7lplqj8svwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh6lqjoh 3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utphyclk phy clk frequency (nominal) i sysclk /2 52 mhz 81 phy clk duty cycle 40 60 % 82 phy clk peak-to-peak jitter - 5 % 83 phy clk rise/fall time - 2 ns 84 rxdatu [15:0], rxprtyu a p input setup to phy clk 4 - ns 87 input hold from phy clk 1 - ns
p input setup to atm clk 5 - ns 85 input hold from atm clk 1 - ns 86 rxsocd, rxenbd [0] a>p input setup to atm clk 4 - ns 87 input hold from atm clk 1 - ns 88 rxclavd[0] a 3;%( data sheet 6-163 04.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh 7udqvplw7lplqj8svwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh0xowl3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utatmclk atm clk frequency (nominal) i sysclk /2 52 mhz 81 atm clk duty cycle 40 60 % 82 atm clk peak-to-peak jitter - 5 % 83 atm clk rise/fall time - 2 ns 84 txdatu [15:0], a p input setup to atm clk 4 - ns 87 txadru [3:0] input hold from atm clk 1 - ns 86 txclavu [3:0] a 3;%( data sheet 6-164 04.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh 5hfhlyh7lplqj8svwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh0xowl3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utphyclk phy clk frequency (nominal) i sysclk /2 52 mhz 81 phy clk duty cycle 40 60 % 82 phy clk peak-to-peak jitter - 5 % 83 phy clk rise/fall time - 2 ns 84 rxenbu [3:0], a>p input setup to phy clk 4 - ns 85 rxadru [3:0] input hold from phy clk 1 - ns 86 rxdatu [15:0], rxprtyu a 3;%( data sheet 6-165 04.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh 7udqvplw7lplqj'rzqvwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh 0xowl3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utphyclk phy clk frequency (nominal) i sysclk /2 52 mhz 81 phy clk duty cycle 40 60 % 82 phy clk peak-to-peak jitter - 5 % 83 phy clk rise/fall time - 2 ns 84 txdatd [15:0], txsocd, a>p input setup to phy clk 4 - ns 85 txprtyd, txenbd [3:0], txadrd [3:0] input hold from phy clk 1 - ns 86 txclavd [3:0] a 3;%( data sheet 6-166 04.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh 5hfhlyh7lplqj'rzqvwuhdp %lw'dwd%xv0+]dw&hoo,qwhuidfh0xowl3+< 1r 6ljqdo1dph ',5 'hvfulswlrq /lplw9doxhv 8qlw 0lq 0d[ 80 utatmclk atm clk frequency (nominal) i sysclk /2 52 mhz 81 atm clk duty cycle 40 60 % 82 atm clk peak-to-peak jitter - 5 % 83 atm clk rise/fall time - 2 ns 84 rxenbd [3:0] a>p input setup to atm clk 4 - ns 85 rxadrd [3:0] input hold from atm clk 1 - ns 86 rxdatd [15:0], rxprtyd a 3;%( data sheet 6-167 04.2000 (ohfwulfdo&kdudfwhulvwlfv 665$0,qwhuidfh timing of the synchronous static ram interfaces is simplified as all signals are referenced to the rising edge of sysclk. in )ljxuh , it can be seen that all signals output by the pxb 4340 e aop have identical delay times with reference to the clock. when reading from the ram, the pxb 4340 e aop samples the data within a window at the rising clock edge. )ljxuh 665$0,qwhuidfh*hqhulf7lplqj'ldjudp 7deoh 665$0,qwhuidfh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 100 7 sysclk : period sysclk 19.2 ns 100a ) sysclk : frequency sysclk 52 mhz 101 sysclk low pulse width 7 ns 102 sysclk high pulse width 7 ns 103 delay sysclk rising to rsc , radv , radr(17:0), rgw , rce , roe 215ns 104 delay sysclk rising to rdat output 2 15 ns 105 setup time rdat input before sysclk rising (read cycles) 6ns 106 hold time rdat input after sysclk rising (read cycles) 1.5 ns sysclk rsc, radv, radr(17:0), rgw, rce, roe rdat(31:0), output rdat(31:0), input 100 101 102 103 104 106 105
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