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1 ? fn4419.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved hot plug? is a trademark of core international, inc. all other trademarks mentioned are the property of their respective owners . hip1012a dual power distribution controller the hip1012a is a hot swap dual supply power distribution controller. two external n-channel mosfets are driven to distribute power while providing load fault isolation. at turn-on, the gate of each external n-channel mosfet is charged with a 10 a current source. capacitors on each gate (see the typical applic ation diagram), create a programmable ramp (soft turn-on) to control inrush currents. a built in charge pump supplies the gate drive for the 12v supply n-channel mosfet switch. over current protection is faci litated by two external current sense resistors. when the curr ent through either resistor exceeds the user programmed va lue the controller enters the current regulation mode. the time-out capacitor, c tim , starts charging as the controller ente rs the time out period. once c tim charges to a 2v threshol d, the n-channel mosfets are latched off. in the event of a fault at least three times the current limit level, the n-channel mosfet gates are pulled low immediately before entering time out period. the controller is reset by a rising edge on either pwron pin. choosing the voltage selection mode the hip1012 controls either +12v/5v or +3.3v/+5v supplies. features ? hot swap dual power distribution control for +5v and +12v or +5v and +3.3v ? provides fault isolation ? programmable current regulation level ? programmable time out ? charge pump allows the use of n-channel mosfets ? power good and over current latch indicators ? enhanced over current sensitivity available ? redundant power on controls ? adjustable turn-on ramp ? protection during turn-on ? two levels of current limit detection provide fast response to varying fault conditions ? less than 1 s response time to dead short ?3 s response time to 200% current overshoot applications ? redundant array of independent disks (raid) system ? power distribution control ? hot plug?, hot swap components ordering information part number temp. range ( o c) package pkg. dwg. # hip1012acb -0 to 70 14 ld soic m14.15 hip1012acb-t -0 to 70 14 ld soic tape and reel m14.15 pinout hip1012a (soic) top view typical application diagram 8 9 10 11 12 14 13 7 6 5 4 3 2 1 3/12vs 3/12vg v dd pwron2 5vg 5vs 3/12visen gnd c pump c tim r ilim pgood 5visen mode/ pwron1 3/12vs 3/12vg m/pon1 pwron2 pgood 5vg 5vs 3/12visen gnd c tim r ilim c pump 5isen v dd hip1012a 12v r load r ilim c tim power on inputs c pump r sense 5v r load r sense 5v or 3.3v optional r filter c filter v dd r gate c gate c gate r gate data sheet august 2003
2 simplified block diagram 2v v dd 12vg 12vs 12isen 5vg 5vs 5isen gnd pwron1 c tim pgood r ilim c pump pwron2 qpump 100 a rising enable v dd r r s qn q por clim 3x enable oc 10 a optional falling edge delay r 2r edge reset r filter c filter c pump c tim r ilim 12v to load to load oc optional latch 12vin 5vin 10 a 12v hip1012a c gate 20 ? c gate 20 ? to v dd + - 12v + - r sense + - pgood + - clim 3x enable oc 10 a falling edge delay r 2r 18v + - 18v + - 12v r sense hip1012a
3 pin descriptions pin # symbol function description 1 3v/12vs 3.3 v/12v source connect to source of associat ed external n-channel mosfet switch to sense output voltage. 2 3v/12vg 3.3v/12v gate connect to the gate of associated n-channel mosfet switch. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to 17.4v by a 10 a current source when in 5v/12v mode of operati on, otherwise capacitor will be charged to 11.4v. a small resistor (10 - 200 ? ) should be placed in series with the gate capacitor to ground to prevent current oscillations. 3v dd chip supply connect to 12v supply. this can be either connected directly to the +12v rail supplying the load voltage or to a dedicated v dd +12v supply. if the former is chosen special attention to v dd decoupling must be paid. 4 mode/ pwron1 power on/ reset invokes 3.3v operation when shorted to v dd , pin 3. pwron1 and pwron2 are used to turn-on and reset the chip. both outputs turn-on when either pin is driven low. after a current limit ti me out, the chip is reset by the rising edge of a reset signal applied to either pwron pin. each input has 100 a pull up capability which is compatible with 3v and 5v open drain and standard logic. pwron1 is also used to invoke 3.3v control operation in preference to +12v cont rol. by tying pin 4 to pin 3 the charge pump is disabled and the uv threshold also shifts to 2.8v. 5pwron2 power on/ reset 6 5vg 5v gate connect to the gate of the external 5v n-channel mosfet. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to 11.4v by a 10 a current source. a small resistor (10 - 200 ? ) should be placed in series with the gate capacitor to ground to prevent current oscillations. 7 5vs 5v source connect to the source side of 5v ex ternal n-channel mosfet switch to sense output voltage. 8 5visen 5v current sense connect to the load side of the 5v sense resistor to measure the voltage drop across this resistor between 5vs and 5visen pins. 9 pgood power good indicator indicates that all output voltages ar e within specification. p good is driven by an open drain n-channel mosfet. it is pulled low when any output is not within specification. 10 c tim current limit timing capacitor connect a capacitor from this pin to ground. this capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). the duration of current limit time-out (in seconds) = 200k ? x c tim (farads). 11 c pump charge pump capacitor connect a 0.1 f capacitor between this pin and v dd (pin3). directly connect this pin to v dd when in 3.3v control mode. 12 gnd chip ground 13 r ilim current limit set resistor a resistor connected between this pin and ground determines the current level at which current limit is activated. this curre nt is determined by the ratio of the r ilim resistor to the sense resistor (r sense ). the current at current limit onset is equal to 10 a x (r ilim / r sense ). 14 3v/12visen 3.3v/12v current sense connect to the load side of sense resistor to measure the voltage drop across this resistor. hip1012a
4 absolute m aximum ratings t a =25 o c thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +13.2v 3/12vg, c pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 18.5v 3/12visen, 3/12vs . . . . . . . . . . . . . . . . . . . . . . . -5v to v dd + 0.3v 5visen, 5vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5v to 7.5v pgood, r ilim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7.5v mode/pwron1 , pwron2 , c tim , 5vg . . . . . -0.3v to v dd + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv (class 2) operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . +10.5v to +13.2 temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 12v, c vg = 0.01 f, c tim = 0.1 f, r sense = 0.1 ? , c bulk = 220 f, esr = 0.5 ? , t a = t j = 0 o c to 70 o c, unless otherwise specified parameter symbol test conditions min typ max units 12v control section current limit threshold voltage (voltage across sense resistor) v il12v v il12v r ilim =10k ? r ilim = 5k ? 92 47 100 53 108 59 mv mv 3x current limit threshold voltage (voltage across sense resistor) 3xv il12v 3xv il12v r ilim =10k ? r ilim = 5k ? 250 100 300 165 350 210 mv mv 20% current limit response time (current within 20% of regulated value) 20%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -2- s 10% current limit response time (current within 10% of regulated value) 10%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -4- s 1% current limit response time (current within 1% of regulated value) 1%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -10- s response time to dead short rt short c 12vg = 0.01 f - 500 1000 ns gate turn-on time t on12v c 12vg = 0.01 f-12-ms gate turn-on current i on12v c 12vg = 0.01 f 8 10 12 a 3x gate discharge current 3xdisi 12vg = 18v 0.5 0.75 - a 12v under voltage threshold 12v vuv 10.5 10.8 11.0 v qpumped 12vg voltage v12vg c pump = 0.1 f 16.8 17.3 17.9 v 3.3v/5v control section current limit threshold voltage (voltage across sense resistor) v il5v r ilim =10k ? r ilim = 5k ? 92 47 100 53 108 59 mv mv 3x current limit threshold voltage (voltage across sense resistor) 3xv il5v r ilim =10k ? r ilim = 5k ? 250 100 300 155 350 210 mv mv 20% current limit response time (current within 20% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -2- s 10% current limit response time (current within 10% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -4- s 1% current limit response time (current within 1% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -10- s response time to dead short rt short c vg = 0.01 f - 500 800 ns gate turn-on time t on5v c vg = 0.01 f-5-ms hip1012a
5 hip1012a descripti on and operation the hip1012a is a multi featured dual power supply distribution controller, including programmable current limiting regulation and time to latch off. additionally the hip1012a operates both as a +3.3v and 5v or a +5v and +12v power supply controller with each mode having appropriate under voltage (uv) fault notification levels. upon initial power up hip1012a can either isolate the voltage supply from the load by holding the external n-channel mosfet switches off or apply the supply rail voltage directly to the load for true hot swap capability. in either case the hip1012a turns on in a soft start mode protecting the supply rail fr om sudden current loading. if either pwron pin is pulled low the hip1012a will be in true hot swap mode. both pwron pins must be high to turn off the hip1012a thus is olating the power supply from the load through the external fets. at turn-on, the gate capacitor of each external n-channel mosfet is charged with a 10 a current source. these capacitors create a programm able ramp (soft turn-on). a charge pump supplies the gate drive for the 12v supply switch driving that gate to 17v. the load currents pass through two external current sense resistors. when the voltage ac ross either resistor exceeds the user programmed over current (oc) voltage threshold value, (see table 1) the cont roller enters current regulation. at this time the time-out capacitor, c tim , starts charging with a 10 a current source and the controller enters the time out period. the length of the time out period is set by the single external capacitor (see table 2) placed from the c tim pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external n-channel mosfet. once c tim charges to 2v, an internal comparator is tripped resulting in both n-channel mosfets being latched off. gate turn-on current i on5v c vg = 0.01 f 8 10 12 a 3x gate discharge current 3xdisi c vg = 0.01 f, pwron = low 0.5 0.75 - a 5v under voltage threshold 5v vuv 4.35 4.5 4.65 v 3.3v under voltage threshold 3.3v vuv 2.65 2.8 2.95 v 3.3/5vg high voltage 3/5vg 11.2 11.9 - v supply current and io specifications v dd supply current i vdd 4810ma v dd por rising threshold 9.5 10.0 10.7 v v dd por falling threshold 9.3 9.8 10.3 v current limit time-out t ilim c tim = 0.1 f162024ms pwron pull-up voltage pwrn_v pwron pin open 1.8 2.4 3.2 v pwron rising threshold pwr_vth 1.1 1.5 2 v pwron hysteresis pwr_hys 0.1 0.2 0.3 v pwron pull-up current pwrn_i 60 80 100 a current limit time-out threshold (c tim )c tim _vth 1.8 2 2.2 v c tim charging current c tim _i 8 10 12 a c tim discharge current c tim _disi 1.7 2.6 3.5 ma c tim pull-up current c tim _disi v ctim = 8v 3.556.5ma r ilim pin current source output r ilim _io 90 100 110 a charge pump output current qpmp_io c pump = 0.1 f, c pump = 16v 320 560 800 a charge pump output voltage qpmp_vo no load 17.2 17.4 - v charge pump output voltage - loaded qpmp_vio load current = 100 a 16.2 16.7 - v charge pump por rising threshold qpmp+vth 15.6 16 16.5 v charge pump por falling threshold qpmp-vth 15.2 15.7 16.2 v electrical specifications v dd = 12v, c vg = 0.01 f, c tim = 0.1 f, r sense = 0.1 ? , c bulk = 220 f, esr = 0.5 ? , t a = t j = 0 o c to 70 o c, unless otherwise specified (continued) parameter symbol test conditions min typ max units hip1012a
6 the hip1012a responds to a l oad short (defined as a current level 3x the oc set point) immediately, driving the relevant n-channel mosfet gate to 0v in less than 10 s. the gate voltage is then slowly ramped up turning on the n-channel mosfet to the programmed current limit level, this is the start of the time out period. the programmed current level is held until either the oc event passes or the time out period expires. if the former is the case then the n-channel mosfet is fully enhanced and the c tim charging current is diverted away from the capac itor. if the time out period expires prior to oc resolution then both gates are quickly pulled to 0v turning off both n-channel mosfets simultaneously. upon any uv condition the pgood signal will pull low when tied high through a resistor to the logic supply. this pin is a fault indicator but not the oc latch off indicator. for an oc latch off indication, monitor ctim, pin 10. this pin will rise rapidly to 12v once the time out period expires. see simplified block diagram on page 2 for oc latch off circuit suggestion. the hip1012a is reset by a rising edge on either pwron pin and is turned on by either pwron pin being driven low. the hip1012a can control either +12v/5v or +3.3v/+5v supplies. tying the pwron1 pin to v dd , invokes the +3.3v/+5v voltage mode. in this mode, the external charge pump capacitor is not needed and cpump, pin 11 is tied directly to v dd . hip1012a applicati on considerations current regulation vs. current trip often causes confusion when using this and other ics wi th a current regulation (cr) feature. the cr level is the level at which the hip1012 will hold an over current load at fo r the programmed duration. this level is programmable by the rlim and rsense resistors values. as the current being monitored by the hip1012a approaches a level >85% of the cr level the hip1012a may trip-off due to variances in manufacturing and the design of the low gain high speed input comparators. in addition with the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current limiting level is crucial to provide both pr otection and still allow for this inrush current without latching off. consider this in addition to the time out delay when choosing mosfets for your design. to these ends it is suggested t hat cr levels be programmed to 150% of nominal load. when using the hip1012a in the 12v and 5v mode additional v dd decoupling may be necessary to prevent a power on reset due to a sag on v dd pin upon an oc latch off. the addition of a capacitor from v dd to gnd may often be adequate but a small value isolation resistor may also be necessary, see the simplified block diagram on page 2. current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. as the hip1012a drives a hi ghly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. a simple method to enhance stability is provided by the substitution of a larger value gate resistor. typically this situation can be avoided by eliminating long point to point wiring to the load. random resets occur if the hip1012a sense pins are pulled below ground when turning off a highly inductive load. place a large load capacitor (10-50 f) on the output or isen clamping diodes to ground to eliminate. during the time out delay period with the hip1012a in current limit mode, the v gs of the external n-channel mosfets is reduced driving th e n-channel mosfet switch into a high r ds(on) state. thus avoid extended time out periods as the external n-channel mosfets may be damaged or destroyed due to excessive internal power dissipation. refer to the mosfet manufacturers data sheet for soa information. external pull down resistors from the xisen pins to ground will prevent the voltage output s from floating up due to leakage current through the external switch fet body diode when the fets are disabled and the outputs are open. physical layout of rsense resistors is critical to avoid the possibility of false over curr ent occurrences. ideally trace routing between the rsense re sistors and the hip1012a is direct and as short as possible with zero current in the sense lines as shown below . table 1. r ilim resistor nominal oc vth 15k ? 150mv 10k ? 100mv 7.5k ? 75mv 4.99k ? 50mv note: nominal oc vth = rilim x 10 a. table 2. c tim capacitor nominal time out period 0.022 f4.4ms 0.047 f9.4ms 0.1 f 20ms note: nominal time-out period in seconds = c tim x 200k ?. correct to isen and current sense resistor incorrect figure 1. sense resistor pcb layout r iset hip1012a
7 typical performance curves figure 2. supply current figure 3. r ilim source current figure 4. c tim current source figure 5. c tim oc voltage threshold figure 6. 12v uv threshold figure 7. 5v/3.3v uv threshold 8.2 8.0 7.8 7.6 7.4 7.2 -40 -200 20406080 temperature ( o c) 8.4 supply current(ma) -30 -10 10 30 50 70 104 103 -40 -20 0 20 40 60 80 102 70 50 30 10 -10 -30 105 temperature ( o c) current ( a) -40 -20 0 20 40 60 -30 -10 10 30 50 70 80 10.7 10.6 10.5 10.4 10.3 c tim current source ( a) temperature ( o c) -40 -20 0 20 40 60 -30 -10 10 30 50 70 80 2.04 2.02 2.00 1.98 1.96 1.94 c tim oc voltage threshold (v) temperature ( o c) temperature ( o c) 12v uv threshold (v) 20 40 60 80 -40 -20 0 11.00 10.98 10.96 10.94 3.3v uv 20 40 60 80 -40 -20 0 4.615 4.610 4.605 4.600 4.595 2.888 2.886 2.884 2.882 2.880 temperature ( o c) 5v uv threshold (v) 3.3v uv threshold (v) 5v uv hip1012a
8 figure 8. 12v, 3/5v gate drive figure 9. pump voltage figure 10. oc voltage threshold with r lim = 5k ? figure 11. oc voltage threshold with r lim = 10k ? figure 12. power on reset voltage threshold typical performance curves (continued) 12v vg 3.3v, 5v vg 20 40 60 80 -40 0 -20 17.36 17.34 17.32 17.30 17.28 17.26 11.935 11.930 11.925 11.920 11.915 11.910 11.905 11.900 temperature ( o c) 3.3v, 5v gate drive (v) 12v gate drive (v) 20 40 60 80 -40 0 -20 voltage (v) temperature ( o c) 17.6 17.4 17.2 16.8 16.6 17.0 charge pump voltage no load charge pump voltage 100 a load 20 40 60 80 -40 0 -20 temperature ( o c) voltage threshold (mv) 54.5 54.0 53.5 53.0 52.5 12 oc vth 5 oc vth 20 40 60 80 -40 0 -20 voltage threshold (mv) 12 oc vtth 5 oc vth temperature ( o c) 102.5 102.0 101.5 101.0 100.5 -40 -20 0 20 40 60 80 -30 -10 10 30 50 70 10.2 10.0 9.8 9.6 power on reset (v) temperature ( o c) v dd low to high v dd high to low hip1012a
9 exploring and using the hip1012eval1 board (figures 13 and 14) the hip1012eval1 is a flexib le platform for a thorough evaluation of the hip1012a dual power supply controller. this eval board comes in three separate parts allowing the evaluation of two principal c onfigurations. to simulate a passive back plane implementation both the generic and load sections are first conne cted together and then the generic board is connected onto the bus board. for an active backplane or for the hip1012a on an interposer board configuration, the bus and generic sections are first connected together and then the load board is connected onto the generic board. the hip1012eval1 board has m any built in features besides the configuration fl exibility described above. the bus board is designed so that adding suitable connectors and/or power supply capacitive filtering is very easy to do through the numerous through holes for each rail voltage and ground. passive backplane power sequencing can be simulated by simply shortening the finger lengths for the rail(s) that need to come up after initial ground connection is made. the generic board, is a flexible evaluation platform with many designed in features for user customizing and evaluation. the circuit is shi pped default configured in the 3.3v and 5v controller mode by jumpers for easy reconfiguration (see table 3 fo r jumper settings). the default configuration is highlighted in table 3. the default oc levels are 5a on the 3.3v and 1a on the 5v supplies. to operate the hip1012 generic board in its default configuration (3v and 5v) a dedicated +12v power supply must be provided for the hip1012 through tie point, w1 on the generic board. to operate the board in the +12v and 5v mode, jp2 and jp3 need to be reconfigured (see table 3) and a suitable current load needs to be provided. a programmable electronic current load is an e xcellent evaluation tool for this device. the load board is configured to sink about 3 1a at 3.3v. for 12v operation, the load must be modified to sink less than 5a, otherwise, an oc failure upon power will occur. the generic board is provided with a single pair of n- channel mosfets, if currents > 6a are to be evaluated then an additional pair of mosfets can be installed in the provided space to reduce distribution losses. additionally for even higher current evaluations space for to-252aa, dpak or d 2 pak devices has been provided. tie points on the output side of the generic board are provided for direct access to a high current load. performance customizing can easily be accomplished by substitution/addition of several smd components to the existing layout or by utilizing the included bread board area. see table 5 for the component listing and applicable formulae. the load board, consists of four load switches, output resistive and capacitive loads and output on indicating led?s. the resistive loads are configured so that either no current, a low or high current load relative to the oc trip point can be invoked for both supplies. an oc event can be emulated by switching both switch es of any one output to the on position (see table 4, oc conditions highlighted). load connection sequencing can be do ne by shorting the desired finger lengths. as noted, t he generic board is default configured for 3v and 5v ope ration. for 12v evaluation replace rl3 and rl4 with a suitable load. table 3. jumper configuration jp # open / short circuit condition 1 short to gnd 2-3 pwron2 shorted to ground. true hot swap mode. pwron1 only controls reset with rising edge. 1 short to 5v 1-2 pwron2 shorted to 5v. reset and turn on controlled only by pwron1 . single input control mode 1 open pwron2 will be internally pulled high to ~2.5v, compatible with logic signal. the hip1012a can not turn on until pwron2 is driven low. 2 open hip1012a must be powered from a dedicated +12v power supply. 2 short hip1012a v dd pin connected to same 12v supply as load. see de coupling concerns in critical items section. 3 open c1 in circuit. charge pump capacitor necessary for 5v and 12v operating mode to develop ~ 11.7v for 12vg voltage. 3 short shorts across charge pump capacitor, c1. capacitor not needed in 3v and 5v mode. 4 short to gnd 1-2 hip1012a mode/pwron1 shorted to ground. true hot swap mode. pwron2 rising edge only resets hip1012a. 4 short to 5v 2-4 mode/pwron1 shorted to 5v. pwron2 only single mode control. 4 short to v dd 2-3 hip1012a mode/pwron1 connected to v dd pin. this along with jp3 installed invokes and configures hip1012a for 3v and 5v operation. controlled by pwron2 4 open hip1012a mode/pwron1 will be internally pulled high to ~2.5v, compatible with logic. redundant controller mode when each pwron pin is driven by separate signals. table 4. load current sw13 sw14 3.3v i out asw11sw12 5.0v i out a 000000 012010.5 104100.74 1 1 6 1 1 1.24 hip1012a
10 note: test point number equals hip1012a pin number. generic board load board bus board figure 13. 3/12vs 1 3/12vg 2 v dd 3 mode/ 4 pwron2 5 5vg 6 5vs 7 3/12isen 14 rilim 13 gnd 12 cpump 11 ctim 10 5visen 8 pgood 9 u1 hip1012a pwron1 c 3 r 1 c 2 r 5 3 /12vin gnd gnd 5v in v dd 3 / 12vout gnd gnd 5vout jp1 jp2 r 2 r 4 c 1 c 4 q 1 q 2 1 r 3 cec1 cec2 jp3 jp4 led1 r 101 c 5 100m ? 20m ? 20 ? 10k ? 20 ? 0.1 f 0.047 f 0.01 f 0.01 f 0.1 f rl1 rl2 rl3 rl4 sw13 sw14 sw11 sw12 r102 cef cef 9,11, cef 1,2,3 cef 4,5,6, 7,8,10 r103 led3 led2 0.8 ? 1.6 ? 7 ? 10 ? 12 3.3/12vin bj1 gnd bj2 gnd bj3 5vin bj4 1 cef 9,11,12 cef 1,2,3 cef 4,5,6 7,8,10 input cef hip1012a
11 figure 14. hip1012eval1 eval board hip1012a
12 table 5. hip1012eval1 board component listing component designator component name component description generic board u1 hip1012cb or hip1012acb intersil corporation, dual power controller q1, q2 rf1k49156, si4404dy n-channel mosfet in 8 soic or equivalent replacement qxb and qxc not populated mounting areas for additional 8 soic , dpak or d 2 pak packaged mosfets r 1 5v sense resistor 100m ?, 1 %, metal strip current sensing resistor r 2 3.3v/12v sense resistor 20m ?, 1 %, metal strip current sensing resistor r 3 , r 4 loop compensation resistors 20 ? , resistor in series with gate ca pacitor. this rc may be necessary to provide current loop stability. keep resistor < 50 ? . r 5 current limit set resistor 10k ? , current limit = ~10 a x (r ilim / r sense ). r* isolation resistor (not provided, see decoupling concerns in critical items section) add resistor (<50 ? ) to isolate v dd from load transients if necessary to eliminate random v dd low reset. cut short to install. c 3 , c 4 gate timing capacitors 0.01 f, 10 a charging i source provides slow ramp on of n-channel mosfets c 1 charge pump capacitor 0.1 f, charge pump capacitor necessary for +12v and +5v operation. c 2 time-out set capacitor 0.047 f, provides ~9ms of time-out period prior to latch off during which ioc can be resolved. the duration of current limit time-out (in seconds) = 200k ? x c tim (farads). c 5 vdd decoupling capacitor 0.1 f, provides v dd decoupling jp1 jp2 jp3 jp4 jumper to configure pwron2 jumper to configure vdd jumper to configure charge pump cap jumper to configure pwron1 see table 3 for jumper c onfiguration descriptions led1 pgood indicator lit indicates a fault condition w1 not provided tie point for dedicated +12v hip1012 supply, use in default configuration tp1 - tp14 test points for hip1012 pin 1 to pin 14 p1 - p2 edge connector fingers modify edge co nnector finger lengths for power sequencing load board sw11 and rl1 5v high load (7 ? ) switch and load resistor pair to invoke high current load on 5v sw12 and rl2 5v low load (10 ? ) switch and load resistor pair to invoke low current load on 5v sw13 and rl3 3.3v high load (0.8 ? ) switch and load resistor pair to invoke high current load on 3.3v sw14 and rl4 3.3v low load (1.6 ? ) switch and load resistor pair to invoke low current load on 3.3v led2, led3 load ?hot? indicators lit indicates n-channel mosfets are on and loads are hot bus board bus interconnect board hip1012a
13 hip1012 evaluati on circuit for disk drive hot swap hip1012eval2 introduction the hip1012eval2 is specifically designed to test and demonstrate hot swapping of disk drives onto passive 12v and 5v power buses using the hip1012 hot-swap control ic. the small size of the board allows it to be included in a shuttle alongside the disk drive during evaluation. the outlined area on the board represents the actual area used for pcb implementation. description the hip1012eval2 board is provided with a standard molex four-terminal disk-drive power connector. the solder holes j2 allows the board to be connected to a power supply connector on the disk-driv e shuttle. pg ood, pwron1 , pwron2 , 5vg. 12vg, ctim, v dd and gnd are all accessible through a ribbon cable. with jp1 installed, the hip1012 is powered from the same 12v power supply as the disk drive motor. jp2 connects the control signal pwron2 to ground allowing the unit to be plugged directly into the power bus for automatic, controlled start up. in this configuration, pwron1 is available to reset the hip1012 in case of an over-current trip. otherwise the hip1012 can be reset by toggling the voltage on v dd . with jp2 removed, the circuit is controlled using one or both of the pwron signal lines. the hip1012eval2 is shipped with both jumpers installed. the hip1012eval2 is configured with a 10k ? rilim resistor (r 5 ) setting the nominal curr ent limit threshold to 100mv. the 12v current sense resistor (r 2 ) is 20m ? and the 5v current sense resistor (r 1 ) is 100m ?. these values set the nominal current limits to 5a and 1a respectively. the c tim capacitor (c 2 ) sets the time out period to approximately 9ms. control connections, fault notification, and test points hip1012 eval2 is shipped with jp2 installed so that a connected disk drive is star ted simply by connecting 12v and 5v power supplies to j2. in this configuration, the ribbon cable is not necessary , since the hip1012 can be reset by toggling the voltage on v dd . this configuration represents a disk dr ive that would be removed after any over-current trip and wo uld start immediately upon insertion. additional control is available using the ribbon cable and resetting the hip1012 by applying a rising edge to pwron1 . if redundant control is desired, removing jp2 makes the second control signal pwron2 available to start or reset the chip. an example of this control configuration would be to turn the chip on using pwron1 and reset it using pwron2 . the pgood pin is an open drain logic output which can be tied high through a resistor for fault indication. upon detection of either over-current or under-voltage fault conditions, pgood goes low and remains low until the fault condition is cleared. also included on the ribbon cable are additional monitor points for 12vg, 5vg and c tim . these are included for monitoring during evaluation and they are not necessary for operation. data line considerations the hip1012a does not integr ate data bus line switches, although control of the data bus can be assisted by the time- out feature of the hip1012a. du ring the time-out period, the operating system software can determine whether to halt i/o activity to a disk drive which is undergoing an under-voltage or over-current fault as indi cated by the status of pgood. hip1012a
14 1 2 3 4 5 6 7 14 13 12 11 10 8 9 u1 hip1012 c 3 0.01 f r 1 0.1 ? 1% c 2 0.047 f r 5 10k ? 1% 12v in gnd gnd 5v in v dd 12vg ctim pwron1 12v out gnd gnd 5v out jp2 jp1 r 2 0.020 ? 1% r 4 , 20 ? 1% c 1 , 0.1 f c 4 , 0.01 f q1 rf1k49157 q2 rf1k49157 j1 1 1 pwron2 pgood 5vg gnd r 3 , 20 ? 1% c 5 0.1 f r 6 10 ? 1% figure 15. hip1012 evaluation circuit schematic and photo for disk drive hot plug j2 3/12vs 3/12vg v dd mode/ pwron2 5vg 5vs 3/12isen rilim gnd cpump ctim 5visen pgood pwron1 hip1012a
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hip1012a small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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