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vishay siliconix dg9432, dg9433, dg9434 document number: 72311 s11-1029-rev. b, 23-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 low-voltage dual spst analog switch features ? wide operation voltage (+ 2.7 v to + 12 v) ? low charge injection - q inj : 1 pc ? low power consumption ? ttl/cmos logic compatible over the full operating voltage range ? available in msop-8 and sot23-8 ? compliant to rohs directive 2002/95/ec benefits ? reduced power consumption ? simple logic interface ? high accuracy ? reduce board space applications ? battery operated systems ? portable test equipment ? sample and hold circuits ? cellular phones ? communication systems ? military radio ? pbx, pabx guidance and control systems description the dg9432, dg9433, dg9434 is a dual single-pole/single- throw monolithic cmos analog switch designed for high performance switching of analog signals. combining low power, high speed (t on : 25 ns, t off : 20 ns), the dg9432, dg9433, dg9434 is ideal for portable and battery powered applications requiring high per formance and efficient use of board space. the dg9432, dg9433, dg9434 is built on vishay siliconix?s low voltage bcd-15 process. an epitaxial layer prevents latchup. break-before-make is guaranteed for dg9432, dg9433, dg9434. each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. functional block diagram and pin configuration - dg9432 nc 1 v+ com 1 dg9432, msop-8 in 1 in 2 com 2 gnd nc 2 1 2 3 4 8 7 6 5 top view device marking: 9432 nc 1 com 1 v+ dg9432, sot23-8 in 1 in 2 gnd com 2 nc 2 1 2 3 4 8 7 6 5 top view device marking: 4g truth table dg9432 logic switch 0on 1off
www.vishay.com 2 document number: 72311 s11-1029-rev. b, 23-may-11 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram and pin configuration - dg9433/dg9434 dg9433, msop-8 no 1 v+ com 1 in 1 in 2 com 2 gnd no 2 1 2 3 4 8 7 6 5 top view device marking: 9433 no 1 com 1 v+ dg9433. sot23-8 in 1 in 2 gnd com 2 no 2 1 2 3 4 8 7 6 5 top view device markin g : 4h truth table dg9433 logic switch 0off 1on no v+ com 1 dg9434, msop-8 in 1 in 2 com 2 gnd nc 2 1 2 3 4 8 7 6 5 top view device marking: 9434 no 1 com 1 v+ dg9434. sot23-8 in 1 in 2 gnd com 2 nc 2 1 2 3 4 8 7 6 5 top view device markin g : 4i truth table dg9434 logic switch-1 switch-2 0offon 1onoff ordering information temp. range package part number - 40 c to 85 c msop-8 dg9432dq-t1-e3 dg9433dq-t1-e3 dg9434dq-t1-e3 sot23-8 DG9432DS-T1-E3 dg9433ds-t1-e3 dg9433ds-t1-e3
document number: 72311 s11-1029-rev. b, 23-may-11 www.vishay.com 3 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6.5 mw/c above 75 c. notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datas heet. d. guarantee by design, not subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 12 v leakage testing, not production tested. g. applies for dg9434 only. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 13.5 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 10 ma peak current (pulsed at 1 ms, 10 % duty cycle) 20 storage temperature (d suffix) - 65 to 150 c power dissipation (packages) b msop-8 c 320 mw sot23-8 c 515 specifications v+ = 3 v parameter symbol test conditions otherwise unless specified v+ = 3.3 v, 10 % , v in = 0.4 v or 1.8 v e temp. a limits - 40 c c to 85 c unit min. c typ. b max. c switch on resistance analog signal range e v analog full v- v+ v drain-source on- resistance r (on) v+ = 2.7 v, i com = 1 ma, v com = 1.5 v room full 81 100 120 ? r on match d ? r on room 0.4 3.0 digital control input, high voltage v inh v+ ranges 2.7 to 5 v full 1.8 v input, low voltage v inl full 0.4 input current i inh - 1 1 a dynamic characteristics break-before-make d,g t open v+ = 3 v, r l = 300 ? v no = v nc = 1.5 v c l = 35 pf, v in = 0 v, 3 v room full 1 tu r n - o n t i m e d t on room full 60 80 100 ns turn-off time d t off room full 14 25 35 charge injection d q c l = 1 nf, r gen = 0 ? , v g = 0 v room 0.16 pc off-isolation d oirr c l = 5 pf, r l = 50 ? , f = 1 mhz room 77 db c l = 5 pf, r l = 50 ? , f = 10 mhz room 55 crosstalk d x ta l k r l = 50 ? , f = 1 mhz, v+ = 2.5 v room 98 source off capacitance d c no/nc(off) f = 1 mhz, v nc/no = 0 v room 7.5 pf drain off capacitance d c com(off) f = 1 mhz v com = 0 v room 7.8 drain on capacitance d c com(on) room 22 supply current i+ v+ = 3.3 v, v in = 0 or v+ room - 1 - 1 a
www.vishay.com 4 document number: 72311 s11-1029-rev. b, 23-may-11 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. guarantee by design, not subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 12 v leakage te sting, not production tested. g. applies for dg9434 only. specifications v+ = 5 v parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 % , v in = 0.4 v or 1.8 v e temp. a limits - 40 c c to 85 c unit min. c typ. b max. c switch on resistance analog signal range e v analog full v- v+ v drain-source on-resistance r (on) v+ = 4.5 v, i com = 1 ma v com = 2.5 v or 3.5 v room full 39 60 70 ? r ds(on) match ? r (on) v+ = 4.5 v, i com = 1 ma, v com = 3.5 v room 0.3 3.0 switch off leakage current f i nc/no(off) v+ = 5 v, v com = 0.5 v, 4.5 v v nc/no = 4.5 v, 0.5 v room full - 1 - 10 0.3 1 10 na i com(off) room full - 1 - 10 0.3 1 10 channel on leakage current f i com(on) room full - 1 - 10 0.3 1 10 digital control input, high voltage v inh v+ ranges 2.7 to 5 v full 1.8 v input, low voltage v inl full 0.4 input current i inh - 1 1 a dynamic characteristics break-before-make d,g t open v+ = 5 v, r l = 300 ? v no = v nc = 3 v c l = 35 pf, v in = 0 v, 5 v room full 1 ns tu r n - o n t i m e t on room full 33 60 70 turn-off time t off room full 10 20 30 charge injection d q c l = 1 nf, r gen = 0 ? , v g = 0 v room 0.56 pc off-isolation d oirr c l = 5 pf, r l = 50 ? , f = 1 mhz room 76 db c l = 5 pf, r l = 50 ? , f = 10 mhz, v+ = 5 v room 54 crosstalk d x ta l k r l = 50 ? , f = 1 mhz, v+ = 5 v room 96 source off capacitance d c nc/no(off) f = 1 mhz, v nc/no = 0 v room 7.5 pf drain off capacitance d c com(off) f = 1 mhz, v com = 0 v room 7.8 drain on capacitance d c com(on) room 22 supply current i+ v+ = 5.5 v, v in = 0 or v+ room - 1 - 1 a
document number: 72311 s11-1029-rev. b, 23-may-11 www.vishay.com 5 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datas heet. d. guarantee by design, not subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 12 v leakage testing, not production tested. g. applies for dg9434 only. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications v+ = 12 v parameter symbol test conditions otherwise unless specified v+ = 12 v, 10 % , v in = 0.8 v or 2.4 v e temp. a limits - 40 c c to 85 c unit min. c typ. b max. c switch on resistance analog signal range e v analog full v- v+ v drain-source on-resistance r (on) v+ = 10.8 v, i com = 1 ma, v com = 9 v room full 19 30 40 ? r ds(on) match ? r (on) room 0.3 3.0 switch off leakage current a i nc/no(off) v+ = 12 v, v s = 1/11 v, v com = 11/1 v room full - 1 - 10 0.3 1 10 na i com(off) room full - 1 - 10 0.3 1 10 channel on leakage current a i com(on) room full - 1 - 10 0.3 1 10 digital control input, high voltage v inh v+ = 12 v full 2.4 v input, low voltage v inl full 0.8 input current i inh - 1 1 a dynamic characteristics break-before-make d,g t open v+ = 12 v, r l = 300 ? v no = v nc = 8 v c l = 35 pf, v in = 0 v, 12 v room full 1 ns tu r n - o n t i m e t on room full 21 35 40 turn-off time t off room full 618 25 charge injection d q c l = 1 nf, r gen = 0 ? , v g = 0 v, v+ = 5 v room 0.36 pc off-isolation d oirr c l = 5 pf, r l = 50 ? , f = 1 mhz room 75 db c l = 5 pf, r l = 50 ? , f = 10 mhz room 53 crosstalk d x ta l k r l = 50 ? , f = 1 mhz, v+ = 5 v room 96 source off capacitance d c no/nc(off) f = 1 mhz, v nc/no = 0 v room 7.5 pf drain off capacitance d c com(off) f = 1 mhz, v com = 0 v room 7.8 drain on capacitance d c com(on) room 22 supply current i+ v+ = 12 v, v in = 0 or v+ room - 1 - 1 a
www.vishay.com 6 document number: 72311 s11-1029-rev. b, 23-may-11 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r on vs. v com and single supply voltage leakage current vs. temperature switching time vs. temperature 0 20 40 60 80 100 120 024681012 v com - analog voltage (v) r on - on-resistance ( ) t = 25 c i s = 1 ma v+ = 5 v v+ = 2.5 v v+ = 10 v v+ = 12 v - 60 - 40 - 20 0 20 40 60 80 100 leakage current (pa) temperature ( c) 100 10 1 v+ = 12 v i com(on) i no(off) i com(off) 0 20 40 60 80 100 - 60 - 40 - 20 0 20 40 60 80 100 t on , t off - switching time (ns) temperature ( c) t on v+ = 2.5 v t off v+ = 2.5 v t on v+ = 5 v t off v+ = 5 v r on vs. analog voltage and temperature leakage current vs. analog voltage supply current vs. temperature 0 25 50 75 100 125 150 024681012 r on - on-resistance ( ) v com - analog voltage (v) a b c c a = 85 c b = 25 c c = - 40 c i com = 1 ma v+ = 2.5 v v+ = 12 v a b c v+ = 5 v a b - 200 - 150 - 100 - 50 0 50 100 150 200 024681012 v com , v no , v nc - analog voltage leakage current (pa) i com(on) i no(off) /i nc(off) i com(off) - 60 - 40 - 20 0 20 40 60 80 100 1000 10 0.1 i+ - supply current (pa) temperature ( c) 1 100 v+ = 5 v v in = 0 v
document number: 72311 s11-1029-rev. b, 23-may-11 www.vishay.com 7 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) switching threshold vs. supply voltage insertion loss, off isolation and crosstalk vs. frequency 0.0 0.5 1.0 1.5 2.0 2.5 02468101214 v+ - supply voltage v t - switching threshold 100k - 120 1m - 20 20 - 40 100m 1g frequency (mhz) loss (db) crosstalk insertion loss - 3 db = 260 mhz 10m 0 - 80 - 60 v+ = 3 v, 5 v r l = 50 oirr - 100 charge injection at source supply current vs. input switching frequency - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 - 0.0 0.2 0.4 0.6 0.8 0123456 q inj (pc) v com - analog voltage (v) v + = 2.5 v v + = 5 v 0 200 400 600 800 1000 input switching frequency i+ supply current (a) 2m 4m 0 6m 8m 10m
www.vishay.com 8 document number: 72311 s11-1029-rev. b, 23-may-11 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 1. switching time switc h input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logi c input r l 300 v out gnd v+ 50 % 0 v 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output 0.9 x v out t r < 20 ns t f < 20 ns v out =v com r l r l +r on figure 2. break-before-make interval c l (includes fixture and stray capacitance) no or nc v 1 no or nc v 2 0 v 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d com 1 v+ gnd v+ c l 35 pf r l 300 com 2 figure 3. charge injection off on on in v out v out q = v out x c l c l com r gen v out nc or no 3 v in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. +
document number: 72311 s11-1029-rev. b, 23-may-11 www.vishay.com 9 vishay siliconix dg9432, dg9433, dg9434 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72311 . figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v nc/ no v com r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71244 12-jul-02 www.vishay.com 1 msop: 8?leads jedec part number: mo-187, (variation aa and ba) n = 8l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.25 - 0.38 8 b 1 0.25 0.30 0.33 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.65 bsc e 1 1.95 bsc l 0.40 0.55 0.70 4 n 8 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
e1 d e1 e e b c l c l c l c l a1 a2 a -a- -a- 0.10 e1 c 0.20 datum a notes: 1. all dimensions are in millimeters. 2. foot length measured at intercept point between datum a and lead surface. 3. package outline exclusive of mold flash and metal burr. 4. package outline inclusive of solder plating. 5. no molding flash allowed on the top and bottom lead surface. 2 l package information vishay siliconix document number: 72207 09-apr-03 www.vishay.com 1 sot?23 : 8?lead millimeters inches dim min nom max min nom max a 0.90 1.27 1.45 0.035 0.05 0.057 a1 0.00 0.0762 0.15 0.000 0.003 0.006 a2 0.90 1.20 1.30 0.035 0.047 0.051 b 0.22 0.30 0.38 0.009 0.012 0.015 c 0.09 0.152 0.20 0.004 0.006 0.008 d 2.80 2.9 3.00 0.11 0.114 0.118 e 2.60 2.8 23.00 0.102 0.11 0.118 e1 1.50 1.65 1.75 0.059 0.065 0.069 e 0.65 ref 0.026 ref e1 1.95 ref 0.077 ref l 0.35 0.45 0.55 0.014 0.018 0.022 0 4 8 0 4 8 ecn: c-03085?rev. a, 07-apr-03 dwg: 5895
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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