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integrated circuit systems, inc. general description features ics9179-03 0258k 12/15/08 block diagram pentiumpro is a trademark of intel corporation i 2 c is a trademark of philips corporation low skew fan out buffers pin configuration the ics9179-03 generates low skew clock buffers required for high speed risc or cisc microprocessor systems such as intel pentiumpro. outputs will handle up to 133mhz clocks. an output enable is provided for testability. the device is a buffer with low output to output skew. this is a fanout buffer device, not using an internal pll. this buffer can also be a feedback to an external pll stage for phase synchronization to a master clock. there are a total of ten outputs, sufficient for feedback to a pll source and to drive four small outline dimm modules (s.o. dimm) at 2 clocks each. or a total of ten outputs as a fanout buffer from a common clock source. the individual clock outputs are addressable through i 2 c to be enabled, or stopped in a low state for reduced emi when the lines are not needed. ? ten high speed, low noise non-inverting buffers for (to 133mhz), clock buffer applications. ? output slew rate faster than 1.5v/ns into 20pf ? supports up to four small outline dimms (s.o. dimm). ? synchronous clocks skew matched to 250 ps window on outputs (0:9). ? i 2 c serial configuration interface to allow individual outputs to be stopped low. ? multiple vdd, vss pins for noise reduction ? tri-state pin for testing ? 3.0v ? 3.7v supply range ? 28-pin (209 mil) ssop and (6.1mm) tssop package 28-pin ssop & tssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9179-03 0258k 12/15/08 pin descriptions power groups vdd (0:5), gnd (0:5) = power supply for output buffer vddi, gndi = power supply for i 2 c circuitry r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 3 , 2) 1 : 0 ( t u p t u ot u os t u p t u o k c o l c 1 0 d n g , 0 d d v s e s u , 7 , 6) 3 : 2 ( t u p t u ot u os t u p t u o k c o l c 1 1 d n g , 1 d d v s e s u , 3 2 , 2 2) 5 : 4 ( t u p t u ot u os t u p t u o k c o l c 1 2 d n g , 2 d d v s e s u 7 2 , 6 2) 7 : 6 ( t u p t u ot u ot u p t u o k c o l c 1 3 d n g , 3 d d v s e s u 1 18 t u p t u ot u ot u p t u o k c o l c 1 4 d n g , 4 d d v s e s u 8 19 t u p t u ot u ot u p t u o k c o l c 1 5 d n g , 5 d d v s e s u 9n i _ f u bn is r e f f u b r o f t u p n i 0 2e on i. p u - l l u p l a n r e t n i s a h . w o l d l e h n e h w s t u p t u o l l a s e t a t s - i r t 2 4 1a t a d so / ii r o f n i p a t a d 2 y r t i u c r i c c 3 5 1k l c so / ii r o f n i p k c o l c 2 y r t i u c r i c c 3 , 0 1 , 5 , 1 8 2 , 4 2 , 9 1 ) 5 : 0 ( d d vr w ps r e f f u b t u p t u o r o f y l p p u s r e w o p v 3 . 3 , 2 1 , 8 , 4 5 2 , 1 2 , 7 1 , 6 1 ) 5 : 0 ( d n gr w ps r e f f u b t u p t u o r o f d n u o r g 3 1i d d vr w pi r o f y l p p u s r e w o p v 3 . 3 2 c i g o l l a n r e t n i d n a y r t i u c r i c c 6 1i d n gr w pi r o f d n u o r g 2 c i g o l l a n r e t n i d n a y r t i u c r i c c notes: 1. at power up all ten outputs are enabled and active. 2. oe has a 100k ohm internal pull-up resistor to keep all outputs active. 3. the sdata and sclk inputs both also have internal pull-up resistors with values above 100k ohms as well for complete platform flexibility.
3 ics9179-03 0258k 12/15/08 vdd this is the power supply to the internal core logic of the device as well as the clock output buffers for output (0:9). this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. output (0:9) these output clocks are use to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the outputs output is controlled by the supply voltage that is applied to vdd of the device, operates at 3.3 volts. i 2 c the sdata and sclock inputs are use to program the device. the clock generator is a slave-receiver device in the i 2 c protocol. it will allow read-back of the registers. see configuration map for register functions. the i 2 c specification in philips i 2 c peripherals data handbook (1996) should be followed. buf_in input for fanout buffers (output 0:9). oe oe tristates all outputs when held low. vdd1 this is the power supply to i 2 c circuitry. technical pin function descriptions
4 ics9179-03 0258k 12/15/08 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 6 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read:
5 ics9179-03 0258k 12/15/08 byte 1: output clock register notes: 1 = enabled; 0 = disabled, outputs held low byte 2: output clock register notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b8 11 ) t c a n i / t c a ( 9 t u p t u o 6 t i b1 11 ) t c a n i / t c a ( 8 t u p t u o 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b7 21 ) t c a n i / t c a ( 7 t u p t u o 6 t i b6 21 ) t c a n i / t c a ( 6 t u p t u o 5 t i b3 21 ) t c a n i / t c a ( 5 t u p t u o 4 t i b2 21 ) t c a n i / t c a ( 4 t u p t u o 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r ics9179-03 power management the values below are estimates of target specifications. note: pwd = power-up default serial configuration command bitmaps byte 0: output clock register (default=0) notes: 1 = enabled; 0 = disabled, outputs held low note: pwd = power-up default t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b -1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b 71 3 t u p t u o 2 t i b61 2 t u p t u o 1 t i b31 1 t u p t u o 0 t i b21 0 t u p t u o functionality # e o) 9 : 0 ( t u p t u o 0z - i h 1n i _ f u b x 1 n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m k c o l c o n ) d n g r o 1 d d v - n i _ f u b ( i 2 e v i t c a y r t i u c r i c c a m 3 z h m 6 6 e v i t c a ) z h m 6 6 . 6 6 = n i _ f u b ( a m 0 3 2 z h m 0 0 1 e v i t c a ) z h m 0 0 . 0 0 1 = n i _ f u b ( a m 0 6 3 z h m 3 3 1 e v i t c a ) z h m 3 3 . 3 3 1 = n i _ f u b ( a m 0 6 4
6 ics9179-03 0258k 12/15/08 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. parameter symbol conditions min typ max units input high voltage v i h 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5ua input low current i il v in = 0 v; inputs with no pull-up resistors -5 ua i il v in = 0 v; inputs with 100k pull-up resistors -60 -33 ua i dd1 c l = 0 pf; f in @ 66m 80 120 ma operating i dd2 c l = 0 pf; f in @ 100m 120 180 ma i dd3 c l = 0 pf; f in @ 133m 170 240 ma supply current i dd4 c l = 30 pf; rs=33 ? ; f in @ 66m 180 260 ma i dd5 c l = 30 pf; rs=33 ? ; f in @ 100m 240 360 ma i dd6 c l = 30 pf; rs=33 ? ; f in @ 133m 350 460 ma input frequency f i 1 v d d = 3.3 v; all outputs loaded 10 133 mhz input capacitance c in 1 logic inputs 5 pf 1 guarenteed by design, not 100% tested in production.
7 ics9179-03 0258k 12/15/08 electrical characteristics - outputs t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp v o = v dd *(0.5) 10 24 ? output impedance r dsn v o = v dd *(0.5) 10 24 ? output high voltage v oh i oh = -30 ma 2.3 3 v output low voltage v ol i ol = 23 ma 0.27 0.4 v output high current i o h v oh = 2.0 v -115 -54 ma output low current i ol v ol = 0.8 v 40 57 ma rise time 1 t r v ol = 0.4 v, v oh = 2.4 v 0.5 0.95 1.33 ns fall time 1 t f v oh = 2.4 v, v o l = 0.4 v 0.5 0.95 1.33 ns duty cycle 1 d t v t = 1.5 v 455055% skew 1 t sk v t = 1.5 v 110 250 ps t phl1 v t = 1.5 v 1 5.2 5.5 ns t plh1 v t = 1.5 v 1 5.2 5.5 ns propagation 1,2 t phl2 50% buffer in to 90% out 1 4.3 5 ns t plh2 50% buffer in to 10% out 1 4.3 5 ns t en v t = 1.5 v 1 8 ns t dis v t = 1.5 v 18ns note2: duty cycle of input clock is 47.5% to 52.5%. input edge rate is for propagation delay 1v/ns note1: paramater is guaranteed by design and characterization for all operating frequencies, (10mhz - 133mhz). not 100% tested in production
8 ics9179-03 0258k 12/15/08 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. capacitor values: all unmarked capacitors are 0.01f ceramic
9 ics9179-03 0258k 12/15/08 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information 9179 y f-03lf-t designation for tape and reel packaging lead free, rohs compliant (optional) pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type example: xxxx y f - ppplf - t 209 mil ssop min max min max a--2.00--.079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic
10 ics9179-03 0258k 12/15/08 ordering information 9179 y g-03lf-t designation for tape and reel packaging lead free, rohs compliant (optional) pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop revision designator (will not correlate with datasheet revision) device type example: xxxx y g - ppplf - t index area index area 12 1 n d e1 e sea ting plane sea ting plane a1 a a2 e -c- -c- b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa--0.10--.004 variations min max min max 28 9.60 9.80 .378 .386 10-0038 reference doc.: jedec publication 95, mo-153 in millimeters in inches common dimensions 0.65 basic 0.0256 basic 8.10 basic 0.319 basic n d (inch) see variations see variations d mm. 6.10 mm. body, 0.65 mm. pitch tssop (240 mil) (25.6 mil) symbol see variations common dimensions see variations
11 ics9179-03 0258k 12/15/08 revision history rev. issue date description page # j 8/29/2005 added lf orderin g information. 9, 10 k 12/15/2008 removed ics prefix from orderin g information 9, 10

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