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application note multifrequency and auto-adaptative applications with tda9102c AN638/0194 by jean-michel moreau summary page i horizontal oscillator ............................................ 2 i.1 programming the horizontal open loop frequency . . . . . . . . ....... 2 i.1.1 frequency-to-current converter . . ......................................... 2 i.1.2 programming precision. . . . . . . . . . . . . . . . . . . . . .......... ................... 3 i.2 pll1 holding and capture range . . . . . . ............................. 3 i.3 miscellaneous.............. ....................................... 3 i.3.1 programming of duty factor . . . . . . . ....................................... 3 i.3.2 shifting the phase reference . . . . . . ....................... ................ 4 i.4 calculations. ............. ......................................... 4 i.4.1 frequency-to-current converter . . ......................................... 4 i.4.2 oscillator . . . . . . . . . . . . . ............................. ................... 5 i.4.3 pll1 holding and capture range . . . . . . . . . . . . . . . . . . . . . . ................... 6 ii vertical oscillator ............................................... 6 ii.1 programming the vertical frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ii.2 frequency-to-current converter . . . . ............................. 7 ii.3 frequency programmation . . . . . . . . . . . ............................. 7 ii.4 s - correction . . ................................................... 7 ii.5 automatic control of oscillator amplitude . . . . ................... 7 ii.6 calculations. ............. ......................................... 8 ii.6.1 f v i 12 converter . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 8 ii.6.2 automatic gain control . . . . . . . . . . . ....................... ................ 8 iii sync system .................................... ................... 9 iv x-ray protection .................................................. 9 v demoboard ..................................... ................... 9 in the following pages, we examine how to design variable frequency applications with tda9102c. the design rules will be applied to the calculation of a self-contained, autoadaptive application with characteristics as below : - horizontal frequency 30....90khz - vertical frequency 40....120hz, constant oscilla- tor amplitude - sync signals : ttl levels, positive or negative - vertical s-correction independent of frequency - dc adjustment of horizontal phase and vertical scanning amplitude. further to the tda9102c, one ttl x-or, one quad op-amp and three small signal transistors are used. in the description, reference will be made to the tda 9102c application note by f. grilli, simply quoted as oan540 application noteo. 1/12
i - horizontal oscillator i.1 - programming the horizontal open loop frequency as explained in page 10 of oan540 application noteo, when the first phase-locked loop pll1 is open, the horizontal frequencyis proportionalto the current sunk from pin 1 : open-loop free-running frequency f 0 = 0.375 ? i 1 c17 ? d v c17 : capacitor on pin 2 d v = 4v typ. (in standard application, oscillation takes place between 2.5v and 6.5v) the main sources of discrepancy versus ideal law are two : - a parasitic bias current (about 2.5 m a) which adds to current sunk from pin 1. - the time q needed for comparators to switch from ochargeo to odischargeo and back, which is about 0.5 m s. first cause will be made negligible by choosing a high value for i 1 (not exceeding 1.5ma for max frequency). second cause represents +3% on pe- riod for 64khz, +4.5% for 90khz. if necessary, this can be compensated by introducing a resistor in series with the oscillator capacitor, as will be seen in i-4-2. i.1.1 - frequency-to-current converter if the phase-locked loop pll1 of tda 9102c were able to lock in the whole range 25 to 90khz, it would have a chance to lock on half the sync frequency f h : to avoid this problem,it is necessary to limit the holding range of pll1 to less than 50% and to preprogram the oscillation frequency by sinking from pin 1 a current roughly proportionnal to sync frequency ; then pll1 performs fine tuning. a simple and sufficiently precise (f h i) converter was designed, using the constant amplitude pulse on pin 5, triggered by the horizontal sync pulse. (see schematic figure 6). for every pulse, capaci- tor c29 is fastly charged to a constant voltage, then discharged in an exponential way through r41. taking the average value of the resulting periodic waveform provides a voltage proportional to fre- quency. this is done by the filter r42 - c30. same voltage will be found on r44, thanks to t2 control- led by an op-amp.: consequently r44 will conduct a current proportional to frequency, sinking from pin 1 either through t2 or through r45. when no sync pulse is present, t2 will not conduct; at that moment, the current sunk from pin 1 will be determined by r44 - r45 in series. this corre- sponds to the no-sync free-running frequency. the aboveanalysis is valid only if c29 is completely discharged when next pulse occurs. this in fact is not the case in the present design : the result is that, compared to low frequencies, the late part of the integrated waveform is missing at high frequen- cies : (figure 1). this, combined with the effect described in 1, leads to a less than linear (i 1 f 0 ) characteristic at high frequencies (see figure 3). the way to compensate for this and other second- order effects will be examined in i.4.2. missing area t t a) low frequency b) high frequency 9102036.eps figure 1 multifrequency and auto-adaptative applications 2/12
i.1.2 - programming precision the precision of this converter may be evaluated as follows : - peak voltage on c29 5% - resistors (2) 2% - oscillator thresholds 4% - capacitors (2) 2 ? x% since unprecision, not including capacitors and non linearity, is already 11%, it is advisable to adopt capacitors with 2% precision in order to maintain the necessary adjustment to a reasonable amount. i.2 - pll1 holding and capture range pll1 maintains the oscillator locked by injecting positive or negative current from pin 3 to pin 1 and thus correcting any difference between f h and f 0 . the capture range is narrower than or equal to holding range. the way pll1 works is explained on page 4 of oan540 application noteo and summarized below : each incoming sync pulse triggers an internal sync pulse, of which the duration t 5 is dependant on the value of capacitor on pin 5, c21. during t 5 , a comparator will activate a 4ma sink or source current (depending on the phase error to be recovered); this current, once filtered, is injected into pin 1 for correction purpose. hence the maximum dc correction current avail- able amounts to : t 5 ? f 0 ? 4 ? 10 -3 the ratio of this dc current to the dc programming current sunk from pin 1 gives the relative hold frequencyrange. since the programming current is proportional to frequency, therefore this ratio is constant : the hold frequency range is a constant fraction of programmed frequency : d f f 0 = t 5 ? f 0 ? 4 ? 10 - 3 ? 0.375 f 0 ? c17 ? d v = 0.375 ? t 5 c17 for instance, with c17 = 1nf and t 5 =1 m s, the relative holding range will be 37.5%. the above analysis is valid only if voltage on pin 3 is not clamped, since possible excursion on this pin is 3.5 2v. when clamping occurs, the possible amount of correction depends on r24 : from equa- tion 1, d f 0 = 0.375 c17 ? d v ? 2 r24 = 0.375 2 ? c17 ? 24 in present design, the holding range (limited by clamping at high frequencies) has been chosen to be higher than desired capture range at 90khz ; it remains constant for lower frequencies, till limita- tion by t 5 occurs in the low end of the range. limiting the holding range improves the capture behaviour. i.3 - miscellaneous though the suggestions below were not used in present design, they might prove helpful in other cases. i.3.1 - programming duty factor when using a single bipolar transistor as horizontal power switch, it can be necessary to increase the duty factor at high frequencies, because the tran- sistor desaturation time, which amounts to 1.5...4 m s, occupies a more and more important fraction of the period (duty factor is defined as the ratio of time during which the transistor base is driven low, to total period). this was not found necessary in the present design, which is intended to control a compound (bipolar + mos) power switch with desaturation time around 1 m s. nevertheless, herebelow is described a method to increase the duty factor. for that purpose, connect a resistor r54 in series with the oscillator capacitor, c17. r54 will be crossed by the charge and discharge currents ; the corresponding voltage drops will reduce the ramp voltage amplitude, while the two thresholds which determine duty factor keep the same interval (figure 2). by this method, duty factor will remain near to 41% in the low frequency range and progressively in- crease at high frequencies. nevertheless, it is advisable not to overcome 50 %, since this could impair the locking capability of pll1. a secondary effect is that in the formula of 1, d v, rather than keeping constant, will decrease when more current is sunk from pin 1 : consequently,the oscillation frequency will increase more than pro- portionally to current in pin 1, as regards the high frequency range.this will more or less compensate the less than proportional characteristic of (f h i) converter described in i.1.1, as will be seen in the calculations section. multifrequency and auto-adaptative applications 3/12
threshold for duty factor threshold for pll2 flyback pulse without modified duty factor flyback pulse with modified duty factor off time off time with modified duty factor horizontal period t t t 9102037.eps figure 2 i.3.2 - shifting the phase reference in standard applications, pll 2 will maintain the flyback pulse centered on that moment when the oscillator sawtooth crosses the 4.5v level (see fig- ure 2). when r54 is used, this moment occurs earlier within the period, allowing lowered adjust- ment margin for fly-back pulse phase. some margin may be recovered by injecting a current into pin 9 ; this will give an offset to pll2 and some point of the fly-back pulse, earlier than its middle, will now coincide with the 4.5v crossing. the flyback pulse can be delayed this way by not more than half its duration. since the sink and source currents of pll2 on pin 9 are in the ma range, substantially less than 1ma (average) should be injected for the duration of flyback pulse, or a dc current with same mean value. the former method is preferred since it provides constant delay versus frequency (injecting dc cur- rent makes the delay increase when frequency decreases with the risk of exceeding the allowed value). it can be implemented with a diode and high value resistor from flyback pulse to pin 9. the phase control of pll2 is not implemented on the demoboard. i.4 - calculations i.4.1 - frequency-to-current converter every occurring sync pulse triggers the rise of pin 5 voltage , up to a threshold normally equal to 6v. in fact, because of a comparator delay, the thresh- old will overstep this level by an amount propor- tional to the reverse of t 5 . if we choose t 5 =1 m s(see i-4), which corresponds to c21 = 27pf, the peak voltage will be 7v. on c29 will be found a peak voltage 0.7v lower, that is v p = 6.3v then c29 will discharge exponentiallyinto r41 till next sync pulse (see figure 1). consequently, if t h = 1 f 0 is the horizontal period, the average voltage on c29 will be : v m = v p t h ? ? ? t 5 2 + 0 t h - t 5 exp ? ? ? - t r41 ? c29 ? ? ? dt ? ? ? = v p t h ? ? ? t 5 2 + r41 ? c29 ? ? ? 1 - exp ? ? ? - t h - t 5 r41 ? c29 ? ? ? ? ? ? ? ? ? the exponential term is responsible for the less than linear response at high frequencies. it can be neglected for a rule-of-thumb calculation or in the low-frequency range. multifrequency and auto-adaptative applications 4/12
in present case, our aim is to obtain on r44 a voltage in the range of 2.5vat 90khz, so as to leave sufficient overhead to the collector of t2 (voltage on pin 1 is 3.5v). a time constant r41 ? c29 = 3 m s is convenient (less than one third of the shortest period), for instance c29 = 680 pf (choice) r41 = 3 ? 10 - 6 0.68 ? 10 - 9 = 4.41k w will provide from (2) : v m = 6.3 11.1 ? ? ? 0.5 + 3 ? ? ? 1 - e - 10.1 3 ? ? ? ? ? ? = 1.945v at 90khz where the exponential term is responsible for -3% deviation at 90khz, compared to linear law. the filter values are not critical : r42 = 1m w ,and c30 = 47nf are convenient. modifying c30 will change the rate at which horizontal frequency can change when receiving a new standard. r43 = 1m w is placed in series with op-amp invert- ing input to compensate its input bias current. for stability reasons it is decoupled by c31. i.4.2 - oscillator according to i.1, c17 should be chosen in such way that i 1 be near to 1ma for the highest fre- quency ; equation (1) gives c17 0.375 ? 10 - 3 90 ? 10 3 ? 4 = 1.04nf c17 = 1nf is adopted. - correction of deviation from linear law equation (1) may be written as follows : 1 f 0 = c17 ? d v 0.375 ? i 1 in fact, it was indicated that a delay q was neces- sary for the comparators to switch from charge to discharge and back, so that a more precise equa- tion is 1 f 0 = c17 ? d v 0.375 ? i 1 + qq 0.5 m s when r54 is connected in series with c17, it introduces a supplementary voltage drop equal to 0.5 ? i 1 ? r54 during charge phase, and 1.5 ? i 1 ? r54 during discharge phase. as a result, d v is reduced by an amount 2 ? i 1 ? r54 and new oscillation frequency is given by 1 f 0 = c17 ? ( d v - 2 ? i 1 ? r54 ) 0.375 ? i 1 + q or i 1 f 0 = c17 ? d v 0.375 1 1 + f 0 ? ? ? 2 ? r54 ? c17 0.375 - q ? ? ? consequently, the relation between i 1 and f o will be perfectly linear if r 54 = 0.375 2 q c17 (this compensation technique is also used in the vertical section, see ii.1) in present case, this would lead to r54 = 94 w . a higher value, 150 w , was adopted in order to compensate also for the 3% shortfall of the (f h i) converter at high frequencies (see i.1.1). - now we can determine the value of i 1 at 90khz : i 1 =f 0 ? c17 ? d v 0.375 1 1 + f 0 ? ? ? 2 ? r54 ? c17 0.375 -q ? ? ? = 0.96 ? 10 -3 ? 1 1 + 0.027 = 0.935ma since v m was calculated to be 1.945v at that frequency, then r44 = 1.945 0.935 = 2.08k w r44 will consist of a fixed resistor of 1.82k w in series with a 500 w variable resistor p7, in order to allow for 12% adjustment, to cope with the unprecision of the (f h i 1 f 0 ) converter. this potentiometer will be set so as to obtain 3.5v on pin 3 of the tda9102c with 80khz horizontal sync signal. all components influencing the (f h i 1 f 0 ) converter slope : c21, c29, r41, r44, c17 will be precision ones. - no-sync free-running frequency it is determined by r44 and r45 in series, accord- ing to the formula in v.1 of oan540 application noteo ; it must be lower than the lowest frequency in the range : in present case r44 + r45 1 3.0476 ? 31.4 ? 10 3 ? 10 - 9 = 10.45k w as safety margin, we need 5% for the precision of factor k 0 = 3.0476, 2% for c17, then r44 + r45 > 11.2k w taking into account the lowest value of r44 (1.82k w ) r45 = 9.53k w 1% multifrequency and auto-adaptative applications 5/12
i.4.3 - pll1 holding and capture range - the value of r24 is chosen so as to provide room for sufficient capture range ; from i.2, r24 = 20k w ensures a holding range of 9.4khz at high frequencies, larger than the 7khz capture range. - time constant c18 ? r23 influences the pll in two ways : it controls the capture range of the loop. it ensures the stability of the loop, once locked at the sync frequency (critical for low frequencies). capture range and instability frequency remain roughly proportional. the value chosen for c18 (2.2nf) ensures a capture range 7khz at 90khz (few dependant of frequency) and stability at frequencies higher than 25khz. - the capture range is influenced by the horizontal phase setting : when shifting the display to the right (that is, when v 10 is low), capture range will shift towards low frequencies by some 4khz and reversedly. in order to maintain a fixed capture range, a resistor r56 was connected between pins 1 and 10; its effect is to shift f 0 (and the capture range which remains centered on it) to higher values when v 10 goes lower. since center value of v 10 is 2.5v and voltage on pin 1 is 3.5v, r57 was connected between pins 1 and 19 in order that no neat current be injected into pin 1 in these conditions. refering again to equation 1, r56 = 43k w will provide a frequency shift d f= 0.375 c17 ? d v 2 43 ? 10 3 = 4.36khz for a 2v variation on pin 10. the 23.3 m a sunk by r56 for center setting will be compensated if r57 = 141k w . global performances of (f h v m f 0 ) converter and pll are depicted in figure 3. the diagram scale is not sufficient to separate the f h v m and v m f 0 characteristics, which differ by less than 1khz once p7 is adjusted. ii - vertical oscillator ii.1 - programming the vertical frequency the law which governs vertical frequency may be found in page 11 of oan540 application noteo : f v = i 12 d v ? c16 where d v = 6.8 - 2 = 4.8v (free-running) d v = 6 - 2 = 4v (ideal sync running) v(v) m ff , (khz) h o 2 1.5 1 0.5 0 20406080 100 f h f o v m v m capture range 9102038.eps figure 3 there are two main sources of discrepancy be- tween real frequency and ideal law : - a parasitic internal bias current (about 1.5 m a) which adds to current sunk from pin 12; in order to make its influence negligible, a high value should be chosen for i 12 (not exceeding 200 m ain order to avoid saturation problems at high tem- perature); - the response time of comparators used to switch from ochargeo to odischargeo. the influence of first factor can be neglected (0.75% frequency offset if i 12 =200 m a); second factor should be examined in detail. when voltage on oscillator capacitor c16 reaches the upper threshold, a very fast discharge is trig- gered. the discharge time to 2v is between 10 and 22 m s if c16 = 0.22 m f, which corresponds to a discharge current between 48 and 106ma. when the lower threshold (2v) is reached, the comparator will trigger a new charge phase only after 0.5 m s, during which the discharge will continue with the same rate. consequently the apparent lower threshold will be less than 2v by an amount 0.5/10 to 0.5/22 of 4v (variable from circuit to circuit) (see figure 4). this cause of imprecision will be miminized if a high value is chosen for c16, because discharge rate will decrease. inserting a low-value resistor r58 in series with c16 (1.2 w for 0.39nf; proportional to 1/c16) will compensate most of the unprecision. the explanation may be found in i.4.2. on the other hand, the discharge time by itself has but low influence on total period (in the range of 0.1 - 0.2%). multifrequency and auto-adaptative applications 6/12
ii.2 - frequency-to-current converter as usual, it consists of a monostable triggered by every sync pulse, and a filter which delivers the mean value of the monostable output pulse : the filtered voltage is proportional to sync frequency. the negative-going vertical sync pulse available at the output of x-or gate is used to discharge ca- pacitor c22 down to 0.7v; then it will charge again through r30 with time constant c22 ? r30. an op-amp compares the capacitor voltage with a fixed voltage from bridge r31 - r32. a constant- width pulse is available on the op-amp output : it is filtered by r35, c25, r36, c26. r35 is chosen high-valued, so that the op-amp can drive it down to almost 0v. a double rc filter was chosen, in order that settling time be low, notwithstanding the high filtering ratio required (imperfect filtering would be visible on the crt). ii.3 - frequency programmation transistor t3, combined with an op-amp, is con- nected in such a way that its emitter voltage keep strictly equal to the filtered voltage, representative of frequency. this way, the current through r47, which is finally sunk from pin 12, is proportional to frequency. r46 is added in order to set the free-running fre- quency when no sync pulse is present. in that case, t3 does not conduct and current sunk from pin 12 is fixed by r46 and r47 in series. ii.4 - s - correction in tda9102c, the vertical s-correction is obtained by adding to the current sunk from pin 2 an m- shaped current from pin 18 (see page 7 of oan540 application noteo ). becausepin 12 currents are integrated by c16, the s-correction obtained is proportional to the reverse of vertical frequency. since the s-correction amplitude is dc controllable through pin 17, controlling it with a voltage in- creasing with frequency will provide constant s- correction versus frequency. nevertheless, since the amplitude of s-correction is proportional to (v 17 - 1.5v), the resistor bridge r39 - r40 is intro- duced, in such a way that v 17 be equal to 1.5v for null frequency. once this proportional control es- tablished, r20 has to be fitted so as to obtain convenient correction on the screen. ii.5 - automatic control of oscillator amplitude the optimal oscillator amplitude is 4v (from 2 to 6v): this corresponds to the center of holding range and provides symetrical s-correction (see page 6 and 16 of oan540 application noteo). since the lower threshold is constant (2v), simply maintain- ing the mean value of oscillator ramp to 4v will keep the oscillation between 2v and 6v levels .for that purpose, taking advantageof the fact that the mean value of oscillation is transmitted to pin 15, a resis- tor bridge r52 - r53 reduces the pin 15 voltage by a ratio 3.5/4; then the reduced voltage is filtered; this way, if the oscillation amplitude is correct, a dc voltage of 3.5v (equal to pin 12 voltage) will be found at filter output. an op-amp measures any difference between pin 12 voltage and filter output voltage, and injects into pin 12 through r48 a current in such direction to correct the shift. the capability to adjust amplitude on pin 15 through dc voltage on pin 16 is not impaired by this system. in particular, the different amplitudes corresponding to the various vga modes may be programmed by switching the dc voltage on pin 16, depending on the sign of sync pulses. diodes d4 and d5 are provided to avoid that op- amp inject such high current (thus reducing the oscillation frequency) that the oscillator might syn- chronize on half the sync frequency. there is no danger in the other direction. d4 is a low-voltage signal schottky diode. 0.5 m s apparent lower threshold lower threshold 10 to 22 m s 9102039.eps figure 4 multifrequency and auto-adaptative applications 7/12
ii.6 - calculations ii.6.1 - f v i 12 converter - if maximum frequency is 120hz, 0.39 m fisa convenient value for c16 : the corresponding programmation current (free-running) is : i 2 = c16 ? d v ? 120 = 187.2 m a (less than 200 m a). this value is preferred to 0.22 m f, as explained in ii.1 - evaluation of the precision of f v i converter c22 : 5% r30 r31 r32 r47 : 4% c16 : 5% total precision about 15% - programmation resistors t3 must not be saturated, even for highest fre- quency and maximum f v i converter deviation : 2.5v on its emitter at 120hz provides sufficient overhead (voltage on pin 12 is 3.5 v). consequently r47 = 2.5 0.39 ? 10 - 6 ? 4 ? 110 13.4k w choosing 13k w , the voltage becomes 2.44v. r46 + r47 must be chosen for min frequency without sync to be lower than 40hz even with min value of c16 and with max voltage 3.8v on pin 12. nevertheless, the calculation should take into account the current injected by op-amp into pin 12 (which will be calculated later to be 36 m a). for this calculation, amplitude is 4.8v instead of 4v. 1 r46 + r47 0.39 ? 10 - 6 ? 4.8 ? 40 1.05 ? 3.8 + 36 ? 10 - 6 3.8 = 28.24 ? 10 -3 w -1 r46 + r47 35.4k w , r46 = 22.1k w -f v i converter must provide 2.44v on its output for 120hz. since the voltage excursion at monostable output is from 0 to (12-1.6) = 10.4v, the pulse duty factor must be 2.44 10.4 at 120hz. this gives the time at which the voltage on c22 will cross the threshold, according to exponential law : v v 0 = exp ? ? ? - t r30 ? c22 ? ? ? with v 0 = 12 - 0.7 = 11.3v v=12 ? 430 430 + 220 = 7.94v t= 2.44 10.4 ? 120 = 1.96 ms t r30 ? c22 = log v 0 v r30 = t c22 log v 0 v = 2.44 10.4 ? 120 ? 10 - 7 ? log 11.3 7.94 = 55.4k w ii.6.2 - automatic gain control - loop gain : at a given frequency, corresponding to some value of i 12 , the variation of mean output voltage is half the variation of output amplitudes, so that d v out = 1 2 v out p - p ? d i 12 i 12 this is amplified by op-amp and injected in pin 12 through r48 ; consequently, loop gain is a= 3.5 4 1 2 v out p - p i 12 g r48 where g is the op-amp gain and gain of 1 is assumed between pins 13 and 15. this gain depends on i 12 and hence on fre- quency; g was fixed to 1 + r49 r50 31 in order to have a = 11 in worst case (120 hz). this way, the initial offset of f v i converter will be reduced by factor a in closed loop. - limitation when sync is absent : when no sync pulse is received, the oscillator reaches 6.8v as peak voltage, which will cause control loop to inject maximum current in pin 12. without limitation, the oscillator would stop. current injected in pin 12 comes through r48, r50 and r51 - d4, the latter being about 2 m a. diode d4 (a signal schottky) limits the voltage on positive (and also negative) input of op-amp to some 150mv. diode d5 limits the output voltage to some 400mv above inputs. hence, a current 0.15 r50 + 0.15 + 0.4 r48 + 2 m a=36 m a will be injected in pin 12 and substract from current sunk by r46, r47. - limitation when sync is present : at any frequency, the agc system must be able to recover the possible offset of f v i converter, (more than 15%), but it must not allow locking on half the sync frequency. since the max current from cag is constant, 15% at 120hz means 15 x 120 40 = 45% at 40hz locking to double frequency means, in the worst case, increasing current by 85%. at 40hz, the cag system must provide not less than 45%, not more than 85% extra current. the current injected into pin 12 : v d5 r48 = 27.8 m a is 45% of programmation current and fulfills the requirements. multifrequency and auto-adaptative applications 8/12
iii - sync system the board can synchronize on positive- or nega- tive-going fronts on h and v sync inputs. a quite well-known system based on x-or gates is used in order to deliver the negative transitions neces- sary for tda9102c. in order to maintain ttl compatibility, a ttl x-or ic is used. consequently, the r.c. filters which store the mean value of sync signal include 330 w resistors, able to drive the inputs to low. the sync inputs of tda9102c itself have thresholds of 1.4v, compatible with other logic families. in addition, wiring r37 and c27 will allow to syn- chronise on composite ttl sync arriving on hori- zontal input, provided vertical input takes a high state when left free. if this facility is not needed, gate input should be connected to 5v instead of r37, c27. the logic is normally fed from already present 5v supply; on this board a to92 - 7805 was included. iv - x-ray protection a possible schematic for x-ray protection is given in figure 5. it uses a thyristor made from two to92 transistors. the zener and resistor bridge must be selected in accordance with the desired threshold on eht transformer winding. this function is not included on the demoboard. 8 100k w 10k w 100k w dz 47nf 4.7k w 10k w +12v 1n4148 r a r b tda9102c eht primary 9102040.eps figure 5 v - demoboard the self adaptative function was implemented on a demoboard, intended to complete the standard tda9102c demoboard. it can also be connected to an already existing tda9102c application in order to make it self- adaptative. it must be kept in mind that this evalu- ation board, connected with flying wires, is more sensitive to parasitics than the final layout will be. the complete schematic (modified demoboard of tda9102c + self adaptative function) is shown in figure 6 and the printed circuit of self-adaptative function in figure 7. multifrequency and auto-adaptative applications 9/12
ic6 7805 414 17 16 5 8 9 10 20 7 6 19 15 18 12 1321113 hor. sync. vert. sync. flyback input 7 2 6 3 5 4 1 tda8172 hor. out vert. yoke v 14v s r10 22k w c9 100nf c8 100 m f r11 22k w r12 10k w c15 1 m f r20 tbd c16 390nf 5% r27 tbd p2 47k w r5 39k w c4 15nf c5 15nf r7 39k w p3 47k w c1 100nf c2 470 m f c6 100nf c7 1000 m f d1 1n4001 c10 220 m f c14 10 m f r18 1.2k w r17 2.7k w c13 47 m f r15 1.5k w r14 1.5 w r13 120 w c12 220nf c11 2200 m f r16 1 w oco correction r9 82 w 2w ic3 vv oi g n d ic1 7812 r6 5.1k w r8 5.1k w r19 47k w * the value of r19 depends on crt. on the mock up r19 is substitued with a resistance + trimmer (p4) for generic applications. hor. power gnd tda9102c ic2 r52 22k w 1% r53 154k w 1% r51 220k w c32 2.2 m f c28 0.1 m f supply ttl supply lm324 c33 100nf r54 150 w r47 13k w r46 22.1k w r48 27k w d4 d5 bat42 r49 1.5m w r50 47k w bc549 t3 r24 20k w c18 2.2nf r45 9.53k w 1% t2 bc549 r43 1m w c31 220pf c20 22nf c21 27pf t1 bc237 c29 680pf r55 0 w r41 4.41k w 1% r42 1m w c34 100nf r39 150k w c30 47nf r40 10k w +12v c26 1 m f c25 1 m f r35 270k w r36 47k w 1 2 3 5 6 7 r32 220k w -1% r31 430k w 1% c22 100nf 5% r30 56k w 1% c27** r37** d3 9 10 8 c23 47 m f r33 330 w 12 13 +5v +5v r38 5 4 6 c24 47 m f r34 330 w 1 2 d2 r44 notes : * ** r37 and c27 for composite sync only ; otherwise connect input to 5v. notes : 1. 2. 3. 4. all diodes (except d1, d4) = 1n4148 all x. or gates from ic4 = 7486 all operational amplifiers from ic5 = lm324 tbd = to be determined depending on crt and eht 12 13 14 11 3 10 8 9 r56 43.2k w r57 191k w 1% 1% c17 1nf 2% c19 150nf r53 1.5k w 1.82k w 1% p7 500 w r58 1.2 w 9102041.eps figure 6 multifrequency and auto-adaptative applications 10/12
list of components resistors c34 c28 c27 c22 c33 c21 c31 c30 c29 ic6 t3 t2 t1 ic5 ic4 r40 r39 in 5v r47 r46 12 r48 r50 d4 r60 r51 r53 r52 15 5 r55 r41 r45 r44 r42 r30 r31 1 p7 d2 r37 d3 r38 4 hs b g r gnd r43 r59 d5 r49 17 c23 vs c24 14 r34 r33 c26 r36 r32 r35 c25 c32 r s9102c 12v 9102042.eps figure 7 comp. value r5 39k w r6 5.1k w r7 39k w r8 5.1k w r9 82 w 2w r10 22k w r11 22k w r12 10k w r13 120 w r14 1.5 w r15 1.5k w r16 1 w r17 2.7k w r18 1.2k w r19 tbd r20 tbd r23 1.5k w comp. value r24 20k w r27 tbd r30 56k w 1% r31 430k w 1% r32 220k w 1% r33 330 w r34 330 w r35 270k w r36 47k w r37 tbd r38 0 w r39 150k w r40 10k w r41 4.41k w 1% r42 1m w r43 1m w r44 1.82k w 1% comp. value r45 9.53k w 1% r46 22.1k w r47 13k w 1% r48 27k w r49 1.5m w r50 47k w r51 220k w r52 22k w 1% r53 154k w 1% r54 150 w r55 0 w r56 43.2k w 1% r57 191k w 1% r58 1.2 w r59 0 w r60 - 9102007.tbl multifrequency and auto-adaptative applications 11/12
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. potentiometers comp. value p2, p3 47k w comp. value p7 500 w comp. value capacitors comp. value c1 100nf c2 470 m f c4 15nf c5 15nf c6 100nf c7 1000 m f c8 100 m f c9 100nf c10 220 m f c11 2200 m f c12 220nf comp. value c13 47 m f c14 10 m f c15 1 m f unpolarized c16 390nf 5% c17 1nf 2% c18 2.2nf c19 150nf c20 22nf c21 27pf 5% c22 100nf 5% c23 47 m f comp. value c24 47 m f c25 1 m f c26 1 m f c27 tbd c28 100nf c29 680pf 2% c30 47nf c31 220pf c32 2.2 m f c33 100nf c34 100nf diodes comp. value d1 1n4001 (100v 1a) comp. value d2,d3,d5 1n4148 comp. value d4 bat42 (signal schottky) transistors comp. value t1 bc237 comp. value t2, t3 bc549c (gain 420..800) comp. value circuits comp. value ic1 l7812cv ic2 tda9102c comp. value ic3 tda8172 ic4 7486 ttl xor comp. value ic5 7805 (to92) ic6 lm324 9102007.tbl multifrequency and auto-adaptative applications 12/12

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