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1 fn6797.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2003-2005, 2007, 2008, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. isl6721a flexible single-ende d current mode pwm controller the isl6721a is a low power, single-ended pulse width modulating (pwm) current mode controller designed for a wide range of dc/dc conversion applications including boost, flyback, and isolated output configurations. peak current mode control effectively handles power transients and provides inherent overcurre nt protection. other features include a low power mode where the supply current drops to less than 200a during overvoltage and overcurrent shutdown faults. it differs from the isl6721 in that the uvlo and uv thresholds have been modified. this advanced bicmos des ign features low operating current, adjustable operating frequency up to 1mhz, adjustable soft-start, and a bidirectional sync signal that allows the oscillator to be locked to an external clock for noise sensitive applications. applications ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems ? isolated buck and flyback regulators ? boost regulators features ? 1a mosfet gate driver ? 100a startup current ? fast transient response with peak current mode control ? adjustable switching frequency up to 1mhz ? bidirectional synchronization ? low power disable mode ? delayed restart from ov and oc shutdown faults ? adjustable slope compensation ? adjustable soft-start ? adjustable overcurrent shutdown delay ? adjustable uv and ov monitors ? leading edge blanking ? integrated thermal shutdown ? 1% tolerance voltage reference ? pb-free (rohs compliant) pinouts isl6721a (16 ld tssop) top view isl6721a (16 ld qfn) top view gate isense sync slope uv ov rtct vc pgnd vcc vref lgnd ss comp 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 9 iset fb 1 3 4 15 sync slope uv ov isense gate vc pgnd 16 14 13 2 12 10 9 11 6 578 vcc vref lgnd ss rtct iset fb comp data sheet august 23, 2011
2 fn6797.0 august 23, 2011 ordering information part number (notes 1, 2, 3) part marking temp range (c) package pkg. dwg. # ISL6721AARZ 21az -40 to +105 16 ld qfn l16.3x3b isl6721aavz 6721a avz -40 to +105 16 ld tssop m16.173 notes: 1. *add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6721a . for more information on msl please see tech brief tb363 . isl6721a
3 fn6797.0 august 23, 2011 functional block diagram vref ss 12k on on on 30k 100 5k 4.5k 20k v cc isense iset comp ss ov uv gate slope vfb pgnd v c sync rtct lgnd vref soft-start charge current fault latch pwm comparator set dominant ss low 0.8 ss clamp 2.5v enable ss low comparator vref uv comparator 4.65v 4.375v 1ma 4v 3.0v 1.5v oscillator comparator 70a 3.0v blanking comparator oc detect ss charged + - start/stop uv comparator v ref 5.00 v 1 % + - bg + - + - 100mv + + 0.1 53a + - + - error amplifie r + - 1/3 vref + - on vref + - vref 15a + - + - 25a + - + - 270mv s r q q + - overcurrent comparator 100ns blanking + - + - start + - + - vref + - + - + - 2.50v 1.93v bg + - 36k + - 2v sync in sync out ext sync blanking no ext sync clk out bi-directional synchronization osc in ss charge voltage clamp thermal protection restart delay s r q q overcurrent shutdown delay ss dchg ss chg shtdn oc oc fault isl6721a
4 fn6797.0 august 23, 2011 typical application - 48v input dual output flyback, 3.3v @ 2.5a, 1.8v @ 1.0a vin+ vin- return sync t1 isolation xfmr q3 36-75v vr1 +1.8v isl6721a lgnd v cc sync rtct isense iset vfb ss gate slope uv ov comp vref v c pgnd +3.3v c1 c2 c3 r1 r2 r24 c18 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 r14 c12 c11 c10 c9 r13 r12 r11 c8 r10 c7 r8 r9 r7 r5 r6 d2 ++ p9 c21 c19 c22 c20 + + d1 q2 r25 c6 tp3 tp2 tp5 tp4 tp1 sp1 sp2 r26 r27 r3 r23 c4 u4 isl6721a
5 fn6797.0 august 23, 2011 typical boost converter application schematic vin+ vin- return isl6721a lgnd vcc sync rtct isense iset vfb ss gate slope uv ov comp vref vc pgnd +vout c1 q1 r1 r3 cr1 c11 c10 r10 r8 r9 c2 c5 c6 c7 r6 r7 c8 r11 c9 + r2 c4 u1 l1 c3 r4 r5 vin+ r12 c12 isl6721a
6 fn6797.0 august 23, 2011 absolute maximum rati ngs thermal information supply voltage, v cc, v c . . . . . . . . . . . . . . . . . gnd -0.3v to +20.0v gate . . . . . . . . . . . . . . . . gnd - 0.3v to gate output limit voltage pgnd to lgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 5.3v signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vref peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a operating conditions temperature range isl6721axx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical, note 4) . . . . . . . . 9vdc to 18vdc thermal resistance (typical) ja (c/w) jc (c/w) 16 ld qfn (notes 5, 6) . . . . . . . . . . . . 44 4 16 ld tssop (notes 7, 8) . . . . . . . . . . 105 33 maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are with respect to gnd. 5. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. ja is measured with the component mounted on a high effective t hermal conductivity test board in free air. see tech brief tb379 for details. 8. for jc , the ?case temp? location is taken at the package top center. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. 9v < v cc = v c < 20v, rt = 11k , ct = 330 pf. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. parameter test conditions min (note 9) typ max (note 9) units undervoltage lockout start threshold 6.40 6.80 6.90 v stop threshold 5.85 6.20 6.30 v hysteresis 0.50 0.60 1.00 v start-up current, i cc v cc < start threshold - 100 175 a oc/ov fault operating current, i cc - 200 300 a operating current, i cc (note 11) - 4.5 10.0 ma operating supply current, i c includes 1nf gate loading - 8.0 12.0 ma reference voltage overall accuracy line, load, 0c to +105c 4.95 5.00 5.05 v line, load, -40c to +105c 4.90 5.00 5.05 v long term stability t a = +125c, 1000 hours (note 10) - 5 - mv fault voltage 4.50 4.65 4.75 v vref good voltage 4.65 4.80 4.95 v hysteresis 75 165 250 mv operational current -10 --ma current limit -20 --ma current sense input impedance -5-k offset voltage 0.08 0.10 0.11 v input voltage range 0 - 1.5 v isl6721a
7 fn6797.0 august 23, 2011 blanking time (note 10) 30 60 100 ns gain, a cs v slope = 0v, v fb = 2.3v, v iset = 0.35v, 1.5v a cs = iset/ isense 0.77 0.79 0.81 v/v error amplifier open loop voltage gain (note 10) 60 90 - db gain-bandwidth product (note 10) - 15 - mhz reference voltage initial accuracy v fb = comp, t a = +25c (note 10) 2.465 2.515 2.565 v reference voltage v fb = comp 2.44 2.515 2.590 v comp to pwm gain, a comp comp = 4v, t a = +25c 0.31 0.33 0.35 v/v comp to pwm offset comp = 4v (note 10) 0.51 0.75 0.88 v fb input bias current v fb = 0v -2 0.1 2 a comp sink current comp = 1.5v, v fb = 2.7v 2 6-ma comp source current comp = 1.5v, v fb = 2.3v -0.25 -0.5 - ma comp voh v fb = 2.3v 4.25 4.4 5.0 v comp vol v fb = 2.7v 0.4 0.8 1.2 v psrr frequency = 120hz (note 10) 60 80 - db ss clamp, v comp ss = 2.5v, v fb = 0v, iset = 2v 2.4 2.5 2.6 v oscillator frequency accuracy 289 318 347 khz frequency variation with v cc t = +105c (f 20v - f 9v )/f 9v t = -40c (f 20v -f 9v )/f 9v -2 2 3 3 % temperature stability (note 10) - 8 - % maximum duty cycle (note 12) 68 75 81 % comparator high threshold - free running - 3.00 - v comparator high threshold - with external sync (note 10) - 4.00 - v comparator low threshold - 1.50 - v discharge current 0c to +105c -40c to +105c 0.75 0.70 1.0 1.0 1.2 1.2 ma synchronization input high threshold --2.5v input pulse width 25 --ns input frequency range (note 10) 0.65 x free running (period) - 1.0 mhz input impedance -4.5-k voh r load = 4.5k 2.5 --v vol r load = open - - 0.1 v sync advance sync rising edge to gate falling edge, c gate = c sync = 100pf -25 55 ns electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. 9v < v cc = v c < 20v, rt = 11k , ct = 330 pf. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 9) typ max (note 9) units isl6721a
8 fn6797.0 august 23, 2011 output pulse width c sync = 100pf 50 --ns soft-start charging current ss = 2v -40 -55 -70 a charged threshold voltage 4.26 4.50 4.74 v initial overcurrent discharge cu rrent sustained oc threshold < ss < charged threshold 30 40 55 a overcurrent shutdown threshold voltage charged threshold minus, t a = +25c 0.095 0.125 0.155 v fault discharge current ss = 2v 0.25 1.0 - ma reset threshold voltage t a = +25c 0.22 0.27 0.31 v slope compensation charge current slope = 2v, 0c to +105c -40c to +105c -45 -41 -53 -53 -65 -65 a slope compensation gain fraction of slope voltage added to i sense , t a = +25c 0.097 - 0.103 v/v fraction of slope voltage added to i sense 0.082 - 0.118 v/v discharge voltage v rtct = 4.5v - 0.1 0.2 v gate output gate output limit voltage v c = 20v, c gate = 1nf, i out = 0ma 11.0 13.5 16.0 v gate voh v c - gate, v c = 10v, i out = 150ma -1.5 2.2 v gate vol gate - pgnd, iout = 150ma iout = 10ma -1.2 0.6 1.5 0.8 v peak output current v c = 20v, c gate = 1nf (note 10) - 1.0 - a output ?faulted? leakage v c = 20v, uv = 0v, gate = 2v 1.2 2.6 - ma rise time v c = 20v, c gate = 1nf 1v < gate < 9v -60 100 ns fall time v c = 20v, c gate = 1nf 1v < gate < 9v -15 40 ns minimum on time iset = 0.5v; v fb = 0v; vc = 11v isense to gate w/10:1 divider rtct = 4.75v through 1k (note 10) -- 110 ns overcurrent protection minimum iset voltage -- 0.35 v maximum iset voltage 1.2 --v iset bias current v iset = 1.00v -1.0 - 1.0 a restart delay t a = +25c 150 295 445 ms ov and uv voltage monitor overvoltage threshold 2.4 2.5 2.6 v undervoltage fault threshold 1.89 1.93 2.00 v electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. 9v < v cc = v c < 20v, rt = 11k , ct = 330 pf. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 9) typ max (note 9) units isl6721a
9 fn6797.0 august 23, 2011 undervoltage clear threshold 1.96 2.01 2.10 v undervoltage hysteresis voltage 20 50 100 mv uv bias current v uv = 2.10 v -1.0 - 1.0 a ov bias current v ov = 2.00 v -1.0 - 1.0 a thermal protection thermal shutdown (note 10) 120 130 140 c thermal shutdown clear (note 10) 105 120 135 c hysteresis (note 10) - 10 - c notes: 9. parameters with min and/or max limits are 100% tested at 25c, unless otherwise specified. temp erature limits established by characterization and are not production tested. 10. this parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production. 11. this is the v cc current consumed when the device is active but not switching. does not include gate drive current. 12. this is the maximum duty cycle achievable using the specified values of rt and ct. larger or smaller maximum duty cycles may be obtained using other values for rt and ct. see equations 1, 2, 3 and 4. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. 9v < v cc = v c < 20v, rt = 11k , ct = 330 pf. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter test conditions min (note 9) typ max (note 9) units typical performance curves figure 1. ea reference voltage vs temperature figure 2. vref reference voltage vs temperature figure 3. oscillator frequency vs temperature fig ure 4. resistance for ct capacitor values given 0.991 0.993 0.995 0.998 1 1.002 normalized ea reference temperature (c) normalized ea reference -40 -10 20 50 80 110 1.002 1.000 0.998 0.995 0.993 0.991 0.991 0.993 0.995 0.998 1 1.002 normalized vref normalized v ref 1.002 1.000 0.998 0.995 0.993 0.991 -10 20 50 80 110 -40 temperature (c) normalized frequency 1.002 0.996 0.989 0.983 0.976 0.970 -10205080110 -40 temperature (c) 10 20 40 50 60 70 80 90 100 10 100 10 3 rt (k ) frequency (khz) 30 100pf 220pf 330pf 470pf 680pf 1000pf 2000pf isl6721a
10 fn6797.0 august 23, 2011 pin descriptions slope - means by which the isense ramp slope may be increased for improved noise immunity or improved control loop stability for duty cycles greater than 50%. an internal current source charges an exte rnal capacitor to gnd during each switching cycle. the resulting ramp is scaled and added to the isense signal. sync - a bidirectional synchronization signal used to coordinate the switching frequ ency of multiple units. synchronization may be achi eved by connecting the sync signal of each unit together or by using an external master clock signal. the oscillat or timing capacitor, c t , is still required, even if an external cl ock is used. the first unit to assert this signal assumes control. rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, r t , between v ref and this pin and a timing capacitor, c t , from this pin to lgnd. the oscillator produces a sawtooth waveform with a programmable frequency range of 100khz to 1.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f sw , and the maximum duty cycle, dmax, can be calculated from equations 1, 2, 3 and 4: figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is con nected between the comp and fb pins. the isl6721a features a built -in full cycle soft-start. soft-start is implemented as a clamp on the maximum comp voltage. fb - feedback voltage input connected to the inverting input of the error amplifier. the non -inverting input of the error amplifier is internally tied to a reference voltage. current sense leading edge blanking is disabled when the fb input is less than 2.0v. ov - overvoltage monitor input pin. this signal is compared to an internal 2.5v reference to detect an overvoltage condition. uv - undervoltage monitor input pin. this signal is compared to an internal 1.45v reference to detect an undervoltage condition. isense - this is the input to the current sense comparators. the ic has two current sensing comparators, a pwm comparator for peak current mode control, and an overcurrent protection comparator. the overcurrent comparator threshold is adjustable through the iset pin. exceeding the overcurrent threshold will start a delayed shutdown sequence. once an overcurrent condition is detected, the soft-start charge current source is disabled and a discharge current source is enabled. the soft-start capacitor begins discharging, and if it discharges to less than 4.375v (sustained overcurrent thresh old), a shutdown condition occurs and the gate output is forced low. at this point a reduced discharge current takes over until the soft-start voltage reaches 0.27v (reset threshold). the gate output remains low until the reset threshold is attained. at this point, a soft-start cycle begins. if the overcurrent condition ceases, and then an additional 50s period elapses before the shutdown threshold is reached, no shutdown occurs an d the soft-start voltage is allowed to recharge. lgnd - lgnd is a small signal reference ground for all analog functions on this device. pgnd - this pin provides a dedica ted ground for the output gate driver. the lgnd and pgnd pins should be connected externally using a short printed circuit board trace close to the ic. this is imperative to prevent large, high frequency switching currents flowing through the ground metallization inside the ic. (decouple v c to pgnd with a low esr 0.1f or larger capacitor.) gate - this is the device output. it is a high current power driver capable of driving the gate of a power mosfet with peak currents of 1.0a. this gate output is actively held low when v cc is below the uvlo threshold. the output high voltage is clamped to ~13.5v. voltages exceeding this clamp value should not be applied to the gate pin. the output stage provides very low impedance to overshoot and undershoot. v c - this pin is for separate collector supply to the output gate drive. separate v c and pgnd helps decouple the ic?s analog circuitry from the high power gate drive noise. (decouple v c to pgnd with a low esr 0.1f or larger capacitor.) v cc - v cc is the power connection for the device. although quiescent current, i cc , is low, it is dependent on the frequency of operation. to optimize noise immunity, bypass v cc to lgnd with a ceramic capacitor as close to the v cc and lgnd pins as possible. t c 0.655 r t c t ? ? s (eq. 1) t d r t ? c t ln 0.001 r t 3.6 ? ? 0.001 r t 1.9 ? ? ------------------------------------------- ?? ?? ? ? s (eq. 2) f sw 1 t d t c + ----------------- = hz (eq. 3) (eq. 4) dmax t c f sw ? = isl6721a
11 fn6797.0 august 23, 2011 the total supply current (i c plus i cc ) will be higher, depending on the load applied to gate. total current is the sum of the quiescent current and the average gate current. knowing the operating frequency, f sw , and the mosfet gate charge, qg, the average gate output current can be calculated in equation 5: vref - the 5v reference voltage output. bypass to lgnd with a 0.01f or larger capacito r to filter this output as needed. using capacitance less than this value may result in unstable operation. ss - connect the soft-start capacitor between this pin and lgnd to control the duration of soft-start. the value of the capacitor determines both the ra te of increase of the duty cycle during start-up, and also controls the overcurrent shutdown delay. iset - a dc voltage between 0.35v and 1.2v applied to this input sets the pulse-by-pulse overcurrent threshold. when overcurrent inception occurs, the ss capacitor begins to discharge and starts the overcurrent delayed shutdown cycle. thermal pad (qfn package only) - the thermal pad located on the bottom of the qfn package is electrically isolated. it is recommended that it be connected to signal ground. functional description features the isl6721a current mode pwms make an ideal choice for low-cost flyback and forward t opology applications requiring enhanced control and supervisory capability. with adjustable overvoltage and undervoltage thresholds, overcurrent threshold, and hic-cup delay, a highly flexible design with minimal external components is possible. other features include peak current mode control, adjustable soft-start, slope compensation, adjustable oscillator frequency and a bi-directional synchronization clock input. oscillator the isl6721a have a sawtooth oscillator with a programmable frequency range to 1mhz, which can be programmed with a resistor and capacitor on the rtct pin. (please refer to figure 4 for the resistance and capacitance required for a given frequency.) implementing synchronization the oscillator can be synchronized to an external clock applied at the sync pin or by connecting the sync pins of multiple ics together. if an external master clock signal is used, it must be at least 65% of the free running frequency of the oscillator for proper synchronization. the external master clock signal should have a pulse width greater than 20ns. if no master clock is used, the first device to assert sync assumes control of the sync signal. an external sync pulse is ignored if it occu rs during the first 1/3 of the switching cycle. during normal operation the rtct voltage charges from 1.5v to 3.0v and back during each cycle. clock and sync signals are generated when the 3.0v threshold is reached. if an external clock signal is detected during the latter 2/3 of the charging cycle, the oscilla tor switches to external synchronization mode and relies upon the external sync signal to terminate the oscilla tor cycle. the generation of a sync signal is inhibited in this mode. if the rtct voltage exceeds 4.0v (i.e. no external sync signal terminates the cycle), the oscillator reverts to the internal clock mode and a sync signal is generated. soft-start operation the isl6721a features soft-start using an external capacitor in conjunction with an internal current source. soft-start is used to reduce voltage stresses and surge currents during start up. upon start up, the soft-start circ uitry clamps the error amplifier output (comp pin) to a value proportional to the soft-start voltage. the error amplifier output rises as the soft-start capacitor voltage rises. this has the effect of increasing the output pulse width from zero to the steady state operating duty cycle during the soft-start period. when the soft-start voltage exceeds the error amplifier voltag e, soft-start is completed. soft-start forces a controlled output voltage rise. soft-start occurs during start-up and after recovery from a fault condition or overcurrent shutdown. the soft-start voltage is clamped to 4.5v. gate drive the isl6721a is capable of sourcing and sinking 1a peak current. separate collector supply (v c ) and power ground (pgnd) pins help isolate the ic?s analog circuitry from the high power gate drive noise. to limit the peak current through the ic, an external resistor may be placed between the totem-pole output of the ic (gate pin) and the gate of the mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. slope compensation for applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. slope compensation is a technique in which the current feedback signal is modified by adding additional slope to it. the minimum amount of slope compensation required corresponds to 1/2 the inductor (eq. 5) igate qg f sw ? = a isl6721a
12 fn6797.0 august 23, 2011 downslope. however, adding excessive slope compensation results in a control loop that behaves more as a voltage mode controller than as current mode controller (figure 5). the minimum amount of capacitance to place at the slope pin is calculated in equation 6: where t on is the on time and v slope is the amount of voltage to be added as slope compensation to the current feedback signal. in general, the amount of slope compensation added is 2 to 3 times the minimum required. example: assume the inductor current signal presented at the isense pin decreases 125mv during the off period, and: switching frequency, f sw = 250khz duty cycle, d = 60% t on = d/f sw = 0.6/250e3 = 2.4s t off = (1 - d)/fsw = 1.6s determine the downslope: downslope = 0.125v/1.6s = 78mv/s. now determine the amount of voltage that must be added to the current sense signal by the end of the on time (equation 7). therefore (equation 8), an appropriate slope compensation capacitance for this example would be 1/2 to 1/ 3 the calculated value, or between 68pf and 33pf. overvoltage and undervoltage monitor the ov and uv signals are inputs to a window comparator used to monitor the input voltage level to the converter. if the voltage falls outside of the user designated operating range, a shutdown fault occurs. for ov faults, the supply current, i cc , is reduced to 200a for ~295ms at which time recovery is attempted. if the fault is cleared, a soft-sta rt cycle begins. otherwise another shutdown cycle occurs. a uv condition also results in a shutdown fault, but the device does not enter the low power mode and no restart delay occurs when the fault clears. a resistor divider between v in and lgnd to each input determines the operational thresholds. the uv threshold has a fixed hysteresis of 75mv nominal. overcurrent operation the overcurrent threshold level is set by the voltage applied at the iset pin. setting the overcurrent level may be accomplished by using a resistor divider network from vref to lgnd. the iset threshold should be set at a level that corresponds to the desired peak output inductor current plus the additive effects of slope compensation. overcurrent delayed shutdown is enabled once the soft-start cycle is complete. if an overcurrent condition is detected, the soft-start charging current source is disabled and the discharging current source is enabled. the soft-start capacitor is discharged at a rate of 40a. at the same time, a 50s retriggerable one-shot timer is activated and it remains active for 50s after the overcurrent condition stops. the soft-start discharge cycle c annot be reset until the one- shot timer becomes inactive. if the soft-start capacitor discharges by more than 0. 125v to 4.375v, the output is disabled and the soft-start capacitor is discharged. the output remains disabled and i cc drops to 200a for approximately 295ms. a new soft-start cycle is then initiated. the shutdown and restart behavio r of the oc protection is often referred to as hic-cup operation due to its repetitive start-up and shutdown characteristic. if the overcurrent condition ceases at least 50s prior to the soft-start voltage reaching 4.375v, the soft-start charging and discharging currents revert to normal operation and the soft-start voltage is allowed to recover. hiccup oc protection may be defeated by setting iset to a voltage that exceeds the erro r amplifier current control voltage, or about 1.5v. leading edge blanking the initial 100ns of the current feedback signal input at isense is removed by the leading edge blanking circuitry. the blanking period begins when the gate output leading edge exceeds 3.0v. leading edge blanking prevents current spikes from parasitic elements in the power supply from causing false trips of t he pwm comparator and the overcurrent comparator. fault conditions a fault condition occurs if vref falls below 4.65v, the ov input exceeds 2.50v, the uv i nput falls below 1.45v, or the junction temperature of the di e exceeds ~+130c. when a fault is detected the gate output is disabled, and the soft-start capacitor is quickly discharged. when the fault time isense signal (v) downslope current sense signal time downslope current sense signal figure 5. slope compensation c slope 4.24 6 ? 10 t on v slope ---------------------- - ? = f (eq. 6) v slope 1 2 -- - 0.078 2.4 ? ? 94mv == (eq. 7) c slope min () 4.24 6 ? 10 2.4 6 ? 10 0.094 ----------------------- ? 110pf = (eq. 8) isl6721a
13 fn6797.0 august 23, 2011 condition clears and the soft-start voltage is below the reset threshold, a soft-start cycle begins. ground plane requirements careful layout is essential fo r satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. power ground (pgnd) can be separated from the logic ground (lgnd) and connected at a single point. v c should be bypassed directly to pgnd with good high frequency capacitors. the return connection for input power and the bulk input capacitor should be connected to the pgnd ground plane. reference design the typical application schematic on page 4 features the isl6721a in a conventional dual output 10w discontinuous mode flyback dc/dc converter. the isl6721eval1 demonstration unit implements this design and is available for evaluation. the input voltage range is from 36vdc to 75vdc, and the two outputs are 3.3v @ 2.5a and 1.8v @ 1.0a. cross regulation is achieved using the weighted sum of the two outputs. circuit element descriptions the converter design may be broken down into the following functional blocks: input storage and filtering capacitance: c 1 , c 2 , c 3 isolation transformer: t1 primary voltage clamp: c r6 , r 24 , c 18 start bias regulator: r 1 , r 2 , r 6 , q 3 , v r1 operating bias and regulator: r 25 , q 2 , d 1 , c 5 , c r2 , d 2 main mosfet power switch: q 1 current sense network: r 4 , r 3 , r 23 , c 4 feedback network:, r 13 , r 15 , r 16 , r 17 , r 18 , r 19 , r 20 , r 26 , r 27 , c 13 , c 14 , u 2 , u 3 control circuit:c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , r 5 , r 6 , r 8 , r 9 , r 10 , r 11 , r 12 , r 14 , r 22 output rectification and filtering: c r4 , c r5 , c 15 , c 16 , c 19 , c 20 , c 21 , c 22 secondary snubber: r 21 , c 17 design criteria the following design requirements were selected: switching frequency, f sw : 200khz v in : 36v to 75v v out(1) : 3.3v @ 2.5a v out(2) : 1.8v @ 1.0a v out(bias) : 12v @ 50ma p out : 10w efficiency: 70% maximum duty cycle, d max : 0.45 transformer design the design of a flyback transformer is a non-trivial affair. it is an iterative process which requires a great deal of experience to achieve the desired result. it is a process of many compromises, and even experienced designers will produce different designs when presented with identical requirements. the it erative design proces s is not presented here for clarity. the abbreviated design process follows: ? select a core geometry suitable for the application. constraints of height, footpr int, mounting preference, and operating environment will affect the choice. ? select suitable core material(s). ? select maximum flux density desired for operation. ? select core size. core size will be dictated by the capability of the core stru cture to stor e the required energy, the number of turns that have to be wound, and the wire gauge needed. often the window area (the space used for the windings) and power loss determine the final core size. for flyback transf ormers, the ability to store energy is the critical factor in determining the core size. the cross sectional area of the core and the length of the air gap in the magnetic path determine the energy storage capability. ? determine maximum desired flux density. depending on the frequency of operation, the core material selected, and the operating environment, the allowed flux density must be determined. the decision of what flux density to allow is often difficult to determine initially. usually the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is required based on flux density and energy storage calculations. ? determine the number of primary turns. ? determine the turns ratio. ? select the wire gauge for each winding. ? determine winding order and insulation requirements. ? verify the design. input power: p out /efficiency = 14.3w (use 15w) max on time: t on(max) = d max /f sw = 2.25s average input current: i avg(in) = p in /v in(min) = 0.42a isl6721a
14 fn6797.0 august 23, 2011 peak primary current (equation 9): maximum primary inductance (equation 10): choose desired primary inductance to be 40h. the core structure must be able to deliver a certain amount of energy to the secondary on each switching cycle in order to maintain the specified output power (equation 11). where w is the amount of energy required to be transferred each cycle and vd is the drop across the output rectifier. the capacity of a gapped ferrite core structure to store energy is dependent on the volume of the airgap and can be expressed in equation 12: where aeff is the effective cro ss sectional area of the core in m 2 , lg is the length of the airgap in meters, o is the permeability of free space (4 ? 10 -7 ), and b is the change in flux density in tesla. a core structure having less airgap volume than calculated will be incapable of providing the full output power over some portion of its operating range. on the other hand, if the length of the airgap becomes large, magnetic field fringing around the gap occurs. this has the ef fect of increasing the airgap volume. some fringing is usually acceptable, but excessive fringing can cause increased losses in the windings around the gap resulting in excessive heating. once a suitable core and gap combination are found, the iterative design cycle begins. a design is devel oped and checked for ease of assembly and thermal performance. if the core does not allow adequate space for the windings, then a core with a larger window area is required. if the transformer runs hot, it may be necessary to lower the flux density (more primary turns, lower operating frequency), select a less lossy core material, change the geometry of the wi ndings (winding order), use heavier gauge wire or multi-filar windings, and/or change the type of wire used (litz wire, for example). for simplicity, only the final design is further described. an epcos efd 20/10/7 core using n87 material gapped to an a l value of 25nh/n 2 was chosen. it has more than the required air gap volume to st ore the energy required, but was needed for the window area it provides. aeff = 31 ? 10 -6 m 2 lg = 1.56 ? 10 -3 m the flux density b is only 0.069t or 690 gauss, a relatively low value. since (equation 13): the number of primary turns, n p , may be calculated. the result is n p = 40 turns. the secondary turns may be calculated as follows (equation 14): where tr is the time required to reset the core. since discontinuous mmf mode operation is desired, the core must completely reset during the off time. to maintain discontinuous mode operation, the maximum time allowed to reset the core is t sw - t on(max) where t sw = 1/f sw . the minimum time is application dependent and at the designers discretion knowing that the secondary winding rms current and ripple current stress in the output capacitors increases with decreasing reset time. the calculation for maximum n s for the 3.3 v output using t = t sw - t on (max) = 2.75s is 5.52 turns. the determination of the number of secondary turns is also dependent on the number of out puts and the required turns ratios required to generate them . if schottky output rectifiers are used and we assume a forward voltage drop of 0.45v, the required turns ratio for the two output voltages, 3.3v and 1.8v, is 5:3. with a turns ratio of 5:3 for the secondary windings, we will use n s1 = 5 turns and n s2 = 3 turns. checking the reset time using these values for the number of secondary turns yields a duration of tr = 2.33s or about 47% of the switching period, an acceptable result. the bias winding turns may be calculated similarly, only a diode forward drop of 0.7v is us ed. the rounded off result is 17 turns for a 12v bias. the next step is to determine the wire gauge. the rms current in the primary windi ng may be calculated using equation 15: the peak and rms current values in the remaining windings may be calculated using equations 16 and 17: i ppk 2i avg in () ? f sw t on max () ? ---------------------------------------- - 1.87 == a (eq. 9) lp max () v in min () t on max () ? i ppk --------------------------------------------------------- 43.3 == h (eq. 10) wp out v out vd + ?? f sw v out ? ----------------------------------- - ? = joules (eq. 11) vg aeff lg ? 2 o w ? ? b 2 ----------------------------- == m 3 (eq. 12) l p o n p 2 aeff ? ? lg ---------------------------------------- = h (eq. 13) n s ig vout vd + ?? tr ? ? n p ippk o aeff ? ? ? ------------------------------------------------------- - (eq. 14) i prms () i ppk t on max () 3t sw ? -------------------------- - ? = a (eq. 15) i spk 2i out t sw ? ? tr ------------------------------------ - = a (eq. 16) i rms 2i out ? t sw 3tr ? -------------- - ? = a (eq. 17) isl6721a
15 fn6797.0 august 23, 2011 the rms current for the primary winding is 0.72a, for the 3.3v output, 4.23a, for the 1.8v output, 1.69a, and for the bias winding, 85ma. to minimize the transformer l eakage inductance, the primary was split into two sections connected in parallel and positioned such that the other windings were sandwiched between them. the output windings were configured so that the 1.8v winding is a tap off of the 3.3v winding. tapping the 1.8v output requires that th e shared portion of the secondary conduct the combined current of both outputs. the secondary wire gauge must be selected accordingly. the determination of current carrying capacity of wire is a compromise between performanc e, size, and cost. it is affected by many design constraints such as operating frequency (harmonic content of the waveform) and the winding proximity/geometry. it generally ranges between 250 and 1000 circular mils per ampere. a circular mil is defined as the area of a circle 0.001? (1 mil) in diameter. as the frequency of operation increases, the ac resistance of the wire increases due to skin and proximity effects. using heavier gauge wire may not alleviate the problem. instead multiple strands of wire in parallel must be used. in some cases, litz wire is required. the winding configuration selected is: primary #1: 40t, 2 #30 bifilar secondary: 5t, 0.003? (3 mil) copper foil tapped at 3t bias: 17t #32 primary #2: 40t, 2 #30 bifilar the internal spacing and insulation system was designed for 1500vdc dielectric withstand rating between the primary and secondary windings. power mosfet selection selection of the main switching mosfet requires consideration of the voltage and current stresses that will be encountered in the application, the power dissipated by the device, its size, and its cost. the input voltage range of the converter is 36vdc to 75vdc. this suggests a mosfet with a voltage rating of 150v is required due to the flyback voltage likely to be seen on the primary of the isolation transformer. the losses associated with mosfet operation may be divided into three categories: conduction, switching, and gate drive. the conduction losses are due to the mosfet?s on resistance (equation 18). where r ds(on) is the on resistance of the mosfet and iprms is the rms primary current. determining the conduction losses is complicated by the variation of r ds(on) with temperature. as juncti on temperature increases, so does r ds(on) , which increases losses and raises the junction temperature more, and so on. it is possible for the device to enter a thermal ru naway situation without proper heatsinking. as a general rule of thumb, doubling the +25c r ds(on) specification yields a reasonable value for estimating the conduction losses at +125c junction temperature. the switching losses have two components: capacitive switching losses and voltage/ current overlap losses. the capacitive losses occur during turn on of the device and may be calculated in equation 19: where cfet is the equivalent output capacitance of the mosfet. device output capacitance is specified on datasheets as coss and is non-linear with applied voltage. to find the equivalent discrete capacitance, cfet, a charge model is used. using a known current source, the time required to charge the mosf et drain to the desired operating voltage is determined and the equivalent capacitance may be calculated in equation 20: the other component of the s witching loss is due to the overlap of voltage and current during the switching transition. a switching transition occurs when the mosfet is in the process of either turnin g on or off. since the load is inductive, there is no overlap of voltage and current during the turn on transition, so only the turn off transition is of significance. the power dissipation may be estimated using equation 21: where t ol is the duration of the overlap period and x ranges from about 3 through 6 in typical applications and depends on where the waveforms intersect. this estimate may predict higher dissipation than is real ized because a portion of the turn off drain current is attributable to the charging of the device output capacitance (coss) and is not dissipative during this portion of the switching cycle (figure 6). pcond r ds on () iprms 2 ? = w (eq. 18) pswcap 1 2 -- - cfet vin 2 f sw ? ? ? = w (eq. 19) cfet ichg t ? v ------------------- - = f (eq. 20) p sw 1 x -- - i ppk ? v in t ol f sw ? ? ? (eq. 21) isl6721a
16 fn6797.0 august 23, 2011 the final component of mosfet loss is caused by the charging of the gate capacitance through the device gate resistance. depending on the relative value of any external resistance in the gate drive circuit, a portion of this power will be dissipated externally (equation 22). once the losses are known, the device package must be selected and the heatsinking method designed. since the design requires a small surface mount part, a 8 ld soic package was selected. a fair child fds2570 mosfet was selected based on these crit eria. the overall losses are estimated at 400mw. output filter design in a flyback design, the primary concern for the design of the output filter is the capacitor ripple current stress and the ripple and noise specific ation of the output. the current flowing in and out of the output capacitors is the difference between the winding current and the output current. the peak secondary current, i spk , is 10.73a for the 3.3v output and 4.29a for the 1.8v output. the current flowing into the output filter capacitor is th e difference between the winding current and the output current. looking at the 3.3v output, the peak winding current is i spk = 10.73a. the capacitor must store this amount minus the out put current of 2.5a, or 8.23a. the rms ripple current in the 3.3v output capacitor is about 3.5a rms . the rms ripple current in the 1.8v output capacitor is about 1.4a rms . voltage deviation on the output during the switching cycle (ripple and noise) is caused by the change in charge of the output capacitance, the equival ent series resistance (esr), and equivalent series inductance (esl). each of these components must be assigned a portion of the total ripple and noise specification. how much to allow for each contributor is dependent on th e capacitor technology used. for purposes of this discussion, we will assume the following: 3.3v output: 100mv total output ripple and noise esr: 60mv capacitor q: 10mv esl: 30mv 1.8v output: 50mv total output ripple and noise esr: 30mv capacitor q: 5mv esl: 15mv for the 3.3v output (equation 23): the change in voltage due to the change in charge of the output capacitor, q, determines how much capacitance is required on the output (equation 24). esl adds to the ripple and noise voltage in proportion to the rate of change of current into the capacitor (v = l ? di/dt) (equation 25). capacitors having high capacitance usually do not have sufficiently low esl. high fr equency capacitors such as surface mount ceramic or film are connected in parallel with the high capacitance capacitors to address the effects of esl. a combination of high frequency and high ripple capability capacitors is used to achieve the desired overall performance. the analysis of t he 1.8v output is similar to that of the 3.3v output and is omitted for brevity. two oscon 4sep560m (560f) electrolytic capacitors and a 22f x5r ceramic 1210 capacitor were selected for both the 3.3 and 1.8v outputs. the 4sep5 60m electrolytic capacitors are each rated at 4520ma ripple current and 13m of esr. the ripple current rating of just one of these capacitors is adequate, but two are needed to meet the minimum esr and capacitance values. the bias output is of such low power and current that it places negligible stress on its filter capacitor. a single 0.1f ceramic capacitor was selected. control loop design the major components of the feedback control loop are a programmable shunt regulator, an opto-coupler, and the inverting amplifier of the isl6721a. the opto-coupler is used to transfer the error signal across the isolation barrier. the opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. it adds a pole at about 10khz and a significant amount of gain variation due the current transfer ratio (ctr). the ctr of the opto-coupler va ries with initial tolerance, temperature, forward current, and age. v d-s ippk tol figure 6. switching cycle pgate qgvgf sw ? ? = w (eq. 22) esr v i spk i out ? -------------------------------- - 0.060 10.73 2.5 ? ---------------------------- - 7.3m == (eq. 23) c ispk iout ? () tr ? 2 v ? ---------------------------------------------- 10.73 2.5 ? () 2.33 6 ? 10 ? 20.010 ? ------------------------------------------------------------------ - 960 f == (eq. 24) l vdt ? di -------------- - 0.030 200 9 ? 10 ? 10.73 --------------------------------------------- - 0.56nh == (eq. 25) isl6721a
17 fn6797.0 august 23, 2011 a block diagram of the feedback control loop is shown in figure 7. the loop compensation is plac ed around the error amplifier (ea) on the secondary side of the converter. the primary side amplifier located in the control ic is used as a unity gain inverting amplifier and provides no loop compensation. a type 2 error amplifier configuration was selected as a precaution in case operation in continuous mode should occur at some operating point (figure 8). development of a small signal model for current mode control is rather complex. the method of reference 1 was selected for its ability to accurately predict loop behavior. to further simplify the analysis, the converter will be modeled as a single output supply with all of the output capacitance reflected to the 3.3v output. on ce the ?single? output system is compensated, adjustments to the compensation will be required based on actual loop measurements. the first parameter to determine is the peak current feedback loop gain. since this application is low power, a resistor in series with the s ource of the power switching mosfet is used for the current feedback signal. for higher power applications, a resistor would dissipate too much power and current transformer would be used instead. there is limited flexibility to adjust the current loop behavior due to the need to provide overcurrent protection. current limit and the current loop gain are determined by the current sense resistor and the iset threshold. iset was set at 1.0v, near its maximum, to minimize noise effects. when determining iset, the internal ga in and offset of the isense signal in the control ic must be taken into account. the maximum peak primary current was determined earlier to be 1.87a, so a choice of 2.25a peak primary current for current limit is reasonable. a current gain, a ext , of 0.5v/a was selected to achieve this (equation 26). the control to output transfer function may be represented as shown in equation 27: if we ignore the current feedback sampled-data effects (equations 28 through 35): the value of k may be determined by assuming all of the output power is delivered by the 3.3v output at the threshold of current limit. the ma ximum power allowed was determined earlier as 15w, therefore (equations 36, 37): where a ext is the external gain of the current feedback network, a cs is the ic internal gain, and a comp is the gain between the error amplifier and the pwm comparator. the type 2 compensation configuration has two poles and one zero. the first pole is at the origin, and provides the integration characteristic which results in excellent dc regulation. referring to the typical application schematic on figure 7. feedback control loop + - pwm power stage z 3 z 4 z 1 z 2 ref ref + - isolation error amplifier primary side amplifier v out figure 8. type 2 error amplifier ref + - v out v error iset 2.25 0.8 0.5 0.100 + ? ? 1.00 == v (eq. 26) v o v c ----- - k r o l s f sw ? ? 2 --------------------------------- 1 s z ------ + 1 s p ------ - + ---------------- - ? ? = (eq. 27) k i spk max () v cmax () ------------------------- - = (eq. 28) r o loadresis ce tan = (eq. 29) l s secondaryinduc ce tan = (eq. 30) p 2 r o c o ? -------------------- = or f p 1 r o c o ? ? ----------------------------- = (eq. 31) z 1 r c c o ? ------------------- - = or f z 1 2 ? r c c o ? ? -------------------------------------- = (eq. 32) c o outputcapaci ce tan = (eq. 33) r c outputcapaci cee tan sr = (eq. 34) v cmax () controlvoltagerange = (eq. 35) i spk max () 2 p out v out ----------- - t sw ? ? tr ----------------------------------- - 2 15 3.3 ------- - 5 6 ? 10 ? ? 2.33 6 ? 10 ----------------------------------------- - 19.5 == = a (eq. 36) v cmax () v isense a ext ? a cs 1 a comp -------------------- - ? ? 2.93 == v (eq. 37) isl6721a
18 fn6797.0 august 23, 2011 page 4, the remaining pole and zero for the compensator are located at (equations 38, 39): the ratio of r 15 to the parallel combination of r 17 and r 18 determine the mid band gain of the error amplifier (equation 40). from equation 27, it can be se en that the control to output transfer function frequency dep endence is a function of the output load resistance, the value of output capacitance, and the output capacitance esr. these variations must be considered when compensating t he control loop. the worst case small signal operating point for the converter is at minimum v in , maximum load, maximum c out , and minimum esr. the higher the desired bandwidth of the converter, the more difficult it is to create a soluti on that is stable over the entire operating range. a good rule of thumb is to limit the bandwidth to about f sw /4. for this example, the bandwidth will be further limited due to the low gbwp of the lm431-based error amplifier and the opto-coupler. a bandwidth of approximately 5khz was selected. for the ea compensation, the fi rst pole is placed at the origin by default (c 14 is an integrating capacitor). the first zero is placed below the crossover frequency, f co , usually around 1/3 f co . the second pole is placed at the lower of the esr zero or at one half of the switching frequency. the midband gain is then adjusted to obtain the desired crossover frequency. if the phase margin is not adequate, the crossover frequency may have to be reduced. using this technique to determine the compensation, the following values for the ea components were selected. r 17 = r 18 = r 15 = 1k r 20 = open c 13 = 100nf c 14 = 100pf a bode plot of the closed loop system at low line, max load appears in figures 9a and 9b. regulation performance f pc c 13 c 14 + 2 r 15 c 14 c 13 ? ? ? ? ------------------------------------------------------------ 1 2 r 15 c 14 ? ? ? -------------------------------------------- = (eq. 38) f zc 1 2 r 15 c 13 ? ? ? -------------------------------------------- = (eq. 39) a midband r 15 r 17 r 18 + () ? r 17 r 18 ? ----------------------------------------------- - = (eq. 40) table 1. output load regulation, v in = 48v i out (a), 3.3v i out (a), 1.8v v out (v), 3.3v v out (v), 1.8v 0 0.030 3.351 1.825 0.39 0.030 3.281 1.956 0.88 0.030 3.251 1.988 1.38 0.030 3.223 2.014 1.87 0.030 3.204 2.029 2.39 0.030 3.185 2.057 2.89 0030 3.168 2.084 3.37 0.030 3.153 2.103 0 0.52 3.471 1.497 0.39 0.52 3.283 1.800 0.88 0.52 3.254 1.836 1.38 0.52 3.233 1.848 1.87 0.52 3.218 1.855 2.39 0.52 3.203 1.859 2.89 0.52 3.191 1.862 0 1.05 3.619 1.347 0.39 1.05 3.290 1.730 figure 9a. gain 10k 100k 1m 10m 100m 50 40 30 20 10 0 -10 -20 -30 -40 -50 frequency (hz) gain (db) figure 9b. phase margin 10k 100k 1m 10m 100m -100 -50 0 50 100 150 200 frequency (hz) phase margin () isl6721a
19 fn6797.0 august 23, 2011 waveforms typical waveforms can be found in figures 10 through 12. figure 10 shows the steady state operation of the sawtooth oscillator waveform at rtct (trace 2), the sync output pulse (trace 1), and the gate output to the converter fet (trace 3). figure 11 shows the converter behavior while operating in an overcurrent fault condition. trace 1 is the soft-start voltage, which increases from 0v to 4.5v, at which point the oc fault function is enabled. the oc condition is detected and the soft-start capacitor is discharged to the 4.375v oc fault threshold at which point the ic enters the fault shutdown mode. trace 2 shows the behavior of the timing capacitor voltage during a shutdown fault. most of the functions of the ic are de-powered during a fault, and the oscillator is among those function s. during a fault, the ic is turned off until the restart delay has timed out. after the delay, power is restored and the ic resumes normal operation. trace 3 is the gate output during the soft-start cycle and oc fault. 0.88 1.05 3.254 1.785 1.38 1.05 3.235 1.805 1.87 1.05 3.220 1.814 2.39 1.05 3.207 1.820 0 1.55 3.699 1.265 0.39 1.55 3.306 1.682 0.88 1.55 3.260 1.750 1.38 1.55 3.239 1.776 1.87 1.55 3.224 1.789 0 2.07 3.762 1.201 0.39 2.07 3.329 1.645 0.88 2.07 3.270 1.722 1.38 2.07 3.245 1.752 0 2.62 3.819 1.142 0.39 2.62 3.355 1.612 0.88 2.62 3.282 1.697 0 3.14 3.869 1.091 0.39 3.14 3.383 1.581 table 1. output load regulation, v in = 48v (continued) i out (a), 3.3v i out (a), 1.8v v out (v), 3.3v v out (v), 1.8v figure 10. typical waveforms note: trace 1: sync output trace 2: rtct sawtooth trace 3: gate output isl6721a
20 fn6797.0 august 23, 2011 figure 12 shows the switching fet waveforms during steady state operation. trace 1 is drain-source voltage and trace 2 is gate-source voltage. figure 11. soft-start with overcurrent fault note: trace 1: ss trace 2: rtct sawtooth trace 3: gate output figure 12. gate and drain-source waveforms note: trace 1: v d-s trace 3: v g-s isl6721a
21 fn6797.0 august 23, 2011 component list reference designator value description c 1 , c 2 , c 3 1.0f capacitor, 1812, x7r, 100v, 20% c 5 , c 13 0.1f capacitor, 0603, x7r, 25v, 10% c 15 , c 16 , c 19 , c 20 560f capacitor, radial, sanyo 4sep560m c 17 470pf capacitor, 0603, cog, 50v, 5% c 18 0.01f capacitor, 0805, x7r, 50v, 10% c 21 , c 22 22f capacitor, 1210, x5r, 10v, 20% c 4 , c 14 100pf capacitor, 0603, cog, 50v, 5% c 6 1500pf capacitor, disc, murata de1e3kx152ma5ba01 c 7 0 jumper, 0603 c 8 330pf capacitor, 0603, cog, 50v, 5% c 9 , c 10 , c 11 , c 12 0.22f capacitor, 0603, x7r, 16v, 10% c r2 , c r6 diode, fairchild es1c c r4 , c r5 diode, ir 12cwq03fn d 1 zener, 18v, zetex bzx84c18 d 2 diode, schottky, bat54c q 1 fet, fairchild fds2570 q 2 transistor, zetex fmmt491a q 3 transistor, on mjd31c r 1 , r 2 1.00k resistor, 1206, 1% r 10 20.0k resistor, 0603, 1% r 7 , r 9 , r 11 , r 26 , r 27 10.0k resistor, 0603, 1% r 12 38.3k resistor, 0603, 1% r 13 , r 15 , r 17 , r 18 , r 19 , r 25 1.00k resistor, 0603, 1% r 14 10 resistor, 0603, 1% r 16 165 resistor, 0603, 1% r 21 10.0 resistor, 1206, 1% r 22 5.11 resistor, 0603, 1% r 24 3.92k resistor, 2512, 1% r 3 , r 23 100 resistor, 0603, 1% r 4 1.00 resistor, 2512, 1% r 5 221k resistor, 0603, 1% r 6 75.0k resistor, 0603, 1% r 8 , r 20 omit t 1 transformer, midcom 31555 u 2 opto-coupler, nec ps2801-1 u 3 shunt reference, national lm431bim3 u 4 pwm, intersil isl6721ib v r1 zener, 15v, zetex bzx84c15 isl6721a
22 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6797.0 august 23, 2011 references 1. ridley, r., ?a new continuous-time model for current mode control?, ieee transactions on power electronics, vol. 6, no. 2, april 1991. 2. dixon, lloyd h., ?closing the feedback loop?, unitrode power supply design seminar, sem-700, 1990. isl6721a
23 fn6797.0 august 23, 2011 isl6721a package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
24 fn6797.0 august 23, 2011 isl6721a l16.3x3b 16 lead quad flat no-lead plastic package rev 1, 4/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 9 ( 2. 80 typ ) ( 1. 70 ) (4x) 0.15 ( 12x 0 . 5 ) ( 16x 0 . 60) ( 16x 0 . 23 ) 0 . 90 0.1 index area pin 1 6 a 3.00 b 3.00 12 4 4 5 8 16x 0.40 0.10 5 0 . 2 ref c 0 . 00 min. 0 . 05 max. b c ma 0.10 c - 0.05 base plane 0.10 c see detail "x" c 0.08 seating plane + 0.07 16x 0.23 16 13 12x 1.5 4x 0.50 1 6 pin #1 index area 1 .70 + 0.10 - 0.15

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