View LCK4993YH-DT_3491457.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet, revision 1 may 5, 2004 lck4993/lck4994 low-voltage pll clock drivers 1 features 12 mhz?100 mhz (lck4993), or 24 mhz?200 mhz (lck4994) output operation matched pair output skew <200 ps zero input-to-output delay 18 lvttl 50% duty-cycle outputs capable of driving 50 ? terminated lines 3.3 v/2.5 v lvttl/lv differential (lvpecl) fault tolerant and hot insertable reference inputs phase adjustments from 625 ps up to 1300 ps steps up to 10.4 ns output divide ratios of (1?6, 8, 10, 12) multiply ratios of (1?6, 8) x input frequency individual output bank disable for aggressive power management and emi reduction output high-impedance (hi-z) option for testing purposes fully integrated pll with lock indicator single 3.3 v/2.5 v 10% supply 100-pin tqfp package 100-ball fsbga package pin-for-pin compatible with cypress ? cy7b993v and cy7b994v 2 description the lck4993 and lck4994 low-voltage pll clock drivers offer user-selectable control over system clock functions. the multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems. each of the eighteen configurable outputs drive terminated transmission lines with impedances as low as 50 ? while delivering minimal and specified output skews at lvttl levels. the outputs are arranged in five banks. banks 1?4 allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps?1300 ps increments up to 10.4 ns. one of the output banks also includes an independent clock invert function. the feedback bank consists of two outputs that allow divide-by functionality from 1 to 12 and limited phase adjustments. any one of these eighteen outputs can be connected to the feedback input or drive other inputs. selectable reference input is a fault tolerance feature that allows smooth change over to the secondary clock source when the primary clock source is not in operation. the reference inputs and feedback inputs are configurable to accommodate both lvttl or differential (lvpecl) inputs. the completely integrated pll reduces jitter and simplifies board layout.
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 table of contents contents page 2 2 agere systems inc. 1 features .................................................................................................................... .........................................................1 2 description ................................................................................................................. .........................................................1 3 functional block diagram .................................................................................................... ...............................................3 4 pin information ............................................................................................................. ......................................................4 4.1 100-pin tqfp diagram ...................................................................................................... .........................................4 4.2 pin descriptions .......................................................................................................... .................................................5 5 functional description ...................................................................................................... ..................................................7 5.1 phase frequency detector and filter ....................................................................................... ...................................7 5.2 vco, control logic, divider, and phase generator .......................................................................... ..........................7 5.3 time unit definition ...................................................................................................... ...............................................7 5.4 divide and phase select matrix ............................................................................................ .......................................8 5.5 timing relationship of programmable skew outputs .......................................................................... .......................9 5.6 output disable description ................................................................................................ ........................................10 5.7 inv3 pin function ......................................................................................................... .............................................10 5.8 lock detect output description ............................................................................................ .....................................10 5.9 factory test mode description ............................................................................................. .....................................11 5.9.1 factory test reset ...................................................................................................... .....................................11 5.10 absolute maximum ratings ................................................................................................. ....................................11 5.11 handling precautions ..................................................................................................... .........................................12 5.12 thermal parameters (definitions and values) .............................................................................. ...........................12 6 electrical characteristics .................................................................................................. ................................................14 7 timing ...................................................................................................................... .........................................................18 7.1 switching characteristics ................................................................................................. .........................................18 7.2 ac test loads and waveforms ............................................................................................... ...................................21 7.3 ac timing diagrams ........................................................................................................ ...........................................22 8 outline diagrams ............................................................................................................ ..................................................23 8.1 100-pin tqfp .............................................................................................................. ..............................................23 8.2 100-ball fsbga ............................................................................................................ ............................................24 9 ordering information ........................................................................................................ .................................................25 tables table 4-1. 100-pin fsbga pin assignments ....................................................................................... ..................................4 table 4-2. 100-pin tqfp descriptions ........................................................................................... ........................................5 table 5-1. frequency range select .............................................................................................. .........................................7 table 5-2. n factor determination.............................................................................................. ............................................7 table 5-3. output skew select function ......................................................................................... .......................................8 table 5-4. output divider function ............................................................................................. ............................................8 table 5-5. dis[1:4]/fbdis pin functionality.................................................................................... .....................................10 table 5-6. factory test mode frequency divide select ........................................................................... ............................ 11 table 5-7. absolute maximum ratings ............................................................................................ ..................................... 11 table 5-8. handling precautions................................................................................................ ...........................................12 table 5-9. thermal parameter values ............................................................................................ ......................................13 table 6-1. electrical characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%)..................................................................14 table 6-2. electrical characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%)..................................................................16 table 7-1. switching characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%) .................................................................18 table 7-2. switching characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%) .................................................................20 table 9-1. lck4993 ordering information........................................................................................ ....................................25 table 9-2. lck4994 ordering information........................................................................................ ....................................25 figures figure 3-1. lck4993 and lck4994 functional block diagram ....................................................................... ......................3 figure 4-1. 100-pin tqfp package (top view).................................................................................... .................................4 figure 5-1. typical outputs with fb connected to a zero-skew output............................................................ ....................9 figure 7-1. ac test loads and waveforms ........................................................................................ ..................................21 figure 7-2. ac timing diagrams ................................................................................................. ..........................................22
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 3 3 functional block diagram figure 3-1. lck4993 and lck4994 functional block diagram divide and phase select matrix 3 3 3 3 1f0 1f1 1ds0 1ds1 dis1 bank 1 1qa0 1qa1 1qb0 1qb1 divide and phase select matrix 3 3 3 3 2f0 2f1 2ds0 2ds1 dis2 bank 2 2qa0 2qa1 2qb0 2qb1 divide and phase select matrix 3 3 3 3 3f0 3f1 3ds0 3ds1 dis3 bank 3 3qa0 3qa1 3qb0 3qb1 divide and phase select matrix 3 3 3 3 4f0 4f1 4ds0 4ds1 dis4 bank 4 4qa0 4qa1 4qb0 4qb1 3 3 3 fbf0 fbds0 fbds1 fbdis feedback bank qfa0 qfa1 divide and phase select matrix 3 3 output_mode fs phase frequency detector control logic divide and phase generator v co filter lock refb+ refb? refsel refa+ refa? fbkb+ fbkb? fbsel fbka + fbka? inv3
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 4 4 agere systems inc. 4 pin information 4.1 100-pin tqfp diagram 5-8885 (f) r.1 figure 4-1. 100-pin tqfp package (top view) table 4-1. 100-pin fsbga pin assignments 1234567 8 910 a 1qb1 1qb0 1qa1 1qa0 qfa0 qfa1 fbkb+ v dd q fbka? fbka+ b v ddn v ddn v ddn v ddn v ddn v ddn v ddq fbkb? fbsel refa+ c gndgndgndgndgndgndv dd q gnd gnd refa? d lock 4f0 3f1 gnd fbds1 fbds0 2f0 v ddq refsel refb? e 4qb1 v ddn 4ds1 gnd 3f0 4f1 gnd fs v ddn refb+ f 4qb0 v ddn 3ds1 gnd gnd gnd gnd fbf0 v ddn 2qa0 g 4qa1 2ds1 v ddq gnd gnd gnd gnd v ddq 1f0 2qa1 h 4qa0 1ds1 1ds0 v ddq gnd gnd v ddq output_ mode fbdis 2qb0 j 4ds0 3ds0 2ds0 dis1 v ddn v ddn gnd inv3 dis3 2qb1 k 2f1 1f1 dis2 v ddn 3qa0 3qa1 gnd 3qb0 3qb1 dis4 gnd v ddq gnd 1qa0 v ddn 1qa1 gnd gnd v ddn 1qb1 gnd fbds0 fbds1 lock 3f1 4f1 3f0 4f0 4ds1 3ds1 gnd 4qb1 v ddn 4qb0 gnd gnd 4qa1 v ddn 4qa0 gnd 2ds1 1ds1 v ddq 4ds0 3ds0 2ds0 1ds0 gnd gnd gnd v ddq v ddq 2f1 1f1 dis1 dis2 gnd 3qa0 v ddn 3qa1 gnd gnd 3qb0 v ddn 3qb1 gnd v ddq inv3 gnd output_mode v ddq refa+ refa? refsel refb? refb+ 2f0 fs gnd 2qa0 v ddn 2qa1 gnd gnd 2qb0 v ddn 2qb1 gnd fbf0 1f0 gnd v ddq fbdis dis3 gnd qfa0 v ddn qfa1 gnd gnd fbkb+ fbkb? fbsel fbka? fbka+ v ddq 1qb0 88 89 90 91 92 93 95 96 97 98 99 100 87 86 85 84 83 82 81 80 79 78 77 76 94 38 37 36 35 34 33 31 30 29 28 27 26 39 40 41 42 43 44 45 46 47 48 49 50 32 13 12 11 10 9 8 6 5 4 3 2 1 14 15 16 17 18 19 20 21 22 23 24 25 7 63 64 65 66 67 68 70 71 72 73 74 75 62 61 60 59 58 57 56 55 54 53 52 51 69 dis4 gnd gnd
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 5 4.2 pin descriptions for all 3-state inputs, low indicates a connection to gnd, mid indicates an open connection, and high indicates a connection to v dd . internal termination circuitry holds an unconnected input to v dd /2. table 4-2. 100-pin tqfp descriptions pin symbol type i/o description 1, 8, 12, 13, 17, 25?28, 35, 39, 40, 44, 47, 50, 55, 58, 62, 63, 67, 82, 83, 87, 88, 92, 93, 97 gnd power ? ground. 2?5, 31, 32, 56, 69 [1:4]f[0:1] 3-level input i output phase function select. each pair controls the phase function of the respective bank of outputs, see ta b le 5 - 3 . 6, 7, 18, 19, 21?24 [1:4]ds[0:1] 3-level input i output divider function select. each pair controls the divide function of the respective bank of outputs, see ta b le 5 - 4 . 9, 11, 14, 16, 36, 38, 41, 43, 59, 61, 64, 66, 89, 91, 94, 96 [1:4]q[a:b][0:1] lvttl o clock output. these outputs provide numerous divide and phase select functions determined by the [1:4]ds[0:1] and [1:4]f[0:1] inputs. 10, 15, 37, 42, 60, 65, 85, 90, 95 v ddn power ? output buffer power. power supply for each output pair. 20, 29, 30, 45, 49, 54, 75, 76 v ddq power ? internal power. power supply for the internal circuitry. 33, 34, 51, 52 dis[1:4] lvttl i d output disable. each input controls the state of the respective output bank. low = the [1:4]q[a:b][0:1] is enabled, see table 5-5 . high = the output bank is disabled to the hold-off or hi-z state; the disable state is determined by output_mode. 46 inv3 3-level input i invert mode. this input only affects bank3. low = each matched output pair will become complementary (3qa0+, 3qa1?, 3qb0+, 3qb1?). mid = all four outputs will be noninverting. high = all four outputs in the same bank will be inverted. 48 output_mode 3-level input i output mode. this pin determines the clock outputs? disable state. low = the clock outputs will disable to hold-off mode. mid = the device enters factory test mode. high = the clock outputs will disable to hi-z. 53 fbdis lvttl i d feedback disable. this input controls the state of qfa[0:1]. low = the qfa[0:1] is enabled, see table 5-5 . high = the qfa[0:1] is disabled to the hold-off or hi-z state; the disable state is determined by output_mode. 57 fbf0 3-level input i feedback output phase function select. this input deter- mines the phase function of the feedback banks qfa[0:1] out- puts, see table 5-3 . 68 fs 3-level input i frequency select. this input must be set according to the nominal frequency (f nom ), see table 5-1 ). 70, 71, 73, 74 refb+, refb?, refa?, refa+ lvttl/ lvdiff i reference inputs. these inputs can operate as differential pecl or single-ended ttl reference inputs to the pll. when operating as a single-ended lvttl input, the complementary input must be left open. note: i d = each input has an internal pull-down resistor.
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 6 6 agere systems inc. 72 refsel lvttl i d reference input select. the refsel input controls how the reference input is configured. low = refsel uses the refa pair as the reference input. high = refsel uses the refb pair as the reference input. 77, 78, 80, 81 fbka+, fbka?, fbkb?, fbkb+ lvttl/ lvdiff i feedback inputs. one pair of inputs selected by the fbsel is used to feedback the clock output xqn to the phase detector. the pll will operate so that the rising edges of the reference and feedback signals are aligned in both phase and frequency. these inputs can operate as differential pecl or single-ended ttl inputs. when operating as a single-ended lvttl input, the complementary input must be left open. 79 fbsel lvttl i d feedback input select. low = fbka inputs are selected. high = fbkb inputs are selected. 84, 86 qfa[0:1] lvttl o clock feedback output. this pair of clock outputs is intended to be connected to the fb input. these outputs have numerous divide options and three choices of phase adjustments. the function is determined by setting the fbds[0:1] pins and fbf0. 98, 99 fbds[0:1] 3-level input i feedback divider function select. these inputs determine the function of the qfa0 and qfa1 outputs, see ta b l e 5 - 4 . 100 lock lvttl o pll lock indicator. low = the pll is attempting to acquire lock. high = this output indicates the internal pll is locked to the ref- erence signal. note: i d = each input has an internal pull-down resistor. table 4-2. 100-pin tqfp descriptions (continued) pin symbol type i/o description
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 7 5 functional description 5.1 phase frequency detector and filter these two blocks accept signals from the ref inputs (refa+, refa?, refb+, or refb?) and the fb inputs (fbka+, fbka?, fbkb+, or fbkb?). correction information is then generated to control the frequency of the voltage-controlled oscillator (v co ). these two blocks, along with the v co , form a phase-locked loop (pll) that tracks the incoming ref signal. the devices have a flexible ref and fb input scheme. these inputs allow using either differential lvpecl or single-ended lvttl inputs. to configure as single-ended lvttl inputs, the complementary input pin must be left open (internally pulled to 1.5 v), and the other input pin can then be used as an lvttl input. the ref inputs are also tolerant to hot insertion. the ref inputs can be changed dynamically. when changing from one reference input to the other reference input of the same frequency, the pll is optimized to ensure that the clock output period will not be less than the calculated system budget (t min = t ref (nominal reference clock period) ? t ccj (cycle-to-cycle jitter) ? t pdev (maximum period deviation)) while reacquiring lock. 5.2 v co , control logic, divider, and phase generator the v co accepts analog control inputs from the pll filter block. the fs control pin setting determines the nominal operational frequency (f nom ) range of the divide-by-one output of the device. f nom is directly related to the v co frequency. there are two versions of the device, a low-speed device (lck4993) where f nom ranges from 12 mhz to 100 mhz, and a high-speed device (lck4994) where f nom ranges from 24 mhz to 200 mhz. the fs setting for each device is shown in ta b l e 5 - 1 . the f nom frequency is seen on divide-by-one outputs. for the lck4994, the upper f nom range extends from 96 mhz to 200 mhz. 5.3 time unit definition selectable skew is in discrete increments of time unit (t u ). the value of t u is determined by the fs setting and the f nom frequency. the equation to be used to determine the t u is as follows: (eq. 1) where n is a multiplication factor, determined by the fs setting and is defined in table 5-2; where f nom is the nominal operating frequency of the vco. table 5-1. frequency range select fs * * the level to be set on fs is determined by the f nom of the v co and phase generator. f nom always appears on an output when the output is operating in the divide by 1 mode. the ref and fb are at f nom when the output connected to fb is in the divide by 1 mode. lck4993 lck4994 f nom (mhz) f nom (mhz) min max min max low 12 26 24 52 mid 24 52 48 100 high 48 100 96 200 table 5-2. n factor determination fs lck4993 lck4994 nf nom (mhz) at which t u = 1.0 ns n f nom (mhz) at which t u = 1.0 ns low 64 15.265 32 31.25 mid 32 31.25 16 62.5 high 16 62.5 8 125 t u 1 f nom n ------------------------- - =
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 8 8 agere systems inc. 5.4 divide and phase select matrix the divide and phase select matrix is comprised of five independent banks as follows: four banks for clock outputs and one bank for feedback. each clock output bank has two pairs of low-skew, high-fanout output buffers ([1:4]q[a:b][0:1]), two phase function select inputs ([1:4]f[0:1]), two divider function selects ([1:4]ds[0:1]), and one output disable (dis[1:4]). the feedback bank has one pair of low-skew, high-fanout output buffers (qfa[0:1]). one of these outputs may connect to the selected feedback input (fbk[a:b]). this feedback bank also has one phase function select input (fbf0), two divider function selects fsds[0:1], and one output disable (fbdis). the phase capabilities that are chosen by the phase function select pins are shown in table 5-3 . the divide capabilities for each bank are shown in table 5-4 . table 5-3. output skew select function function selects output skew function [1:4]f1 [1:4]f0 and fbf0 bank1 bank2 bank3 bank4 feedback bank low low ?4 t u ?4 t u ?8 t u ?8 t u ?4 t u low mid ?3 t u ?3 t u ?7 t u ?7 t u na low high ?2 t u ?2 t u ?6 t u ?6 t u na mid low ? 1t u ?1 t u bk1 * * bk1 denotes following the skew of bank1. ? bk2 denotes following the skew of bank2. bk1* na mid mid 0 t u 0 t u 0 t u 0 t u 0 t u mid high 1 t u 1 t u bk2 ? bk2 ? na high low 2 t u 2 t u 6 t u 6 t u na high mid 3 t u 3 t u 7 t u 7 t u na high high 4 t u 4 t u 8 t u 8 t u 4 t u table 5-4. output divider function function selects * output divider function [1:4]ds1 and fbds1 [1:4]ds0 and fbds0 bank1 bank2 bank3 bank4 feedback bank low low /1 /1 /1 /1 /1 low mid /2 /2 /2 /2 /2 low high /3/3/3/3 /3 mid low /4 /4 /4 /4 /4 mid mid /5 /5 /5 /5 /5 mid high /6/6/6/6 /6 high low /8/8/8/8 /8 high mid /10 /10 /10 /10 /10 high high /12 /12 /12 /12 /12 * output frequency = f nom (vco frequency)/value of output divisor.
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 9 5.5 timing relationship of programmable skew outputs figure 5-1 illustrates the timing relationship of programmable skew outputs. all times are measured with respect to ref, with the output used for feedback programed with 0 t u skew. the pll naturally aligns the rising edge of the fb input and ref input. if the output used for feedback is programmed to another skew position, then the whole t u matrix will shift with respect to ref. for example, if the output used for feedback is programmed to shift ?8 t u , then the whole matrix is shifted forward in time by 8 t u . therefore, an output programed with 8 t u of skew will effectively be skewed 16 t u with respect to ref. note: fb connected to an output selected for zero skew (i.e., fbf0 = mid or xf[1:0] = mid). figure 5-1. typical outputs with fb connected to a zero-skew output 1f[1:0] 2f[1:0] 3f[1:0] 4f[1:0] na ll ?8 t u na lm ?7 t u na lh ?6 t u ll na ?4 t u lm na ?3 t u lh na ?2 t u ml na ?1 t u mm mm 0 t u mh na 1 t u hl na 2 t u hm na 3 t u hh na 4 t u na hl 6 t u na hm 7 t u na hh 8 t u t 0 ? 8 t u t 0 ? 7 t u t 0 ? 6 t u t 0 ? 4 t u t 0 ? 3 t u t 0 ? 2 t u t 0 ? 1 t u t 0 t 0 + 1 t u t 0 + 2 t u t 0 + 3 t u t 0 + 4 t u t 0 + 5 t u t 0 + 6 t u t 0 + 7 t u t 0 + 8 t u t 0 ? 5 t u fb input ref input
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 10 10 agere systems inc. 5.6 output disable description the feedback divide and phase select matrix bank has two outputs, each of the four divide and phase select matrix banks have four outputs. the outputs of each bank can be independently put into a hold-off, or hi-z state. the combination of the output_mode and dis[1:4]/fbdis inputs determines the clock outputs? state for each bank. when the dis[1:4]/fbdis is low, the outputs of the corresponding bank will be enabled. when the dis[1:4]/fbdis is high the outputs for that bank will be disabled to a hi-z or hold-off state, depending on the output_mode input. table 5-5 defines the disabled output functions. the hold-off state is intended to be a power saving feature. an output bank is disabled to the hold-off state in a maximum of six output clock cycles from the time when the disable input (dis[1:4]/fbdis) is high. when disabled to the hold-off state, noninverting outputs are driven to a logic-low state on its falling edge. inverting outputs are driven to a logic-high state on its rising edge. this ensures the output clocks are stopped without a glitch. when a bank of outputs is disabled to a hi-z state, the respective bank of outputs will go hi-z immediately. 5.7 inv3 pin function bank3 has signal invert capability. the four outputs of bank3 will act as two pairs of complementary outputs when the inv3 pin is driven low. in complementary output mode, 3qa0 and 3qb0 are noninverting; 3qa1 and 3qb1 are inverting outputs. all four outputs will be inverted when the inv3 pin is driven high. when the inv3 pin is left in mid, the outputs will not inve rt. inversion of the outputs are independent of the skew and divide functions. therefore, clock outputs of bank3 can be inverted, divided, and skewed at the same time. 5.8 lock detect output description the lock detect output indicates the lock condition of the integrated pll. lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit (t pd ). when in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the lock output will be forced low to indicate out-of-lock state. when in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the lock output to indicate lock condition (lock = high). if the feedback clock is removed after lock has gone high, a watchdog circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting lock low. this time-out period is based on a divided down reference clock. this assumes that there is activity on the selected ref input. if there is no activity on the selected ref input, then the lock detect pin may not accurately reflect the state of the internal pll. table 5-5. dis[1:4]/fbdis pin functionality output_mode dis[1:4]/fbdis output mode high/low low enabled high high hi-z low high hold-off mid x factory test
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 11 5.9 factory test mode description the device will enter factory test mode when the output_mode input is driven to a mid level. in factory test mode, the device will operate with its internal pll disconnected. the reference input will replace the pll output. while operating in factory test mode, the selected fb input(s) must both be tied low. the output frequency is a function of the input level set on the fs pin (see table 5-6). when operating in factory test mode, all outputs must be set to the divide by 1 function. output skew select function operates normally, output bank disable is unavailable while operating in factory test mode. the output_mode input is designed to be a static input. dynamically toggling this input from low to high may temporarily cause the device to go into factory test mode (when passing through the mid state). 5.9.1 factory test reset when operating in factory test mode (output_mode = mid), the device can be reset to a deterministic state by forcing the dis4 input to a logic high. with dis4 in a logic high state, all clock outputs will go to hi-z. after the selected referenc e clock pin has five positive transitions, all the internal finite state machines (fsm) will be set to a deterministic state. the deterministic state of the state machines will depend on the configuration of the divide select, skew select, and frequency select inputs. all clock outputs will stay in high-impedance mode, and all fsms will stay in the deterministic state until dis4 is deasserted. when dis4 is deasserted (with output_mode still at mid), the device will re-enter factory test mode. 5.10 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 5-6. factory test mode frequency divide select fs lck4993 lck4994 output frequency output frequency divide by divide by low 32 16 mid 16 8 high 8 4 table 5-7. absolute maximum ratings parameter symbol min max unit storage temperature t stg ?40 125 c supply voltage v dd ?0.5 4.6 v dc input voltage v dc ?0.3 v dd + 0.5 v output current into outputs (low) i out ?40ma latch-up current i l ?200ma
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 12 12 agere systems inc. 5.11 handling precautions although electrostatic discharge (esd) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to esd and electrical overstress (eos) during all handling, assembly, and test operations. agere employs both a human-body model (hbm) and a charged-device model (cdm) qualification requirement in order to deter- mine esd susceptibility limits and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by jedec's jesd22-a114 (hbm) and jesd22-c101 (cdm) stan- dards. caution: mos devices are susceptible to damage from electrostatic charge. reasonable precautions in handling and pack- aging mos devices should be observed. 5.12 thermal parameters (definitions and values) system and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. the thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. when the die temperature is kept below 125 c, temperature-activated failure mechanisms are minimized. the thermal parameters that agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and in- tegrate their systems. it should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja - junction to air thermal resistance ja is a number used to express the thermal performance of a part under jedec standard natural convection conditions. ja is calculated using the following formula: ja = (t j ? t amb ) / p; where p = power jma - junction to moving air thermal resistance jma is effectively identical to ja but represents performance of a part mounted on a jedec four-layer board inside a wind tunnel with forced air convection. jma is reported at airflows of 200 lfpm and 500 lfpm (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). jma is calculated using the following formula: jma = (t j ? t amb ) / p jc - junction to case thermal resistance jc is the thermal resistance from junction to the top of the case. this number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. this is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. jc is calculated using the following formula: jc = (t j ? t c ) / p table 5-8. handling precautions device minimum threshold hbm cdm lck4993 2000 v 500 v lck4994 2000 v 500 v
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 13 jb - junction to board thermal resistance jb is the thermal resistance from junction to board. this number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. this is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. jb is calculated using the following formula: jb = (t j ? t b ) / p jt jt correlates the junction temperature to the case temperature. it is generally used by the customer to infer the junction temperature while the part is operating in their system. it is not considered a true thermal resistance. jt is calculated using the following formula: jt = (t j ? t c ) / p table 5-9. thermal parameter values parameter temperature c/watt 100-pin tqfp 100-ball fsbga ja 38 71.9 jma (1 m/s) 32.9 66.6 jma (2.5 m/s) 30.4 64.7 jc 32.9 24.5 jb 29.9 56.8 jt 11
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 14 14 agere systems inc. 6 electrical characteristics . table 6-1. electrical characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%) parameter symbol description test conditions min max unit lvttl compatible output pins (qfa[0:1], [1:4]q[a:b], lock high-voltage output (lvttl) v oh qfa[0:1], [1:4]q[a:b][0:1] v dd = min, i oh = ?30 ma 2.4 ? v lock v dd = min, i oh = ?2 ma 2.4 ? v low-voltage output (lvttl) v ol qfa[0:1], [1:4]q[a:b][0:1] v dd = min, i oh = 30 ma ? 0.5 v lock v dd = min, i oh = 2 ma ? 0.5 v high-imped- ance state leak- age current i oz ? ? ?100 100 a lvttl compatible pins (fbka, fbkb, refa, refb, fbsel, refsel, fbdis, dis[1:4]) high-voltage input (lvttl) v ih fbk[a:b], ref[a:b] min v dd max 2.0 v dd + 0.3 v refsel, fbsel, fbdis, dis[1:4] ? 2.0 v dd + 0.3 v low-voltage input (lvttl) v il fbk[a:b], ref[a:b] min v dd max ?0.3 0.8 v refsel, fbsel, fbdis, dis[1:4] ? ?0.3 0.8 v high-input current (lvttl) i ih fbk[a:b], ref[a:b] v dd = max, v in = v dd ? 500 a refsel, fbsel, fbdis, dis[1:4] v in = v dd ? 500 a low-input current (lvttl) i il fbk[a:b], ref[a:b] v dd = max, v in = gnd ?500 ? a refsel, fbsel, fbdis, dis[1:4] v in = gnd ?500 ? a 3-level input pins (fbf0, fbds[0:1], [1:4]f[0:1], [1:4]ds[0:1], fs, output_mode(test) low-voltage 3-level input 1 v ill ?min v dd max ? 0.13 x v dd v mid-voltage 3-level input 1 v imm ?min v dd max 0.47 x v dd 0.53 x v dd v high-voltage 3-level input 1 v ihh ?min v dd max 0.87 x v dd ?v low-current 3-level input i ill 3-level input pins excluding fbf0 v in = gnd ?200 ? a fbf0 v in = gnd ?400 ? a mid-current 3-level input i imm 3-level input pins excluding fbf0 v in = v dd /2 ?50 50 a fbf0 v in = v dd /2 ?100 100 a high-current 3-level input i ihh 3-level input pins excluding fbf0 v in = v dd ? 200 a fbf0 v in = v dd ? 400 a 1. these inputs are normally wired to v dd , gnd, or left unconnected (actual threshold voltages vary as a percentage of v dd ). internal termination resistors hold the unconnected inputs at v dd /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved.
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 15 lvdiff input pins (fbk[a:b], ref[a:b]) input differential voltage v diff ? ? 400 v dd mv lowest input low voltage v illp ??gndv dd ? 0.4 v highest input high voltage v ihhp ??1.0v dd v common-mode range (crossing voltage) v com ??0.8v dd v operating current internal operat- ing current i cci lck4993 v dd = max, f max ? 250 ma lck4994 v dd = max, f max 1 ? 250 ma output current dissipation/pair 2 i ccn lck4993 v dd = max, c load = 25 pf, r load = 50 ? at v dd /2, f max ?40ma lck4994 v dd = max, c load = 25 pf, r load = 50 ? at v dd /2, f max ?50ma capacitance input capaci- tance c in ?t a = 25 c, f = 1 mhz, v dd = 3.3 v/2.5 v ?5pf 1. i cci measurements are performed with bank1 and fb bank configured to run at maximum frequency (f nom = 100 mhz for lck4993, f nom = 200 mhz for lck4994), and all other clock output banks to run at half the maximum frequency. fs and output_mode are asserted to the high state. 2. this is dependent upon frequency and number of outputs of a bank being loaded. the value indicates maximum i ccn at maximum frequency and maximum load of 25 pf terminated to 50 ? at v dd /2. table 6-1. electrical characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%) (continued) parameter symbol description test conditions min max unit
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 16 16 agere systems inc. table 6-2. electrical characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%) parameter symbol description test conditions min max unit lvttl compatible output pins (qfa[0:1], [1:4]q[a:b], lock) high-voltage output (lvttl) v oh qfa[0:1], [1:4]q[a:b][0:1] v dd = min, i oh = ?30 ma 1.6 ? v lock v dd = min, i oh = ?2 ma 1.6 ? v low-voltage output (lvttl) v ol qfa[0:1], [1:4]q[a:b][0:1] v dd = min, i oh = 30 ma ? 0.5 v lock v dd = min, i oh = 2 ma ? 0.5 v high-imped- ance state leak- age current i oz ? ? ?100 100 a lvttl compatible pins (fbka, fbkb, refa, refb, fbsel, refsel, fbdis, dis[1:4]) high-voltage input (lvttl) v ih fbk[a:b], ref[a:b] min v dd max 2.0 v dd + 0.3 v refsel, fbsel, fbdis, dis[1:4] ? 2.0 v dd + 0.3 v low-voltage input (lvttl) v il fbk[a:b], ref[a:b] min v dd max ?0.3 0.8 v refsel, fbsel, fbdis, dis[1:4] ? ?0.3 0.8 v high-input current (lvttl) i ih fbk[a:b], ref[a:b] v dd = max, v in = v dd ? 500 a refsel, fbsel, fbdis, dis[1:4] v in = v dd ? 500 a low-input current (lvttl) i il fbk[a:b], ref[a:b] v dd = max, v in = gnd ? 500 a refsel, fbsel, fbdis, dis[1:4] ? ?500 ? a 3-level input pins (fbf0, fbds[0:1], [1:4]f[0:1], [1:4]ds[0:1], fs, output_mode(test)) low-voltage 3-level input 1 v ill ?min v dd max ? 0.13 x v dd v mid-voltage 3-level input 1 v imm ?min v dd max 0.47 x v dd 0.53 x v dd v high-voltage 3-level input 1 v ihh ?min v dd max 0.87 x v dd ?v low-current 3-level input i ill 3-level input pins excluding fbf0 v in = gnd ?200 ? a fbf0 v in = gnd ?400 ? a mid-current 3-level input i imm 3-level input pins excluding fbf0 v in = v dd /2 ?50 50 a fbf0 v in = v dd /2 ?100 100 a high-current 3-level input i ihh 3-level input pins excluding fbf0 v in = v dd ? 200 a fbf0 v in = v dd ? 400 a 1. these inputs are normally wired to v dd , gnd, or left unconnected (actual threshold voltages vary as a percentage of v dd ). internal termination resistors hold the unconnected inputs at v dd /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved.
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 17 lvdiff input pins (fbk[a:b], ref[a:b]) input differential voltage v diff ? ? 400 v dd mv lowest input low voltage v illp ??gndv dd ? 0.4 v highest input high voltage v ihhp ??1.0v dd v common-mode range (crossing voltage) v com ??0.8v dd v operating current internal operat- ing current i cci lck4993 v dd = max, f max ? 250 ma lck4994 v dd = max, f max 1 ? 250 ma output current dissipation/pair 2 i ccn lck4993 v dd = max, c load = 25 pf, r load = 50 ? at v dd /2, f max ?40ma lck4994 v dd = max, c load = 25 pf, r load = 50 ? at v dd /2, f max ?50ma capacitance input capaci- tance c in ?t a = 25 c, f = 1 mhz, v dd = 3.3 v/2.5 v ?5pf 1. i cci measurements are performed with bank1 and fb bank configured to run at maximum frequency (f nom = 100 mhz for lck4993, f nom = 200 mhz for lck4994), and all other clock output banks to run at half the maximum frequency. fs and output_mode are asserted to the high state. 2. this is dependent upon frequency and number of outputs of a bank being loaded. the value indicates maximum i ccn at maximum frequency and maximum load of 25 pf terminated to 50 ? at v dd /2. table 6-2. electrical characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%) (continued) parameter symbol description test conditions min max unit
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 18 18 agere systems inc. 7 timing 7.1 switching characteristics the following switching characteristics and assumptions apply for non 3-level inputs. a maximum 25 pf load capacitance is used for frequencies up to 185 mhz. a maximum 10 pf load capacitance is used for the frequency of 200 mhz. both outputs of the pair must be terminated, even if only one is being used. ac parameters are measured at 50%, unless otherwise indicated. table 7-1. switching characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%) parameter symbol description min max unit clock input frequency f in lck4993 12 100 mhz lck4994 24 200 mhz clock output frequency f out lck4993 12 100 mhz lck4994 24 200 mhz ref input t refpwl pulse width low. 8 2.0 ? ns t refpwh pulse width high. 8 2.0 ? ns matched-pair skew 1, 2 t skewpr same frequency and phase, rise-to-rise and fall-to- fall. (matched pair outputs within a bank.) 1, 2 ?200 ps interbank skew t skewbnk same frequency and phase, rise-to-rise and fall-to- fall. (all outputs within a bank.) 1, 2 ?200 ps output-output skew t skew0 same frequency and phase, rise-to-rise and fall-to- fall. (all outputs across all banks.) 1, 2 ?250 ps t skew1 different frequency same phase, rise-to-rise and fall-to-fall. (all outputs all banks.) 1, 2 ?250 ps t skew2 same frequency and phase, rise-to-fall and fall-to- rise. (bank 3 inverted to all other banks.) 1, 2, 3 ?250 ps t skew3 all output configurations outside t skew1 and t skew2 . 1, 2 ?500 ps complementary outputs skew t skewcpr crossing to crossing, complementary outputs. (bank 3 only.) 1, 2, 3, 4 ?200 ps cycle-to-cycle jitter t ccj divide by 1 output frequency, fb = divide by 1?8 . ?150 ps propagation delay t pd ref to fb rise. ?250 250 ps t pddelta difference between two devices. 4 ?200 ps output rise/fall time 5 t r /t f ? 0.15 2.0 ns 1. test load c l maximum 25 pf (fnom 185 mhz) and maximum 10 pf (fnom = 200 mhz) both terminated 50 ? to v dd /2. 2. skew is defined as the time between the earliest and latest output transition among all outputs for which the same phase del ay has been selected and all outputs are equally loaded and properly terminated. 3. complementary output skews are measured at complementary signal pair intersections. 4. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 5. rise and fall times are measured at 20% and 80% of the output voltage swing. 6. f nom must be within the frequency range defined by the fs state (see table 5-1). 7. ac parameters are measured at 50%, unless otherwise indicated. 8. t pwl is measured at 20%. t pwh is measured at 80%. 9. ui = unit interval. examples: 1 ui is a full period. 0.1 ui is 10% of a period. 10. measured at 0.5 v deviation from starting voltage. 11. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf at 200 mhz.
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 19 parameter symbol description min max unit pll lock time from powerup t lock ??10ms pll relock time t relock1 from same frequency, different phase, and with sta- ble power supply. ?500 s t relock2 from different frequency, different phase, and with stable power supply. 6 ?1000 s output duty cycle 7 t odcv ?4555% period deviation t pdev when changing from reference to reference. ? 0.025 ui 9 output disable time t oza dis[1:4]/fbdis low to output active from output is high-impedance. 10, 11 0.5 14 ns output enable time t oaz dis[1:4]/fbdis high to output high-impedance from active. 1, 10 1.0 10 ns 1. test load c l maximum 25 pf (fnom 185 mhz) and maximum 10 pf (fnom = 200 mhz) both terminated 50 ? to v dd /2. 2. skew is defined as the time between the earliest and latest output transition among all outputs for which the same phase del ay has been selected and all outputs are equally loaded and properly terminated. 3. complementary output skews are measured at complementary signal pair intersections. 4. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 5. rise and fall times are measured at 20% and 80% of the output voltage swing. 6. f nom must be within the frequency range defined by the fs state (see table 5-1). 7. ac parameters are measured at 50%, unless otherwise indicated. 8. t pwl is measured at 20%. t pwh is measured at 80%. 9. ui = unit interval. examples: 1 ui is a full period. 0.1 ui is 10% of a period. 10. measured at 0.5 v deviation from starting voltage. 11. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf at 200 mhz. table 7-1. switching characteristics (t a ?40 c to +85 c, v dd = 3.3 v 10%) (continued)
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 20 20 agere systems inc. table 7-2. switching characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%) parameter symbol description min max unit clock input frequency f in lck4993. 12 100 mhz lck4994. 24 200 mhz clock output frequency f out lck4993. 12 100 mhz lck4994. 24 200 mhz ref input t refpwl pulse width low. 8 2.0 ? ns t refpwh pulse width high. 8 2.0 ? ns matched-pair skew 1, 2 t skewpr same frequency and phase, rise-to-rise and fall-to- fall. (matched pair outputs within a bank.) 1, 2 ? 200 ps interbank skew t skewbnk same frequency and phase, rise-to-rise and fall-to- fall. (all outputs within a bank.) 1, 2 ? 200 ps output-output skew t skew0 same frequency and phase, rise-to-rise and fall-to- fall. (all outputs across all banks.) 1, 2 ? 250 ps t skew1 different frequency same phase, rise-to-rise and fall-to-fall. (all outputs all banks.) 1, 2 ? 250 ps t skew2 same frequency and phase, rise-to-fall and fall-to- rise. (bank 3 inverted to all other banks.) 1, 2, 3 ? 250 ps t skew3 all output configurations outside t skew1 and t skew2 . 1, 2 ? 500 ps complementary outputs skew t skewcpr crossing to crossing, complementary outputs. (bank 3 only.) 1, 2, 3, 4 ? 200 ps cycle-to-cycle jitter t ccj1?3 divide by 1 output frequency, fb = divide by 1?8 . ? 150 ps propagation delay t pd ref to fb rise . ?250 250 ps t pddelta difference between two devices. 4 ? 200 ps output rise/fall time 5 t r /t f ? 0.15 2.0 ns 1. test load c l maximum 25 pf (fnom 185 mhz) and maximum 10 pf (fnom = 200 mhz) both terminated 50 ? to v dd /2. 2. skew is defined as the time between the earliest and latest output transition among all outputs for which the same phase del ay has been selected and all outputs are equally loaded and properly terminated. 3. complementary output skews are measured at complementary signal pair intersections. 4. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 5. rise and fall times are measured at 20% and 80% of the output voltage swing. 6. f nom must be within the frequency range defined by the fs state (see table 5-1). 7. ac parameters are measured at 50%, unless otherwise indicated. 8. t pwl is measured at 20%. t pwh is measured at 80%. 9. ui = unit interval. examples: 1 ui is a full period. 0.1 ui is 10% of a period. 10. measured at 0.5 v deviation from starting voltage. 11. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf at 200 mhz.
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 21 7.2 ac test loads and waveforms note: figure 7-1 is for illustrative purposes only. the actual ate loads may vary. figure 7-1. ac test loads and waveforms parameter symbol description min max unit pll lock time from powerup t lock ??10ms pll relock time t relock1 from same frequency, different phase, and with stable power supply. ? 500 s t relock2 from different frequency, different phase, and with stable power supply. 6 ? 1000 s output duty cycle 7 t odcv ?4555% period deviation t pdev when changing from reference to reference. ? 0.025 ui 9 output disable time t oza dis[1:4]/fbdis low to output active from output is high-impedance. 10, 11 0.5 14 ns output enable time t oaz dis[1:4]/fbdis high to output high-impedance from active. 1, 10 1.0 10 ns 1. test load c l maximum 25 pf (fnom 185 mhz) and maximum 10 pf (fnom = 200 mhz) both terminated 50 ? to v dd /2. 2. skew is defined as the time between the earliest and latest output transition among all outputs for which the same phase del ay has been selected and all outputs are equally loaded and properly terminated. 3. complementary output skews are measured at complementary signal pair intersections. 4. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 5. rise and fall times are measured at 20% and 80% of the output voltage swing. 6. f nom must be within the frequency range defined by the fs state (see table 5-1). 7. ac parameters are measured at 50%, unless otherwise indicated. 8. t pwl is measured at 20%. t pwh is measured at 80%. 9. ui = unit interval. examples: 1 ui is a full period. 0.1 ui is 10% of a period. 10. measured at 0.5 v deviation from starting voltage. 11. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf at 200 mhz. table 7-2. switching characteristics (t a ?40 c to +85 c, v dd = 2.5 v 10%) (continued) 0.8 v 2.0 v 3.3 v 0.8 v 2.0 v gnd 1 ns 1 ns output 3.3 v r1 r2 c l ttl input lvttl ac test load test waveform for lock output only: ? r1 = 910 ? ? r2 = 910 ? ?c l < 30 pf for all other outputs: ? r1 = 100 ? ? r2 = 100 ? ?c l max = 25 pf to 185 mhz or c l max = 10 pf at 200 mhz (the above include fixture and probe capacitances.) ttl input waveform lvttl ac test load
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 22 22 agere systems inc. 7.3 ac timing diagrams ac parameters are measured at 50%, unless otherwise indicated. figure 7-2. ac timing diagrams ref t refpwl t refpwh fb q t pd t pwh t pwl 80% 20% t ccj1?3, 4?12 ref to device 1 and 2 fb device 1 fb device 2 t pd t pdelta t pdelta q inverted q t skew2 t skew2 q other q t skew0,1 t skew0, 1 qfa0 or qfa1 or t skewpr t skewpr [1:4]q[a:b]0 [1:4]q[a:b]1 t skewbnk t skewbnk [1:4]qa[0:1] [1:4]qb[0:1] t odcv t odcv complementary a crossing t skewcpr complementary b crossing
data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers agere systems inc. 23 8 outline diagrams 8.1 100-pin tqfp controlling dimensions are in millimeters. 5-2146 (f) r.1 0.50 typ 1.60 max seating plane 0.08 1.40 0.05 0.20 max detail a detail b 14.00 0.05 16.00 0.25 76 100 1 25 26 50 51 75 14.00 0.05 16.00 0.25 pin #1 identifier zone detail b 0.22 0.05 0.08 m 0.05/0.15 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25
lck4993/lck4994 data sheet, revision 1 low-voltage pll clock drivers may 5, 2004 24 24 agere systems inc. 8.2 100-ball fsbga controlling dimensions are in millimeters. 5-8159.a (f) r.1 note: the ball diameter, ball pitch, and stand-off and package thicknesses are different from jedec spec m0192 (low-pro- file bga family). a b c d e f g h j k 10 0.53 0.05 0.40 0.05 0.36 0.15 1.45 max 11.00 0.10 11.00 0.10 1.00 typ ? 0.45 0.05 typ 1.00 solder balls a1 indicator a1 indicator top view bottom view 11.00 0.10 8 7 6 5 4 3 2 1 9
copyright ? 2004 agere systems inc. all rights reserved may 5, 2004 ds04-014lck-1 (replaces ds04-014lck) agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere is a registered trademark of agere systems inc. agere systems and the agere logo are trademarks of agere systems inc. for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 296 400 data sheet, revision 1 lck4993/lck4994 may 5, 2004 low-voltage pll clock drivers 9 ordering information cypress is a registered trademark of cypress semiconductor corporation. table 9-1. lck4993 ordering information device package type comcode delivery lck4993yh-db 100fsbga 700034618 tray LCK4993YH-DT 100fsbga 700034619 tape lck4993kb-db 100tqfp 700024614 tray lck4993kb-dt 100tqfp 700024615 tape table 9-2. lck4994 ordering information device package type comcode delivery lck4994yh-db 100fsbga 700042835 tray lck4994yh-dt 100fsbga 700042836 tape lck4994kb-db 100tqfp 700025705 tray lck4994kb-dt 100tqfp 700025708 tape

▲Up To Search▲

Price & Availability of LCK4993YH-DT

	To Download LCK4993YH-DT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .