tl/f/6476 dm54s195/DM74S195 4-bit parallel access shift registers june 1989 dm54s195/DM74S195 4-bit parallel access shift registers general description these 4-bit registers feature parallel inputs, parallel outputs, j-k serial inputs, shift/load control input, and a direct over- riding clear. all inputs are buffered to lower the input drive requirements. the registers have two modes of operation: parallel (broadside) load shift (in the direction q a toward q d ) parallel loading is accomplished by applying the four bits of data and taking the shift/load control input low. the data is loaded into the associated flip-flop and appears at the out- puts after the positive transition of the clock input. during loading, serial data flow is inhibited. shifting is accomplished synchronously when the shift/load control input is high. serial data for this mode is entered at the j-k inputs. these inputs permit the first stage to perform as a j-k , d, or t-type flip-flop as shown in the truth table. the high-performance s195, with a 105 mhz typical shift frequency, is particularly attractive for very high-speed data processing systems. in most cases existing systems can be upgraded merely by using this schottky-clamped shift regis- ter. features y synchronous parallel load y positive-edge-triggered clocking y parallel inputs and outputs from each flip-flop y direct overriding clear y j and k inputs to first stage y complementary outputs from last stage y for use in high-performance: accumulators/processors serial-to-parallel, parallel-to-serial converters y typical clock frequency 105 mhz y typical power dissipation 350 mw connection diagram dual-in-line package tl/f/6476 1 order number dm54s195j or DM74S195n see ns package number j16a or n16e c 1995 national semiconductor corporation rrd-b30m105/printed in u. s. a.
absolute maximum ratings (note) if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply voltage 7v input voltage 5.5v operating free air temperature range dm54s b 55 cto a 125 c dm74s 0 cto a 70 c storage temperature range b 65 cto a 150 c note: the ``absolute maximum ratings'' are those values beyond which the safety of the device cannot be guaran- teed. the device should not be operated at these limits. the parametric values defined in the ``electrical characteristics'' table are not guaranteed at the absolute maximum ratings. the ``recommended operating conditions'' table will define the conditions for actual device operation. recommended operating conditions symbol parameter dm54s195 DM74S195 units min nom max min nom max v cc supply voltage 4.5 5 5.5 4.75 5 5.25 v v ih high level input voltage 2 2 v v il low level input voltage 0.8 0.8 v i oh high level output current b 1 b 1ma i ol low level output current 20 20 ma f clk clock frequency (note 1) 0 105 70 0 105 70 mhz f clk clock frequency (note 2) 0 90 60 0 90 60 mhz t w pulse width clock 7 7 ns (note 3) clear 12 12 t su setup time shift/load 11 11 ns (note 3) data 5 5 t h data hold time (note 3) 3 3 ns t rel shift/load release time (note 3) 6 6 ns clear release time (note 3) 9 9 t a free air operating temperature b 55 125 0 70 c note 1: c l e 15 pf, r l e 280 x ,t a e 25 c and v cc e 5v. note 2: c l e 50 pf, r l e 280 x ,t a e 25 c and v cc e 5v. note 3: t a e 25 c and v cc e 5v. electrical characteristics over recommended operating free air temperature (unless otherwise noted) symbol parameter conditions min typ max units (note 4) v i input clamp voltage v cc e min, i i eb 18 ma b 1.2 v v oh high level output v cc e min, i oh e max dm54 2.5 3.4 v voltage v il e max, v ih e min dm74 2.7 3.4 v ol low level output v cc e min, i ol e max 0.5 v voltage v ih e min, v il e max i i input current @ max v cc e max, v i e 5.5v 1ma input voltage i ih high level input current v cc e max, v i e 2.7v 50 m a i il low level input current v cc e max, v i e 0.5v b 2ma i os short circuit v cc e max dm54 b 40 b 100 ma output current (note 5) dm74 b 40 b 100 i cc supply current v cc e max (note 6) 70 109 ma note 4: all typicals are at v cc e 5v, t a e 25 c. note 5: not more than one output should be shorted at a time, and the duration should not exceed one second. note 6: with all inputs open, shift/load grounded, and 4.5v applied to the j, k, and data inputs, i cc is measured by applying a momentary ground, then 4.5v to the clear and then applying a momentary ground then 4.5v to the clock. 2
switching characteristics at v cc e 5v and t a e 25 c (see section 1 for test waveforms and output load) r l e 280 x symbol parameter from (input) c l e 15 pf c l e 50 pf units to (output) min max min max f max maximum clock 70 60 mhz frequency t plh propagation delay time clock to 12 15 ns low to high level output any q t phl propagation delay time clock to 16.5 20 ns high to low level output any q t phl propagation delay time clear to 18.5 23 ns high to low level output any q function table inputs outputs clear shift/ clock serial parallel q a q b q c q d q d load jk abcd lxxxxxxxxllllh hl u xxabcda b c d d hh lxxxxxxq a0 q b0 q c0 q d0 q d0 hh u lhxxxxq a0 q a0 q bn q cn q cn hh u llxxxxlq an q bn q cn q cn hh u hhxxxxhq an q bn q cn q cn hh u hlxxxxq an q an q bn q cn q cn h e high level (steady state), l e low level (steady state), x e don't care (any input, including transitions) u e transition from low to high level a, b, c, d e the level of steady state input at a, b, c, or d, respectively. q a0 ,q b0 ,q c0 ,q d0 e the level of q a ,q b ,q c ,orq d , respectively, before the indicated steady state input conditions were established. q an ,q bn ,q cn e the level of q a ,q b ,q c , respectively, before the most recent transition of the clock. logic diagram tl/f/6476 2 3
timing diagram typical clear, shift, and load sequences tl/f/6476 3 4
physical dimensions inches (millimeters) 16-lead ceramic dual-in-line package (j) order number dm54s195j ns package number j16a 5
dm54s195/DM74S195 4-bit parallel access shift registers physical dimensions inches (millimeters) (continued) 16-lead molded dual-in-line package (n) order number DM74S195n ns package number n16e life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: ( a 49) 0-180-530 85 86 13th floor, straight block, tel: 81-043-299-2309 arlington, tx 76017 email: cnjwge @ tevm2.nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: ( a 49) 0-180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: ( a 49) 0-180-532 78 32 hong kong fran 3 ais tel: ( a 49) 0-180-532 93 58 tel: (852) 2737-1600 italiano tel: ( a 49) 0-180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.
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