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e preliminary december 1998 order number: 290434-008 n 2, 4, 10 and 20 megabyte capacities n pcmcia 2.1/jeida 4.1 68-pin standard ? hardwired card information structure ? byte- or word-wide selectable n component management registers for card status/control and flexible system interface n automatic erase/write ? monitored with ready/busy output n card power-down modes ? deep-sleep for low power applications n mechanical write protect switch n solid-state reliability n intel flashfile? memory architecture n high-performance read access ? 150 ns maximum n high-performance random writes ? 6 s typical word write n erase suspend to read command ? keeps erase as background task n nonvolatility (zero retention power) ? no batteries required for back-up n 0.4 etox? v flash memory technology ? 5 v read, 12 v erase/write ? high-volume manufacturing experience the intel ? series 2 flash memory card facilitates high-performance disk emulation in mobile pcs and dedicated equipment. manufactured with intel ? etox? iii 0.8 and intel ? flashfile? memory devices, the series 2 card allows code and data retention while erasing and/or writing other blo cks. additi onally, the series 2 flash memory card features low power modes, flexible system interfacing and a 150 ns read access time. when coupled with intels low-power microprocessors, these cards enable high-performance implementations of mobile computers and systems. series 2 cards conform to the personal computer memory card international association (pcmcia 2.1)/japanese electronics industry development association (jeida 4.1) 68-pin standard, providing electrical and physical compatibility. data file management software, flash translation layer (ftl), provides data file storage and memory management, much like a disk operating system. intel series 2 flash memory cards, c oupled with flash file management software, effectively provide a removable, all-silicon mass storage solution with higher performance and reliability than disk-based memory architectures. designing with intel flashfile memory architecture enables oem system m anufacturers to design and manufacture a new generation of mobile pcs and dedicated equipment where high performance, ruggedness, long battery life and lighter weight are a requirement. for large user groups in workstation environments, the series 2 cards provide a means to securely store user data and backup system configuration/status information. note: this document formerly known as series 2 flash memory cards . 5 volt series 2 flash memory card imc002flsa, IMC004FLSA, imc010flsa, imc020flsa
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the imc002flsa, IMC004FLSA, imc010flsa, imc020flsa may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800 548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1996, 1997, 1998 cg-041493 *third-part y brands and names are the propert y of their respective owners
e imc002/004/010/020flsa 3 preliminary contents page page 1.0 applications.............................................. 5 2.0 series 2 architecture overview ....... 7 3.0 pcmcia/jeida interface ......................... 7 4.0 write protect switch.......................... 11 5.0 battery voltage detect .................... 11 6.0 card detect............................................. 11 7.0 design considerations ....................... 11 8.0 address decode..................................... 12 9.0 data control.......................................... 12 10.0 principles of operaton .................... 12 11.0 common memory array ..................... 14 12.0 hardwired cis ....................................... 14 13.0 component management registers (cmrs)......................................................... 14 13.1 soft reset register (pcmcia) ................ 14 13.2 global power-down register (pcmcia).. 15 13.3 card status register (intel) ..................... 16 13.4 write protection register (intel) ............... 17 13.5 sleep control register (intel)................... 18 13.6 ready-busy status register (intel).......... 18 13.7 ready-busy mask register (intel) ........... 19 13.8 ready-busy mode register (intel) ........... 20 14.0 principles of device operation..... 21 15.0 command definitions.......................... 23 15.1 read array (ffh) .................................... 23 15.2 intelligent identifier (90h)......................... 23 15.3 read status register (70h)..................... 23 15.4 clear status register (50h)..................... 23 15.5 write setup/write..................................... 23 15.6 erase setup/erase confirm commands (20h) ........................................................ 24 15.7 erase suspend (b0h)/erase resume (d0h)........................................................ 24 15.8 invalid/reserved ...................................... 24 16.0 device status register..................... 25 17.0 power consumption ........................... 28 17.1 standby mode.......................................... 28 17.2 sleep mode.............................................. 29 18.0 system design considerations ...... 29 18.1 power supply decoupling ........................ 29 19.0 power up/down protection............. 29 20.0 hot insertion/removal...................... 29 21.0 pcmcia card information structure ............................................... 29 21.1 the device information tuple .................. 29 21.2 the device geometry tuple .................... 30 21.3 jedec programming information tuple .... 30 21.4 level 1 version/product information tuple......................................................... 30 21.5 the configurable card tuple ................... 31 21.6 the end-of-list tuple .............................. 31 22.0 electrical specifications ............... 35 22.1 absolute maximum ratings ..................... 35 22.2 operating conditions ............................... 35 22.3 capacitance............................................. 35 22.4 common dc characteristics cmos and ttl ........................................................... 36 22.5 dc characteristicscmos..................... 37 22.6 dc characteristicsttl ......................... 39 22.7 ac characteristics ................................... 40 23.0 ordering information ....................... 51 24.0 additional information..................... 51
imc002/004/010/020flsa e 4 preliminary revision history version description -001 original version -002 added 150 ns tuple, deleted 250 ns tuple corrected global power register address to 4002h corrected write protection register address to 4104h corrected ready-busy mode register address to 4140h i cc standby byte wide mode max/typ increased added power-on timing spec added first access after reset spec changed advanced information to preliminary -003 added 2-mbyte card support changed write timing waveforms to match pcmcia changed powerdown (pwd) to reset-powerdown (rp) -004 extended operating temperature range added maximum byte write time -005 added 150 ns timings change cover drawing to accommodate label -006 modified dc characteristics to reflect a conversion to new memory components the 0.4 version of the 28f008sa. the new devices also have improved program and erase performance. -007 updated dc characteristics, cmos table to correct i ccs , i pps1 and i pps2 specification values updated dc characteristics, ttl, table to correct i ccs , i pps1 and i pps2 specification values eliminated provisions for extended temperature version of card -008 changed name of document from series 2 flash memory cards
e imc002/004/010/020flsa 5 preliminary 1.0 applications intels second generation series 2 flash memory cards facilitate high performance disk emulation for the storage of data files and application programs on a purely solid-state removable medium. file management software, flash translation layer (ftl), in conjunction with the series 2 flash memory cards, enable the design of high-performance light-weight notebook, palmtop, and pen-based pcs that have the processing power of todays desktop computers. application software stored on the flash memory card substantially reduces the slow disk-to-dram download process. replacing the mechanical disk results in a dramatic enhancement of read performance and substantial reduction of power consumption, size and weightconsiderations particularly important in portable pcs and equipment. the series 2 cards high performance read access time allows the use of series 2 cards in an execute-in-place (xip) architecture. xip eliminates redundancy associated with dram/disk memory system architectures. operating systems stored in flash memory decreases system boot or program load times, enabling the design of pcs that boot, operate, store data files and execute application programs from/to nonvolatile memory without losing the ability to perform an update. file management systems modify and store data files by allocating flash memory space intelligently. wear leveling algorithms, employed to equally distribute the number of rewrite cycles, ensure that no particular block is cycled excessively relative to other blocks. this provides hundreds of thousands of hours of power on usage. this file management software enables the user to interact with the flash memory card in precisely the same way as a magnetic disk. series 2 flash memory cards provide durable nonvolatile memory storage for mobile pcs on the road, facilitating simple transfer back into the desktop environment. for systems currently using a static ram/battery configuration for data acquisition, the series 2 flash memory cards nonvolatility eliminates the need for battery backup. the concern for battery failure no longer exists, an important consideration for portable computers and medical instruments, both requiring continuous operation. series 2 cards consume no power when the system is off, and only 60 a in deep-sleep mode (2 megabyte card). furthermore, flash memory cards offer a considerable cost and density advantage over memory cards based on static ram with battery backup. besides disk emulation, the series 2 cards electrical block-erasure, data writability, and inherent nonvolatility fit well with data accumulation and recording needs. electrical block-erasure provides design flexibility to selectively rewrite blocks of data, while saving other blocks for infr equently updated parameters and lookup tables. for example, networks and systems that utilize large banks of battery-backed dram to store configuration and status benefit from the series 2 flash cards nonvolatility and reliability.
imc002/004/010/020flsa e 6 preliminary 29043403 figure 1. 16-mbyte flash memory card block diagram showing major functional elements
e imc002/004/010/020flsa 7 preliminary 2.0 series 2 architecture overview the series 2 flash memory card contains a 2 to 20 mb flash memory array consisting of 2 to 20 28f008sa flashfile memory devices. each 28f008sa contains sixteen individually-erasable, 64 kbyte blocks; therefore, the flash memory card contains from 32 to 320 device blo cks. it also contains two card control logic devices that manage the external interface, address decoding, and component management logic. (refer to figure 1 for a block diagram.) to support pcmcia-compatible word-wide access, devices are paired so that each accessible memory block is 64 kwords (see figure 2). card logic allows the system to write or r ead one word at a time, or one byte at a time by referencing the high or low byte. erasure can be performed on the entire block pair (high and low device blocks simultaneously), or on the high or low byte portion separately. also in accordance with pcmcia specifications this product supports byte-wide operation, in which the flash array is divided into 128k x 8 bit device blocks. in this configuration, odd bytes are multiplexed onto the low byte data bus. series 2 flash memory cards offer additional features over the bulk erase flash card product family (refer to imc001flka, imc002flka and imc004flka datasheets). some of the more notable enhancements include: high density capability, erase blocking, internal write/erase automation, erase suspension to read, component management registers (cmrs) that provide software control of device-level functions and a deep-sleep mode. erase blocking facilitates solid-state storage applications by allowing selective memory reclamation. multiple 64-kbyte blocks may be simultaneously erased within the memory card as long as not more than one block per device is erasing. this shortens the total time required for erasure, but requires additional supply current. a block typically requires 1.6 seconds to erase. each memory block can be erased and completely written 100,000 times. erase suspend allows the system to temporarily interrupt a block erase operation. this mode permits reads from alternate device blo cks while that same device contains an erasing block. upon completion of the read operation, erasure of the suspended block must be resumed. write/erase automation simplifies the system software interface to the card. a two-step command sequence initiates write or erase operations and provides additional data security. internal device circuits automatically execute the algorithms and timings necessary for data-write or block-erase operations, including verifications for long-term data integrity. while performing either data-write or block-erase, the memory card interface reflects this by bringing its rdy/bsy# (ready/busy) pin low. this output goes high when the operation completes. this feature reduces cpu overhead and allows software polling or hardware interrupt mechanisms. writing memory data is achieved in single byte or word increments, typically in 6 s. read access time is 150 ns or less over the entire operating temperature range. the reset power-down mode reduces power consumption to less than 60 a to help extend battery life of portable host systems. activated through software control, this mode optionally affects the entire flash array (global reset power- down register) or specific device pairs (sleep control register). 3.0 pcmcia/jeida interface the series 2 flash memory card interface supports the pcmcia 2.1 and jeida 4.1 68-pin card format (see tables 1 and 2). detailed specifications are described in the pc card standard , release 2.1, july, 1993, published by pcmcia. the series 2 card conforms to the requirements of both release 1 and release 2 of the pc card standard . series 2 card pin definitions are equivalent to the bulk erase flash card except that certain no connects are now used. a 22 through a 24 , rst (reset), and rdy/bsy# (ready/busy) have pin assignments as set by the pcmcia standard. note: the ready/busy signal is abbreviated as rdy/bsy# by pcmcia (card level) and as ry/by# by jedec (component level). the outer shell of the series 2 card meets all pcmcia/jeida type 1 mechanical specifications. see figure 19 for mechanical dimensions.
imc002/004/010/020flsa e 8 preliminary table 1. series 2 flash memory card pinout pin signal i/o function active 1 gnd ground 2dq 3 i/o data bit 3 3dq 4 i/o data bit 4 4dq 5 i/o data bit 5 5dq 6 i/o data bit 6 6dq 7 i/o data bit 7 7ce 1 # i card enable 1 lo 8a 10 i address bit 10 9 oe# i output enable lo 10 a 11 i address bit 11 11 a 9 i address bit 9 12 a 8 i address bit 8 13 a 13 i address bit 13 14 a 14 i address bit 14 15 we# i write enable lo 16 rdy/bsy# ready-busy hi/lo 17 v cc supply voltage 18 v pp1 supply voltage 19 a 16 i address bit 16 20 a 15 i address bit 15 21 a 12 i address bit 12 22 a 7 i address bit 7 23 a 6 i address bit 6 24 a 5 i address bit 5 25 a 4 i address bit 4 26 a 3 i address bit 3 27 a 2 i address bit 2 28 a 1 i address bit 1 pin signal i/o function active 29 a 0 i address bit 0 30 dq 0 i/o data bit 0 31 dq 1 i/o data bit 1 32 dq 2 i/o data bit 2 33 wp o write protect hi 34 gnd ground 35 gnd ground 36 cd 1 # o card detect 1 lo 37 dq 11 i/o data bit 11 38 dq 12 i/o data bit 12 39 dq 13 i/o data bit 13 40 dq 14 i/o data bit 14 41 dq 15 i/o data bit 15 42 ce 2 # i card enable 2 lo 43 vs 1 o voltage sense 1 n.c. 44 rfu reserved 45 rfu reserved 46 a 17 i address bit 17 47 a 18 i address bit 18 48 a 19 i address bit 19 49 a 20 i address bit 20 50 a 21 i address bit 21 51 v cc supply voltage 52 v pp2 supply voltage 53 a 22 i address bit 22 54 a 23 i address bit 23 55 a 24 i address bit 24 56 a 25 no connect
e imc002/004/010/020flsa 9 preliminary pin signal i/o function active 57 vs 2 o voltage sense 2 n.c. 58 rst i reset hi 59 wait# o extend bus cycle lo 60 rfu reserved 61 reg# i register select lo 62 bvd 2 o batt. volt det 2 pin signal i/o function active 63 bvd 1 o batt. volt det 1 64 dq 8 i/o data bit 8 65 dq 9 i/o data bit 9 66 dq 10 i/o data bit 10 67 cd 2 # o card detect 2 lo 68 gnd ground table 2. series 2 flash memory card pin descriptions symbol type name and function a 0 C a 25 i address inputs: a 0 through a 25 are address bus lines which enable direct addressing of 64 megabytes of memory on a card. a 0 is not used in word access mode. a 24 is the most significant address bit. note: a 25 is a no-connect but should be provided on host side. dq 0 C dq 15 i/o data input/output: dq 0 through dq 15 constitute the bidirectional data bus. dq 15 is the most significant bit. ce 1 #, ce 2 #i card enable 1, 2: ce 1 # enables even bytes, ce 2 # enables odd bytes. multiplexing a 0 , ce 1 # and ce 2 # allows 8-bit hosts to access all data on dq 0 through dq 7 . (see table 3 for a more detailed description.) oe# i output enable: active low signal gating read data from the memory card. we# i write enable: active low signal gating write data to the memory card. rdy/bsy# o ready/busy output: indicates status of internally timed erase or write activities. a high output indicates the memory card is ready to accept accesses. a low output indicates that a device(s) in the memory card is(are) busy with internally timed activities. see text for an alternate function ( ready-busy mode register ). cd 1 # & cd 2 #o card detect 1, 2: these signals provide for correct card insertion detection. they are positioned at opposite ends of the card to detect proper alignment. the signals are connected to ground internally on the memory card and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins. wp o write protect: write protect reflects the status of the write-protect switch on the memory card. wp set high = write protected, providing internal hardware write lockout to the flash array. v pp1 , v pp2 write/erase power supply: (12 v nominal) for erasing memory array blocks or writing data in the array. they must be 12 v to perform an erase/write operation. v cc card power supply (5 v nominal) for all internal circuitry.
imc002/004/010/020flsa e 10 preliminary table 2. series 2 flash memory card pin descriptions (continued) symbol type name and function gnd i ground for all internal circuitry. reg# i register select provides access to series 2 flash memory card registers and card information structure in the attribute memory plane. rst i reset from system, active high. places card in power-on default state. reset pulse width must be 3 200 ns. wait# o wait (extend bus cycle) is used by intels i/o cards and is driven high. bvd 1 , bvd 2 o battery voltage detect: upon completion of the power on reset cycle, these signals are driven high to maintain sram-card compatibility. rfu reserved for future use nc no internal connection . pin may be driven or left floating. vs 1 , vs 2 voltage sense: notifies the host socket of the cards v cc requirements. vs 1 and vs 2 are both open, indicating a 5 v v cc card. 29043401 figure 2. memory architecture; each device pair consists of sixteen 64-kword blocks
e imc002/004/010/020flsa 11 preliminary 4.0 write protect switch a mechanical write protect switch provides the cards memory array with internal write lockout. the write-protect (wp) output pin reflects the status of this mechanical switch. it outputs a high signal (v oh ) when writes are disabled. this switch does not lock out writes to the cmrs. 5.0 battery voltage detect pcmcia requires two signals, bvd 1 and bvd 2 , be supplied at the interface to reflect card battery condition. flash memory cards do not require batteries. when the power on reset cycle is complete, bvd 1 and bvd 2 are driven high to maintain compatibility. 6.0 card detect two signals, cd 1 # and cd 2 #, allow the host to determine proper socket seating. they reside at opposite ends of the connector and are tied to ground within the memory card. 7.0 design considerations the series 2 card consists of two separate memory planes: the common memory plane (or main memory) and the attribute memory plane. the common memory plane resides in the banks of device pairs and represents the user-alterable memory space. the component management registers (cmr) and the hardwired card information structure (cis) reside in the attribute memory plane within the card control logic, as shown in figure 3. the card control logic interfaces the pcmcia connector and the internal flash memory array and performs address decoding and data control. 29043402 figure 3. component management registers allow s/w control of components within card
imc002/004/010/020flsa e 12 preliminary 8.0 address decode address decoding provides the decoding logic for the 2 to 20 device chip enables and the elements of the attribute memory plane. reg# selects between the common memory plane (reg# = v ih ) and the attribute memory plane (reg# = v il ). note the series 2 card has active address inputs a 0 to a 24 implying that reading and writing to addresses beyond 32 megabytes causes wraparound. furthermore, reads to illegal addresses (for example, between 20 and 32 meg on a 20-mb card) returns default data (00ffh or ffffh). the 28f008sa devices, storing data, applications or firmware, form the common memory plane accessed individually or as device pairs. memory is linearly mapped in the common memory plane. three memory access modes are available when accessing the common memory plane: byte-wide, word-wide, and odd-byte modes. additional decoding selects the hardwired pcmcia cis and cmrs mapped in the attribute memory plane beginning at address 000000h. the 512 memory-mapped even-byte cmrs are linearly mapped beginning at address 4000h in the attribute memory plane. 9.0 data control data control logic selects the path and direction for accessing the common or attribute memory plane. it controls any of the pcmcia-defined byte-wide, word-wide, and odd-byte modes, for either reads or writes to these areas. as shown in table 3, input pins which determine these selections are reg#, a 0 through a 24 , we#, oe#, ce 1 #, and ce 2 #. pcmcia specifications allow only even-byte access to the attribute memory plane. in byte-wide mode, bytes contiguous in software actually alternate between two device blo cks of a device pair. therefore, erasure of one device block erases every other contiguous byte. in accordance with the pcmcia standard for memory configuration, the series 2 card does not support confining contiguous bytes within one flash device when in x8 mode. 10.0 principles of operaton intels series 2 flash memory card provides electrically-alterable, nonvolatile, random-access storage. individual 28f008sa devices utilize a command user interface (cui) and write state machine (wsm) to simplify block-erasure and data write operations.
e imc002/004/010/020flsa 13 preliminary table 3. data access mode truth table function mode reg# ce# 2 ce# 1 a 0 oe# we# v pp2 v pp1 d 15 Cd 8 d 7 Cd 0 common memory plane standby (1) xhhxxxv ppl (2) v ppl (2) high-z high-z byte read h h l l l h v ppl (2) v ppl (2) high-z even-byte hhlhlhv ppl (2) v ppl (2) high-z odd-byte word read h l l x l h v ppl (2) v ppl (2) odd-byte even-byte odd-byte read hlhxlhv ppl (2) v ppl (2) odd-byte high-z byte write h h l l h l v pph v pph x even-byte hhlhhlv pph v pph x odd-byte word write h l l x h l v pph v pph odd-byte even-byte odd-byte write hlhxhlv pph v ppl (2) odd-byte x attribute memory plane byte read l h l l l h x (2) x (2) high-z even-byte lhlhlhx (2) x (2) high-z invalid word read l l l x l h x (2) x (2) invalid data (3) even-byte odd-byte read llhxlhx (2) x (2) invalid data (3) high-z byte write l h l l h l x (2) x (2) x even-byte lhlhhlx (2) x (2) x invalid operation (3) word write l l l x h l x (2) x (2) invalid operation (3) even-byte odd-byte write llhxhlx (2) x (2) invalid operation (3) x notes: 1. standby mode is valid in common memory or attribute memory access. 2. to meet the low power specifications, v pp = v ppl ; however v pph presents no reliability problems. 3. odd-byte data are not valid during access to the attribute memory plane. 4. h = v ih , l = v il , x = dont care.
imc002/004/010/020flsa e 14 preliminary 11.0 common memory array figure 4 shows the common memory planes organization. the first block pair (64 kwords) of common memory, referred to as the common memory card information structure block, optionally extends the hardwired cis in the attribute memory plane for additional card information. this may be written during initial card formatting for oem customization. since this cis block is part of common memory, its data can be altered. write access to the common memory cis block is controlled by the write protect control register which may be activated by system software after power- up. additionally, the entire common memory plane (minus the common memory cis block) may be software write protected. note: the common memory cis block is not part of the attribute memory plane. do not assert reg# to access the common memory cis block. device pair 9 device pair 8 device pair 7 device pair 6 device pair 5 device pair 4 device pair 3 device pair 2 device pair 1 device pair 0 optional cis 0000000h 0020000h 0200000h 0400000h 0600000h 0800000h 0a00000h 0c00000h 0e00000h 1000000h 1200000h 13fffffh fig4 figure 4. common memory plane use the optional common memory plane cis for custom card format information 12.0 hardwired cis the cards structure description resides in the even- byte locations starting at 0000h and going to the cis ending tuple (fnull) within the attribute memory plane. data included in the hardwired cis consists of tuples. tuples are a variable-length list of data blocks describing details such as manufacturers name, the size of each memory device and the number of flash devices within the card. 13.0 component management registers (cmrs) the cmrs in the attribute memory plane provide special, software-controlled functionality. card control logic includes circuitry to access the cmrs. reg (pcmcia, pin 61) selects the attribute memory plane (and therefore the cmrs) when equal to v il . cmrs are classified into two categories: those defined by pcmcia r2.1 and those included by intel (referred to as performance enhancement registers) to enhance the interface between the host system and the cards flash memory array. cmrs (see figure 3) provide seven control functionsready-busy interrupt mode, device ready-busy status, device ready-busy mask, reset- powerdown control, software-controlled write protection, card status and soft reset. 13.1 soft reset register (pcmcia) (configuration option) the soft reset register (attribute memory plane address 4000h, figure 5) is defined in the pcmcia release 2.0 specification as the configuration option register. bit 7 is the soft reset bit (sreset). writing a 1 to this bit initiates card reset to the power-on default state. this bit must be cleared to use the cmrs or to access the devices. sreset implements in software what the reset pin implements in hardware. on power-up, the card automatically assumes default conditions. similar to the reset pin (pin 58), this bit clears at the end of a power-on reset cycle or a system reset cycle. bits 0 through 6 are not used by this memory card, but power up as zeroes for pcmcia compatibility.
e imc002/004/010/020flsa 15 preliminary soft reset register (configuration option register) (read/write register) 1 = reset, clear to access card address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sreset 4000h pcmcia configuration index resets to zero on power-up fig5 figure 5. soft reset register (pcmcia) sets the memory card in the power-on default state power-on default conditions all devices powered-up in standby mode common memory available for writes all device ready/busy outputs unmasked pcmcia ready/busy mode enabled ready/busy output goes to ready 13.2 global power-down register (pcmcia) (configuration and status) the global reset power-down register (attribute memory plane address 4002h, figure 6) is referred to as the configuration and status register in the pcmcia release 2.0 specification. bit 2 (rp) controls global card power-down. writing a 1 to this bit places each device within the card into deep-sleep mode. devices in deep-sleep are not accessible. recovery from power-down requires 500 ns for reads and 1 s for writes. the rp bit defaults to 0 on card power-up or reset. setting or clearing this bit has no affect on the bit settings of the sleep control register. the remaining global reset power-down register bits are defined for intels family of i/o cards and are driven low for compatibility.
imc002/004/010/020flsa e 16 preliminary global reset power-down register (configuration and status register) (read/write register) 1 = power-down address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 zeroes 4002h rp zeroes fig6 figure 6. global reset power-down register (pcmcia) the rp bit enables reset power-down of all flash memory devices 13.3 card status register (intel) the read-only, card status register (attribute memory plane address 4100h, figure 7) returns generalized status of the series 2 card and its cmrs. bit 0 (rdy/bsy#) reflects the cards rdy/bsy# (ready-busy) output. software polling of this bit provides data-write or block-erase operation status. a zero indicates a busy device(s) in the card.? bit 1 (wp) reports the position of the cards write protection switch with 1 indicating write protected. it reports the status of the wp pin. bit 2 (ciswp) reflects whether the common memory cis is write protected using the write protect register, with 1 indicating write protected. bit 3 (rp) reports whether the entire flash memory array is in deep-sleep (reset power-down) mode, with 1 indicating deep-sleep. this bit reflects the rp bit of the global reset power-down register. powering down all device pairs individually (using the sleep control register), also sets this bit. bit 4 (cmwp) reports whether the common memory plane (minus common memory cis) is write protected via the write protect register with 1 indicating write protected. bit 5 (sreset) reflects the sreset bit of the soft reset register. it reports that the card is in soft reset with 1 indicating reset. when this bit is zero, the flash memory array and cmrs may be accessed, otherwise clear it via the sreset register. bit 6 (ads, any device sleep) is the ored value of the sleep control register. powering down any device pair sets this bit. bit 7 (adm, any device masked) is the ored value of the ready/busy mask register. masking any device sets this bit.
e imc002/004/010/020flsa 17 preliminary card status register (read only register) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm 4100h ads sreset cmwp rp ciswp wp rdy/bsy# fig7 figure 7. card status register (intel) provides a quick review of the cards status write protection register (read/write register) 1 = write protect address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved for future use 4104h cmwp ciswp fig8 figure 8. write protection register (intel) eliminates accidental data corruption 13.4 write protection register (intel) the write protection register (attribute memory plane address 4104h, figure 8) selects whether the optional common memory cis and the remaining common memory blocks are write protected (see figure 4). enable common memory cis write protection by writing a 1 to the ciswp bit (bit 0). enable write protection of the remaining common memory blocks by writing a 1 to the cmwp bit (bit 1). in the power-on default state, both bits are 0, and therefore not write protected. reserved bits (2 C7) have undefined values and should be written as zeroes for future compatibility.
imc002/004/010/020flsa e 18 preliminary sleep control register (read/write register) 1 = selected device pair in power-down mode and reset address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 411ah devices 18/19 devices 16/17 4118h devices 14/15 devices 12/13 devices 10/11 devices 8/9 devices 6/7 devices 4/5 devices 2/3 devices 0/1 fig9 figure 9. sleep control register (intel) allows specific devised to be reset and put into power-down mode 13.5 sleep control register (intel) unlike the global reset power-down register, which simultaneously resets and places all flash memory devices into a deep-sleep mode, the sleep control register (attribute memory plane address 4118h C 411ah, figure 9) allows selective power-down control of individual device pairs. writing a 1 to a specific bit of the sleep control register places the corresponding device pair into the deep-sleep mode . devices in deep-sleep are not accessible . on cards with fewer than 20 mb (10 device pairs), writing a one to an absent device pair has no affect and reads back as zero. this register contains all zeroes (i.e., not in deep- sleep mode) when the card powers up or after a hard or soft reset. furthermore, the global reset power-down register has no affect on the contents of this register. therefore, any bit settings of the sleep control register will remain unchanged after returning from a global reset and power down (writing a zero to the rp bit of the global reset power-down register). 13.6 ready-busy status register (intel) the bits in the read-only, ready-busy status register (attribute memory plane address 4130h-4134h, figure 10) reflect the status (ready=1, busy=0) of each devices ry/by# output. a busy condition indicates that a device is currently processing a data-write or block-erase operation. these bits are logically and-ed to form the ready/busy output (rdy/bsy#, pin 16) of the pcmcia interface. on memory cards with fewer than 20 devices, unused device ry/by# status register bits appear as ready.
e imc002/004/010/020flsa 19 preliminary ready-busy status register (read/write register) 1 = device ready, 0 = device busy address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 4134h device 17 device 16 device 19 device 18 4132h device 15 device 14 device 13 device 12 device 11 device 10 device 9 device 8 4130h device 7 device 6 device 5 device 4 device 3 device 2 device 1 device 0 fig10 figure 10. ready-busy status register (intel) provides operation status of all flash memory devices ready-busy mask (read/write register) 1 = mask enabled address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 4124h device 17 device 16 device 19 device 18 4122h device 15 device 14 device 13 device 12 device 11 device 10 device 9 device 8 4120h device 7 device 6 device 5 device 4 device 3 device 2 device 1 device 0 fig11 figure 11. ready-busy mask register (intel) essential for write optimization 13.7 ready-busy mask register (intel) the bits of the read/write ready-busy mask register (attribute memory plane address 4120h C4124h, figure 11) mask out the corresponding and-ed ready-busy status register bits from the pcmcia data bus (rdy/bsy#, pin 16) and the card status register rdy/bsy# bit (bit 0). in an unmasked condition (mask register bits = 0), any device ry/by# output going low pulls the cards rdy/bsy# output to v il (busy). in this case, all devices must be ready to allow the cards rdy/bsy# output to be ready (v ih ). this is referred to as the pcmcia ready-busy mode. an alternate type of ready-busy function is described in the next section, ready-busy mode register .
imc002/004/010/020flsa e 20 preliminary if the ready-busy mask register bits are set to ones (masked condition), the rdy/bsy# output and the card status register rdy/bsy# bit will reflect a ready condition regardless of the state of the corresponding devices. the ready-busy mask register does not affect the ready-busy status register allowing software polling to determine operation status. unmasked is the default condition for the bits in this register. on memory cards with fewer than 20 devices, unused device mask bits appear as masked. 13.8 ready-busy mode register (intel) the ready-busy mode register (attribute memory plane address 4140h, figure 12) provides the selection of two types of system interfacing for the busy-to-ready transition of the cards rdy/bsy# pin: 1. the standard pcmcia ready-busy mode, in which the cards rdy/bsy# signal generates a low-to-high transition (from busy to ready) only after all busy devices (not including masked devices) have completed their data-write or block-erase operations. this may result in a long interrupt latency. 2. a high-performance mode that generates a low- to-high (from busy-to-ready) transition after each device becomes ready. this provides the host system with immediate notification that a specific devices operation has completed and that device may now be used. this is particularly useful in a file management application where a block pair, containing only deleted files, is being erased to free up space so new file data may be written. enabling the high-performance ready-busy mode requires a three step sequence: 1. set all bits in the ready/busy mask register. this prevents ready devices from triggering an unwanted interrupt when step 3 is performed. 2. write 01h to the ready-busy mode register. this sets the mode bit. 3. write 01h to the ready-busy mode register. this clears the rack bit. the mode and rack bits must be written in the prescribed sequence, not simultaneously. the cards circuitry is designed purposely in this manner to prevent an initial, unwanted busy-to-ready transition. note that in step 2, writing to the rack bit is a dont care. when the high-performance mode is enabled, specific ready-busy mask bits must be cleared after an operation is initiated on the respective devices. after each device becomes ready, the rdy/bsy# pin makes a low-to-high transition. to catch the next devices completion of an operation, the rack bit must be cleared by writing 01h to the ready-busy mode register. ready-busy mode register (read/write register) mode = read-busy mode 0 = pcmcia mode 1 = high performance rack = ready acknowledge clear to set up rdy/bsy# pin, then clear after each device becomes ready to acknowledge transition. address bit 7 bit 6 bit 5 bit 4 bit 4 bit 2 bit 1 bit 0 rack 4140h reserved for future use mode fig12 figure 12. high performance ready-busy mode register (intel)
e imc002/004/010/020flsa 21 preliminary 14.0 principles of device operation individual 28f008sa devices include a command user interface (cui) and a write state machine (wsm) to manage write and erase functions in each device block. the cui serves as the devices interface to the card control logic by directing commands to the appropriate device circuitry (table 4). it allows for fixed power supplies during block erasure and data writes. the cui handles the we# interface into the device data and address latches, as well as system software requests for status while the wsm is operating. the cui itself does not occupy an addressable memory location. the cui provides a latch used to store the command and address and data information needed to execute the command. erase setup and erase confirm commands require both appropriate command data and an address within the block to be erased. the data write setup command requires both appropriate command data and the address of the location to be written, while the data write command consists of the data to be written and the address of the location to be written. the cui initiates flash memory writing and erasing operations only when v pp is at 12 v. depending on the application, the system desi gner may choose to make the v pp power supply switchable (available when writes and erases are required) or hardwired to v pph . when v pp = v ppl , power savings are incurred and memory contents cannot be altered. the cui architecture provides protection from unwanted write and erase operations even when high voltage is applied to v pp . additionally, all functions are disabled whenever v cc is below the write lockout voltage v lko , or when the cards deep-sleep modes are enabled. the wsm automates the writing and erasure of blo cks within a device. this on-chip state machine controls block erase and data-write, freeing the host processor for other tasks. after receiving the erase setup and erase confirm commands from the cui, the wsm controls block-erase. progress is monitored via the devices status register, the cards control logic, and the rdy/bsy# pin of the pcmcia interface. data- write is similarly controlled, after destination address and expected data are supplied.
imc002/004/010/020flsa e 22 preliminary table 4. device command set first bus cycle second bus cycle data data 28f008sa command (1) bus cycles reqd operation addr (2) x8 mode x16 mode operation addr (2) x8 mode x16 mode read array/reset 1 write da ffh ffffh intelligent identifer 3 write da 90h 9090h read ia iid (3) iid (3) read device status register 2 write da 70h 7070h read da srd (4) srd (4) clear device status register 1 write da 50h 5050h erase setup/erase confirm 2 write ba 20h 2020h write ba d0h d0d0h erase suspend/ erase resume 2 write da b0h b0b0h write da d0h d0d0h write setup/write 2 write wa 40h 4040h write wa wd (5) wd (5) alternate write setup/write (6) 2 write wa 10h 1010h write wa wd (5) wd (5) notes: 1. commands other than those shown above are reserved by intel for future device implementations and should not be used. 2. da = a device-level (or device pair) address within the card. ba = address within the block of a specific device (device pair) being erased. wa = address of memory location to be written. ia = a device-level address; 00h for manufacturer code, 01 for device code. 3. following the intelligent identifier command, two read operations access manufacturer (89h) and device codes (a2h). 4. srd = data read from device status register. 5. wd = data to be written at location wa. data is latched on the rising edge of we#. 6. either 40h or 10h are recognized by the wsm as the write setup command.
e imc002/004/010/020flsa 23 preliminary 15.0 command definitions 15.1 read array (ffh) upon initial card power-up, after exit from the deep- sleep modes, and whenever illegal commands are given, individual devices default to the read array mode. this mode is also entered by writing ffh into the cui. in this mode, microprocessor read cycles retrieve array data. devices remain enabled for reads until the cui receives an alternate command. once the internal wsm has started a block-erase or data-write operation within a device, that device will not recognize the read array command until the wsm has completed its operation (or the erase suspend command is issued during erase). 15.2 intelligent identifier (90h) after executing this command, the intelligent identifier values can be read. only address a 0 of each device is used in this mode, all other address inputs are reserved and should be cleared to 0. [(manufacturer code = 89h for a 0 = 0), (device code = a2h for a 0 = 1)]. the device will remain in this mode until the cui receives another command. this information is useful by system software in determining what type of flash memory device is contained within the card and allows the correct matching of device to write and erase algorithms. system software that fully utilizes the pcmcia specification will not use the intelligent identifier mode, as this data is available within the card information structure (refer to section on pcmcia card information structure). 15.3 read status register (70h) after writing this command, a device read outputs the contents of its status register, regardless of the address presented to that device. the contents of this register are latched on the falling edge of oe#, ce 1 # (and/or ce 2 #), whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register changed while reading its contents. ce 1 # (and ce 2 # for odd-byte or word access) or oe# must be toggled with each subsequent status read, or the completion of a write or erase operation will not be evident. this command is executable while the wsm is operating, however, during a block-erase or data-write operation, reads from the device will automatically return status register data. upon completion of that operation, the device remains in the status register read mode until the cui receives another command. the read status register command functions when v pp = v ppl or v pph . 15.4 clear status register (50h) the erase status and write status bits may be set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions. by allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in s equence). the devices status register may then be polled to determine if an error occurred during that sequence. this adds flexibility to the way the device may be used. additionally, the v pp status bit (sr.3) must be reset by system software (clear status register command) before further block-erases are attempted (after an error). the clear status register command functions when v pp = v ppl or v pph . this command puts the device in the read array mode. 15.5 write setup/write a two-command sequence executes a data-write operation. after the system switches v pp to v pph , the write setup command (40h) is written to the cui of the appropriate device, followed by a second write specifying the address and write data (latched on the rising edge of we#). the devices wsm controls the data-write and write verify algorithms internally. after receiving the two-command write sequence, the device automatically outputs status register data when read (see figure 13). the cpu detects the completion of the write operation by analyzing card-level or device-level indicators. card-level indicators include the rdy/bsy# pin and the ready-busy status register; while device-level indicators include the specific devices status register. only the read status register command is valid while the write operation is active. upon completion of the data-write sequence (see section on status register) the devices status register reflects the result of the write operation.
imc002/004/010/020flsa e 24 preliminary the device remains in the read status register mode until the cui receives an alternate command. 15.6 erase setup/erase confirm commands (20h) within a device, a two-command sequence initiates an erase operation on one device block at a time. after the system switches v pp to v pph , an erase setup command (20h) prepares the cui for the erase confirm command (d0h). the devices wsm controls the erase algorithms internally. after receiving the two-command erase sequence, the device automatically outputs status register data when read (see figure 14). if the command after erase setup is not an erase confirm command, the cr sets the write railure and erase failure bits of the status register, places the device into the read status register mode, and waits for another command. the erase confirm command enables the wsm for erase (simultaneously closing the address latches for that devices block (a 16 Ca 19 ). the cpu detects the completion of the erase operation by analyzing card-level or device-level indicators. card-level indicators include the rdy/bsy pin and the ready-busy status register; while device-level indicators include the specific devices status register. only the read status register and erase suspend command is valid during an active erase operation. upon completion of the erase sequence (see section on status register) the devices status register reflects the result of the erase operation. the device remains in the read status register mode until the cui receives an alternate command. the two-step block-erase sequence ensures that memory contents are not accidentally erased. erase attempts while v ppl < v pp < v pph produce spurious results and are not recommended. reliable block erasure only occurs when v pp = v pph . in the absence of this voltage, memory contents are protected against erasure. if block erase is attempted while v pp = v ppl , the v pp status bit will be set to 1. when erase completes, the erase status bit should be checked. if an erase error is detected, the devices status register should be cleared. the cui remains in read status register mode until receiving an alternate command. 15.7 erase suspend (b0h)/erase resume (d0h) erase suspend allows block erase interruption to read data from another block of the device or to temporarily conserve power for another system operation. once the erase process starts, writing the erase suspend command to the cui (see figure 15) requests the wsm to suspend the erase sequence at a predetermined point in the erase algorithm. in the erase suspend state, the device continues to output status register data when read. polling the devices ry/by# and erase suspend status bits (status register) will determine when the erase suspend mode is valid. it is important to note that the cards rdy/bsy# pin will also transition to v oh and will generate an interrupt if this pin is connected to a system-level interrupt. at this point, a read array command can be written to the devices cui to read data from blo cks other than those which are suspended . the only other valid commands at this time are read status register (70h) and erase resume (d0h). if v pp goes low during erase suspend, the v pp status bit is set in the status register and the erase operation is aborted. the erase resume command clears the erase suspend state and allows the wsm to continue with the erase operation. the devices ry/by# status and erase suspend status bits and the cards ready- busy status register are automatically updated to reflect the erase resume condition. the cards rdy/bsy# pin also returns to v ol . 15.8 invalid/reserved these are unassigned commands having the same effect as the read array command. do not issue any command other than the valid commands specified above. intel reserves the right to redefine these codes for future functions.
e imc002/004/010/020flsa 25 preliminary 16.0 device status register each 28f008sa device in the series 2 card contains a status register which displays the condition of its wsm. the status register is read at any time by writing the read status command to the cui. after writing this command, all subsequent read operations output data from the status register, until another command is written to the cui. bit 7 wsm status this bit reflects the ready/busy condition of the wsm. a 1 indicates that read, block-erase or data- write operations are available. a 0 indicates that write or erase operations are in progress. bit 6 erase suspend status if an erase suspend command is issued during the erase operation, the wsm halts execution and sets the wsm status bit and the erase suspend status bit to a 1. this bit remains set until the device receives an erase resume command, at which point the cui resets the wsm status bit and the erase suspend status bit. bit 5 erase status this bit will be cleared to 0 to indicate a successful block-erasure. when set to a 1, the wsm has been unsuccessful at performing an erase verification. the devices cui only resets this bit to a 0 in response to a clear status register command. bit 4 write status this bit will be cleared to a 0 to indicate a successful data-write operation. when the wsm fails to write data after receiving a write command, the bit is set to a 1 and can only be reset by the cui in response to a clear status register command. bit 3 v pp status during block-erase and data-write operations, the wsm monitors the output of the devices internal v pp detector. in the event of low v pp , the wsm sets (1) the v pp status bit, the status bit for the operation in progress (either write or erase). the cui resets these bits in response to a clear status register command. also, the wsm ry/by# bit will be set to indicate a device ready condition. this bit must be reset by system software (clear status register command) before further data writes or block erases are attempted. device status register (read only register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wsm status erase suspend status erase status write status v pp status reserved
imc002/004/010/020flsa e 26 preliminary start issue write setup (1) command write data read status register (2) done writing data? full status (3) check if desired write operation (4) completed full status check procedure yes no read status register data (see above) voltage range error (5) data write error (6) v pp level ok? data write ok? no yes no yes bus operation write x8 mode data to be written address = byte within card to be written x16 mode write data = 40h address = byte within card to be written data = 4040h address = word within card to be written data to be written address = word within card to be written read status register data. toggle oe#, ce 1 # or ce 2 # to update status register status register data. toggle oe#, (ce 1 # or ce 2 #) to update status registers check sr bits 7 and 15 1 = ready 2 = busy standby check sr bit 7 1 = ready 2 = busy data write successful bus operation standby x8 mode x16 mode check sr bits 4 and 12 1 = data write error standby check sr bit 4 1 = data write error check sr bit 3 1 = v pp detected low check sr bits 3 and 11 1 = v pp detected low command data write write setup defaults to device status register read mode command fig13 notes: 1. repeat for subsequent data writes. 2. in addition, the cards ready-busy status register or the rdy/bsy# pin may be used. 3. full device-level status check can be done after each data write or after a sequence of data writes. 4. write ffh (or ffffh) after the last data write operation to reset the device(s) to read array mode. 5. if a data write operation fails due to a low v pp (setting sr bit 3), the clear status register command must be issued before further attempts are allowed by the write state machine. 6. if a data write operation fails during a multiple write sequence, sr bit 4 (write status) will not be cleared until the command user interface receives the clear status register command. figure 13. device-level automated write algorithm
e imc002/004/010/020flsa 27 preliminary start write erase setup (1) command write erase confirm command read status register (2) erase done? full status (3) check if desired block erase (4) completed full status check procedure yes no read status register data (see above) voltage range error (5) cmd sequence error v pp level ok? cmd sequence ok? no yes no yes block erase successful suspend erase? suspend erase loop no yes command erase erase setup defaults to device status register read mode command block erase error (6) block erase ok? no bus operation write write read standby bus operation standby standby standby x8 mode check sr bit 3 1 = v pp detected low check sr bit 5 1 = blk erase error check sr bits 4 and 5 both 1 = comd seq error x16 mode check sr bits 3 and 11 either bit 1= v pp detected low check sr bits 5 and 13 both 1 = blk erase failure check sr bits 4, 5, 12, 13 all 1 = comd seq error data = 20h address = block within card to be erased x8 mode data = d0h address = block within card to be erased status register data. toggle oe#, ce 1 # or ce 2 # to update status register check sr bit 7 1 = ready 2 = busy x16 mode data = 2020h address = blk pair within card to be erased status register data. toggle oe#, (ce 1 # or ce 2 #) to update status registers check sr bits 7 and 15 1 = ready 2 = busy data = d0d0h address = blk pair within card to be erased fig14 notes: 1. repeat for subsequent data writes. 2. in addition, the cards ready-busy status register or the rdy/bsy# pin may be used. 3. full device-level status check can be done after each block erase or after a sequence of block erases. 4. write ffh (or ffffh) after the last block erase operation to reset the device(s) to ready array mode. 5. if a block erase operation fails due to a low v pp (setting sr bit 3), the clear status register command must be issued before further attempts are allowed by the write state machine. 6. if a block erase operation fails during a multiple block erase sequence, sr bit 4 (write status) will not be cleared until th e command user interface receives the clear status register command. figure 14. device-level automated erase algorithm
imc002/004/010/020flsa e 28 preliminary start write erase suspend command write read status register command read status register wsm busy? write read array cmd continue erase yes no bus operation read x8 mode x16 mode write data = b0h address = desired block to erase suspend standby check sr bits 6 and 14 1 = suspended 2 = in progress standby check sr bit 6 1 = suspended 2 = in progress command suspend erase erase suspended? write resume cmd done reading? erase has completed write data = d0h address = valid block address erase resume data = b0b0h address = desired block pair to erase suspend status register data. toggle oe#, ce 1 # or ce 2 # to update status register status register data. toggle oe#, (ce 1 # or ce 2 #) to update status registers check sr bits 7 and 15 1 = ready 2 = busy check sr bit 7 1 = ready 2 = busy write data = ffh data = ffffh read array command read read data until finished read data until finished data = d0d0h address = valid block address fig15 figure 15. erase suspend/resume algorithm. allows reads to interrupt erases 17.0 power consumption 17.1 standby mode in most applications, software will only be accessing one device pair at a time. the series 2 card is defined to be in the standby mode when one device pair is in the read array mode while the remaining devices are in the deep-sleep mode. the series 2 cards ce 1 # and ce 2 # input signals must also be at v ih . in standby mode, much of the cards circuitry is shut off, substantially reducing power consumption. typical power consumption for a 20-mb series 2 card in standby mode is 65 a.
e imc002/004/010/020flsa 29 preliminary 17.2 sleep mode writing a 1 to the pwrdwn bit of the global power-down register places all flashfile memory devices into a deep-sleep mode. this disables most of the 28f008sas circuitry and reduces current consumption to 0.2 a per device. additionally, when the host system pulls asic control logic high and latches all address and data lines (i.e., not toggling), the cards total current draw is reduced to approximately 5 a (cmos input levels) for a 20-mb card. on writing a 0 to the pwrdwn bit (global power-down register) or any individual device pair (sleep control register), a deep-sleep mode recovery period must be allowed for 28f008sa device circuitry to power back on. 18.0 system design considerations 18.1 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current issuesstandby, active and transient current peaks, produced by rising and falling edges of ce 1 # and ce 2 #. the capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks. the flash memory card features on-card ceramic decoupling capacitors connected between v cc and gnd, and between v pp1 /v pp2 and gnd to help transient voltage peaks. on the host side, the card connector should also have a 4.7 f electrolytic capacitor between v cc and gnd, as well as between v pp1 /v pp2 and gnd. the bulk capacitors will overcome voltage slumps caused by printed-circuit-board trace inductance, and will supply charge to the smaller capacitors as needed. 19.0 power up/down protection each device in the flash memory card is designed to offer protection against accidental erasure or writing, caused by spurious system-level si gnals that may exist during power transitions. the card will power-up into the read array mode. a system desi gner must guard against active writes for v cc voltages above v lko when v pp is active. since both we# and ce 1 # (and/or ce 2 #) must be low for a command write, driving either to v ih will inhibit writes. with its cui, alteration of device contents only occurs after successful completion of the two-step command sequences. while these precautions are sufficient for most applications, an alternative approach would allow v cc to reach its steady state value before raising v pp1 /v pp2 above v cc + 2.0 v. in addition, upon powering-down, v pp1 /v pp2 should be below v cc + 2.0 v, before lowering v cc . 20.0 hot insertion/removal the capability to remove or insert pc cards while the system is powered on (i.e., hot insertion/removal) requires careful design approaches on the system and card levels. to design for this capability consider card overvoltage stress, system power dr oop and control line stability. a pcmcia/jeida specified socket properly sequences the power supplies to the flash memory card via shorter and longer pins. this assures that hot insertion and removal will not result in card damage or data loss. 21.0 pcmcia card information structure the card information structure (cis) starts at address zero of the cards attribute memory plane. it contains a variable-length chain of data blocks (tuples) that conform to a basic format as shown in table 5. this section describes each tuple contained within the series 2 flash memory card. 21.1 the device information tuple this tuple (cistpl_dev = 01h) contains information pertaining to the cards speed and size. the series 2 card is offered with a 150 nanosecond access time. card sizes range between 2 and 20 megabytes.
imc002/004/010/020flsa e 30 preliminary table 5. tuple format bytes data 0 tuple code: cistpl_xxx. the tuple code 0ffh indicates no more tuples in the list. 1 tuple link: tpl_llnk. link to the next tuple in the list. this can be viewed as the number of additional bytes in tuple, excluding this byte. if the link field is zero, the tuple body is empty. if the link field contains 0ffh, this tuple is the last tuple in the list. 2 Cn bytes specific to this tuple. 21.2 the device geometry tuple this tuple (cistpl_devlcegeo = 1eh) is conceptually similar to a dos disk geometry tuple (cistpl_geometry), except it is not a format- dependent property; this deals with the fixed architecture of the memory device(s). fields are defined as follows: dgtpl bus value = n, where system bus width = 2 (n C1) bytes. n = 2 for standard pcmcla release 1.0/2.0 cards. dgtpl ebs value = n, where the memory arrays physical memory segments have a minimum erase block size of 2 (n C1) address increments of dgtpl_bus-wide accesses. dgtpl rbs value = n, where the memory arrays physical memory segments have a minimum read block size of 2 (n C1) address increments of dgtpl_bus-wide accesses. dgtpl wbs value = n, where the memory arrays physical memory segments have a minimum write block size of 2 (n C1) address increments of dgtpl_bus-wide accesses. dgtpl part value = n, where the memory arrays physical memory segments can have partitions subdividing the arrays in minimum granularity of 2 (n C1) number of erase blocks. fl device interleave value = n, where card architectures employ a multiple of 2 (n C1) times interleaving of the entire memory arrays with the above characteristics. non-interleaved cards have values n = 1. 21.3 jedec programming information tuple this tuple (cistpl_jedec = 18h) contains the intel manufacturing identifier (89h) and the 28f008sa device id (a2h). 21.4 level 1 version/product information tuple this tuple (cistpl_veri = 15h) contains level-1- version compliance and card-manufacturer information. fields are described as follows: tpllv1 major major version number = 04h. tpllv1 minor minor version number = 01h for release 2.0. tpllv1 info name of manufacturer = intel; name of product = series2-card size; card type = 2; speed = 150 ns or 200 ns register base = regbase 4000h test codes = dbbdrelp legalities = copyright intel corporation 1991
e imc002/004/010/020flsa 31 preliminary 21.5 the configurable card tuple this tuple (clstpl_conf = 1ah) describes the interface supported by the card and the locations of the card configuration registers and the card configuration table. fields are described as follows: tpcc sz size of fields byte = 01h. tpcc last index number of the last entry in the card configuration table = 00h. tpcc radr configuration registers base address in reg space = 4000h. tpcc rmsk configuration registers present mask = 03h. 21.6 the end-of-list tuple the end-of-list tuple (cistpl_end = ffh) marks the end of a tuple chain. upon encountering this tuple, continue tuple processing as if a long-link to address 0 of common memory space were encountered.
imc002/004/010/020flsa e 32 preliminary tuple address value description 00h 01h cistpl_dev 02h 03h tpl_link 04h 53h device_info = flash 150 ns 52h device_info = flash 200 ns card size 06h 06h 2m 0eh 4m 26h 10m 4eh 20m 08h ffh end of device 0ah 1eh cistpl_ devicegeo 0ch 06h tpl_link 0eh 02h dgtpl_bus 10h 11h dgtpl_ebs 12h 01h dgtpl_rbs 14h 01h dgpl_wbs 16h 03h dgtpl_part 18h 01h fl_device interleave 1ah 18h cistpl_jedec 1ch 02h tpl_link 1eh 89h intel j-id 20h a2h 28f008 j-id 22h 15h cistpl_ver1 24h 50h tpl_link 26h 04h tpllv1 major 28h 01h tpllv1 minor 2ah 69h tpllv1 info i 30h 65h e tuple address value description 32h 6ch l 34h 00h end text 36h 53h s 38h 45h e 3ah 52h r 3ch 49h i 3eh 45h e 40h 53h s 42h 32h 2 44h 2dh 46h 30h 2m = 0 30h 4m = 0 31h 10m = 1 32h 20m = 2 48h 32h 2m = 2 34h 4m = 4 30h 10m = 0 30h 20m = 0 4ah 20h space 4ch 00h end text 4eh 32h card type 2 50h 41h a = 2m, 150 ns 42h b = 4m, 150 ns 45h e = 10m, 150 ns 5ah z = 20m, 150 ns 48h h = 2m, 200 ns 49h i = 4m, 200 ns 4ch l = 10m, 200 ns 4fh o = 20m, 200 ns 52h 20h space 54h 52h regbase-r
e imc002/004/010/020flsa 33 preliminary tuple address value description 56h 45h e 58h 47h g 5ah 42h b 5ch 41h a 5eh 53h s 60h 45h e 62h 20h space 64h 34h 4000h 4 66h 30h 0 68h 30h 0 6ah 30h 0 6ch 68h h 6eh 20h space 70h 44h d 72h 42h b 74h 42h b 76h 44h d 78h 52h r 7ah 45h e 7ch 4ch l 7eh 50h p 80h 00h end text 82h 43h copyright c 84h 4fh o 86h 50h p 88h 59h y 8ah 52h r 8ch 49h i 8eh 47h g 90h 48h h tuple address value description 92h 54h t 94h 20h space 96h 69h i 98h 6eh n 9ah 74h t 9ch 65h e 9eh 6ch l a 0 h 20h space a2h 43h corporation c a4h 4fh o a6h 52h r a8h 50h p aah 4fh o ach 52h r aeh 41h a b0h 54h t b2h 49h i b4h 4fh o b6h 4eh n b8h 20h space bah 31h 1 bch 39h 9 beh 39h 9 c0h 31h 1 c2h 00h end text c4h ffh end of list c6h 1ah cistpl_conf cah 01h tpcc_sz cch 00h tpcc_last ceh 00h tpcc_radr
imc002/004/010/020flsa e 34 preliminary tuple address value description d0h 40h tpcc_radr d2h 03h tpcc_rmsk d4h ffh end of list d6h ffh cistpl_end d8h 00h invalid ecis address
e imc002/004/010/020flsa 35 preliminary 22.0 electrical specifications 22.1 absolute maximum ratings* storage temperature ................... C40 c to +85 c voltage on any pin with respect to ground ........C2.0 v to v cc +2.0 v (1) v pp1 /v pp2 supply voltage with respect to ground .................C2.0 v to +14.0 v (1, 2) v cc supply voltage with respect to ground .................. C0.5 v to +7.0 v output short circuit current .................... 100 ma (3) notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc input voltage is C0.5 v. during transitions, inputs may undershoot to C2.0 v tor periods of less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v. the voltage may overshoot to v cc + 2.0 v for periods of less than 20 ns. 2. maximum dc input voltage on v pp1 /v pp2 may overshoot to +14.0 v for periods of less than 20 ns. 22.2 operating conditions temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature 0 +70 c ambient temperature v cc v cc supply voltage (5%) 4.75 5.25 v 22.3 capacitance t a = 25 c, f = 1.0 mhz commercial symbol characteristics min max unit c in address/control capacitance (a 0 Ca 8 , ce 1 #, ce 2 #) 30 pf address/control capacitance (a 9 Ca 24 , all others) 20 pf v cc , v pp 2f c out output capacitance 20 pf note: sampled, not 100% tested
imc002/004/010/020flsa e 36 preliminary 22.4 common dc characteristics cmos and ttl symbol parameter notes min typ max unit test condition i li input leakage current 1, 3 1 20 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 1 20 a v cc = v cc max v out = v cc or gnd v il input low voltage 1 C0.5 0.8 v v ih input high voltage (ttl) 1 2.4 v cc + 0.3 v input high voltage (cmos) 0.7 v cc v cc + 0.3 v ol output low voltage 1 v ss 0.4 v v cc = v cc min i ol = 3.2 ma v oh output high voltage 1 4.0 v cc vv cc = v cc min i oh = C2.0 ma v ppl v pp during read only operations 1, 2 0.0 6.5 v v pph v pp during read/write operations 1 11.4 12.6 v v lko v cc erase/write lock voltage 1 2.0 v notes: 1. values are the same for byte and word wide modes and for all card densities. 2. block erases/data writes are inhibited when v pp = v ppl and not guaranteed in the range between v pph and v ppl . 3. exceptions: with vi n = gnd, the leakage on ce 1 #, ce 2 #, reg#, oe#, we#, will be 500 a due to internal pullup resistors and, with v in = v cc , rst leakage will be 500 a due to internal pulldown resistor.
e imc002/004/010/020flsa 37 preliminary 22.5 dc characteristics cmos byte wide mode word wide mode symbol parameter notes min typ max min typ max unit test condition i ccr v cc read current 1, 3 45 85 65 120 ma v cc = v cc max control signals = gnd t cycle = 200 ns i out = 0 ma i ccw v cc write current 1, 3 35 80 45 110 ma data write in progress i cce v cc erase current 1, 2, 3 35 80 45 110 ma block (pair) erase in progress i ccs v cc standby current 2 meg 1, 4, 6 120 420 120 420 a v cc = v cc max control signals = v ih 4 meg 120 460 120 460 10 meg 120 580 120 580 20 meg 120 580 120 580 i ccsl v cc sleep current 2 meg 1, 4, 5 60 60 a 4 meg 100 100 10 meg 260 260 20 meg 460 460 i ppw v pp write current (v pp = v pph ) 1, 3 15 30 ma data write in progress i ppe v pp erase current (v pp = v pph ) 1, 3 15 30 ma block (pair) erase in progress i ppsl v pp sleep current 2 meg 1, 5 0.2 10 0.2 10 a 4 meg 0.4 20 0.4 20 10 meg 1 50 1 50 20 meg 2 100 2 100
imc002/004/010/020flsa e 38 preliminary 22.5 dc characteristics cmos (continued) byte wide mode word wide mode symbol parameter notes min typ max min typ max unit test condition i pps1 v pp standby or read current (v pp v cc ) 2 meg 1, 6 2.8 25 3 25 a 4 meg 2.9 30 3 30 10 meg 3.2 45 3 45 20 meg 3.7 70 4 70 i pps2 v pp standby or read current (v pp > v cc ) 2 meg 1, 6 12 210 11.8 210 a 4 meg 12 220 11.9 220 10 meg 12 230 12.2 230 20 meg 13 255 12.7 255 notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, v pp = 12.0 v, t = 25 c. 2. the datasheet specification for the 28f008sa in erase suspend (i cces ) is 5 ma typical and 10 ma max with the device deselected. if the device(s) are read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. standby or sleep currents are not included for non-accessed devices. 4. address and data inputs to card static. control line voltages equal to v ih or v il . 5. all 28f008sa devices in deep-sleep (reset power-down) mode. 6. in byte and word mode, all but two devices in deep-sleep.
e imc002/004/010/020flsa 39 preliminary 22.6 dc characteristics ttl byte wide mode word wide mode symbol parameter notes min typ max min typ max unit test condition i ccr v cc read current 1, 3 70 135 90 170 ma v cc = v cc max control signals = gnd t cycle = 200 ns i out = 0 ma i ccw v cc write current 1, 3 60 130 70 160 ma data write in progress i cce v cc erase current 1, 2, 3 60 130 70 160 ma block (pair) erase in progress i ccs v cc standby current 2 meg 1, 4, 6 20 100 20 100 ma v cc = v cc max control signals = v ih 4 meg 10 meg 20 meg i ccsl v cc sleep current 2 meg 1, 4, 5 20 100 20 100 ma 4 meg 10 meg 20 meg i ppw v pp write current (v pp = v pph ) 1, 3 10 30 20 60 ma data write in progress i ppe v pp erase current (v pp = v pph ) 1, 3 10 30 20 60 ma block (pair) erase in progress i ppsl v pp sleep current 2 meg 1, 5 0.2 10 0.2 10 a 4 meg 0.4 20 0.4 20 10 meg 1.0 50 1.0 50 20 meg 2.0 100 2.0 100
imc002/004/010/020flsa e 40 preliminary 22.6 dc characteristics ttl (continued) byte wide mode word wide mode symbol parameter notes min typ max min typ max unit test condition i pps1 v pp standby or read current (v pp v cc ) 2 meg 1, 6 2.8 25 3 25 a 4 meg 2.9 30 3 30 10 meg 3.2 45 3 45 20 meg 3.7 70 4 70 i pps2 v pp standby or read current (v pp > v cc ) 2 meg 1, 6 12 210 11.8 210 a 4 meg 12 220 11.9 220 10 meg 12 230 12.2 230 20 meg 13 255 12.7 255 notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, v pp = 12.0 v, t = 25 c. 2. the datasheet specification for the 28f008sa in erase suspend (i cces ) is 5 ma typical and 10 ma max with the device deselected. if the device(s) are read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. standby or sleep currents are not included for non-accessed devices. 4. address and data inputs to card static. control line voltages equal to v ih or v il . 5. all 28f008sa devices in deep-sleep (reset power-down) mode. 6. in byte and word mode, all but two devices in deep-sleep. 7. the current consumption from the 28f008sa is insignificant in relation to the asics. 22.7 ac characteristics ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia release 2.0 specifications. pcmcia allows a 300 ns access time for attribute memory. note that read and write access timings to the series 2 flash memory cards common and attribute memory planes are identical at 150 ns. furthermore, there is no delay in switching between the common and attribute memory planes.
e imc002/004/010/020flsa 41 preliminary 22.7.1 read-only operations common and attribute memory symbol jedec pcmcia parameter notes min max unit t avav t rc read cycle time 150 ns t avqv t a (a) address access time 150 ns t elqv t a (ce) card enable access time 150 ns t glqv t a (oe) output enable access time 75 ns t ehqx t dis (ce) output disable time from ce# 75 ns t ghqz t dis (ce) output disable time from oe# 75 ns t glqx t en (ce) output enable time from ce# 5 ns t elqx t en (oe) output enable time from oe# 5 ns t axqx t v (a) data valid from add change 0 ns t rhqv reset-pwrdwn recovery to output delay 500 ns t su (v cc ) ce setup time on power-up 1 ms first access after reset 500 ns test points input 1.5 0.7 v cc 0.0 1.5 0581_06 figure 16. transient input/output reference waveform (v cc = 5 v) for standard test configuration output test points input 1.5 3.0 1.5 0.0 figure 17. transient input/output reference waveform (v cc = 3.3 v) for standard test configuration
imc002/004/010/020flsa e 42 preliminary 29043421 note: 1. the hatched area may be either high or low. figure 18. ac waveform for read operations
e imc002/004/010/020flsa 43 preliminary 22.7.2 write operations common and attribute memory (1) symbol jedec pcmcia parameter notes min max unit t avav t wc write cycle time 150 ns t wlwh t w (we) write pulse width 80 ns t avwl t su (a) address setup time 20 ns t avwh t su (a-weh) address setup time for we# 100 ns t vpwh t vps v pp setup to we# going high 100 ns t elwh t su (ce-weh) card enable setup time for we# 100 ns t dvwh t su (d-weh) data setup time for we# 50 ns t whdx t h (d) data hold time 20 ns t whax t rec (we) write recover time 20 ns t whrl we# high to rdy/bsy# 120 ns t whqv1 duration of data write operation 6 s t whqv2 duration of block erase operation 0.3 sec t qvvl v pp hold from operation complete 2 0 ns t whgl t h (oe-we) write recovery before read 10 ns t rhwl reset-pwrdwn recovery to we# going low 1s notes: 1. read timing characteristics during erase and data write operations are the same as during read-only operations. refer to read-only operations common and attribute memory . 2. refer to text on data-write and block-erase operations. 22.7.3 block erase and data write performance parameter notes min typ (3) max unit block pair erase time (1) 2, 4 1.1 10 sec block pair write time 2, 4 0.5 2.1 sec byte/word write time 4 4.8 s 6 s 3 ms notes: 1. individual blocks can be erased 100,000 times. 2. excludes system-level overhead. 3. 25 c, 12.0 v v pp . 4. monitor ready/busy registers for the completion of a write/erase command.
imc002/004/010/020flsa e 44 preliminary 0491_03 note: 1. by writing the appropriate reagister, or on power-up, the card control asic generates the rp# signal to the cards devices. figure 19. ac waveforms for write operations
e imc002/004/010/020flsa 45 preliminary 22.7.4 ce#-controlled write operations common and attribute memory (1) symbol jedec pcmcia parameter notes min max unit t avav t wc write cycle time 1 150 ns t eleh t w (we) chip enable pulse width 1 80 ns t avel t su (a) address setup time 1 20 ns t aveh t su (a-weh) address setup time for ce# 1 100 ns t vpeh t vps v pp setup to ce# going high 1 100 ns t wleh t su (ce-weh) write enable setup time for ce# 1 100 ns t dveh t su (d-weh) data setup time for ce# 1 50 ns t ehdx t h (d) data hold time 1 20 ns t ehax t rec (we) write recover time 1 20 ns t ehrl ce# high to rdy/bsy# 1 120 ns t ehqv1 duration of data write duration of data write operation 1 6 s t ehqv2 duration of erase duration of block erase operation 1 0.3 sec t qvvl v pp hold from operation complete 1, 2 0 ns t ehgl t h (oe-we) write recovery before read 1 10 ns t rhel reset-pwrdwn recovery to ce# going low 1 s notes: 1. read timing characteristics during erase and data write operations are the same as during read-only operations. refer to read-only operations common and attribute memory . 2. refer to text on data-write and block-erase operations.
imc002/004/010/020flsa e 46 preliminary 049105 note: 1. by writing the appropriate reagister, or on power-up, the card control asic generates the rp# signal to the cards devices. figure 20. alternate ac waveform for write operations
e imc002/004/010/020flsa 47 preliminary 29043424 figure 21. series 2 flash memory card package dimensions
imc002/004/010/020flsa e 48 preliminary 29043425 figure 22. card connector socket 29043426 figure 23. pin/socket contact length with wipe l1 max l2 l3 ref 0.020 (0.5) pin type see table 1 detect 0.059 (1.5) 0.039 general 0.084 (2.1) 0.064 power 0.098 (2.5) 0.078 0.024 (0.6)
e imc002/004/010/020flsa 49 preliminary 29043430 notes: 1. total label dimensions are 0.003" 2. total label thickness with adhesive is 0.002" figure 24. label dimensions
imc002/004/010/020flsa e 50 preliminary 29043431 figure 25. card dimensions with label
e imc002/004/010/020flsa 51 preliminary 23.0 ordering information imc020flsa-15 m9508014,sbxxxx where: i = intel m = manila mc = memory card 95 = 1995 020 = density in megabytes 08 = week 08 (002,004,010,020 available) 014 = lot # fl = flash technology sbxxxx = customer identifier s = blocked architecture a = series 2 15 = 150 ns 24.0 additional information order number document 297868 series 2 flash memory specification update 290429 5 volt flashfile? memory; 28f008sa datasheet note 3 ap-361 implementing the integrated registers of the series 2 flash memory card note 3 ap-364 28f008sa automation and algorithms note 3 ap-359 28f008sa hardware interfacing notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. these documents can be located at the intel world wide web support site, http://www.intel.com/support/flash/memory

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