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| applications description features transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 xbert device bit error rate generator receiver txc-06125 document number: txc-06125-mb ed. 3, august 1995 ? bit-serial, nibble-parallel, and byte-parallel interface capability, selectable via control bits ? transmit and receive clock rate: 100 hz to 78 mhz for serial, nibble, byte i/o (all telecom rates up to oc-12/stm-4) ? test patterns at up to 622 mbit/s using byte- parallel interface and some external circuitry ?2 15 - 1, 2 20 - 1, 2 20 - 1 qrss and 2 23 - 1 pseudo-random generators and detectors ? fixed word test generator and detector - all ones - all zeros - alternate 1/0 pattern - alternate 11/00 pattern ? microprocessor-programmable test word generator and detector (1 to 4 bytes) ? error generators (single, or 10 -3 and 10 -6 ber) ? bit error counter and clock counter (24 bits each) ? 44-pin plastic leaded chip carrier the bit error rate generator/receiver (xbert) vlsi device is a microprocessor-programmable multi-rate test pattern generator and receiver on a single chip. it is used for testing the performance of digital communica- tion circuits and communication links. it provides a bit- serial, nibble-parallel or byte-parallel interface, and is capable of operating in a burst data mode by using external signals to enable/disable the transmit and receive clocks. the xbert generates and analyzes pseudo-random patterns, ?xed words, or programmable words. four pseudo-random test patterns are provided: 2 15 - 1, 2 20 - 1, 2 20 - 1 with zero suppression (quasi- random signal source, not available in byte-parallel mode), and 2 23 - 1. the ?xed word mode generates and analyzes all zeros, all ones, alternate one/zero pattern or a double alternate one/zero (1100) pattern. the pro- grammable mode allows a choice of one to four bytes written by the microprocessor. ? transmission and switching systems ? data communications ? test equipment ? remote testing and fault isolation ? embedded test for proprietary framing algorithms ? embedded test for secure lines +5v receive serial/nibble/byte microprocessor bit error rate generator/receiver xbert interface data, clock & enable signal transmit serial/nibble/byte transmit clock & enable signal data & clock txc-06125 data sheet copyright 1995 transwitch corporation. txc, transwitch and xbert are registered trademarks of transwitch corporation.
- 2 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 table of contents section page block diagram ............................................................................................................ 3 block diagram description ......................................................................................... 3 pin diagram ................................................................................................................ 5 pin descriptions .......................................................................................................... 5 absolute maximum ratings ........................................................................................ 9 thermal characteristics .............................................................................................. 9 power requirements .................................................................................................. 9 input, output and i/o parameters ............................................................................ 11 timing characteristics .............................................................................................. 12 operation ............................................................................................................. 20-21 decoupling of power supply pins....................................................................... 20 external circuit for proper updating of bit error and clock counters ................ 20 memory map ............................................................................................................. 22 memory map descriptions ........................................................................................ 23 package information ................................................................................................. 26 ordering information ................................................................................................. 27 related products ...................................................................................................... 27 standards documentation sources .......................................................................... 28 list of data sheet changes ...................................................................................... 29 documentation update registration form .......................................................... 33 list of figures figure 1. xbert txc-06125 block diagram ......................................................... 3 figure 2. xbert txc-06125 pin diagram ............................................................. 5 figure 3. power dissipation as a function of frequency ...................................... 10 figure 4. receive serial interface timing ............................................................. 12 figure 5. receive nibble interface timing ............................................................ 13 figure 6. receive byte interface timing ............................................................... 14 figure 7. transmit serial interface timing ............................................................ 15 figure 8. transmit nibble interface timing ........................................................... 16 figure 9. transmit byte interface timing .............................................................. 17 figure 10. microprocessor read timing ................................................................. 18 figure 11. microprocessor write timing ................................................................. 19 figure 12. recommended decoupling of power supply pins ................................. 20 figure 13. protection of xbert from read/write signals intended for other devices ..................................................................... 21 figure 14. xbert txc-06125 44-pin plastic leaded chip carrier ....................... 26 - 3 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 block diagram figure 1. xbert txc-06125 block diagram block diagram description figure 1 is a simpli?ed block diagram of the xbert. the input block accepts bit-serial (rxsd), nibble-parallel (rxd3-rxd0) or byte-parallel (rxd7-rxd0) data, one of which is selected by writing control bits in the mem- ory map. incoming data is clocked into the xbert on positive transitions of the clock signal (rxck). an input for a receive enable signal (rxcken) is provided. a low on this signal lead disables the input clock from clock- ing in data and permits operation in burst mode. rxsd rxck serial nibble byte rxck rxck rxcken rxcken rxcken rxd0 rxd0 rxd1 rxd1 rxd2 rxd2 rxd3 rxd3 rxd5 rxd4 rxd6 rxd7 txsd txck serial nibble byte txck txck txcken txcken txcken txd0 txd0 txd1 txd1 txd2 txd2 txd3 txd3 txd5 txd4 txd6 txd7 txsc rspf tspf i n p u t o u t p u t data bit-serial polynomial detector nibble-parallel polynomial detector byte-parallel polynomial detector programmable word detector fixed word detector bit-serial polynomial nibble-parallel polynomial byte-parallel polynomial programmable word generator fixed bit error counter clock counter clock cycles errors generator error rate data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cs rd wr clock clock txnc txbc microprocessor input/output interface word generator clock data tr loopback - 4 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 the test pattern, which is common to both the receiver and transmitter, is selected by writing control bits in the memory map. each of the test pattern detectors is equipped with a pattern generator and comparator. the comparison between the incoming data and the pattern generator is enabled after frame alignment takes place, or when the receive start of the pseudo-random feature ( rspf) is used. for a 1100 test pattern, a simpli?ed view of the frame alignment (after two consecutive pattern matches), error detection, and loss of frame alignment (after three consecutive pattern match failures) is shown below: running counts of the numbers of bit errors and clock cycles are maintained in two 24-bit counters. bit error rate performance is determined by having the microprocessor read the counters on a scheduled basis and compute the ratio as an error rate, making due allowance for bit/clock ratios of 4 in nibble-parallel operation and 8 in byte-parallel operation. the clock counter operates regardless of frame alignment status. both counters should be read together, and at intervals of less than the roll-over interval of the clock counter (about 16 million clock cycles). when xbert is in frame, errors are detected one event later. no bit errors are detected after a loss of frame condition occurs. the transmit clock signal (txck) provides the time base for transmitter operation. an input transmit enable signal (txcken) is provided. a low disables the input clock (txck) from clocking out data and permits opera- tion in burst mode. this feature is provided for applications where a gapped clock signal is required to prevent the transmitter from clocking out test pattern data. the interface selection is common to both the receiver and transmitter. the transmit clock signal (txck) is used to derive the txsc, txnc and the txbc clock signals. bit-serial, nibble-parallel and byte-parallel data are clocked out of the xbert on the falling edges of txsc, txnc and txbc respectively. for framer applications, a transmit start of pseudo-random pattern framing pulse ( tspf) is used to preset the transmit pseudo-random generators shift registers to ones. this feature permits the xbert to start the pseudo-random pattern immediately with a ?xed relationship to the start of a frame. for framer applications, a receive start of pseudo-random pattern framing pulse ( rspf) disables the frame alignment circuits in the pseudo-random pattern detectors and presets the pseudo-random generators shift registers to ones, which will result in an immediate in frame condition. used in conjunction with the transmit start of pseudo-random pattern pulse, this feature permits the xbert to start a search immediately for bit errors in the receive data. a software reset is required to enable the frame alignment circuitry in the pseudo- random detectors for normal operation. the microprocessor interface consists of four address bits (a3-a0), eight bidirectional data bus bits (d7-d0), chip select ( cs), and the read ( rd) and write ( wr) signal inputs. a transmit-to-receive (tr) loopback feature is provided for self-testing the xbert device. start detected in frame 12 3 lof detected count good/bad patterns 1 2 0 received signal local generated signal detected errors 000000000000000 . . . . 000010000100001 1100110011001100 . . . . 1100110011001100 1100110011001100 . . . . 1100100011101101 1100 - 5 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 pin diagram figure 2. xbert txc-06125 pin diagram pin descriptions power supply and ground *note: i = input; o = output; p = power symbol pin no. i/o/p* type name/function vdd 1, 23 p v dd : +5 volt supply, 5% gnd 12, 22 29, 34 p ground: zero volt reference level. xbert (top view) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 cs a3 a2 a1 a0 gnd rxd7 rxd6 rxd5 rxd4 rxd3 gnd txd2 txd3 txd4 txd5 gnd txd6 txd7 d0 d1 d2 d3 d4 d5 d6 d7 vdd rxck rxcken rxsd/rxd0 rxd1 rxd2 txd1 txsd/txd0 txsc/txnc/txbc txcken txck vdd gnd tspf rspf wr rd pin diagram txc-06125 - 6 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 receive interface * see input, output and i/o parameters section for type de?nitions. note 1: use of a gapped receive clock input (rxck) or the receive clock enable (rxcken) input to disable clocking in of receive data for de?ned time intervals is subject to restrictions. please contact transwitch applications engi- neering for additional technical information relevant to applications employing these capabilities. symbol pin no. i/o/p type* name/function rxck 2 i ttlp receive clock: bit-serial, nibble-parallel, and byte-par- allel receive data is clocked into the xbert on the rising edge of this clock. this clock is used as the time base for all receive functions. it may be gapped to accommodate overhead bit times. loss of this clock causes the xbert receiver to become inoperative. see note 1. rxcken 3 i ttlp receive clock enable: a high enables the receive clock for clocking data into the xbert. a low disables the clock from clocking in receive bit-serial, nibble-paral- lel, or byte-parallel data. see note 1. rxsd/rxd0 4 i ttlp receive bit-serial data/receive nibble- or byte- parallel data, bit 0: this is the input pin for receive bit- serial data. it is also used as the least signi?cant bit (bit 0) input pin for receive nibble- or byte-parallel data. rxd1 5 i ttlp receive nibble- or byte-parallel data, bit 1. rxd2 6 i ttlp receive nibble- or byte-parallel data, bit 2. rxd3 7 i ttlp receive nibble- or byte-parallel data, bit 3: this is the input pin for the most signi?cant bit (bit 3) for the receive nibble-parallel interface. rxd4 8 i ttlp receive byte-parallel data, bit 4. rxd5 9 i ttlp receive byte-parallel data, bit 5. rxd6 10 i ttlp receive byte-parallel data, bit 6 . rxd7 11 i ttlp receive byte-parallel data, bit 7: this is the input pin for the most signi?cant bit (bit 7) for the receive byte-par- allel interface. rspf 20 i ttlp receive start of pseudo-random pattern framing: an active low enables the prbs detector to search for an all ones pattern, de?ning the start of prbs pattern detection. the ?rst receive pulse sequence (all ones) disables the loss of frame alignment circuit and enables the bit error counter and clock cycle counter. rxcken must be enabled before rspf is clocked in. once enabled, this feature can only be disabled by a reset. this pin is inoperative for ?xed or programmable word patterns. - 7 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 transmit interface symbol pin no. i/o/p type name/function txck 24 i ttlp transmit clock: an input clock used as the time base for generating the test patterns and for sourcing bit- serial, nibble-parallel, and byte-parallel transmit data out of the xbert. this clock may be gapped to accommo- date overhead bit times, as required. loss of this clock causes the xbert transmitter to become inoperative. txcken 25 i ttlp transmit clock enable: a high enables the transmit clock (txck) for clocking data out of the xbert. a low disables the clock from clocking out transmit bit-serial, nibble-parallel, or byte-parallel data. txsc/ txnc/ txbc 26 o ttl8ma transmit serial/nibble/byte clock: this clock is derived from the transmit clock signal (txck), and is used for clocking out data from the xbert. data is clocked out of the xbert on the falling edge of this clock. this clock will have gapped periods correspond- ing to the times when the transmit enable signal (txcken) is low. txsd/txd0 27 o ttl8ma transmit bit-serial data/transmit nibble- or byte- parallel data, bit 0: this is the output pin for transmit bit-serial data. it is also used as the least signi?cant bit (bit 0) output pin for transmit nibble- or byte-parallel data. this bit is the least signi?cant bit and the last bit clocked out for transmit nibble- or byte-parallel data. txd1 28 o ttl8ma transmit nibble- or byte-parallel data, bit 1. txd2 30 o ttl8ma transmit nibble- or byte-parallel data, bit 2. txd3 31 o ttl8ma transmit nibble- or byte-parallel data, bit 3: this is the output pin for the most signi?cant bit (bit 3) for the transmit nibble-parallel interface. txd4 32 o ttl8ma transmit byte-parallel data, bit 4. txd5 33 o ttl8ma transmit byte-parallel data, bit 5. txd6 35 o ttl8ma transmit byte-parallel data, bit 6. txd7 36 o ttl8ma transmit byte-parallel data, bit 7. this is the output pin for the most signi?cant bit (bit 7) for the transmit byte- parallel interface. tspf 21 i ttlp transmit start of pseudo-random pattern framing: an active low pulse causes the xbert to reset to the beginning of the prbs pattern. the starting pulse sequence is an all ones pattern, which de?nes the start of the transmitted prbs test pattern. if the transmit clock enable signal (txcken) is high when tspf is clocked in on the positive edge of the clock, the generator trans- mits the start of the pseudo-random test pattern one and one half clock cycles later (on a negative clock transi- tion). this pin is inoperative for ?xed or programmable word patterns. - 8 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 microprocessor interface symbol pin no. i/o/p type name/function d(7-0) 44-37 i/o ttl8ma data bus: used for programming and reading the regis- ters which reside in the xbert. the most signi?cant bit is d7. high is logic 1. cs 17 i ttlp chip select: a low enables data transfers between the microprocessor and the xbert memory map during a read/write bus cycle. rd 18 i ttlp read data: an active low signal generated by the micro- processor for reading the registers which reside in the memory map. the xbert memory i/o is selected by placing a low on the chip select lead. wr 19 i ttlp write data: an active low signal generated by the micro- processor for writing to the registers which reside in the memory map. the xbert memory i/o is selected by placing a low on the chip select lead. a(3-0) 16-13 i ttlp address lines: the four address lines are used to select an xbert register location. a7 is the most signi?- cant bit. high is logic 1. - 9 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 absolute maximum ratings *operating conditions exceeding those listed in absolute maximum ratings may cause permanent failure. exposure to absolute maximum ratings for extended periods may impair device reliability. **the minimum and maximum allowable ambient operating temperatures, and the maximum power dissipation, will be dependent on the total thermal analysis. thermal characteristics power requirements *power dissipation is application speci?c and depends on the operating frequency, as shown in figure 3. parameter symbol min* max* unit supply voltage v dd -0.3 7.0 v dc input voltage v in -0.5 v dd + 0.5 v continuous power dissipation p c ** mw ambient operating temperature t a ** ** o c operating junction temperature t j 125 o c storage temperature range t s -55 125 o c parameter min typ max unit test conditions thermal resistance - junction to ambient 68 o c/w 0 ft/min linear airflow thermal resistance - junction to case 13.4 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v i dd *ma p dd * mw inputs switching - 10 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 3. power dissipation as a function of frequency for operation of the xbert device in still air without a heat sink, the safe operating regions are defined by the equation: t jmax = t a + [(68 c/w) x (pd)] = 125 c region 1 = xbert may be used in a maximum ambient temperature of t a = 85 o c for txck and rxck clock frequencies < 35 mhz. this yields a maximum bit rate of 8 x 35 = 280 mbit/sec. region 2 = xbert may be used in a maximum ambient temperature of t a = 70 o c for txck and rxck clock frequencies 35 mhz < f < 45 mhz. this yields a maximum bit rate of 8 x 45 = 360 mbit/sec. note: combinations of frequency and ambient temperature beyond the safe operating regions require additional heat dis- sipation methods (the maximum power is 1.38 watts at 622/8 = 78 mhz). a transwitch application note entitled designing with transwitch xbert devices for byte interface at the oc-12 rate, document number txc-06125-an1, provides guid- ance on circuit and heat sink requirements for operation of xbert at 622 mbit/s. pd (mw) f (mhz) 1000 900 800 700 600 500 400 300 200 100 0 010 20 30 40 50 60 byte-parallel i/o interface region 2 region 1 1.544 mhz 8.448 mhz 2.048 mhz 6.312 mhz 19.44 mhz 34.368 mhz 44.736 mhz 51.84 mhz 35 45 to 1.38w at 78 mhz - 11 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 input, output and i/o parameters input parameters for ttlp note: input has a 72k (nominal) internal pullup resistor. output parameters for ttl8ma input/output parameters for ttl8ma parameter min typ max unit test conditions v ih 2.0 v 4.75 - 13 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 5. receive nibble interface timing note: rxck may be gapped or stretched without the use of the rxcken input to accommodate overhead bit times. the set-up and hold times speci?ed for rxcken must be met to ensure correct operation. parameter symbol min typ max unit rxck clock period t cyc 12.8 ns rxck high time t pwh 5.4 1/2 t cyc ns rxck low time t pwl 5.4 1/2 t cyc ns rxcken set-up time before rxck - t su(1) 2.5 ns rxcken hold time after rxck t h(1) 2.5 ns rxd(3-0) set-up time before rxck - t su(2) 3.0 ns rxd(3-0) hold time after rxck - t h(2) 3.0 ns parameter symbol min typ max unit rspf set-up time before rxck - t su 2.5 ns rspf hold time after rxck - t h 2.5 ns rxck* t pwh t h(2) t cyc t su(2) ignore (input) rxd(3-0) (input) t su(1) t h(1) gapped clock t pwl ignore ignore rxcken* (optional input) rspf (optional t h t su input) rxck (input) rxd(3-0) (input) nib n-3 nib 0 nib 1 nib 2 nib n nib n-1 nib n-2 nib n-4 * see note in pin descriptions section. - 14 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 6. receive byte interface timing note: rxck may be gapped or stretched without the use of the rxcken input to accommodate overhead bit times. the set-up and hold times speci?ed for rxcken must be met to ensure correct operation. parameter symbol min typ max unit rxck clock period t cyc 12.8 ns rxck high time t pwh 5.4 1/2 t cyc ns rxck low time t pwl 5.4 1/2 t cyc ns rxcken set-up time before rxck - t su(1) 2.5 ns rxcken hold time after rxck t h(1) 2.5 ns rxd(7-0) set-up time before rxck - t su(2) 3.0 ns rxd(7-0) hold time after rxck - t h(2) 3.0 ns parameter symbol min typ max unit rspf set-up time before rxck - t su 2.5 ns rspf hold time after rxck - t h 2.5 ns rxck* t pwh t h(2) t cyc t su(2) ignore (input) rxd(7-0) (input) t su(1) t h(1) gapped clock t pwl ignore ignore rxcken* (optional input) rspf (optional t h t su input) rxck (input) rxd(7-0) (input) byte n-3 byte 0 byte 1 byte 2 byte n byte n-1 byte n-2 byte n-4 * see note in pin descriptions section. - 15 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 7. transmit serial interface timing note: the clock (txck) may be gapped or stretched without the use of txcken to accommodate overhead bit times. the set-up and hold times speci?ed for txcken must be met to ensure correct operation. parameter symbol min typ max unit txck clock period t cyc 12.8 ns txck high time t pwh 5.4 1/2 t cyc ns txck low time t pwl 5.4 1/2 t cyc ns txcken set-up time before txck - t su 2.5 ns txcken hold time after txck t h 2.5 ns txsc output delay after txck - t od 5.0 ns txsc high time t pwh(1) 5.4 ns parameter symbol min typ max unit txsd output delay after txsc t od 5.0 ns tspf set-up time before txck - t su 2.5 ns tspf hold time after txck - t h 2.5 ns txck txcken t pwh t od t cyc (input) (optional txsc (output) t su t h t pwh(1) gapped clock input) gapped clock t pwl tspf (optional t h txsd (output) t od input) txck (input) txsc (output) bit n-3 bit 0 bit 1 bit 2 bit n bit n-1 bit n-2 t su bit n-4 - 16 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 8. transmit nibble interface timing note: the clock (txck) may be gapped or stretched without the use of txcken to accommodate overhead bit times. the set-up and hold times speci?ed for txcken must be met to ensure correct operation. parameter symbol min typ max unit txck clock period t cyc 12.8 ns txck high time t pwh 5.4 1/2 t cyc ns txck low time t pwl 5.4 1/2 t cyc ns txcken set-up time before txck - t su 2.5 ns txcken hold time after txck t h 2.5 ns txnc output delay after txck - t od 5.0 ns txnc high time t pwh(1) 5.4 ns parameter symbol min typ max unit txd output delay after txnc t od 5.0 ns tspf set-up time before txck - t su 2.5 ns tspf hold time after txck - t h 2.5 ns txck txcken t pwh t od t cyc (input) (optional txnc (output) t su t h t pwh(2) gapped clock input) gapped clock t pwl tspf (optional t h txd(3-0) (output) t od input) txck (input) txnc (output) nib n-3 nib 0 nib 1 nib 2 nib n nib n-1 nib n-2 t su nib n-4 - 17 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 9. transmit byte interface timing note: the clock (txck) may be gapped or stretched without the use of txcken to accommodate overhead bit times. the set-up and hold times speci?ed for txcken must be met to ensure correct operation. parameter symbol min typ max unit txck clock period t cyc 12.8 ns txck high time t pwh 5.4 1/2 t cyc ns txck low time t pwl 5.4 1/2 t cyc ns txcken set-up time before txck - t su 2.5 ns txcken hold time after txck t h 2.5 ns txbc output delay after txck - t od 5.0 ns txbc high time t pwh(1) 5.4 ns parameter symbol min typ max unit txd output delay after txbc t od 5.0 ns tspf set-up time before txck - t su 2.5 ns tspf hold time after txck - t h 2.5 ns txck txcken t pwh t od t cyc (input) (optional txbc (output) t su t h t pwh(1) gapped clock input) gapped clock t pwl tspf (optional t h txd(7-0) (output) t od input) txck (input) txbc (output) byte n-3 byte 0 byte 1 byte 2 byte n byte n-1 byte n-2 t su byte n-4 - 18 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 10. microprocessor read timing parameter symbol min typ max unit a(3-0) set-up time before rd t su(2) 10.0 ns cs set-up time before rd t su(1) 5.0 ns a(3-0) hold time after rd - t h 10.0 ns rd pulse width t pw 38 ns data output delay after rd t od 8.0 ns data ?oat time after rd - t f 2.0 ns cs hold time after rd - t h(3) 5.0 ns a(3-0) cs t h t f d(7-0) data output t su(1) t pw t su(2) rd data valid t od t h(3) note: a minimum of 10 txck clock cycles must occur after power-up, before the read cycles will operate correctly. - 19 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 figure 11. microprocessor write timing note: a minimum of 10 txck clock cycles must occur after power-up, before the write cycles will operate correctly. parameter symbol min typ max unit a(3-0) set-up time before wr t su(2) 10.0 ns cs set-up time before wr t su(1) 5.0 ns a(3-0) hold time after wr - t h(1) 10.0 ns wr pulse width t pw 38 ns data set-up time before wr - t su(3) 10.0 ns data hold time after wr - t h(2) 5.0 ns cs hold time after wr - t h(3) 5.0 ns a(3-0) cs t h(1) t h(2) d(7-0) data input t su(1) t pw t su(3) t su(2) wr data valid t h(3) - 20 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 operation decoupling of power supply pins each of the two +5 volt power supply pins of the xbert device, pins 1 and 23, should be decoupled using a series inductor (ferrite bead) and capacitors that are effective at both low and high frequencies, as shown in figure 12. these external components should be placed close to the pin, especially the lower-valued rf capacitor. figure 12. recommended decoupling of power supply pins external circuit for proper updating of bit error and clock counters under certain combinations of microprocessor access and telecommunications usage, the bit error counter (at memory map addresses 06h, 07h and 08h) and the clock counter (at memory map addresses 09h, 0ah and 0bh) may not be updated correctly by the xbert device. since it is not possible to specify all the combi- nations of conditions under which this incorrect operation can occur, it is recommended that users of the xbert device should either contact the applications engineering department at transwitch for advice on the susceptibility of their particular applications, or avoid any potential problems in their designs by employing the external circuit and special software precautions described below. the two 24-bit counters are specially designed to record their event counts accurately even when the counters are being read by the microprocessor. the counters latch during a microprocessor read operation, and both counters must be read together by six read cycles performed on addresses 09h (?rst), 0ah, 0bh, 06h, 07h and 08h (last). the ?nal reading of address 08h starts a state machine that transfers the counts synchro- nously with the receive clock. this transfer occurs upon the third ungapped receive clock after the rising edge of the rd input signal applied during the address 08h read access. however, the state machine is cleared from its update sequence upon the next microprocessor initiation of active rd or wr input signals, so correct update operation requires that one of these does not occur before the update has been processed, i.e., before three clock periods have elapsed. incorrect operation will result in a failure to update the counters, which will appear to be stuck. v dd = +5v gnd ferrite bead 10, 6.3v + 0.1 ferrite bead + 0.1 gnd 10, 6.3v xbert 123 notes: 1. fair-rite products part no. 2743002111, or equivalent, should be used for each ferrite bead (walkill, ny, 914-895-2055). 2. all capacitor values are shown in microfarads. - 21 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 this problem may avoided by employing an external circuit and special software to ensure that the xbert does not experience an active rd or wr input during the critical period of three clock cycles. the circuit shown in figure 13 gates the read and write lines with the xberts chip select input to ensure that the xbert does not see any read or write signals intended for other devices, which may occur during the critical period (the gate in the chip select line is intended only to equalize the gate delays on all three input pins so that the microprocessor read/write cycle timing diagrams of this data sheet are applicable without special adjustment for differences in the relative timing between rd or wr and cs). read or write signals which are intended for the xbert (i.e., those which are active when cs is low) must be programmed not to occur during the critical period. the hold-off time from reading address 08h to the next read or write of the group starting with address 09h must be arranged to be a minimum of: [3 + (maximum number of successive read clock gaps)] x 1/(receive clock frequency) for example, a t1 application requires the following hold-off time from accessing address 08h to accessing address 09h: [3 + (1 overhead bit time)] x 1/1.544mhz = 4 x 0.666 = 2.664 microseconds (rounded up to 2.7). . figure 13. protection of xbert from read/write signals intended for other devices xbert or or or wr rd cs wr rd cs 19 18 17 74f32 - 22 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 memory map the xbert memory map consists of register bit positions and counters, which may be accessed by a micro- processor for read and (except for counters) write cycles. the unused bit position at bit 3 of register 01h is a dont care bit, but it is recommended that it should be set to 0. *read/write (r/w); read only (r). address (hex) mode* bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 r/w poly prog sel1 sel0 reset invtd mode1 mode0 01 r/w err1 err0 sse resetc unused trlbk test lof 02 r/w programmable word, byte 4 03 r/w programmable word, byte 3 04 r/w programmable word, byte 2 05 r/w programmable word, byte 1 06 r bit error counter (ms byte) 07 r bit error counter (middle byte) 08 r bit error counter (ls byte) 09 r clock counter (ms byte) 0a r clock counter (middle byte) 0b r clock counter (ls byte) - 23 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 memory map descriptions address* bit symbol description 00 7 6 5 4 poly prog sel1 sel0 test pattern generator and detector: bits 7 through 4 are used to select a test pattern according to the truth table shown below. the 2 20 - 1 pseudo- random test pattern designator zs stands for zero suppression. the 2 20 - 1 with zero suppression is also de?ned as a qrss signal. this test pattern is not supported in the byte mode. the test pattern is common for both genera- tion and detection (including programmable words). for in frame and loss of frame conditions please refer to the lof bit description for address 01h, bit 0. 3 reset reset xbert: a global reset occurs when a one is written to this bit posi- tion. this must be followed by writing a zero into this location. reset clears the internal counters, generators, and detectors, as well as the control bits and performance counters in the memory map. all r/w memory map bit positions must be set to their desired values after a reset. 2 invtd invert transmit data: a one written into this position causes the data to be inverted for transmission. the data is inverted for the bit-serial, nibble-paral- lel, and byte-parallel interfaces. 1 0 mode1 mode0 xbert interface selection: the xbert transmit and receive interface is selected according to the following table: polynomial (poly) program (prog) select 1 (sel1) select 0 (sel0) test pattern 0 0 0 0 0000000000. . . . 0 0 0 1 1111111111. . . . 0 0 1 0 1010101010. . . . 0 0 1 1 1100110011. . . . 0 1 0 0 byte 1 only 0 1 0 1 bytes 1 & 2 0 1 1 0 bytes 1,2 &3 0 1 1 1 bytes 1, 2, 3 & 4 1000 2 15 - 1 10012 20 - 1(zs) 1010 2 20 - 1 1011 2 23 - 1 mode1 mode0 interface selected 0 0 bit-serial 0 1 nibble-parallel 1 1 byte-parallel * note: all addresses are shown in hexadecimal form. - 24 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 01 7 6 err1 err0 transmit error rate: these two bits control the generation of the ?xed bit error rates given in the table below. for example, a 10e -3 error rate results in the xbert transmitting one bit in a thousand in error. the error is generated by inverting a single bit in the bit pattern. the error rate generation is inde- pendent of the pattern selected (pseudo-random, ?xed word, or programma- ble). 5 sse send single error: a single bit error is transmitted by writing a one into this bit position. the error is sent in the next bit time after being written. after sending the single error, the bit is reset by the xbert. the microprocessor must write a one in order to send another single bit error. 4 resetc reset performance counters: a one causes the bit error counter (loca- tions 06h, 07h, and 08h) and the clock counter (locations 09h, 0ah, and 0bh) to be reset to 0. xbert resets this bit after the performance counters have been reset. this bit does not affect registers 00h through 05h. 3 unused. 2 trlbk transmit-to-receive (tr) loopback: a one activates the transmit-to- receive loopback testing feature. data is transmitted and is also looped back as receive data. the receive data input is disabled. 1 test transwitch test: a zero must be written into this bit position. 0 lof loss of frame: an in frame condition for any ?xed word pattern (e.g., 1100, 1010) occurs when two consecutive error-free 4-bit patterns are received. loss of frame occurs when three consecutive 4-bit patterns are received in error or when 30 or more bits in a block of 1000 consecutive bits are in error. an in frame condition for any programmable word occurs when two con- secutive error-free word patterns are received. the programmable word pat- tern can vary from 1 to 4 words, which equates to 2 to 8 words before an in frame condition can occur. loss of frame occurs when three consecutive word patterns are received in error or when 30 or more bits in a block of 1000 consecutive bits are in error. an in frame condition for any prbs pattern occurs when the start of frame pulse sequence is received. the length of the start of frame pulse sequence equals the exponent number of the prbs pattern. therefore, a 2 23-1 prbs pattern has a 23 consecutive ones sequence for its start of frame pulse sequence and a 2 15-1 prbs pattern has a 15 consecutive ones sequence. if the tspf and rspf pins are activated, the prbs pattern will reset and begin with a start of frame pulse sequence, which will be detected with mini- mum delay. loss of frame occurs when 30 or more bits in a block of 1000 consecutive bits are in error. for all word patterns and prbs sequences, the clock counter maintains its functionality during a lof condition and the bit error counter is disabled. address* bit symbol description err1 err0 error rate 0 0 no errors 01 10 -3 error rate 10 10 -6 error rate - 25 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 02 7-0 programmable word, byte 4: the xbert provides four register locations (02h, 03h, 04h, and 05h) for four bytes of programmable test word pattern. the actual number of bytes that comprise the test word pattern (1-4) is selected by bits 7-4 in the 00h register location. the word is transmitted with byte 1 sent last. bit 7 in each byte is its most signi?cant bit and the ?rst bit transmitted. bit 0 in byte 1 is the last bit transmitted in the test word sequence. for example, the test sequence for a four-byte test word pattern bounded by bits msb and lsb is shown below: for a single-byte test word, only byte 1 is used. the receive detector checks the incoming data for frame alignment by comparing it with the programmed test word pattern. 03 7-0 programmable word, byte 3: see address 02h. 04 7-0 programmable word, byte 2: see address 02h. 05 7-0 programmable word, byte 1: see address 02h. 06 07 08 7-0 bit error counter: register locations 06h, 07h, and 08h provide a total count of the number of bit errors that have occurred for the three interface modes. multiple errors in a single nibble or byte are counted separately. the counter is enabled after frame alignment occurs for the test pattern selected. bit 7 in address 06h is the most signi?cant bit, while bit 0 in address 08h is the least signi?cant bit. the counter is non-saturating and will roll-over to zero when it becomes full. to ensure that no counts are lost, all clock counter registers plus all bit error counter registers must be read together in the fol- lowing order: 09h, 0ah, 0bh, 06h, 07h, 08h. they will all be simultaneously latched when register 08h is read last. if the counter registers are always read in the same order, then no counts will be lost. the counter is cleared by writing a one to bit 4 (resetc) in address 01h, or through a global reset (bit 3 in address 00h). 09 0a 0b 7-0 clock counter: register locations 09h, 0ah, and 0bh provide a total count of the number of clock pulses that have been received. when xbert is in serial mode, the clock counter provides a count of the total number of received data bits. when xbert is in nibble-parallel or byte-parallel mode, the clock counter indicates the number of received nibbles or bytes, respec- tively. the counter is enabled upon power-up. events are counted even dur- ing a lof condition. bit 7 in address 09h is the most signi?cant bit, while bit 0 in address 0bh is the least signi?cant bit. the counter is non-saturating and will roll-over to zero when it becomes full. it takes approximately 0.32 seconds for the counter to roll-over for a 51.84 mbit/s bit-serial signal. to ensure that no counts are lost, all clock counter registers plus all bit error counter registers must be read together in the following order: 09h, 0ah, 0bh, 06h, 07h, 08h. they will all be simultaneously latched when register 08h is read last. if the counter registers are always read in the same order, then no counts will be lost. the counter is cleared by writing a one to bit 4 (resetc) in address 01h, or through a global reset (bit 3 in address 00h). address* bit symbol description byte 4 byte 3 byte 2 byte 1 byte 4 msbxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxlsb msbxxxxxxx 7 070707 07 0 bit - 26 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 package information the xbert is available in a 44-pin plastic leaded chip carrier as illustrated in figure 14. figure 14. xbert txc-06125 44-pin plastic leaded chip carrier transwitch 40 6 29 39 17 7 28 18 .500 sq. .653 sq. .075 .149 .170 bottom view top view 40 6 29 39 17 7 28 18 1 1 .690 sq. .017 typ. .050 typ. note: all dimension values are shown in inches and are nominal unless otherwise indicated. - 27 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 ordering information part number: TXC-06125-ACPL 44-pin plastic leaded chip carrier related products txc-02020, art vlsi device (advanced sts-1/ds3 receiver/transmitter). art performs the transmit and receive line interface functions required for transmission of sts-1 (51.840 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02021, arte vlsi device (advanced sts-1/ds3 receiver/transmitter). arte has the same functionality as art, plus expanded features. txc-02050, mrt multi-rate line interface vlsi device. the mrt provides the functions for terminating itu-speci?ed 8448 kbit/s (e2) and 34368 kbit/s (e3) line rate signals, or 6312 kbit/s (jt2) line signals speci?ed in the japanese ntt technical reference for high speed digital leased circuits. an optional hdb3 codec is provided for the two itu line rates. txc-02623, staf vlsi device (sonet/sdh transceiver and framer). the staf is a 622/155.5 mbit/s device that combines multiplexing, demultiplexing, sonet/sdh framing, clock synthesis pll and loopback functions in a single chip. txc-02624, cdr vlsi device (sonet/sdh clock and data recovery). the cdr is a 622 mbit/s monolithic clock and data recovery component that receives nrz data, extracts the high-speed clock, and presents the separated data and clock as its outputs. txc-03301, m13 vlsi device (ds3/ds1 mux/demux). this single-chip multiplex/ demultiplex device provides the complete interfacing function between a single ds3 signal and 28 independent ds1 signals. txc-03303, m13e vlsi device, extended feature version of the txc-03301 (m13). txc-03401, ds3f vlsi device (ds3 framer). maps broadband payloads into the ds3 frame format. operates in either the c-bit parity or m13 operating modes. txc-03701 e2/e3f framer vlsi device. the e2/e3 framer directly interfaces with the mrt and provides multi-mode framing for itu-t rec. g.751/g.753 (34368 kbit/s) or itu-t rec. g.742/g.745 (8448 kbit/s) signals. txc-03702 jt2f framer vlsi device. the jt2f framer directly interfaces with the mrt and provides framing for itu-t rec. g.704 (6312 kbit/s) signals. txc-20153d, ds3/sts-1 line interface module (ds3lim-sn). complete and compact analog to digital interface serving b3zs encoded ds3 signals. txc-21075, xbert evaluation board. a complete, ready-to-use board that demonstrates the functions and features of the xbert vlsi device. - 28 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute (ansi) 11 west 42nd street new york, new york 10036 tel: 212-642-4900 fax: 212-302-1286 bellcore (u.s.a.): bellcore attention - customer service 8 corporate place piscataway, nj 08854 tel: 800-521-core (in u.s.a.) tel: 908-699-5800 fax: 908-336-2559 ieee (u.s.a.) the institute of electrical and electronics engineers, inc. customer service department 445 hoes lane p. o. box 1331 piscataway, nj 08855-1331 tel: 800-701-4333 (in u.s.a.) tel: 908-981-0060 fax: 908-981-9667 itu-tss (international): publication services of international telecommunication union (itu) telecommunication standardization sector (tss) place des nations ch 1211 geneve 20, switzerland tel: 41-22-730-5285 fax: 41-22-730-5991 ttc (japan): ttc standard publishing group of the telecommunications technology committee 2nd floor, hamamatsucho - suzuki building, 1 2-11, hamamatsu-cho, minato-ku, tokyo tel: 81-3-3432-1551 fax: 81-3-3432-1553 - 29 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 list of data sheet changes this change list identi?es those areas within this updated xbert data sheet that have technical differences relative to the previous and now superseded xbert data sheet: updated xbert data sheet: edition 3, august 1995 superseded xbert data sheet: edition 2, august 1992 the page numbers indicated below of this updated data sheet include changes relative to the superseded data sheet. page number of updated data sheet summary of the change all changed document status by deleting preliminary. 1 changed edition number and date. 1 made changes to features list. 1 made changes to description list. 1 made minor clari?cations to the ?gure. 2-33 added edition number and date to the bottom. 2 added table of contents and list of figures. 3 made changes to figure 1. 3-4 made changes to block diagram description section. 5-7 changed rsf to rspf and tsf to tspf. 5 made changes to figure 2. 5 made changes to name/function column for gnd. 6 made changes to name/function column for rxsd/rxd0, rxd3, rxd7 and rspf. 6 added notes to the bottom to explain type column heading and to indicate restrictions on the use of rxck and rxcken inputs to disable data input. 7 made changes to name/function column for txck, txsd/txd0, txd3, txd7 and tspf. 8 made changes to name/function column for d(7-0) and a(3-0). 9 changed max for p c row and modi?ed the second note to absolute maxi- mum ratings section. 9 added test conditions to thermal characteristics table. 9 deleted typ and added max to thermal resistance - junction to case. 9 modi?ed the note under power requirements table. 10 modi?ed figure 3. 11 input parameters for ttlp: changed typ for input capacitance. - 30 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 11 output parameters for ttl8ma: changed min, typ and max for t rise and t fall . 11 input/output parameters for ttl8ma: changed type for input capacitance and changed min, typ and max for t rise and t fall . 12-17 in figures 4-9, changed timing parameters to correspond to highest clock frequency of 78 mhz instead of 52 mhz. added note to timing diagrams in figures 4-6. 18-19 added last row and a note to the table. 20-21 changed operation section. 22 made changes to memory map section 23-25 made changes to memory map descriptions section. 26 made minor changes to package information section. 27 changed ordering information and related products sections. 28 added standards documentation sources section. 29-30 added list of data sheet changes section. 33 added documentation update registration form. page number of updated data sheet summary of the change - 31 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - 32 - transwitch vlsi: powering communication innovation transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 - 33 - xbert txc-06125 txc-06125-mb ed. 3, august 1995 documentation update registration form if you would like be added to our database of customers who have registered to receive updated documenta- tion for this device as it becomes available, please provide your name and address below, and fax or mail this page to mary koch at transwitch. mary will ensure that relevant product information sheets, data sheets, application notes and technical bulletins are sent to you. please print or type the information requested below, or attach a business card. name: ________________________________________________________________________ title: _________________________________________________________________________ company: _____________________________________________________________________ dept./mailstop: ________________________________________________________________ street: _______________________________________________________________________ city/state/zip: _________________________________________________________________ if located outside u.s.a., please add - postal code: ___________ country: ______________ telephone:______________________________________________ ext.: _________________ fax: __________________________________ e-mail: _______________________________ purchasing dept. location: _______________________________________________________ please describe brie?y your intended application for this device, and indicate whether you would care to have a transwitch applications engineer contact you to provide assistance: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ please fax this page to mary koch at (203) 926-9453 or fold, tape and mail it (see other side) transwitch vlsi: powering communication innovation transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 transwitch corporation attention: mary koch 8 progress drive shelton, ct 06484 u.s.a. first class postage required please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line ?rst.) (fold back on this line second, then tape closed, stamp and mail.) |
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