20 n-channel enhancement mode field effect transistor preliminary features 20v , 3.0a , r ds(on) =55m (typ) @v gs =4.5v. high dense cell design for low r ds(on) . rugged and reliable. sot-23 package. absolute maximum ratings (t a =25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 8 v drain current-continuous -pulsed i d 3.0 10 0.94 1.25 a a a w i dm drain-source diode forward current i s maximum power dissipation p d operating junction and storage temperature range t j ,t stg -55to150 c thermal characteristics thermal resistance, junction-to-ambient r / ja 100 /w c ? r ds(on) =82m (typ) @v gs =2.5v. ? CES2302 a a a a b s g d g d s sot-23 1 7
CES2302 electrical characteristics (t a =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d =10 a 20 v zero gate voltage drain current i dss v ds = 20v, v gs =0v 1 a gate-body leakage i gss v gs =8v,v ds =0v 100 na on characteristics b gate threshold voltage v gs(th) v ds =v gs ,i d =50 a 0.65 1.2 v drain-source on-state resistance r ds(on) v gs = 4.5v, i d = 3.6a 72 m ? v gs = 2.5v, i d = 3.1a 110 m ? on-state drain current i d(on) v ds =5v,v gs = 4.5v 6 8.5 a s forward transconductance fs g v ds =5v,i d = 3.6a dynamic characteristics c input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =10v, v gs =0v f =1.0mh z 237 p f 120 p f p f 45 switching characteristics c turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =10v, i d = 3.6a, v gen = 4.5v, r gen =6 ? 23 45 ns ns ns ns 11 30 34 70 36 70 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =10v, i d = 3.6a, v gs =4.5v 6.0 nc nc nc 1.4 1.8 c fall time 7 2 10 55 82
parameter symbol condition min typ max unit electrical characteristics (t a =25 c unless otherwise noted) c drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =0.94a 1.2 v b notes a.surface mounted on fr4 board, t 5sec. c.guaranteed by design, not subject to production testing. b.pulse test:pulse width 300 3 s, duty cycle 2%. figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) c, capacitance (pf) i d , drain current (a) i d , drain current (a) [ [ 7 3 CES2302 048121620 ciss coss crss 400 300 200 100 0 10 8 6 4 2 0 0 1 2 3 4 5 v gs =4.5,3.5,2.5v v g s =1.5 v v gs =2 v 10 8 6 4 2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 -55 c tj=125 c 25 c figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) -50 -25 0 25 50 75 100 125 150 1.80 1.60 1.40 1.20 1.00 0.80 0.60 v gs =4.5v i d =3.6a r ds(on) , normalized r ds(on) , [
CES2302 figure 5. gate threshold variation with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 7 10 8 0 2 4 6 012 34 v ds =5v 4 1.60 1.40 1.20 1.00 0.60 0.80 0.40 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 ? a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 ? a 1 0.1 0.01 0.001 0.2 0.4 0.6 0.8 1.2 10 1.0 10 10 -1 10 10 2 1 0 10 -2 10 0 10 1 10 -1 t a =25 c single pulse tj=150 c r ds(o n )li m it dc 1s 100ms 1ms 10ms 4 5 3 2 1 0 0 13 45 v ds =10v i d =3.6a 2 6
figure 11. switching test circuit figure 12. switching waveforms 5 7 CES2302 t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted v dd r d v v r s v g gs in gen out l transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective 10 -4 p dm t 1 t 2 10 -3 10 -2 10 -1 10 0 p dm t 1 t 2 1. r / ja (t)=r (t) * r / ja 2. r / ja =see datasheet 3. t jm- t a =p*r / ja (t) 4. duty cycle, d=t1/t2 0.01 0.1 2 10 2 10 1 single pulse 0.02 0.05 0.1 0.2 d=0.5 1
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