EDI8F8257C 256kx8 sram module 1 EDI8F8257C rev. 8.0 4/96 eco#7470 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a dq dq1 dq2 vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc a15 a17 w a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 a -a16 w g a17 e decoder dq -dq7 128kx8 128kx8 256kx8 static ram cmos, module the EDI8F8257C is a two megabit cmos static ram based on two 128kx8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. functional equivalence to the monolithic two megabit static ram is achieved by utilization of an on-board decoder that interprets the higher order address (a17) to select one of the 128kx8 static rams. the 32 pin dip pinout adheres to the jedec standard for the two megabit device, to ensure compatibility with future monolithics. the device is available with low power and data retention (edi8f8257lp). all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the EDI8F8257C requires no clocks or refreshing for operation. pin configurations and block diagram features 256kx8 bit cmos static random access memory ? access times 70, 85 and 100ns ? data retention function (lp version) ? ttl compatible inputs and outputs ? fully static, no clocks high density packaging ? 32 pin soic module, no. 21 ? 32 pin dip module, no. 184 single +5v ( 10%) supply operation pin names a?-a17 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v 10%) vss ground nc no connection electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748
EDI8F8257C 256kx8 sram module 2 EDI8F8257C rev. 8.0 4/96 eco#7470 absolute maximum ratings* recommended dc operating conditions parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0 c to +70 c industrial -40 c to +85 c storage temperature plastic -55 c to +125 c power dissipation 1 watt output current. 20 ma dc electrical characteristics parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 110 130 ma supply current min cycle standby (ttl) power icc2 e 3 vih, vin vil -- 10 35 ma supply current vin 3 vih full standby power icc3 e 3 vcc-0.2v c -- 2 5 ma supply current (cmos) vin 3 vcc-0.2v lp -- 40 400 m a vin 0.2v input leakage current ili vin = 0v to vcc -10 -- 10 m a output leakage current ilo v i/o = 0v to vcc -10 -- 10 m a output high voltage voh ioh =-1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v *typical: ta = 25 c, vcc = 5.0v capacitance truth table g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 (f=1.0mhz, vin=vcc or vss) parameter sym max unit input capacitance (except dq pins) ci 15 pf capacitance (dq pins) cd/q 20 pf input (e) cc 10 pf input (w) line cw 15 pf these parameters are sampled, not 100% tested. ac test conditions input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (note: for tehqz,tghqz and twlqz, cl = 5pf)
EDI8F8257C 256kx8 sram module 3 EDI8F8257C rev. 8.0 4/96 eco#7470 ac characteristics read cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time tavav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 40 45 50 ns output disable to output in high z(1) tghqz tohz 30 35 40 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns read cycle 1 - w high, g, e low note: parameter guaranteed, but not tested tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv read cycle 2 - w high tavav tavqv tavqx data 2 a q address 1 address 2 data 1
EDI8F8257C 256kx8 sram module 4 EDI8F8257C rev. 8.0 4/96 eco#7470 symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns ac characteristics write cycle tavav tavwl tdvwh data valid q a twhdx tavwh twlwh twhax twhqx twlqz high z w d e telwh write cycle 1 - w controlled note 1: parameter guaranteed, but not tested.
EDI8F8257C 256kx8 sram module 5 EDI8F8257C rev. 8.0 4/96 eco#7470 write cycle 2 - e controlled characteristic sym test conditions vdd min typ max unit 70 c85 c data retention voltage vdd vdd = 0.2v 2 -- -- -- v data retention quiescent current iccdr e 3 vdd -0.2v 2v -- 10 125 185 m a vin 3 vdd -0.2v 3v -- 20 200 250 m a chip disable to data retention time tcdr or vin 0.2v 0 -- -- -- ns operation recovery time tr tavav* -- -- -- ns data retention characteristics *read cycle time data retention mode e 3 vdd -0.2v e vcc tcdr tr 4.5v 4.5v vdd lp version only e controlled a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh data retention e controlled
EDI8F8257C 256kx8 sram module 6 EDI8F8257C rev. 8.0 4/96 eco#7470 pin 1 indicator 0.825 0.810 0.550 0.525 0.185 0.170 0.050 typ 0.020 0.016 0.230 max 0.080 typ 0.565 0.535 standard power low power with data retention speed package (ns) no. EDI8F8257C70bpc edi8f8257lp70bpc 70 21 EDI8F8257C85bpc edi8f8257lp85bpc 85 21 EDI8F8257C100bpc edi8f8257lp100bpc 100 21 EDI8F8257C70b6c edi8f8257lp70b6c 70 184 EDI8F8257C85b6c edi8f8257lp85b6c 85 184 EDI8F8257C100b6c edi8f8257lp100b6c 100 184 note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. EDI8F8257C70bpc becomes EDI8F8257C70bpi. ordering information pin 1 indicator 0.100 typ 15x 0.100 =1.500 0.620 0.590 1.665 max. 0.610 max. 0.095 0.070 0.020 0.016 0.175 0.125 0.274 max. electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 package no. 184 32 pin dual-in-line package package no. 21 32 pin soic module package description
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