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w83194br-903 & W83194BG-903 stepless via pt/pm main clock generator date: 5/2/2006 revision: 1.0
w83194br-903/W83194BG-903 publication release date: may 2006 - i - revision 1.0 w83194br-903 datasheet revision history pages dates version web version main contents 1 n.a. n.a. all of the versions before 0.50 are for internal use. 2 n.a. 09/07/03 0.5 n.a. first pub lished preliminary version. 3 6 10/28/03 0.6 n.a. modify frequency table 4 7,9,19 12/18/03 0.7 n.a. correction ic version, correction some description and default value 5 05/02/06 1.0 1.0 update on web and add lead free part 6 7 8 9 1 0
w83194br-903/W83194BG-903 - ii - table of contents- 1. general des cription ............................................................................................................ .. 1 2. product f eatures............................................................................................................... .... 1 3. pin config uration.............................................................................................................. ...... 2 4. block diagram.................................................................................................................. ......... 2 5. pin descri ption ................................................................................................................ ......... 3 5.1 crystal i/o.................................................................................................................... .......................3 5.2 cpu, agp, and pci clock outputs................................................................................................ ...3 5.3 fixed frequency outputs........................................................................................................ ...........4 5.4 i 2 c control interface............................................................................................................ ...............4 5.5 power management pins.......................................................................................................... .........5 5.6 iref selects function .......................................................................................................... ..............5 5.7 power pins ..................................................................................................................... ....................5 6. frequency selection by ha rdware or so ftware..................................................... 6 7. i 2 c control and stat us registers.................................................................................... 7 7.1 register 0: frequency select (defaul t = 10h)................................................................................... 7 7.2 register 1: cpu clock (1 = enable, 0 = st opped) (default: e2h)....................................................7 7.3 register 2: pci clock (1 = enable, 0 = st opped) (default: ffh)......................................................8 7.4 register 3: pci, agp clock (1 = enable, 0 = stopped) (default: ffh)............................................8 7.5 register 4: 24_48mhz, 48mhz, ref, 25mhz control (1 = enable, 0 = stopped) (default: bfh)..8 7.6 register 5: watchdog control (default: 02h) .................................................................................... 9 7.7 register 6: reserved (def ault: 50h) (read only) .............................................................................9 7.8 register 7: winbond chip id (default: 70h) (read only)...............................................................10 7.9 register 8: m/n program (default: 90h)......................................................................................... .10 7.10 register 9: m/n program (default: 7ah) ......................................................................................... 10 7.11 register 10: m/n program (default: bbh).......................................................................................1 1 7.12 register 11: spread spectrum programming (default: 0bh) .........................................................11 7.13 register 12: divisor and step- less enable control (default: fbh).................................................11 7.14 register 13: divisor and step- less enable control (default: 0fh) .................................................12 7.15 register 14: control (default: 0ah)............................................................................................ ......12 7.16 register 15: sst & skew control (defa ult: 2ch) ...........................................................................13 7.17 register 16: skew control (defaul t: 24h)....................................................................................... .13 7.18 register 17: slew rate control (default: 00h).................................................................................. 13 7.19 register 18: slew rate control (default: 00h).................................................................................. 14 7.20 register 19: slew rate control (default: d2h).................................................................................1 4
w83194br-903/W83194BG-903 publication release date: may 2006 - iii - revision 1.0 7.21 register 20: watch dog timer (default: 08h)...................................................................................1 4 7.22 register21: fix mode co ntrol (default: 00h)...................................................................................1 5 8. access inte rface............................................................................................................... .... 16 8.1 block write protocol ........................................................................................................... ..............16 8.2 block read protocol ............................................................................................................ .............16 8.3 byte write protocol ............................................................................................................ ...............16 8.4 byte read protocol............................................................................................................. ..............16 9. specificat ions................................................................................................................. ........ 17 9.1 absolute maximum ratings .................................................................................................17 9.2 general operating characteristics .............................................................................................. ....17 9.3 skew group timing clock ........................................................................................................ .........18 9.4 cpu 0.7v electrical characteristics ............................................................................................ ....18 9.5 agp electrical characteristics................................................................................................. ........18 9.6 pci electrical characteristics................................................................................................. ..........19 9.7 24m, 48m electrical characteristics ............................................................................................ ....19 9.8 ref electrical characteristics ................................................................................................. ........19 10. ordering info rmation ......................................................................................................... 20 11. how to read the top marking .......................................................................................... 20 12. package drawing an d dimens ions .................................................................................. 21
w83194br-903/W83194BG-903 publication release date: may 2006 - 1 - revision 1.0 1. general description the w83194br-903 is a clock synthesizer for via pt880/pm880 chipset. w83194br-903 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of cpu, pci, and agp cloc ks setting, support two 25 mhz clock outputs, all clocks are externally selectable with smooth transitions. the w83194br-903 provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and pr ovides -0.5% and +/-0.25% center ty pe spread spectrum or programmable s.s.t. scale to reduce emi. the w83194br-903 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. the w83194br-903 accepts a 14.318 mhz reference crys tal as its input and runs on a 3.3v supply. 2. product features ? 3 0.7v current-mode differ ential pairs clock outputs ? 2 2.5v 25mhz clock outputs ? 3 agp clock outputs ? 10 pci synchronous clocks ? 1 24_48mhz clock output for super i/o. ? 1 48 mhz clock output for usb. ? 2 14.318mhz ref clock outputs. ? agp/pci clock out supports synchronous and asynchronous mode ? smooth frequency switch with selections from 100 to 400mhz ? step-less frequency programming ? i 2 c 2-wire serial interface and support byte read/write and block read/write. ? -0.5% and +/- 0.25% center type spread spectrum ? programmable s.s.t. scale to reduce emi ? programmable registers to enable/st op each output and select modes ? programmable clock outputs slew rate control and skew control ? watch dog timer and reset# output pins ? 48-pin ssop package
w83194br-903/W83194BG-903 - 2 - 3. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 fs1* /ref0 fs0 & /ref1 vddref xin xout gnd fs2 & /pci_f0 fs4 & /pci_f1 pci_f2 vddpci gnd mode & /pci0 pci1 pci2 pci3 pci4 vddpci gnd pci_stop#*/pci5 cpu_stop#*/pci6 fs3 & /48mhz sel24_48# & /24_48mhz gnd vdd48 vdda gnd iref cput_itp cpuc_itp gnd cput1 cpuc1 vddcpu cput0 cpuc0 gnd 25mhz_0 25mhz_1 vdd2.5 vtt_pwrgd/pd#* sdata* sclk* reset# agp_0 gnd vddagp agp_1 agp_2 #: active low *: internal pull up resistor 120k to vdd &: internal pull-down resistor 120k to gnd 4. block diagram pll2 xtal osc pll1 spread spectrum m/n/ratio rom latch &por control logic &config register i2c interface divider vcoclk 48mhz ref 0:1 cput0:1 cpuc0:1 agp 0:2 pci_f0:2,pc i_0:6 reset# rref xin xout vtt_pwrgd fs(0:4) pd#* sel24_48# & sdata* sclk* 3 1 0 mode & divider 24_48mhz 2 2 ? ? 2 25mhz_0:1 2 pci_stop#* cpu_stop#* cput_itp cpuc_itp
w83194br-903/W83194BG-903 publication release date: may 2006 - 3 - revision 1.0 5. pin description buffer type symbol description in input in tp120k latched input at power up, internal 120k ? pull up. in td120k latched input at power up, internal 120k ? pull down. out output od open drain i/od bi-directional pin, open drain. # active low * internal 120k ? pull-up & internal 120 k ? pull-down 5.1 crystal i/o pin pin name type description 4 xin in crystal input with internal loading capacitors (18pf) and feedback resistors. 5 xout out crystal output at 14.318mhz nominally with internal loading capacitors (18pf). 5.2 cpu, agp, and pci clock outputs pin pin name type description 42,39,41,38 cput [0:1] cpuc [0:1] out low skew (< 250ps) differential clock outputs for host frequencies of cpu 45,44 cput_itp, cpuc_itp out differential clock outputs for host frequencies of cpu 29,26,25 agp0: 2 out 3.3v agp clock outputs. pci_f0 out 3.3v pci free running clock output. 7 fs2 & in td120k latched input for fs2 at initial power up for h/w selecting the output frequency. this is internal 120k pull down. pci_f1 out 3.3v pci free running clock output. 8 fs4 & in td120k latched input for fs4 at initial power up for h/w selecting the output frequency, this is internal 120k pull down. pci0 out 3.3v pci clock output. 12 mode & in td120k latched input for pin 19,20 at initial power up selecting the 0=pci5, pci6 clock output, 1=pci_stop and cpu _stop control pin. this is internal 120k ? pull down.
w83194br-903/W83194BG-903 - 4 - cpu, agp, and pci clock outputs, continued. pin pin name type description 9 pci_f2 out 3.3v pci free running clock output. pci5 out 3.3v pci clock output. select by pin 12 mode & power up initial =0. 19 pci_stop#* in tp120k a ctive low, stop all pci clock ou tput besides the free running clocks. select by pin 12 mode & power up initial =1. pci6 out 3.3v pci clock output. select by pin 12 mode & power up initial =0. 20 cpu_stop#* in tp120k active low, stop all cpu clock outputs. select by pin 12 mode & power up initial =1. 13,14,15,16 pci [1:4] out low skew (< 250ps) pci clock outputs. 5.3 fixed frequency outputs pin pin name type description ref0 out 14.318mhz output. 1 fs1* in tp120k latched input for fs1 at initial power up for h/w selecting the output frequency. this is internal 120k pull up. ref1 out 14.318mhz output. 2 fs0 & in td120k latched input for fs0 at initial power up for h/w selecting the output frequency. this is internal 120k pull down. 48mhz out 48mhz clock output for usb. 21 fs3 & in td120k latched input for fs3 at initial power up for h/w selecting the output frequency. this is internal 120k pull down. 24_48mhz out 24mhz or 48mhz(default) clock output, in power on reset period, it is a hardware-latc hed pin, and it can be r/w by i2c control after power on reset period. select by register 5 bit 7. 22 sel24_48# & in td120k latched input for 24mhz or 48mhz select pin. this is internal 120k pull down default 48mhz. in power on reset period, it is a hardware-latc hed pin, and it can be r/w by i2c control after power on reset period. select by register 5 bit 7. 36,35 25mhz_[0:1] out 25mhz 2.5v push pull clock output. 5.4 i 2 c control interface pin pin name type description 32 sdata* i/od serial data of i 2 c 2-wire control interface with internal 120k pull-up resistor. 31 sclk* in tp120k serial clock of i 2 c 2-wire control interface with internal 120k pull-up resistor.
w83194br-903/W83194BG-903 publication release date: may 2006 - 5 - revision 1.0 5.5 power management pins pin pin name type description vtt_pwrgd in power good input signal is power on trapping with high active. this 3.3v input is level sensitive strobe used to determine fs [4:0]. this pin is high active. 33 pd#* in tp120k power down function. this is power down pin, low active (pd#). internal 120k pull up 46 iref out deciding the reference cu rrent for the cpuclk pairs. the pin was connected to the precision resistor tied to ground to decide the appropriate current. 30 reset# od system reset signal when the watchdog is time out. this pin will generate 250ms low phase when the watchdog timer is timeout. 5.6 iref selects function board target trace/term z reference r, iref = add/(3*rr) output current voh @ z 50 ? rr =221 1% iref = 5.00ma ioh=4*iref 1.0v @ 50 50 ? rr =475 1% iref = 2.32ma ioh=6*iref 0.7v @ 50 5.7 power pins pin pin name type description 3 vddref pwr 3.3v power supply for ref. 10,17 vddpci pwr 3.3v power supply for pci. 27 vddagp pwr 3.3v power supply for agp. 40 vddcpu pwr 3.3v power supply for cpu. 24 vdd48 pwr 3.3 power supply for 48mhz. 34 vdd2.5 pwr 2.5v power supply for 25mhz. 48 vdda pwr 3.3v power for analog power 6,11,18,23,28, 37,43,47 gnd pwr ground pin
w83194br-903/W83194BG-903 - 6 - 6. frequency selection by hardware or software this frequency table is used at power on latched fs [4:0] value or software programming at ssel [4:0] (register 0 bit 7 ~ 3). fs4 fs3 fs2 fs1 fs0 cpu (mhz) 3v66 (mhz) pci (mhz) 0 0 0 0 0 100.00 66.67 33.33 0 0 0 0 1 200.01 66.67 33.33 0 0 0 1 0 133.34 66.67 33.33 0 0 1 0 0 200.01 66.67 33.33 0 0 1 0 1 400.01 66.67 33.33 0 0 1 1 0 266.68 66.67 33.33 0 1 0 0 0 101.1 67.34 33.67 0 1 0 0 1 202.2 67.34 33.67 0 1 0 1 0 134.68 67.34 33.67 1 0 0 0 0 100.00 66.67 33.33 1 0 0 0 1 200.01 66.67 33.33 1 0 0 1 0 133.34 66.67 33.33 1 0 1 0 0 200.01 66.67 33.33 1 0 1 0 1 400.01 66.67 33.33 1 0 1 1 0 266.68 66.67 33.33 1 1 0 0 0 105.04 70.02 35.01 1 1 0 0 1 210.07 70.02 35.01 1 1 0 1 0 140.05 70.02 35.01
w83194br-903/W83194BG-903 publication release date: may 2006 - 7 - revision 1.0 7. i 2 c control and status registers 7.1 register 0: frequency select (default = 10h) bit name pwd description 7 ssel [4] 0 6 ssel [3] 0 5 ssel [2] 0 4 ssel [1] 1 3 ssel [0] 0 frequency selection by software via i 2 c 2 en_ssel 0 enable software program fs [4:0]. 0 = select frequency by hardware. 1= select frequency by software i 2 c - bit 7~ 3. 1 en_spsp 0 enable spread spectrum in the frequency table. 0 = normal 1 = spread spectrum enabled 0 en_safe_freq 0 enable reload safe frequency when the watchdog is timeout. 0 = reload the fs [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at register 5 bit 4~0. 7.2 register 1: cpu clock (1 = enable, 0 = stopped) (default: e2h) bit pin no pwd description 7 45,44 1 cput_ipt/cpuc_ipt output control. 6 42,41 1 cput1 / c1 output control. 5 39,38 1 cput0 / c0 output control. 4 - x power on latched value of fs4 pin. default: 0 (read only) 3 - x power on latched value of fs3 pin. default: 0 (read only) 2 - x power on latched value of fs2 pin. default: 0 (read only) 1 - x power on latched value of fs1 pin. default: 1 (read only) 0 - x power on latched value of fs0 pin. default: 0 (read only)
w83194br-903/W83194BG-903 - 8 - 7.3 register 2: pci clock (1 = enable, 0 = stopped) (default: ffh) bit pin no pwd description 7 9 1 pci_f2 output control. 6 8 1 pci_f1 output control. 5 7 1 pci_f0 output control. 4 reserve 1 reserved 3 20 1 pci6 output control. 2 19 1 pci5 output control. 1 16 1 pci4 output control. 0 15 1 pci3 output control. 7.4 register 3: pci, agp clock (1 = enable, 0 = stopped) (default: ffh) bit pin no pwd description 7 14 1 pci2 output control. 6 13 1 pci1 output control. 5 12 1 pci0 output control. 4 - 1 don?t modify it 3 25 1 agp_2 output control. 2 26 1 agp_1 output control. 1 29 1 agp_0 output control. 0 - 1 don?t modify it 7.5 register 4: 24_48mhz, 48mhz, ref, 25mhz control (1 = enable, 0 = stopped) (default: bfh) bit pin no pwd description 7 22 1 24_48mhz output control. 6 - 0 reserved 5 21 1 48mhz output control. 4 - 1 reserved 3 2 1 ref1 output control. 2 1 1 ref0 output control. 1 35 1 25mhz_1 output control. 0 36 1 25mhz_0 output control.
w83194br-903/W83194BG-903 publication release date: may 2006 - 9 - revision 1.0 7.6 register 5: watchdog control (default: 02h) bit name pwd description 7 sel24_48 x 24 / 48 mhz output sele ction, 1: 24 mhz.0: 48 mhz. (default) default value follow hardware trapping data on sel24_48# pin. 6 en_wd 0 program this bit => 1: enable watchdog timer feature. 0: disable watchdog timer feature. read-back this bit => during timer count down the bit read back to 1. if count to zero, this bit read back to 0. 5 wd_timeout 0 read back only, timeout flag, this bit is read only. 1: watchdog has ever started and counts to zero. 0: watchdog is restarted and counting. 4 saf_freq [4] 0 3 saf_freq [3] 0 2 saf_freq [2] 0 1 saf_freq [1] 1 0 saf_freq [0] 0 these bits will be reloaded in reg-0 to select frequency table. as the watchdog is timeout and en_safe_freq=1. 7.7 register 6: reserved (default: 50h) (read only) bit name pwd description 7 reserved 0 6 reserved 1 reserved 5 reserved 0 4 reserved 1 reserved 3 reserved 0 2 reserved 0 reserved 1 reserved 0 0 reserved 0 reserved
w83194br-903/W83194BG-903 - 10 - 7.8 register 7: winbond chip id (default: 70h) (read only) bit name pwd description 7 chpi_id [7] 0 winbond chip id. w83194br-903 (sa5870) 6 chpi_id [6] 1 winbond chip id. 5 chpi_id [5] 1 winbond chip id. 4 chpi_id [4] 1 winbond chip id. 3 chpi_id [3] 0 winbond chip id. 2 chpi_id [2] 0 winbond chip id. 1 chpi_id [1] 0 winbond chip id. 0 chpi_id [0] 0 winbond chip id. 7.9 register 8: m/n program (default: 90h) bit name pwd description 7 n_div [8] 1 programmable n divisor value. bit 7 ~0 are defined in the register 9. 6 m_div [6] 0 5 m_div [5] 0 4 m_div [4] 1 3 m_div [3] 0 2 m_div [2] 0 1 m_div [1] 0 0 m_div [0] 0 programmable m divisor value. 7.10 register 9: m/n program (default: 7ah) bit name pwd description 7 n_div [7] 0 6 n_div [6] 1 5 n_div [5] 1 4 n_div [4] 1 3 n_div [3] 1 2 n_div [2] 0 1 n_div [1] 1 0 n_div [0] 0 programmable n divisor value bit 7 ~0. the bit 8 is defined in register 8.
w83194br-903/W83194BG-903 publication release date: may 2006 - 11 - revision 1.0 7.11 register 10: m/n program (default: bbh) bit name pwd description 7 n_div [9] 1 programmable n divisor bit 9. 6 n3<6> 0 5 n3<5> 1 4 n3<4> 1 3 n3<3> 1 2 n3<2> 0 1 n3<1> 1 0 n3<0> 1 programmable n3 divisor bit 6 ~0 for programmable 25m clocks. m3=10000 (fix) frequency range: 21.7m ~ 28.8m resolution: 56k 7.12 register 11: spread spectrum programming (default: 0bh) bit name pwd description 7 sp_up [3] 0 6 sp_up [2] 0 5 sp_up [1] 0 4 sp_up [0] 0 spread spectrum up counter bit 3 ~ bit 0. 3 sp_down [3] 1 2 sp_down [2] 0 1 sp_down [1] 1 0 sp_down [0] 1 spread spectrum down counter bit 3 ~ bit 0 2?s complement representation. ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 7.13 register 12: divisor and step-less enable control (default: fbh) bit name pwd description 7 reserved 1 reserved 6 ds9 1 5 ds5 1 define the agp divider ratio table-2 integrate the all divider configuration 4 reserved 1 3 reserved 1 reserved 2 ds2 0 1 ds1 1 0 ds0 1 define the cpu divider ratio refer to table-2
w83194br-903/W83194BG-903 - 12 - table-2 cpu, agp, pci di vider ratio selection table agp cpu bit5 bit1, 0 lsb msb 0 1 00 01 10 11 0 div6 div7 div2 div3 div4 div6 bit2/ bit9 1 div10 div12 div8 div8 div8 div8 7.14 register 13: divisor and step-less enable control (default: 0fh) bit name pwd description 7 en_mn_prog 0 0: output frequency depend on frequency table 1: program all clock frequency by changing m/n value the equation is vco =14.318mhz*(n+4)/ m . once the watchdog timer timeout, the bit will be clear. then the frequency will be decided by hardware default fs<4:0> or desired frequency select saf_freq [4:0] depend on en_safe_freq (reg0 - bit 0). 6 reserved 0 reserved 5 reserved 0 reserved 4 reserved 0 reserved 3 ival<3> 1 2 ival<2> 1 1 ival<1> 1 0 ival<0> 1 charge pump current selection 7.15 register 14: control (default: 0ah) bit name pwd description 7 cput_dri 0 cput output state in during power down or stop mode assertion. 1: driven (2*iref), 0: tristate (floating) cpuc always tri-state (floati ng) in power down assertion. 6 reserved 0 reserved 5 spcnt [5] 0 4 spcnt [4] 0 3 spcnt [3] 1 2 spcnt [2] 0 1 spcnt [1] 1 0 spcnt [0] 0 spread spectrum programmable time, the resolution is 280ns. default period is 11.8us
w83194br-903/W83194BG-903 publication release date: may 2006 - 13 - revision 1.0 7.16 register 15: sst & skew control (default: 2ch) bit name pwd description 7 inv_cpu 0 invert the cpu phase, 0: default, 1: inverse 6 reserved 0 reserved 5 spsp_type 1 spread spectrum implementation method 1: pendulum type, 0: original 4 spsp1 0 3 spsp0 1 spread spectrum type select. 00: down 1% 01: down 0.5% 10: center +/- 0.5% 11: center +/- 0.25% 2 askew [2] 1 1 askew [1] 0 0 askew [0] 0 cpu to agp skew control, skew resolution is 340ps expand the skew direction is same as cpu_agp_skew [2:0] setting 7.17 register 16: skew control (default: 24h) bit name pwd description 7 inv_agp 0 invert the agp phase, 0: default, 1: inverse 6 inv_pci 0 invert the pci phase, 0: default, 1: inverse 5 reserved 1 4 reserved 0 3 reserved 0 reserved 2 pskew [2] 1 1 pskew [1] 0 0 pskew [0] 0 cpu to pci skew control, skew resolution is 340ps expand the skew direction is same as cpu_pci_skew [2:0] setting 7.18 register 17: slew rate control (default: 00h) bit name pwd description 7 pci_f2_s2 0 6 pci_f2_s1 0 pci_f2 slew rate control 11: strong, 00: weak, 10/01: normal 5 pci_f0_s2 0 4 pci_f0_s1 0 pci_f1 / pci_f0 slew rate control 11: strong, 00: weak, 10/01: normal 3 agp_2_s2 0 2 agp_2_s1 0 agp2 slew rate control 11: strong, 00: weak, 10/01: normal 1 agp_10_s2 0 0 agp_10_s1 0 agp_1 /agp_0 slew rate control 11: strong, 00: weak, 10/01: normal
w83194br-903/W83194BG-903 - 14 - 7.19 register 18: slew rate control (default: 00h) bit name pwd description 7 pci_65_s2 0 6 pci_65_s1 0 pci6, 5 slew rate control 11: strong, 00: weak, 10/01: normal 5 pci_42_s2 0 4 pci_42_s1 0 pci4, 3,2 slew rate control 11: strong, 00: weak, 10/01: normal 3 pci_10_s2 0 2 pci_10_s1 0 pci1, 0 slew rate control 11: strong, 00: weak, 10/01: normal 1 ref_s2 0 0 ref_s1 0 ref0, 1 slew rate control 11: strong, 00: weak, 10/01: normal 7.20 register 19: slew rate control (default: d2h) bit name pwd description 7 cpu1stop_en 1 stop cpu1 clocks, 1: enable stop feature, 0: disable 6 cpu0stop_en 1 stop cpu0 clocks, 1: enable stop feature, 0: disable 5 25mhz_s2 0 4 25mhz_s1 1 25mhz_1,0 slew rate control 11: strong, 00: weak, 10/01: normal 3 inv_48mhz 0 invert the 48mhz phase, 0: in phase with 24_48mhz 1: 180 degrees out of phase 2 48mhz_s2 0 1 48mhz_s1 1 48mhz/24_48mhz slew rate control 11: strong, 00: weak, 10/01: normal 0 mode x pin 19,20 mode selection 1: pci_stop, cpu_stop control pin 0: pci5, pci6 (default) default value follow hardware trapping data on mode & /pci0 pin. 7.21 register 20: watch dog timer (default: 08h) bit name pwd description 7 srcf1 0 src frequency select, 00/01: 25mhz(default), 10: 100mhz, 11: 200mhz 6 wd_time [6] 0 5 wd_time [5] 0 4 wd_time [4] 0 3 wd_time [3] 1 2 wd_time [2] 0 1 wd_time [1] 0 0 wd_time [0] 0 setting the down count depth. one bit resolution represents 250ms. default time depth is 8*250ms = 2.0 second. if the watchdog timer is counting, this register will re turn present down count value
w83194br-903/W83194BG-903 publication release date: may 2006 - 15 - revision 1.0 7.22 register21: fix mode control (default: 00h) bit name pwd description 7 tri-state 0 tri-state all output if set 1 6 reserved 0 don?t modify it 5 reserved 0 don?t modify it 4 fix_sel 0 agp output frequency select mode 0: output frequency according to frequency selection table 1: output frequency according to fix frequency reg21 bit 0~2 3 srcf0 0 src frequency select 2 asel_2 0 1 asel_1 0 0 asel_0 0 asynchronous agp/pci frequency table selection asel_<2:0> 001: 66 / 33m 010: 75.43 / 37.7m 011: 88 / 44m 100: 88 / 44m 101: 66 / 33m 110: 75.43 / 33m 111: 88 / 33m 000: clock from pll1
w83194br-903/W83194BG-903 - 16 - 8. access interface the w83194br-903 provides i 2 c serial bus for microprocessor to r ead/write internal registers. in the w83194br-903 is provided block read/block wri te and byte-data read/write protocol. the i 2 c address is defined at 0xd2. block read and block write protocol 8.1 block write protocol 8.2 block read protocol ## in block mode, the command code must filled 8?h00 8.3 byte write protocol 8.4 byte read protocol
w83194br-903/W83194BG-903 publication release date: may 2006 - 17 - revision 1.0 9. specifications 9.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. subjection to maximum conditions for extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd). parameter rating absolute 3.3v core supply voltage -0.5v to +4.6v absolute 3.3v i/o supple voltage - 0.5 v to + 4.6 v operating 3.3v core supply voltage 3.135v to 3.465v operating 3.3v i/o supple voltage 3.135v to 3.465v storage temperature - 65 c to + 150 c ambient temperature - 55 c to + 125 c operating temperature 0 c to + 70 c input esd protection (human body model) 2000v 9.2 general operating characteristics vdda=vddagp=vddcpu=vddref=vddpci= 3.3v 5 %, ta = 0 c to +70 c, cl=10pf parameter symbol min max units test conditions input low voltage v il 0.8 v dc input high voltage v ih 2.0 v dc output low voltage v ol 0.4 v dc all outputs using 3.3v power output high voltage v oh 2.4 v dc all outputs using 3.3v power operating supply current i dd 350 ma cpu = 100 to 400 mhz pci = 33.3 mhz with load input pin capacitance cin 5 pf output pin capacitance cout 6 pf input pin inductance lin 7 nh
w83194br-903/W83194BG-903 - 18 - 9.3 skew group timing clock vdda=vddagp=vddcpu=vddref=vddpci = 3.3v 5 %, ta = 0 c to +70 c, cl=10pf parameter min typ max units test conditions agp to pci skew 1.5 2.6 3.5 ns measured at 1.5v cpu to cpu skew 200 ps crossing point agp to agp skew 250 ps measured at 1.5v pci to pci skew 500 ps measured at 1.5v 48mhz to 48mhz skew 1000 ps measured at 1.5v ref to ref skew 500 ps measured at 1.5v 9.4 cpu 0.7v electrical characteristics vdda=vddcpu= 3.3v 5 %, ta = 0 c to +70 c, test load rs=33, rp=49.9 cl=10pf, vr=475, iref=2.32ma, ioh=6*iref parameter min max units test conditions rise time 175 700 ps 100 to 200 mhz fall time 175 700 ps 100 to 200mhz absolute crossing point voltages 250 550 mv 100 to 200mhz cycle to cycle jitter 150 ps 100 to 200mhz duty cycle 45 55 % 100 to 200mhz 9.5 agp electrical characteristics vddagp= 3.3v 5 %, ta = 0 c to +70 c, test load, cl=10pf, parameter min max units test conditions rise time 500 2000 ps measure from 0.4v to 2.4v fall time 500 2000 ps measure from 2.4v to 0.4v cycle to cycle jitter 250 ps measure 1.5v point duty cycle 45 55 % pull-up current min -33 ma vout=1.0v pull-up current max -33 ma vout=3.135v pull-down current min 30 ma vout=1.95v pull-down current max 38 ma vout=0.4v
w83194br-903/W83194BG-903 publication release date: may 2006 - 19 - revision 1.0 9.6 pci electrical characteristics vddpci= 3.3v 5 %, ta = 0 c to +70 c, test load, cl=10pf, parameter min max units test conditions rise time 500 2000 ps measure from 0.4v to 2.4v fall time 500 2000 ps measure from 2.4v to 0.4v cycle to cycle jitter 250 ps measure 1.5v point duty cycle 45 55 % pull-up current min -33 ma vout=1.0v pull-up current max -33 ma vout=3.135v pull-down current min 30 ma vout=1.95v pull-down current max 38 ma vout=0.4v 9.7 24m, 48m electrical characteristics vdd48= 3.3v 5 %, ta = 0 c to +70 c, test load, cl=10pf, parameter min max units test conditions rise time 500 2000 ps measure from 0.4v to 2.4v fall time 500 2000 ps measure from 2.4v to 0.4v long term jitter 500 ps measure 1.5v point duty cycle 45 55 % pull-up current min -33 ma vout=1.0v pull-up current max -33 ma vout=3.135v pull-down current min 30 ma vout=1.95v pull-down current max 38 ma vout=0.4v 9.8 ref electrical characteristics vddref= 3.3v 5 %, ta = 0 c to +70 c, test load, cl=10pf, parameter min max units test conditions rise time 1000 4000 ps measure from 0.4v to 2.4v fall time 1000 4000 ps measure from 2.4v to 0.4v cycle to cycle jitter 1000 ps measure 1.5v point duty cycle 45 55 % pull-up current min -33 ma vout=1.0v pull-up current max -33 ma vout=3.135v pull-down current min 30 ma vout=1.95v pull-down current max 38 ma vout=0.4v
w83194br-903/W83194BG-903 - 20 - 10. ordering information part number package type production flow w83194br-903 48 pin ssop commercial, 0 c to +70 c W83194BG-903 48 pin ssop (lead free part) commercial, 0 c to +70 c 11. how to read the top marking 1st line: winbond logo and the type number: normal:w83194br-903, lead free part:W83194BG-903 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 342 g a a sa 320 : packages made in '2003, week 42 g : assembly house id; o means ose, g means gr a : internal use code a : ic revision sa : internal use code all the trademarks of products and companies menti oned in this datasheet belong to their respective owners. w83194br-903 28051234 342 g a a sa W83194BG-903 28051234 342 g a a sa
w83194br-903/W83194BG-903 publication release date: may 2006 - 21 - revision 1.0 12. package drawing and dimensions
w83194br-903/W83194BG-903 - 22 - important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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