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never stop thinking. data sheet, ds1, jan. 2003 wired communications isac-sx te isdn subscriber access controller for terminals psb 3186, v 1.4
edition 2003-01-30 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? is a registered trademark of microsoft corporation. linux ? is a registered trademark of linus torvalds. the information in this document is subject to change without notice.
data sheet revision history: 2003-01-30 ds1 previous version: data sheet, ds1, v1.3, 2000-08-23 page subjects (major changes since last revision) chapter 1 comparison isac-s te/isac-sx te chapter 3.3.6.2 s- transceiver synchronization new chapter 3.3.10 test functions extended chapter 3.7.1.1 cda handler description extended chapter 3.7.5.1 tic bus access control: note added chapter 5.6 iom-2 interface timing: explanation added chapter 5.7.2 parallel microcontroller interface timing: explanation added chapter 5.9 s-transceiver chapter 5.10 recommended transformer specification: changed chapter 5.11 line overload protection added chapter 5.12 emc/esd added
isac-sx te psb 3186 table of contents page data sheet 4 2003-01-30 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 description of functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 microcontroller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.1.1 programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.2 parallel microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.3 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.4 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.5 timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.6 activation indication via pin acl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 s/t-interface coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.2 s/t-interface multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.3 data transfer and delay between iom-2 and s/t . . . . . . . . . . . . . . . . 44 3.3.4 transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.5 receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.6 s/t interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.6.1 external protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.6.2 s-transceiver synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.7 s/t interface delay compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.8 level detection power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.9 transceiver enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.10 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.4.1 description of the receive pll (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.2 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.3 oscillator clock output c768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5 control of layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.1 state machine te mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5.1.1 state transition diagram (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5.1.2 states (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.1.3 c/i codes (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5.1.4 infos on s/t (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.5.2 command/ indicate channel codes (c/i0) - overview . . . . . . . . . . . . . 66 3.6 control procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.6.1 example of activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
isac-sx te psb 3186 table of contents page data sheet 5 2003-01-30 3.7 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.7.1 iom-2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.7.1.1 controller data access (cda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.7.2 serial data strobe signal and strobed data clock . . . . . . . . . . . . . . . 82 3.7.2.1 serial data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.7.2.2 strobed iom-2 bit clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.7.3 iom-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.7.3.1 handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.7.3.2 error treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.7.3.3 monitor channel programming as a master device . . . . . . . . . . . 91 3.7.3.4 monitor channel programming as a slave device . . . . . . . . . . . . 91 3.7.3.5 monitor time-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.7.3.6 monitor interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.7.4 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.7.5 d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.7.5.1 tic bus d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.7.5.2 s-bus priority mechanism for d-channel . . . . . . . . . . . . . . . . . . . . . 97 3.7.6 activation/deactivation of iom-2 interface . . . . . . . . . . . . . . . . . . . . . 100 3.8 hdlc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.8.1 message transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.8.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.8.2.1 structure and control of the receive fifo . . . . . . . . . . . . . . . . . . . 104 3.8.2.2 receive frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.8.3 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.8.3.1 structure and control of the transmit fifo . . . . . . . . . . . . . . . . . . 112 3.8.3.2 transmit frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.8.4 access to iom-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.8.5 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.8.6 hdlc controller interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.9 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.1 d-channel hdlc control and c/i registers . . . . . . . . . . . . . . . . . . . . . . 128 4.1.1 rfifod - receive fifo d-channel . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.2 xfifod - transmit fifo d-channel . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.3 istad - interrupt status register d-channel . . . . . . . . . . . . . . . . . . . 128 4.1.4 maskd - mask register d-channel . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.1.5 stard - status register d-channel . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.1.6 cmdrd - command register d-channel . . . . . . . . . . . . . . . . . . . . . . 131 4.1.7 moded - mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.8 exmd1- extended mode register d-channel 1 . . . . . . . . . . . . . . . . . 134 4.1.9 timr1 - timer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.1.10 sap1 - sapi1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
isac-sx te psb 3186 table of contents page data sheet 6 2003-01-30 4.1.11 sap2 - sapi2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.1.12 rbcld - receive frame byte count low d-channel . . . . . . . . . . . . 136 4.1.13 rbchd - receive frame byte count high d-channel . . . . . . . . . . . 137 4.1.14 tei1 - tei1 register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.1.15 tei2 - tei2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.1.16 rstad - receive status register d-channel . . . . . . . . . . . . . . . . . . 138 4.1.17 tmd -test mode register d-channel . . . . . . . . . . . . . . . . . . . . . . . . 140 4.1.18 cir0 - command/indication receive 0 . . . . . . . . . . . . . . . . . . . . . . . 140 4.1.19 cix0 - command/indication transmit 0 . . . . . . . . . . . . . . . . . . . . . . . 141 4.1.20 cir1 - command/indication receive 1 . . . . . . . . . . . . . . . . . . . . . . . 142 4.1.21 cix1 - command/indication transmit 1 . . . . . . . . . . . . . . . . . . . . . . . 142 4.2 transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.2.1 tr_conf0 - transceiver configuration register 0 . . . . . . . . . . . . . . 144 4.2.2 tr_conf1 - transceiver configuration register 1 . . . . . . . . . . . . . . 145 4.2.3 tr_conf2 - transmitter configuration register 2 . . . . . . . . . . . . . . 145 4.2.4 tr_sta - transceiver status register . . . . . . . . . . . . . . . . . . . . . . . 146 4.2.5 sqrr1 - s/q-channel receive register 1 . . . . . . . . . . . . . . . . . . . . 147 4.2.6 sqxr1- s/q-channel tx register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.2.7 sqrr2 - s/q-channel receive register 2 . . . . . . . . . . . . . . . . . . . . . 148 4.2.8 sqrr3 - s/q-channel receive register 3 . . . . . . . . . . . . . . . . . . . . 148 4.2.9 istatr - interrupt status register transceiver . . . . . . . . . . . . . . . . . 148 4.2.10 masktr - mask transceiver interrupt . . . . . . . . . . . . . . . . . . . . . . . . 149 4.2.11 acfg2 - auxiliary configuration register . . . . . . . . . . . . . . . . . . . . . 149 4.3 iom-2 and monitor handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.3.1 cdaxy - controller data access register xy . . . . . . . . . . . . . . . . . . . 151 4.3.2 xxx_tsdpxy - time slot and data port selection for chxy . . . . . . . 151 4.3.3 cdax_cr - control register controller data access ch1x . . . . . . . 152 4.3.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) . . . 153 4.3.4.1 trc_cr - control register transceiver c/i0 (iom_cr.ci_cs=1) 154 4.3.5 dci_cr - control register for d and ci1 handler (iom_cr.ci_cs=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.3.6 mon_cr - control register monitor data . . . . . . . . . . . . . . . . . . . . . 156 4.3.7 sds_cr - control register serial data strobe . . . . . . . . . . . . . . . . . 156 4.3.8 iom_cr - control register iom data . . . . . . . . . . . . . . . . . . . . . . . . 157 4.3.9 sti - synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.3.10 asti - acknowledge synchronous transfer interrupt . . . . . . . . . . . . 159 4.3.11 msti - mask synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . 160 4.3.12 sds_conf - configuration register for serial data strobe . . . . . . . 160 4.3.13 mcda - monitoring cda bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.3.14 mor - monitor receive channel . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.3.15 mox - monitor transmit channel . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.3.16 mosr - monitor interrupt status register . . . . . . . . . . . . . . . . . . . 162
isac-sx te psb 3186 table of contents page data sheet 7 2003-01-30 4.3.17 mocr - monitor control register . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.3.18 msta - monitor status register . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.3.19 mconf - monitor configuration register . . . . . . . . . . . . . . . . . . . 164 4.4 interrupt and general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.4.1 ista - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.4.2 mask - mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.4.3 auxi - auxiliary interrupt status register . . . . . . . . . . . . . . . . . . . . . . 166 4.4.4 auxm - auxiliary mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.4.5 mode1 - mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.4.6 mode2 - mode2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.4.7 id - identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.4.8 sres - software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 4.4.9 timr2 - timer 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.4 oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.6 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.7 microcontroller interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.7.1 serial control interface (sci) timing . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.7.2 parallel microcontroller interface timing . . . . . . . . . . . . . . . . . . . . . . . 180 5.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.9 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.10 recommended transformer specification . . . . . . . . . . . . . . . . . . . . . . . 186 5.11 line overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.12 emc / esd aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
isac-sx te psb 3186 list of figures page data sheet 8 2003-01-30 figure 1 logic symbol of the isac-sx te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2 applications of the isac-sx te. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3 pin configuration of the isac-sx te . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4 functional block diagram of the isac-sx te . . . . . . . . . . . . . . . . . . . 26 figure 5 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7 direct/indirect register address mode . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8 interrupt status and mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10 timer interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11 timer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12 timer 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13 acl indication of activated layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14 acl configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15 wiring configurations in user premises . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17 frame structure at reference points s and t (itu i.430). . . . . . . . . . 41 figure 18 data delay between iom-2 and s/t interface . . . . . . . . . . . . . . . . . . . 44 figure 19 data delay between iom-2 and s/t interface with s/g bit evaluation 45 figure 20 equivalent internal circuit of the transmitter stage . . . . . . . . . . . . . . 46 figure 21 equivalent internal circuit of the receiver stage . . . . . . . . . . . . . . . . 46 figure 22 connection of line transformers and power supply to the isac-sx te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23 external circuitry for transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24 external circuitry for symmetrical receivers. . . . . . . . . . . . . . . . . . . . 49 figure 25 external circuitry for symmetrical receivers. . . . . . . . . . . . . . . . . . . . 50 figure 26 disabling of s/t transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27 external loop at the s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 28 clock system of the isac-sx te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 29 phase relationships of isac-sx te clock signals . . . . . . . . . . . . . . 55 figure 30 buffered oscillator clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 31 layer-1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 32 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 33 state transition diagram (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 34 state transition diagram of unconditional transitions (te) . . . . . . . . 61 figure 35 example of activation/deactivation initiated by the terminal . . . . . . . 67 figure 36 iom -2 frame structure in terminal mode . . . . . . . . . . . . . . . . . . . . 69 figure 37 architecture of the iom handler (example configuration). . . . . . . . . . 71 figure 38 data access via cdax1 and cdax2 register pairs . . . . . . . . . . . . . . 73 figure 39 examples for data access via cdaxy registers . . . . . . . . . . . . . . . . . 74 figure 40 data access when looping tsa from du to dd . . . . . . . . . . . . . . . . . 75 figure 41 data access when shifting tsa to tsb on du (dd) . . . . . . . . . . . . . . 76
isac-sx te psb 3186 list of figures page data sheet 9 2003-01-30 figure 42 example for monitoring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 43 interrupt structure of the synchronous data transfer . . . . . . . . . . . . . 79 figure 44 examples for the synchronous transfer interrupt control with one enabled stixy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 45 data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 46 strobed iom-2 bit clock. register sds_conf programmed to 01h . 84 figure 47 examples of monitor channel applications in iom -2 te mode . . . 85 figure 48 monitor channel protocol (iom-2) . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 49 monitor channel, transmission abort requested by the receiver. . . . 90 figure 50 monitor channel, transmission abort requested by the transmitter. . 90 figure 51 monitor channel, normal end of transmission . . . . . . . . . . . . . . . . . . 90 figure 52 monitor interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 53 cic interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 54 applications of tic bus in iom-2 bus configuration . . . . . . . . . . . . . . 96 figure 55 structure of last octet of ch2 on du . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 56 structure of last octet of ch2 on dd . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 57 d-channel access control on the s-interface . . . . . . . . . . . . . . . . . . . 99 figure 58 deactivation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 59 activation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 60 rfifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 61 data reception procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 62 reception sequence example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 63 receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 64 data transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 65 transmission sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 66 transmit data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 67 interrupt status registers of the hdlc controllers . . . . . . . . . . . . . . 118 figure 68 layer 2 test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 69 register mapping of the isac-sx te . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 70 oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 71 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 72 iom-2 timing (te mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 73 definition of clock period and width . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 74 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 75 microprocessor read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 76 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 77 multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 78 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 79 microprocessor read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 80 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 81 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 82 reset signal res . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
isac-sx te psb 3186 data sheet 10 2003-01-30 figure 83 maximum line input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 84 transformer circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
isac-sx te psb 3186 list of tables page data sheet 11 2003-01-30 table 1 comparison of the isac-sx te with the previous version isac-s te: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2 isac-sx te pin definitions and functions . . . . . . . . . . . . . . . . . . . . . 20 table 3 host interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4 header byte code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5 bus operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6 reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7 isac-sx te timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8 s/q-bit position identification and multiframe structure . . . . . . . . . . . 42 table 9 iom-2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 10 examples for synchronous transfer interrupts . . . . . . . . . . . . . . . . . . 79 table 11 cda register combinations with correct read/write access . . . . . . 81 table 12 transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 13 receive direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 14 hdlc controller address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 15 receive byte count with rbc11...0 in the rbchd/rbcld registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 16 receive information at rme interrupt . . . . . . . . . . . . . . . . . . . . . . . . 111 table 17 xpr interrupt (availability of xfifod) after xtf, xme commands . 113
isac-sx te psb 3186 overview data sheet 12 2003-01-30 1overview the isdn subscriber access controller for terminals isac-sx te integrates a d-channel hdlc controller and a four wire s/t interface used to link voice/data terminals to the isdn. it is based on the isac-s te psb 2186, and provides enhanced features and functionality. the system integration is simplified by several configurations of the parallel microcontroller interface selected via pin strapping. they include multiplexed and demultiplexed interface selection as well as the optional indirect register access mechanism which reduces the number of necessary registers in the address space to 2 locations. the isac-sx te also provides a serial control interface (sci). the fifo size of the cyclic d-channel buffer is 64 bytes per direction with programmable block size (threshold). the s-transceiver supports terminals mode (te), activation/ deactivation, timing recovery and d-channel access control and priority control. one led output which is capable to indicate the activation status of the s-interface automatically or can be programmed by the host. the isac-sx te is produced in advanced cmos technology.
isac-sx te psb 3186 overview data sheet 13 2003-01-30 table 1 comparison of the isac-sx te with the previous version isac-s te: isac-sx te psb 3186 isac-s te psb 2186 operating modes te te supply voltage 3.3 v 5% 5 v 5% technology cmos cmos package p-mqfp-64 / p-tqfp-64 p-mqfp-64 / p-lcc-44 / p-dip-40 transceiver transformer ratio for the transmitter receiver 1:1 1:1 2:1 2:1 test functions - dig. loop via layer 2 (tlp) - layer 1 disable (dis_tr) - analog loop (lp_a- bit exlp- bit, arl) - dig. loop via layer 2(tlp) - layer 1 disable (dis_tr) - analog loop (arl) microcontroller interface serial interface (sci) 8-bit parallel interface: motorola mux siemens/intel mux siemens/intel non-mux direct/ indirect addressing not provided 8-bit parallel interface: motorola mux siemens/intel mux siemens/intel non-mux command structure of the register access (sci) header/address/data address/data crystal 7.68 mhz 7.68 mhz buffered 7.68 mhz output provided not provided controller data access to iom-2 timeslots all timeslots; various possibilities of data access restricted access to b- and ic-channel data control and manipulation various possibilities of data control and data manipulation (enable/ disable, shifting, looping, switching) b- and ic-channel looping
isac-sx te psb 3186 overview data sheet 14 2003-01-30 iom-2 iom-2 interface double clock (dcl), bit clock pin (bcl), serial data strobe (sds) double clock (dcl), bit clock (bcl), serial data strobe (sds) monitor channel programming provided (mon0, 1, 2, ..., 7) provided (mon0 or 1) c/i channels ci0 (4 bit), ci1 (4/6 bit) ci0 (4 bit), ci1 (6 bit) layer 1 state machine with changes for correspondence with the actual itu specification layer 1 state machine in software not possible not possible hdlc support d- and b-channel timeslots; non-auto mode, transparent mode 1-3, extended transparent mode d-channel timeslot; auto mode, non-auto mode, transparent mode 1-3 d-channel fifo size 64 bytes cyclic buffer per direction with programmable fifo thresholds 2x32 bytes buffer per direction reset signals res input signal rsto output signal rst input/output signal reset sources res input watchdog c/i code change eaw pin software reset rst input watchdog c/i code change eaw pin interrupt output signals int low active (open drain) by default, reprogrammable to high active (push-pull) low active int pin sclk 1.536 mhz 512 khz isac-sx te psb 3186 isac-s te psb 2186
data sheet 15 2003-01-30 type package psb 3186 h p-mqfp-64-1 psb 3186 f p-tqfp-64-1 isdn subscriber access controller for terminals isac-sx te psb/psf 3186 v 1.4 p-mqfp-64-1, -2, -3, -8 p-mqfp-64-1 p-tqfp-64-1 1.1 features full duplex 2b + d s/t interface transceiver according to itu-t i.430 successor of isac-s te psb 2186 in 3.3 v technology 8-bit parallel microcontroller interface, motorola and siemens/intel bus type multiplexed or non-multiplexed, direct-/indirect register addressing serial control interface (sci) microcontroller access to all iom-2 timeslots various types of protocol support (non-auto mode, transparent mode, extended transparent mode) d-channel hdlc controller with 2 x 64 byte fifos iom-2 interface in te mode, single/double clocks one serial data strobe signal (sds) monitor channel handler (master/slave) iom-2 monitor and c/i-channel protocol to control peripheral devices conversion of the frame structure between the s/t-interface and iom-2 receive timing recovery d-channel access control activation and deactivation procedures with automatic activation from power down state access to s and q bits of s/t-interface adaptively switched receive thresholds two programmable timers watchdog timer software reset
isac-sx te psb 3186 overview data sheet 16 2003-01-30 one led pin automatically indicating layer 1 activated state test loops sophisticated power management for restricted power mode power supply 3.3 v 3.3 v output drivers, inputs are 5 v safe advanced cmos technology
isac-sx te psb 3186 overview data sheet 17 2003-01-30 1.2 logic symbol the logic symbol gives an overview of the isac-sx te functions. figure 1 logic symbol of the isac-sx te ad0...4 a0...7 cs rd / ds wr / r/w ale res int du ad5 / scl ad6 / sdr ad7 / sdx rsto xtal2 xtal1 7.68 mhz output 7.68 mhz 100ppm sr1 sr2 sx1 sx2 s interface amode c768 dd fsc dcl bcl vss vssa vdd vdda +3.3v 0v iom-2 interface host interface 3186_17 tp 0v acl led output address mode setting external awake eaw sds
isac-sx te psb 3186 overview data sheet 18 2003-01-30 1.3 typical applications the isac-sx te is designed for the user area of the isdn basic access, especially for subscriber terminal equipment with s interface. figure 2 illustrates the general application fields of the isac-sx te. figure 2 applications of the isac-sx te its05407 lt-s lt-s lt-t sn cp line card te(8) te(1) te(1) s cp sn = = switching network central processor pbx (nt2) nt1 t u = te(1) te(8) u s nt1 direct subscriber access (point-to-point, short and extended passive bus) -s te isac r s x te
isac-sx te psb 3186 pin configuration data sheet 19 2003-01-30 2 pin configuration figure 3 pin configuration of the isac-sx te p-mqfp-64-1 p-tqfp-64-1 sr2 isac-sx te psb 3186 12345 6 7 8 910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 32 28 29 30 25 26 27 22 23 24 19 20 21 17 18 50 49 53 52 51 56 55 54 59 58 57 62 61 60 64 63 sr1 vdda vssa sx2 sx1 n.c. ale wr / r/w rd / ds xtal2 xtal1 vss vdd a1 amode vss int n.c. cs tp res rsto vss bcl du dd fsc dcl vss vss vdd res_l eaw acl res_c res_c res_c res_c res_c 3186_22 vdd ad0 ad1 ad2 ad3 ad4 scl / ad5 sdr / ad6 sdx / ad7 a0 vdd vss a5 a4 a3 a2 res. c768 a7 a6 res_c res_c res_c sds
isac-sx te psb 3186 pin configuration data sheet 20 2003-01-30 table 2 isac-sx te pin definitions and functions pin no. mqfp-64 tqfp-64 symbol input (i) output (o) open drain (od) function host interface 19 20 21 22 23 24 25 26 a0 a1 a2 a3 a4 a5 a6 a7 i i i i i i i i non-multiplexed bus mode: address bus address bus transfers addresses from the microcontroller to the isac-sx te. for indirect address mode only a0 is valid (a1-a7 to be connected to vdd). multiplexed bus mode: not used in multiplexed bus mode. in this case a0-a7 should directly be connected to vdd. 9 10 11 12 13 ad0 ad1 ad2 ad3 ad4 i/o i/o i/o i/o i/o multiplexed bus mode: address/data bus transfers addresses from the microcontroller to the isac-sx te and data between the microcontroller and the isac-sx te. non-multiplexed bus mode: data bus transfers data between the microcontroller and the isac-sx te. 14 ad5 scl i/o i multiplexed bus mode: address/data bus address/data line ad5 if the parallel interface is selected. non-multiplexed bus mode: data bus data line d5 if the parallel interface is selected. sci - serial clock clock signal of the sci interface if a serial interface is selected.
isac-sx te psb 3186 pin configuration data sheet 21 2003-01-30 15 ad6 sdr i/o i multiplexed bus mode: address/data bus address/data line ad6 if the parallel interface is selected. non-multiplexed bus mode: data bus data line d6 if the parallel interface is selected. sci - serial data receive receive data line of the sci interface if a serial interface is selected. 16 ad7 sdx i/o od multiplexed bus mode: address/data bus address/data line ad7 if the parallel interface is selected. non-multiplexed bus mode: data bus data line d7 if the parallel interface is selected. sci - serial data transmit transmit data line of the sci interface if a serial interface is selected. 39 rd ds i i read indicates a read access to the registers (siemens/ intel bus mode). data strobe the rising edge marks the end of a valid read or write operation (motorola bus mode). 40 wr r/w i i write indicates a write access to the registers (siemens/ intel bus mode). read/write a high identifies a valid host access as a read operation and a low identifies a valid host access as a write operation (motorola bus mode). table 2 isac-sx te pin definitions and functions (cont?d) pin no. mqfp-64 tqfp-64 symbol input (i) output (o) open drain (od) function
isac-sx te psb 3186 pin configuration data sheet 22 2003-01-30 41 ale i address latch enable a high on this line indicates an address on the external address/data bus (multiplexed bus type only). ale also selects the microcontroller interface bus type (multiplexed or non multiplexed). 3cs i chip select a low level indicates a microcontroller access to the isac-sx te. 1int od (o) interrupt request int becomes active low (open drain) if the isac-sx te requests an interrupt. the polarity can be reprogrammed to high active with push-pull characteristic. 5res i reset a low on this input forces the isac-sx te into a reset state. 38 amode i address mode selects between direct (0) and indirect (1) register access mode. iom-2 interface 52 fsc o frame sync 8-khz frame synchronization signal. 53 dcl o data clock iom-2 interface data clock signal 1.536 mhz (double bit clock). 49 bcl o bit clock iom-2 interface bit clock signal 768 khz (single bit clock). 51 dd o (od) data downstream iom-2 data signal in downstream direction. table 2 isac-sx te pin definitions and functions (cont?d) pin no. mqfp-64 tqfp-64 symbol input (i) output (o) open drain (od) function
isac-sx te psb 3186 pin configuration data sheet 23 2003-01-30 50 du i data upstream iom-2 data signal in upstream direction. 29 sds o serial data strobe programmable strobe signal for time slot and/or d-channel indication on iom-2. miscellaneous 43 44 sx1 sx2 o o s-bus transmitter output (positive) s-bus transmitter output (negative) 47 48 sr1 sr2 i i s-bus receiver input s-bus receiver input 35 36 xtal1 xtal2 i o crystal 1 connection for a crystal or used as external clock input. 7.68 mhz clock or crystal required. crystal 2 connection for a crystal. not connected if an external clock is supplied to xtal1. 58 eaw i external awake if a falling edge on this input is detected, the isac- sx te generates an interrupt and, if enabled, a reset pulse. 59 acl o activation led this pin can either function as a programmable output or it can automatically indicate the activated state of the s interface by a logic ?0?. an led with pre-resistance may directly be connected to acl . 27 c768 o clock output a 7.68 mhz clock is output to support other devices. this clock is not synchronous to the s interface. 6rsto od reset output low active reset output, either from a watchdog timeout or programmed by the host. table 2 isac-sx te pin definitions and functions (cont?d) pin no. mqfp-64 tqfp-64 symbol input (i) output (o) open drain (od) function
isac-sx te psb 3186 pin configuration data sheet 24 2003-01-30 4tp i test pin must be connected to v ss . 2, 42 n.c. i not connected 28 res. reserved this pin is reserved and should be left not connected. 57 res_l i reserved, connect low this pin is reserved and must be connected to v ss . 30, 31, 32, 60, 61, 62, 63, 64 res_c i reserved, connect high or low these pins are reserved and must be connected either to v ss or v dd . power supply 8, 18, 33, 56 v dd ? digital power supply voltage (3.3 v 5%) 46 v dda ? analog power supply voltage (3.3 v 5%) 7, 17, 34, 37, 54, 55 v ss ? digital ground (0 v) 45 v ssa ? analog ground (0 v) table 2 isac-sx te pin definitions and functions (cont?d) pin no. mqfp-64 tqfp-64 symbol input (i) output (o) open drain (od) function
isac-sx te psb 3186 description of functional blocks data sheet 25 2003-01-30 3 description of functional blocks 3.1 general functions a nd device architecture figure 4 shows the architecture of the isac-sx te containing the following functions: s/t-interface transceiver supporting te mode different host interface modes: - parallel microcontroller interface (siemens/intel multiplexed, siemens/intel non multiplexed, motorola modes) - serial control interface (sci) optional indirect register address mode reduces number of registers to be accessed to two locations one d-channel hdlc-controller with 64 byte flfos per direction with programmable fifo block size (threshold) of 4, 8, 16 or 32 byte (receive) and 16 or 32 byte (transmit). iom-2 interface for terminal mode (te) one serial data strobe signals (sds) iom handler with controller data access regi sters (cda) allows flexible access to iom timeslots for reading/writing, looping and shifting data synchronous transfer interrupts (sti) allow controlled access to iom timeslots monitor channel handler on iom-2 for master mode, slave mode or data exchange c/i-channel handler and tic bus access controller d-channel access mechanism led connected to pin acl indicates s-interface activation status automatically or can be controlled by the host level detect circuit on the s interface reduces power consumption in power down mode two timers for periodic or single interrupts (periods between 1 ms and 14.336 s) clock and timing generation digital pll to synchronize the transceiver to the s/t interface buffered 7.68 mhz oscillator clock output allows connection of further devices and saves another crystal on the system board reset generation (watchdog timer)
isac-sx te psb 3186 description of functional blocks data sheet 26 2003-01-30 figure 4 functional block diagram of the isac-sx te reset interrupt -generation sci 8-bit parallel iom-2 interface iom-2 handler d-channel hdlc rx/tx fifos s transceiver c/i tic mon handler host interface osc dpll host peripheral devices 3186_18
isac-sx te psb 3186 description of functional blocks data sheet 27 2003-01-30 3.2 microcontroller interfaces the isac-sx te supports a serial or a parallel microcontroller interface. for applications where no controller is connected to t he isac-sx te microcontroller interface programming is done via the iom-2 monitor channel from a master device. in such applications the isac-sx te operates in the iom-2 slave mode (refer to the corresponding chapter of the iom-2 monitor handler). this mode is suitable for control functions (e.g. programming registers of the s/t transceiver), but the bandwidth is not sufficient for access to the hdlc controllers. the interface selections are all done by pinstrapping (see table 3 ). the selection pins are evaluated when the reset input res is active. for the pin levels stated in the tables the following is defined: ?high?, ?low?: dynamic pin; value must be ?high? or ?low? only during reset v dd , v ss : static pin; pin must statically be strapped to ?high? or ?low? level edge: dynamic pin; any transition (?high? to ?low?, ?low? to ?high?) has occured note: for a selected interface mode which doesn?t need all input selection and address pins the unused pins must be tied to v dd or v ss . the interfaces contain all circuitry necessary for the access to programmable registers, status registers and hdlc fifos. the mapping of all these registers can be found in chapter 4 . the microcontroller interface also provides an interrupt request at pin int which is low active by default but can be reprogrammed to high active, a reset input pin res and a reset output pin rsto . the interrupt request pin int becomes active if the isac-sx te requests an interrupt and this can occur at any time. table 3 host interface selection pins serial /parallel interface pins interface type/mode wr (r/w ) rd (ds ) cs ale v dd motorola ?high? ?high? parallel ?high? v ss siemens/intel non-mux edge siemens/intel mux v ss v ss serial ?high? v ss serial control interface(sci) no host interface v ss v ss iom-2 monitor channel (slave mode)
isac-sx te psb 3186 description of functional blocks data sheet 28 2003-01-30 3.2.1 serial control interface (sci) the serial control interface (sci) is compatible to the spi interface of motorola or siemens c510 family of microcontrollers. the sci consists of 4 lines: scl, sdx, sdr and cs . data is transferred via the lines sdr and sdx at the rate given by scl. the falling edge of cs indicates the beginning of a serial access to the registers. the isac-sx te latches incoming data at the rising edge of scl and shifts out at the falling edge of scl. each access must be terminated by a rising edge of cs . data is transferred in groups of 8 bits with the msb first. figure 5 shows the timing of a one byte read/write access via the serial control interface. figure 5 serial control interface timing 7 654321076543210 header address c s s cl s dr s dx 7 654321 c s s cl s dr s dx 76543210 data 0 data '0' write header address 7 654321 0 7 654321 0 '1' read 21150_19 write access read access
isac-sx te psb 3186 description of functional blocks data sheet 29 2003-01-30 3.2.1.1 programming sequences the basic structure of a read/write access to the isac-sx te registers via the serial control interface is shown in figure 6 . figure 6 serial control interface timing a new programming sequence starts with the transfer of a header byte. the header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the isac-sx te. the possible sequences for access to the complete address range 00 h -7f h are listed in table 4 and described after that. note: in order to access the address range 00 h -7f h bit 2 of the header byte must be set to ?0? (header bytes 40 h , 48 h , 43 h , 41 h , 49 h ), and for the addresses 80 h -ff h bit 2 must be set to ?1? (header bytes 44 h , 4c h , 47 h , 45 h , 4d h ). table 4 header byte code header byte sequence sequence type 40 h /44 h adr-data-adr-data alternating read/write (non-interleaved) 48 h /4c h alternating read/write (interleaved) 43 h /47 h adr-data-data-data read-only/write-only (constant address) 41 h /45 h read and following write-only (non-interleaved) 49 h /4d h read and following write-only (interleaved) sdr write sequence: read sequence: sdr 7 076 07 0 write data address read data 0 1 write read 7 076 07 0 header byte 2 byte 3 header byte 2 byte 3 sdx address
isac-sx te psb 3186 description of functional blocks data sheet 30 2003-01-30 header 40 h : non-interleaved a-d-a-d sequences the non-interleaved a-d-a-d sequence gives direct read/write access to the complete address range and can have any length. in this mode sdx and sdr can be connected together allowing data transmission on one line. example for a read/write access with header 40 h : header 48 h : interleaved a-d-a-d sequences the interleaved a-d-a-d sequence gives direct read/write access to the complete address range and can have any length. this mode allows a time optimized access to the registers by interleaving the data on sdx and sdr (sdr and sdx must not be connected together). example for a read/write access with header 48 h : header 43 h : read-/write- only a-d-d-d sequence (constant address) this mode can be used for a fast access to the hdlc fifo data. any address (rdadr, wradr) in the range 00 h -1f h and 6a h /7a h gives access to the current fifo location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. the sequence can have any length and is terminated by the rising edge of cs . example for a write access with header 43 h : example for a read access with header 43 h : sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rdata sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx sdr header rdadr sdx rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr)
isac-sx te psb 3186 description of functional blocks data sheet 31 2003-01-30 header 41 h : non-interleaved a-d-d-d sequence this sequence allows in front of the a-d-d-d write access a non-interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . example for a read/write access with header 41 h : header 49 h : interleaved a-d-d-d sequence this sequence allows in front of the a-d-d-d writ e access an interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of the cs line. example for a read/write access with header 49 h : 3.2.2 parallel microcontroller interface the 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. the parallel interface of the isac-sx te provides three types of p buses which are selected via pin ale. the bus operation modes with corresponding pins are listed in table 5 . the occurrence of an edge on ale, either positive or negative, at any time during the operation immediately selects the interface type (3). a return to one of the other interface types is possible only if a hardware reset is issued. sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata table 5 bus operation modes bus mode pin ale control pins (1) motorola v dd cs , r/w , ds (2) siemens/intel non-multiplexed v ss cs , wr , rd (3) siemens/intel multiplexed edge cs , wr , rd , ale
isac-sx te psb 3186 description of functional blocks data sheet 32 2003-01-30 note: if the multiplexed address/data bus type (3) is selected, the unused address pins a0-a7 must be tied to v dd . a read/write access to the isac-sx te registers can be done in multiplexed or non- multiplexed mode: in non-multiplexed mode the register address must be applied to the address bus (a0- a7) for the data access via the data bus (ad0-ad7). in multiplexed mode the address on the address/data bus (ad0-ad7) is latched in by ale before a data read/write access via the same bus is performed. the isac-sx te provides two different ways to address the register contents which is selected with the amod pin (?0? = direct mode, ?1? = indirect mode). figure 7 illustrates both register addressing modes. direct address mode (amod = ?0?): the register address to be read or written is directly set in the way described above. indirect address mode (amod = ?1?): only the lsb of the address is used to select either the address register (a0 = ?0?) or t he data register (a0 = ?1?). the microcontroller writes the register address to the address r egister before it reads/writes data from/to the corresponding data register. in indirect address mode the isac-sx te evaluates no address line except the least significant address bit. the remaining address lines must not be left open but have to be tied to logical ?1?. figure 7 direct/indirect register address mode 21150_11 00h 01h : 8eh 8fh data : address address a0-7 address 0h data 1h data ad0-7 indirect address mode mode2:amod=1 direct address mode mode2:amod=0 data ad0-7 address a0
isac-sx te psb 3186 description of functional blocks data sheet 33 2003-01-30 3.2.3 interrupt structure special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. since only one interrupt request pin (int ) is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the device. the structure of the interrupt status registers is shown in figure 8 . figure 8 interrupt status and mask registers all six interrupt bits in the ista register point at interrupt sources in the d-channel hdlc controller (icd), monitor- (mos) and c/i- (cic) handler, the transceiver (tran), the synchronous transfer (st) and th e auxiliary interrupts (auxi). all these interrupt sources are described in the corresponding chapters. after the device has requested an interrupt activating the interrupt pin (int ), the host must read first the device interrupt status register (ista) in the associated interrupt service routine. the interrupt pin of the device remains active until all interrupt sources are cleared by reading the corresponding interrupt register. therefore it is possible that the interrupt pin is still active when the interrupt service routine is finished. each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the mask register. for some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. this can be done by masking all interrupts at the end of the interrupt service routine (writing ff h into the mask register) and write back the old mask to the mask register. icd mos tran aux cic st icd mos tran aux cic st sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti ack10 ack11 ack20 ack21 asti msti ci1e cic1 cic0 cir0 cix1 xdu xmr xpr rfo rpf rme maskd xdu xmr xpr rfo rpf rme istad mie mre mab mda mer mdr sqw sqc ric ld masktr istatr sqw sqc ric ld mask ista 3186_16.vsd interrupt mocr mosr tin1 tin2 wov auxm auxi tin1 tin2 wov eaw eaw d-channel
isac-sx te psb 3186 description of functional blocks data sheet 34 2003-01-30 3.2.4 reset generation figure 9 shows the organization of the reset generation of the device. . figure 9 reset generation reset source selection the internal reset sources c/i code change, eaw and watchdog can be output at the low active reset pin rsto . the selection of these reset sources can be done with the rss2,1 bits in the mode1 register according table 6 . the setting rss2,1 = ?01? is reserved for further use. in this case no reset except software reset (sres.rsto) is output on rsto . the internal reset sources set the mode1 register to its reset value. table 6 reset source selection rss2 bit 1 rss1 bit 0 c/i code change eaw watchdog timer 0 0 -- -- -- 0 1 reserved 10xx-- 1 1 -- -- x c/i code change (exchange awake) eaw (subscriber awake) watchdog 1 125s t 250s 125s t 250s software reset register (sres) reset functional block d, c/i-channel (00 h -2f h ) transceiver (30 h -3f h ) iom-2 (40 h -5b h ) mon-channel (5c h -5f h ) reset mode1 register internal reset of all registers 1 rss1 rss2,1 '0' '1' '1x' '00' rss2,1 '01' ' 01 ' pin rsto pin res 3186_21 (reserved) 1 125s t 250s 125s t 250s general config (60 h -6f h )
isac-sx te psb 3186 description of functional blocks data sheet 35 2003-01-30 c/i code change (exchange awake) a change in the downstream c/i channel (c/i0) generates an external reset pulse of 125 s t 250 s. eaw (subscriber awake) a low level on the eaw input starts the oscillator from the power down state and generates a reset pulse of 125 s t 250 s. watchdog timer after the selection of the watchdog timer (rss = ?11?) an internal timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1- and wtc2 bits in the following sequence to reset and restart the watchdog timer: if not, the timer expires and a wov-interrupt (ista register) together with a reset pulse of 125 s is generated. deactivation of the watchdog timer is only possible with a hardware reset. external reset input at the res input an external reset can be applied forcing the device in the reset state. this external reset signal is additionally fed to the rsto output. the length of the reset signal is specified in chapter 5.8 . after an external reset from the res pin all registers of the device are set to its reset values (see register description in chapter 4 ). software reset register (sres) every main functional block of the device can be reset separately by software setting the corresponding bit in the sres register. a reset to external devices can also be controlled in this way. the reset state is activated by setting the corresponding bit to ?1? and onchip logic resets this bit again automatically after 4 bcl clock cycles. the address range of the registers which will be reset at each sres bit is listed in figure 9 . 3.2.5 timer modes the isac-sx te provides two timers which can be used for various purposes. each of them provides two modes ( table 7 ), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. wtc1 wtc2 1. 2. 1 0 0 1
isac-sx te psb 3186 description of functional blocks data sheet 36 2003-01-30 when the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ista.aux. the source of the interrupt can be read from auxi (tin1, tin2) and each of the interrupt sources can be masked in auxm. figure 10 timer interrupt status registers timer 1 the host controls the timer 1 by setting bit cmdrd.sti to start the timer and by writing register timr1 to stop the timer. after time period t1 an interrupt (auxi.tin1) is generated continuously if cnt= 7 or a single interrupt is generated after timer period t if cnt<7 ( figure 11 ). table 7 isac-sx te timers address register modes period 24 h timr1 periodic 64 ... 2048 ms count down 64 ms ... 14.336 s 65 h timr2 periodic 1 ... 63 ms count down 1 ... 63 ms st mos tran icd cic aux interrupt ista mask mos tran aux st icd cic wov tin2 tin1 wov tin2 tin1 auxm auxi eaw eaw
isac-sx te psb 3186 description of functional blocks data sheet 37 2003-01-30 figure 11 timer 1 register timer 2 the host starts and stops timer 2 in timr2.cnt ( figure 12 ). if timr2.tmd=0 the timer is operating in count down mode, for timr2.tmd=1 a periodic interrupt auxi.tin2 is generated. the timer length (for count down ti mer) or the timer period (for periodic timer), respectively, can be configured to a value between 1 - 63 ms (timr2.cnt). figure 12 timer 2 register 21150_14 cnt value 7 6 5 4 3 2 1 0 24 h expiration period t1 = (value + 1) x 0.064 sec retry counter 0 ... 6 : count down timer t = cnt x 2.048 sec + t1 7 : periodic timer t = t1 timr1 21150_14 cnt 7 6 5 4 3 2 1 0 65 h timer count 0 : timer off 1 ... 63 : 1 ... 63 ms timer mode 0 : count down timer 1 : periodic timer timr2 tmd 0
isac-sx te psb 3186 description of functional blocks data sheet 38 2003-01-30 3.2.6 activation indication via pin acl the activated state of the s-interface is directly indicated via pin acl (activation led). an led with pre-resistance may directly be connected to this pin and a low level is driven on acl as soon as the layer 1 state machine reaches the activated state (see figure 13 ). figure 13 acl indication of activated layer 1 by default (acfg2.acl=0) the state of layer 1 is indicated at pin acl . if the automatic indication of the activated layer 1 is not required, the state on pin acl can also be controlled by the host (see figure 14 ). if acfg2.acl=1 the led on pin acl can be switched on (acfg2.led=1) and off (acfg2.led=0) by the host. figure 14 acl configuration 3086_15 layer 1 acfg2:led 0 : off 1 : on acfg2:acl '1' '0' acl +3.3v s interface
isac-sx te psb 3186 description of functional blocks data sheet 39 2003-01-30 3.3 s/t-interface the layer-1 functions for the s/t interface of the isac-sx te are: ? line transceiver functions for the s/t interface according to the electrical specifications of itu-t i.430; ? conversion of the frame structure between iom-2 and s/t interface; ? conversion from/to binary to/from pseudo-ternary code; ? level detection ? receive timing recovery for point-to-point, passive bus and extended passive bus configuration ? s/t timing generation using iom-2 timing synchronous to system, or vice versa; ? d-channel access control and priority handling; ? d-channel echo bit generation by handling of the global echo bit; ? activation/deactivation procedures, triggered by primitives received over the iom-2 c/i channel or by info's received from the line; ? execution of test loops. the wiring configurations in user premises, in which the isac-sx te can be used, are illustrated in figure 15 .
isac-sx te psb 3186 description of functional blocks data sheet 40 2003-01-30 figure 15 wiring configurations in user premises 3.3.1 s/t-interface coding transmission over the s/t-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (b1+b2+d), 48 kbit/s are used for framing and maintenance information. line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. 3186_20 isac-sx te tr te tr lt-s 1000 m 1) point-to-point configuration tr tr nt / lt-s 100 m tr te1 tr nt / lt-s 10 m extended passive bus te8 25 m 500 m .... te1 10 m te8 .... short passive bus tr: terminating resistor 1) the maximum line attenuation tolerated by the isac-sx te is 7 db at 96 khz. isac-sx isac-sx isac-sx te isac-sx te isac-sx te isac-sx te isac-sx
isac-sx te psb 3186 description of functional blocks data sheet 41 2003-01-30 figure 16 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 17 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. figure 17 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. 011 code violation
isac-sx te psb 3186 description of functional blocks data sheet 42 2003-01-30 3.3.2 s/t-interface multiframing according to itu recommendation i.430 a multiframe provides extra layer 1 capacity in the te-to-nt direction by using an extra channel between the te and nt (q-channel). the q bits are defined to be the bits in the f a bit position. in the nt-to-te direction the s-channel bits are used for information transmission. one s channel (s1) out of five possible s-channels can be accessed by the isac-sx te. in the nt-to-te direction the s-channel bits are used for information transmission. the s and q channels are accessed via the c interface or the iom-2 monitor channel, respectively, by reading/writing the sqr or sqx bits in the s/q channel registers (sqrrx, sqxrx). table 8 shows the s and q bit positions within the multiframe. table 8 s/q-bit position identification and multiframe structure after multiframe synchronization has been established, the q data will be inserted at the upstream (te nt) f a bit position in each 5th s/t frame (see table 8 ). when synchronization is not achieved or lost, each received f a bit is mirrored to the next transmitted f a bit. multiframe synchronization is achieved after two complete multiframes have been detected with reference to f a /n bit and m bit positions. multiframe synchronization is lost if bit errors in f a /n bit or m bit positions have been detected in two consecutive ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ?f a auxiliary framing bit see section 6.3 in itu i.430 ?n n = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multiframe f a
isac-sx te psb 3186 description of functional blocks data sheet 43 2003-01-30 multiframes. the synchronization state is indicated by the msyn bit in the s/q-channel receive register (sqrr1). the multiframe synchronization can be enabled or disabled by programming the mfen bit in the s/q-channel transmit register (sqxr1). interrupt handling for multiframing to trigger the microcontroller for a multiframe access an interrupt can be generated once per multiframe (sqw) or if the received s-channels have changed (sqc). in both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). frame number nt-to-te f a bit position nt-to-te m bit nt-to-te s bit te-to-nt f a bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s11 s21 s31 s41 s51 q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s12 s22 s32 s42 s52 q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s13 s23 s33 s43 s53 q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s14 s24 s34 s44 s54 q4 zero zero zero zero 1 2 one zero one zero s11 s21 q1 zero
isac-sx te psb 3186 description of functional blocks data sheet 44 2003-01-30 3.3.3 data transfer and delay between iom-2 and s/t in the state f7 (activated) the b1, b2, d a nd e bits are transferred transparently from the s/t to the iom-2 interface. in all other states ?1?s are transmitted to the iom-2 interface. to transfer data transparently to the s/t interface any activation request c/i command (ar8, ar10 or arl) is additionally necessary . figure 18 shows the data delay between the iom-2 and the s/t interface and vice versa. for the d channel the delay from the iom-2 to the s/t interface is only valid if s/g evaluation is disabled (moded.dim0=0). if s/g evaluation is enabled (moded.dim2-0=0x1) the delay depends on the selected priority and the relation between the echo bits on s and the d channel bits on the iom-2, e.g. for priority 8 the timing relation between the 8th d-bit on s bus and the d-channel on iom-2. figure 18 data delay between iom-2 and s/t interface line_iom_s.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1
isac-sx te psb 3186 description of functional blocks data sheet 45 2003-01-30 figure 19 data delay between iom-2 and s/t interface with s/g bit evaluation 3.3.4 transmitter characteristics the full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source (v sx1/sx2 = +/-1.0 v; i max = 26 ma). the equivalent circuit of the transmitter is shown in figure 20 . the nominal pulse amplitude on the s-interface 750 mv (zero-peak) is adjusted with external resistors (see chapter 3.3.6.1 ). line_iom_s_dch.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 mapping of b-channel timeslots 1. possibility 2. possibility mapping of a 4-bit group of d-bits on s and iom depends on prehistory (e.g. priority control):
isac-sx te psb 3186 description of functional blocks data sheet 46 2003-01-30 figure 20 equivalent internal circuit of the transmitter stage 3.3.5 receiver characteristics the receiver consists of a differential input stage, a peak detector and a set of comparators. additional noise immunity is achieved by digital oversampling after the comparators. a simplified equivalent circuit of the receiver is shown in figure 21 . figure 21 equivalent internal circuit of the receiver stage the input stage works together with external 10 k resistors to match the input voltage to the internal thresholds. the data detection threshold vref is continuously adapted between a maximal (vrefmax) and a minimal (vrefmin) reference level related to the line level. the peak detector requires maximum 2 s to reach the peak value while storing the peak level for at least 250 s (rc > 1 ms). the additional level detector for power up/down control works with a fixed thresholds vrefld. the level detector monitors the line input signals to detect whether an info is present. when closing an analog loop it is therefore possible to indicate an incoming signal during activated loop. 21150_28 level '+0' '-0' '1' '+0' '-0' '1' vcm+0.525v vcm-0.525v vcm vcm-0.525v vcm+0.525v vcm tr_conf2.dis_tx '+0' '1' '-0' + - v=1 vcm - + v=1 sx2 sx1 100 k l evel detected vcm v refmin v ref + vref- s r 1 10 k 10 k 40 k 40 k v refld sr2 p eak d etect or n egative detecte d reccirc p ositive detecte d
isac-sx te psb 3186 description of functional blocks data sheet 47 2003-01-30 3.3.6 s/t interface circuitry for both, receive and transmit direction a 1:1 transformer is used to connect the isac- sx te transceiver to the 4 wire s/t interface. typical transformer characteristics can be found in the chapter on electrical characteristics. the connections of the line transformers is shown in figure 22 . figure 22 connection of line transformers and power supply to the isac-sx te for the transmit direction an external transformer is required to provide isolation and pulse shape according to the itu-t recommendations. 3.3.6.1 external protection circuitry the itu-t i.430 specification for both transmitter and receiver impedances in tes results in a conflict with respect to external s-protection circuitry requirements: ? to avoid destruction or malfunction of the s-device it is desirable to drain off even small overvoltages reliably. ? to meet the 96 khz impedance test specified for transmitters and receivers (for tes only, itu-t i.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be dimensioned such that voltages below 1.2 v (itu-t i.430 amplitude) x transformer ratio are not affected. this requirement results from the fact that this test is also to be performed with no supply voltage being connected to the te. therefore the second reference point for overvoltages v dd , is tied to gnd. then, if the amplitude of the 96 khz test signal is greater than the combined forward voltages of the diodes, a current exceeding the specified one may pass the protection circuit. the following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 khz impedance tests. 21150_05 protection circuit protection circuit 1:1 1:1 transmit pair receive pair sx1 sx2 sr1 sr2 gnd vdd vss 3.3 v 10 f
isac-sx te psb 3186 description of functional blocks data sheet 48 2003-01-30 protection circuit for transmitter figure 23 external circuitry for transmitter figure 23 illustrates the secondary protection circuit recommended for the transmitter. the external resistors (r = 5 ... 10 ) are required in order to adjust the output voltage to the pulse mask on the one hand and in order to meet the output impedance of minimum 20 (transmission of a binary zero according to itu-t i.430) on the other hand. two mutually reversed diode paths protect the device against positive or negative overvoltages on both lines. an ideal protection circuit should limit the voltage at the sx pins from ? 0.4 v to v dd + 0.4 v. with the circuit in figure 23 the pin voltage range is increased from ? 1.4 v to v dd + 0.7 v. the resulting forward voltage of 1.4 v will prevent the protection circuit from becoming active if the 96 khz test signal is applied while no supply voltage is present. protection circuit for receiver figure 24 illustrates the external circuitry used in combination with a symmetrical receiver. protection of symmetrical receivers is rather simple. sx1 r r vdd s bus 1:1 3186_23 sx2
isac-sx te psb 3186 description of functional blocks data sheet 49 2003-01-30 figure 24 external circuitry for symmetrical receivers between each receive line and the transformer a 10 k resistor is used. this value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 khz test, and the second one between input pin and protection diodes to limit the maximum input current of the chip. with symmetrical receivers no difficulties regarding lcl measurements are observed; compensation networks thus are obsolete. in order to comply to the physical requirements of itu-t recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the isac-sx te may need additional circuitry. note: up to 10 pf capacitors are optional for noise reduction 1:1 s bus
isac-sx te psb 3186 description of functional blocks data sheet 50 2003-01-30 3.3.6.2 s-transceiver synchronization synchronization problems can occur on a s-bus that is not terminated properly. therefore, it is recommended to change the resistor values in the receive path. the sum of both resistors is increased from 10 k (1.8 + 8.2) to e.g. 34 k (6.8 + 27) for either receiver line. this change is possible but not necessary for a s-bus that is terminated properly. figure 25 external circuitry for symmetrical receivers note: lower or higher values than 34 k may be used as well, however for values above 34 k the additional delay must be compensated by setting tr_conf2.pds=1 (compensates 260 ns) so the allowed input phase delay is not violated. 3.3.7 s/t interface delay compensation the s/t transmitter is shifted by two s/t bits minus 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. to compensate additional delay introduced into the receive and transmit path by the external circuit the delay of the transmit data can be reduced by another two oscillator periods (2 x 130 ns). therefore pds of the tr_conf2 register must be programmed to ?1?. this delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of itu-t recommendation i.430 which specifies a phase deviation in the range of ? 7% to + 15% of a bit period. 3.3.8 level detection power down if mode1.cfs is set to ?0?, the clocks are also provided in power down state, whereas if cfs is set to ?1? only the analog level detector is active in power down state. all clocks, including the iom-2 interface, are stopped (dd, du are ?high?, dcl and bcl are ?low?). note: capacitors (up to 10 pf ) are optional for noise reduction. 21150_33 1:1 s bus sr2 sr1 gnd v dd r1 r2 r1 r2
isac-sx te psb 3186 description of functional blocks data sheet 51 2003-01-30 an activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if tr_conf0.ldd is set to ?0?. if tr_conf0.ldd is set to ?1? the microcontroller has to take care of an interrupt caused by the level detect circuit (istatr.ld) from the terminal side an activation must be started by setting and resetting the spu- bit in the iom_cr register and writing tim to the cix0 register or by resetting mode1.cfs=0. 3.3.9 transceiver enable/disable the layer-1 part of the isac-sx te can be enabled/disabled by configuration (see figure 26 ) with the two bits tr_conf0.dis_tr and tr_conf2.dis_tx . by default all layer-1 functions with the exception of the transmitter buffer is enabled (dis_tr = ?0?, dis_tx = ?1?). with several terminals connected to the s/t interface, another terminal may keep the interface activated although the isac-sx te does not establish a connection. the receiver will monitor for incoming calls in this configuration. if the transceiver is disabled (dis_tr = ?1?) all layer-1 functions are disabled including the level detection circuit of the receiver. in this case the power consumption of the layer-1 is reduced to a minimum. the hdlc controller can still operate via iom-2. the dcl and fsc pins become input. figure 26 disabling of s/t transmitter tr_conf2.dis_tx ?1? ?0? tr_conf0.dis_tr
isac-sx te psb 3186 description of functional blocks data sheet 52 2003-01-30 3.3.10 test functions the isac-sx te provides test and diagnostic functions for the s/t interface: note: for more details please refer to the application note ?test function of new s- transceiver family? ? the internal local loop (internal loop a) is activated by a c/i command arl. the transmit data of the transmitter is looped back internally to the receiver. the data of the iom-2 input b- and d-channels are looped back to the output b- and d- channels. the s/t interface level detector is enabled, i.e. if a level is detected this will be reported by the resynchronization indication (rsy) but the loop function is not affected. depending on the dis_tx bit in the tr_conf2 register the internal local loop can be transparent or non transparent to the s/t line. ? the external local loop (external loop a) is activated in the same way as the internal local loop described above. additionally the exlp bit in the tr_conf0 register has to be programmed and the loop has to be closed externally as described in figure 27 . the s/t interface level detector is disabled. this allows complete system diagnostics. ?in remote line loop (rlp) received data is looped back to the s/t interface. the d- channel information received from the line card is transparently forwarded to the output iom-2 d-channel. the output b-channel information on iom-2 is fixed to ?ff? h while this test loop is active. the remote loop is programmable in tr_conf2.rlp. figure 27 external loop at the s/t-interface scout-s(x) sx1 sx2 sr1 sr2 100 100
isac-sx te psb 3186 description of functional blocks data sheet 53 2003-01-30 ? transmission of special test signals on the s/t interface according to the modified ami code are initiated via a c/i command written in cix0 register (see chapter 3.5.2 ) two kinds of test signals may be transmitted by the isac-sx: ? the single pulses are of alternating polarity. one pulse is transmitted in each frame resulting in a frequency of the fundamental mode of 2 khz. the corresponding c/i command is ssp (send single pulses). ? the continuous pulses are of alternating polarity. 48 pulses are transmitted in each frame resulting in a frequency of the fundamental mode of 96 khz. the corresponding c/i command is scp (send continuous pulses).
isac-sx te psb 3186 description of functional blocks data sheet 54 2003-01-30 3.4 clock generation figure 28 shows the clock system of the isac-sx te. the oscillator is used to generate a 7.68 mhz clock signal (f xtal ). the dpll generates the iom-2 clocks fsc (8 khz), dcl (1536 khz) and bcl (768 khz) synchronous to the received s/t frames. the fsc signal is used to generate the pulse lengths of the different reset sources c/i code, eaw pin and watchdog (see chapter 3.2.4 ). the iom-2 clocks are summarized in table 9 . figure 28 clock system of the isac-sx te table 9 iom-2 clocks signal function fsc o:8 khz (dis_tr=0), normal mode i:8 khz (dis_tr=1), s transceiver disabled *1) dcl o:1536 khz (dis_tr=0), normal mode i:1536/768 khz (dis_tr=1), s transceiver disabled *1) bcl o:768 khz du i *2) dd o *2) 3186_06 osc xtal 7.68 mhz dpll reset generation sw reset c/i eaw watchdog f xtal fsc dcl bcl 125 s t 250 s 125 s t 250 s 125 s t 250 s pin rsto 125 s t 250 s
isac-sx te psb 3186 description of functional blocks data sheet 55 2003-01-30 note: i = input; o = output; 1) the s transceiver can be disabled (tr_conf0.dis_tr=1) so the iom clocks become inputs and with iom_cr.clkm the dcl input can be selected to double clock (0) or single bit clock (1). 2) the direction input/output refers to the direction of the b- and d-channel data stream across the s-transceiver. due to the capabilites of the iom-2 handler the direction of some other timeslots may be different if this is programmed by the host (e.g. for data exchange between different devices connected to iom-2). 3.4.1 description of the receive pll (dpll) the receive pll performs phase tracking between the f/l transition of the receive signal and the recovered clock. phase adjustment is done by adding or subtracting 0.5 or 1 xtal period to or from a 1.536-mhz clock cycle. the 1.536-mhz clock is than used to generate any other clock synchronized to the line. during (re)synchronization an internal reset condition may effect the 1.536-mhz clock to have high or low times as short as 130 ns. after the s/t interface frame has achieved the synchronized state (after three consecutive valid pairs of code violations) the fsc output is set to a specific phase relationship, thus causing once an irregular fsc timing. the phase relationships of the clocks are shown in figure 29 . figure 29 phase relationships of isac-sx te clock signals 3.4.2 jitter the timing extraction jitter of the isac-sx te conforms to itu-t recommendation i.430 (? 7% to + 7% of the s-interface bit period). itd09664 7.68 mhz 1536 khz * 768 khz * synchronous to receive s/t. duty ratio 1:1 normally f-bit fsc
isac-sx te psb 3186 description of functional blocks data sheet 56 2003-01-30 3.4.3 oscillator clock output c768 the isac-sx te derives its system clocks from an external clock connected to xtal1 (while xtal2 is not connected) or from a 7.68 mhz crystal connected across xtal1 and xtal2. at pin c768 a buffered 7.68 mhz output clock is provided to drive further devices, which is suitable in multiline applications for example (see figure 30 ). this clock is not synchronized to the s-interface. in power down mode the c768 output is disabled (low signal). figure 30 buffered oscillator clock output 3086_12 xtal1 xtal2 c768 xtal1 xtal2 c768 xtal1 xtal2 c768 7.68 mhz n.c. n.c. n.c. n.c.
isac-sx te psb 3186 description of functional blocks data sheet 57 2003-01-30 3.5 control of layer-1 the layer-1 activation / deactivation is controlled by an internal state machine via the iom-2 c/i0 channel. the isac-sx te layer-1 control flow is shown in figure 31 . figure 31 layer-1 control in the following sections the layer-1 control by the isac-sx te state machine will be described. for the description of the iom-2 c/i0 channel see also chapter 3.7.4 . the layer-1 functions are controlled by commands issued via the cix0 register. these commands, sent over the iom-2 c/i channel 0 to layer 1, trigger certain procedures, such as activation/deactivation, switching of test loops and transmission of special pulse patterns. these procedures are governed by layer-1 state diagrams. responses from layer 1 are obtained by reading the cir0 register after a cic interrupt (ista). the state diagrams of the isac-sx te are shown in figure 33 and figure 34 . the activation/deactivation implemented by t he isac-sx te agrees with the requirements set forth in itu recommendations. state identifiers f1-f8 are in accordance with itu i.430. state machines are the key to understanding the transceiver part of the isac-sx te. they include all information relevant to the user and enable him to understand and predict the behaviour of the isac-sx te. the state diagram notation is given in figure 32 . the informations contained in the state diagrams are: ? state name (based on itu i.430) ? s/t signal transmitted (info) ? c/i code received ? c/i code transmitted ? transition criteria the coding of the c/i commands and indications are described in detail in chapter 3.5.2 . 3186_01 layer-1 state machine transmitter receiver transmit info receive info s/t interface info signals command indication ci0 data register cix0 cir0 layer-1 control c interface iom-2 c/i0 channel
isac-sx te psb 3186 description of functional blocks data sheet 58 2003-01-30 figure 32 state diagram notation the following example illustrates the use of a state diagram with an extract of the te state diagram. the state explained is ?f3 deactivated?. the state may be entered: ? from the unconditional states (arl, res, tm) ? from state ?f3 pending deactivation?, ?f3 power up?, ?f4 pending activation? or ?f5 unsynchronized? after the c/i command ?di? has been received. the following informations are transmitted: ? info 0 (no signal) is sent on the s/t-interface. c/i message ?dc? is issued on the iom-2 interface. the state may be left by either of the following methods: ? leave for the state ?f3 power up? in case c/i = ?tim? code is received. ? leave for state ?f4 pending activation? in case c/i = ar8 or ar10 is received. ? leave for the state ?f6 synchronized? after info 2 has been recognized on the s/ t-interface. ? leave for the state ?f7 activated? after info 4 has been recognized on the s/ t-interface. ? leave for any unconditional state if any unconditional c/i command is received. as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? stands for a logical and combination. and a ?+? indicates a logical or combination. the sections following the state diagram contain detailed information on all states and signals used. itd09657 cmd. ind. state c / unconditional transition s / t interface info out ipac in i x i r ipac iom-2 interface isac-sx te
isac-sx te psb 3186 description of functional blocks data sheet 59 2003-01-30 3.5.1 state machine te mode 3.5.1.1 state transition diagram (te) figure 33 shows the state transition diagram of the isac-sx te state machine. figure 34 shows this for the unconditional transitions (reset, loop, test mode i).
isac-sx te psb 3186 description of functional blocks data sheet 60 2003-01-30 figure 33 state transition diagram (te) x 1) dr for transition from f7 or f8 dr6 for transition from f6 2) ar stands for ar8 or ar10 3) ai stands for ai8 or ai10 4) x stands for commands initiating unconditional transitions (res, arl, ssp or scp) to1: 16 ms to2: 0.5 ms statem_te_s.vsd f3 pending deact. dr 1) i0 i0 f3 deactivated dc di i0 i0 ar i2 tim i0*to1 f3 power up pu tim i0 i0 di tim di i2 di*to2 tim*to2 i0 f8 lost framing rsy i0 x i4 i0*to1 i0*to1 ar di i2 f7 activated ai 3) ar 2) i3 i4 f6 synchronized ar i3 i2 x f5 unsynchronized rsy i0 ix i2 i0 f4 pending act. pu ar 2) i1 i0 x i4 i2 i2 i4 ix ix tim i4 i4 i4 tim di tim x 4) uncond. state x di
isac-sx te psb 3186 description of functional blocks data sheet 61 2003-01-30 figure 34 state transition diagram of unconditional transitions (te) 3.5.1.2 states (te) f3 pending deactivation state after deactivation from the s/t interface by info 0. note that no activation from the terminal side is possible starting from this state. a ?di? command has to be issued to enter the state ?deactivated state?. f3 deactivated state the s/t interface is deactivated and the clocks are deactivated 500 s after entering this state and receiving info 0 if the cfs bit of the isac-sx te configuration register is set to ?0?. activation is possible from the s/t interface and from the iom-2 interface. f3 power up the s/t interface is deactivated (info 0 on the line) and the clocks are running. f4 pending activation the isac-sx transmits info 1 towards the network, waiting for info 2. f5 unsynchronized any signal except info 2 or 4 detected on the s/t interface. f6 synchronized the receiver has synchronized and detects info 2. info 3 is transmitted to synchronize the nt. statem_te_aloop_s.vsd loop a activated ail rsy arl i3 * loop a closed arl arl i3 * di tim di tim arl reset res res i0 * di tim ssp scp test mode i tma ssp scp it i * di tim i3 i3 res any state rst
isac-sx te psb 3186 description of functional blocks data sheet 62 2003-01-30 f7 activated the receiver has synchronized and detects info 4. all user channels are now conveyed transparently to the iom-2 interface. to transfer user channels transparently to the s/t interface either the command ar8 or ar10 has to be issued and the signal from remote side must be synchronous. f8 lost framing the receiver has lost synchronization in the states f6 or f7 respectively. unconditional states loop a closed (internal or external) the isac-sx loops back the transmitter to the receiver and activates by transmission of info 3. the receiver has not yet synchronized. for a non transparent internal loop the dis_tx bit of register tr_conf2 has to be set to ?1?. loop a activated (internal or external) the receiver has synchronized to info 3. data may be sent. the indication ?ail? is output to indicate the activated state. if the loop is closed internally and the s/t line awake detector detects any signal on the s/t interface, this is indicated by ?rsy?. test mode - ssp single alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 2 khz. test mode - scp continuous alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 96 khz.
isac-sx te psb 3186 description of functional blocks data sheet 63 2003-01-30 3.5.1.3 c/i codes (te) note: in the activated states (ai8, ai10 or ail indication) the 2b+d channels are only transferred transparently to the s/t interface if one of the three ?activation request? commands is permanently issued. command abbr. code remark activation request with priority class 8 ar8 1000 activation requested by the isac-sx, d-channel priority set to 8 ( see note ) activation request with priority class 10 ar10 1001 activation requested by the isac-sx, d-channel priority set to 10 ( see note ) activation request loop arl 1010 activation requested for the internal or external loop a ( see note ). for a non transparent internal loop bit dis_tx of register tr_conf2 has to be set to ?1? additionally. deactivation indication di 1111 deactivation indication reset res 0001 reset of the layer-1 statemachine timing tim 0000 layer-2 device requires clocks to be activated test mode ssp ssp 0010 one ami-coded pulse transmitted in each frame, resulting in a frequency of the fundamental mode of 2 khz test mode scp scp 0011 ami-coded pulses transmitted continuously, resulting in a frequency of the fundamental mode of 96 khz
isac-sx te psb 3186 description of functional blocks data sheet 64 2003-01-30 indication abbr. code remark deactivation request dr 0000 deactivation request via s/t-interface if left from f7/f8 reset res 0001 reset acknowledge test mode acknowledge tma 0010 acknowledge for both ssp and scp slip detected sld 0011 resynchronization during level detect rsy 0100 signal received, receiver not synchronous deactivation request from f6 dr6 0101 deactivation request from state f6 power up pu 0111 iom-2 interface clocking is provided activation request ar 1000 info 2 received activation request loop arl 1010 internal or external loop a closed illegal code violation cvr 1011 illegal code violation received. this function has to be enabled by setting the en_icv bit of register tr_conf0. activation indication loop ail 1110 internal or external loop a activated activation indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9. activation indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11. deactivation confirmation dc 1111 clocks are disabled if cfs bit of register mode1 is set to ?1?, quiescent state
isac-sx te psb 3186 description of functional blocks data sheet 65 2003-01-30 3.5.1.4 infos on s/t (te) receive infos on s/t (downstream) transmit infos on s/t (upstream) name abbr. description info 0 i0 no signal on s/t info 2 i2 4 khz frame a=?0? info 4 i4 4 khz frame a=?1? info x ix any signal except info 2 or info 4 name abbr. description info 0 i0 no signal on s/t info 1 i1 continuous bit sequence of the form ?00111111? info 3 i3 4 khz frame test info 1 it 1 ssp - send single pulses test info 2 it 2 scp - send continuous pulses
isac-sx te psb 3186 description of functional blocks data sheet 66 2003-01-30 3.5.2 command/ indicate channel codes (c/i0) - overview the table below presents all defined c/i0 codes. a command needs to be applied continuously until the desired action has been initiated. indications are strictly state orientated. refer to the state diagrams in the previous sections for commands and indications applicable in various states. code te mode cmd ind 0000tim dr 0001res res 0010ssp tma 0011scp sld 0100? rsy 0101? dr6 0110? ? 0111? pu 1000ar8 ar 1001ar10 ? 1010arl arl 1011? cvr 1100? ai8 1101? ai10 1110? ail 1111di dc
isac-sx te psb 3186 description of functional blocks data sheet 67 2003-01-30 3.6 control procedures 3.6.1 example of activation/deactivation an example of an activation/deactivation of the s/t interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 35 . figure 35 example of activation/deactivation initiated by the terminal a_deact.dr w n t/linecard t e i nfo 0 i nfo 1 i nfo 2 i nfo 3 i nfo 4 i nfo 0 i nfo 0 d r a i a r r sy 16 ms 0.5 ms max. 6 ms a r
isac-sx te psb 3186 description of functional blocks data sheet 68 2003-01-30 3.7 iom-2 interface the isac-sx te supports the iom-2 interface in terminal mode with single clock and double clock. the iom-2 interface consists of four lines: fsc, dcl, dd and du. another clock signal bcl provides a single bit clock. the rising edge of fsc indicates the start of an iom-2 frame. the dcl and the bcl clock signals synchronize the data transfer on both data lines du and dd. the dcl is twice the bit rate, the bcl rate is equal to the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle and sampled at the falling edge of the second clock cycle. the iom-2 interface can be enabled/disabled with the dis_iom bit in the iom_cr register. the iom clock signals are generated by the receive dpll which synchronizes the fsc to the received s/t frame. the bcl clock together with the serial data strobe signals sds can be used to connect timeslot oriented standard devices to the iom-2 interface. if the transceiver is disabled (tr_con.dis_tr) the dcl and fsc pins become input and the hdlc part can still work via iom-2. in this case the clock mode bit (iom_cr.clkm) selects between a double clock and a single clock input for dcl. the clock rate/frequency of the iom-2 signals in te mode are: dd, du: 768 kbit/s fsc (o): 8 khz dcl (o): 1536 khz (double clock rate) bcl (o): 768 khz (single clock rate) option - transceiver disabled (dis_tr = ?1?): fsc (i): 8 khz dcl (i): 1536 ... 4096 khz, in steps of 512 khz (double clock rate)
isac-sx te psb 3186 description of functional blocks data sheet 69 2003-01-30 iom-2 frame structure (te mode) the frame structure on the iom-2 data ports (du,dd) of a master device in iom-2 terminal mode is shown in figure 36 . figure 36 iom -2 frame structure in terminal mode the frame is composed of three channels channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (mon0) and a command/indication channel (ci0) for control and programming of the layer-1 transceiver. channel 1 contains two 64-kbit/s intercommunication channels (ic) plus a monitor and command/indicate channel (mon1, ci1) to program or transfer data to other iom-2 devices. channel 2 is used for the tlc-bus access. only the command/indicate bits are specified in this channel.
isac-sx te psb 3186 description of functional blocks data sheet 70 2003-01-30 3.7.1 iom-2 handler the iom-2 handler offers a great flexibility for handling the data transfer between the different functional units of the isac-sx te and voice/data devices connected to the iom-2 interface. additionally it provides a microcontroller access to all timeslots of the iom-2 interface via the four controller data access registers (cda). figure 37 shows the architecture of the iom-2 handler. for illustrating the functional description it contains all configuration and control registers of the iom-2 handler. a detailed register description can be found in chapter 4.3 . the pcm data of the functional units transceiver (tr) and the controller data access (cda) can be configured by programming the timeslot and data port selection registers (tsdp). with the tss bits (timeslot selection) the pcm data of the functional units can be assigned to each of the 12 pcm timeslots of the iom-2 frame. with the dps bit (data port selection) the output of each functional unit is assigned to du or dd respectively. the input is assigned vice versa. with the data control registers (xxx_cr) the access to the data of the functional units can be controlled by setting the corresponding control bits (en, swap). the iom-2 handler also provides access to the monitor channel (mon) c/i channels (c/i0,c/i1) tic bus (tic) and hdlc control the access to these channels is controlled by the registers mon_cr and dci_cr. the iom-2 interface with the serial data strobe sds is controlled by the control registers iom_cr, sds_cr. the reset configuration of the isac-sx te iom-2 handler corresponds to the defined frame structure and data ports of a master device in iom-2 terminal mode (see figure 36 ).
isac-sx te psb 3186 description of functional blocks data sheet 71 2003-01-30 . figure 37 architecture of the iom handler (example configuration) 3186_07 cda control ( dps, tss, en_tbm, swap, en_i1/0, en_o1/0, mcdaxy, stixy, stovxy, ackxy ) cda registers cda10 cda11 cda20 cda21 cda_tsdpxy cdax_crx mcda sti msti asti controller data access (cda) control monitor data (dps, cs2-0, en_mon) mon_cr tic bus disable (tic_dis) iom_cr dci_cr c/i1 (dps_ci1, en_ci1) control transceiver data access (dps, tss, cs2-0, en_d, en_b1r, en_b1x, en_b2r, en_b2x ) tr_tsdp_bc1 tr_tsdp_bc2 trc_cr d data d, b1, b2, c/i0 data c/i1 data c/i0 data tic bus data monitor data cda data transceiver data tr d-channel rx/tx b1-channel rx b1-channel tx mon handler tic c/i0 c/i1 data d-ch fifos microcontroller interface iom_cr ( ens_tss, ens_tss+1, ens_tss+3, tss, sds_bcl iom-2 interface du dd fsc dcl bcl sds iom-2 handler c/i0 (cs2-0) dcic_cr d-channel (cs2-0, d_en_d, d_en_b1, d_en_b2) control b2-channel rx b2-channel tx sds_cr en_bcl, clkm, dis_od, dis_iom, diom_inv, diom_sds note: the registers shown above are used to control the corresponding functional block (e.g. programming of timeslot, data port, enabling/disabling, etc.) c/i data hdlc data
isac-sx te psb 3186 description of functional blocks data sheet 72 2003-01-30 3.7.1.1 controller data access (cda) with its four controller data access registers (cda10, cda11, cda20, cda21) the isac-sx te iom-2 handler provides a very flexible solution for the host access to up to 32 iom-2 timeslots. however, in the normal mode (dcl output = 1.536 mhz) 12 timeslots are supported. only if the transcei ver is disabled (dis_tr = ?1?) and external clocks are provided, up to 32 timeslots (dcl input = 4.096 mhz) can be used. the functional unit cda (controller data access) allows with its control and configuration registers looping of up to four independent pcm channels from du to dd or vice versa over the four cda registers shifting of two independent pcm channels to another two independent pcm channels on both data ports (du, dd). between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. if this is not the case a switching function is performed monitoring of up to four timeslots on the iom-2 interface simultaneously microcontroller read and write access to each pcm timeslot the access principle which is identical for the two channel register pairs cda10/11 and cda20/21 is illustrated in figure 38 . each of the index variables x,y used in the following description can be 1 or 2 for x and 0 or 1 for y. the prefix ?cda_? from the register names has been omitted for simplification. to each of the four cdaxy data registers a tsdpxy register is assigned by which the timeslot and the data port can be determined. with the tss (timeslot selection) bits a timeslot from 0...31 can be selected. with the dps (data port selection) bit the output of the cdaxy register can be assigned to du or dd, respectively. the timeslot and data port for the output of cdaxy is always defined by its own tsdpxy register. the input of cdaxy depends on the swap bit in the control registers crx. if the swap bit = ?0? (swap is disabled) the timeslot and data port for the input and output of the cdaxy register is defined by its own tsdpxy register. if the swap bit = ?1? (swap is enabled) the input port and timeslot of the cdax0 is defined by the tsdp register of cdax1 and the input port and timeslot of cdax1 is defined by the tsdp register of cdax0. the input definition for timeslot and data port cdax0 are thus swapped to cdax1 and for cdax1 swapped to cdax0. the output timeslots are not affected by swap. the input and output of every cdaxy register can be enabled or disabled by setting the corresponding en (-able) bit in the control register cdax_cr. if the input of a register is disabled the output value in the register is retained. usually one input and one output of a functional unit (transceiver, hdlc controller, cda register) is programmed to a timeslot on iom-2 (e.g. for b-channel transmission in upstream direction the hdlc controller writes data onto iom and the transceiver reads data from iom). for monitoring data in such cases a cda register is programmed as
isac-sx te psb 3186 description of functional blocks data sheet 73 2003-01-30 described below under ?monitoring data?. besides that none of the iom timeslots must be assigned more than one input and output of any functional unit. . figure 38 data access via cdax1 and cdax2 register pairs looping and shifting data figure 39 gives examples for typical configurations with the above explained control and configuration possibilities with the bits tss, dps, en and swap in the registers tsdpxy or cdax_cr: a) looping iom-2 timeslot data from du to dd or vice versa (swap = 0) b) shifting data from tsa to tsb and tsc to tsd in both transmission directions (swap = 1) c)sswitching data from tsa to tsb and looping from du to dd or tsc to tsd and looping from dd to du respectively tsa is programmed in tsdp10, tsb in ts dp11, tsc in tsdp20 and tsd in tsdp21. it should also be noted that the input control of cda registers is swapped if swap=1 while the output control is not affected (e.g. for cda11 in example a: en_i1=1 and en_o1=1, whereas for cda11 in example b: en_i0=1 and en_o1=1). du cdax1 control register cda_crx dd 1 1 time slot selection (tss) input swap (swap) 1 x = 1 or 2; a,b = 0...11 data port cda_tsdpx2 0 1 0 1 iom_hand.fm4 1 0 1 1 enable input * (en_o0) output cda_tsdpx1 1 0 cdax0 1 (en_i0) (en_i1) input * enable output (en_o1) selection (dps) data port selection (dps) selection (tss) time slot tsa tsa tsb tsb *) in the normal mode (swap=0) the input of cdax0 and cdax1 is enabled via en_i0 and en_i1, respectively. if swap=1 en_i0 controls the input of cdax1 and en_i1 controls the input of cdax0. the output control (en_o0 and en_o1) is not affected by swap.
isac-sx te psb 3186 description of functional blocks data sheet 74 2003-01-30 figure 39 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) shifting and looping data tsa tsb tsc tsd cda10 cda11 cda20 cda21 tsa tsb tsc tsd du dd tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd b) shifting d ata a) looping data .tss: .dps .swap ?0? ?1? ?1? ?0? ?0? ?0? tsa tsb tsc tsd .tss: .dps .swap ?1? ?1? ?0? ?1? ?0? ?1? tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd c) s witching d ata tsa tsb tsc tsd .tss: .dps .swap ?1? ?1? ?1? ?0? ?0? ?1?
isac-sx te psb 3186 description of functional blocks data sheet 75 2003-01-30 figure 40 shows the timing of looping tsa from du to dd (a = 0...11) via cdaxy register. tsa is read in the cdaxy register from du and is written one frame later on dd. . figure 40 data access when looping tsa from du to dd figure 41 shows the timing of shifting data from tsa to tsb on du (dd). in figure 41a) shifting is done in one frame because tsa and tsb didn?t succeed direct one another (a, b = 0...9 and b a+2
in figure 41b) shifting is done from one frame to the following frame. this is the case when the timeslots succeed one other (b = a+1) or b is smaller than a (b < a). at looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). sti and stov are explained in the section ?synchronous transfer?. if there is no controller intervention the looping and shifting is done autonomous. tsa du tsa fsc cdaxy c rd wr ack stov tsa dd tsa sti a = 0...11 *) if access by the c is required *)
isac-sx te psb 3186 description of functional blocks data sheet 76 2003-01-30 figure 41 data access when shifting tsa to tsb on du (dd) tsa du tsb fsc cdaxy c rd wr ack stov sti tsa sti tsa fsc cdaxy c rd wr ack stov sti tsb tsa tsb (dd) (a,b: 0...11 and (b = a+1 or b isac-sx te psb 3186 description of functional blocks data sheet 77 2003-01-30 monitoring data figure 42 gives an example for monitoring of two iom-2 timeslots each on du or dd simultaneously. for monitoring on du and/or dd the channel registers with even numbers (cda10, cda20) are assigned to time slots with even numbers ts(2n) and the channel registers with odd numbers (cda11, cda21) are assigned to timeslots with odd numbers ts(2n+1). the user has to take care of this restriction by programming the appropriate timeslots.. . figure 42 example for monitoring data monitoring tic bus monitoring the tic bus (ts11) is handled as a special case. the tic bus can be monitored with the registers cdax0 by setting the en_tbm (enable tic bus monitoring) bit in the control registers crx. in this special case the tsdpx0 must be set to 08 h for monitoring from du or 88 h for monitoring from dd respectively. by this it is possible to monitor the tic bus (ts11) and the odd numbered d-channel (ts3) simultaneously on du and dd. cda10 cda11 cda20 cda21 ts(2n) ts(2n+1) du dd a) monitoring data tss: ts(2n) ts(2n+1) tss: ?1? ?1? dps: ?0? ?0? dps: ?0? ?0? en_o: ?1? ?1? en_i: ?0? ?0? en_o: ?1? ?1? en_i: cda_cr1. cda_cr2.
isac-sx te psb 3186 description of functional blocks data sheet 78 2003-01-30 synchronous transfer while looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). the microcontroller access to the cdaxy registers can be synchronized by means of four programmable synchronous transfer interrupts (stixy) 1) and synchronous transfer overflow interrupts (stovxy) 2) in the sti register. depending on the dps bit in the corresponding cda_tsdpxy register the stixy is generated two (for dps=?0?) or one (for dps=?1?) bcl clock after the selected timeslot (cda_tsdpxy.tss). one bcl clock is equivalent to two dcl clocks. in the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (sti/stov) out of the four cda interrupt pairs (sti10/stov10, sti11/ stov11, sti20/stov20, sti21/stov21). an stovxy 0 is related to its stixy 0 and is only generated if stixy 0 is enabled and not acknowledged. however, if stixy 0 is masked, the stovxy 0 is generated for any other stixy 1 which is enabled and not acknowledged. table 10 gives some examples for that. it is assumed that an stov interrupt is only generated because an sti interrupt was not acknowledged before. in example 1 only the stixy 0 is enabled and thus stixy 0 is only generated. if no sti is enabled, no interrupt will be generated even if stov is enabled (example 2). in example 3 stixy 0 is enabled and generated and the corresponding stovxy 0 is disabled. stixy 1 is disabled but its stovxy 1 is enabled, and therefore stovxy 1 is generated due to stixy 0 . in example 4 additionally the corresponding stovxy 0 is enabled, so stovxy 0 and stovxy 1 are both generated due to stixy 0 . in example 5 additionally the stixy 1 is enabled with the result that stovxy 0 is only generated due to stixy 0 and stovxy 1 is only generated due to stixy 1 . compared to the previous example stovxy 0 is disabled in example 6, so stovxy 0 is not generated and stovxy 1 is only generated for stixy 1 but not for stixy 0 . compared to example 5 in example 7 a third stovxy 2 is enabled and thus stovxy2 is generated additionally for both stixy 0 and stixy 1 . 1) in order to enable the sti interrupts the input of the corresponding cda register has to be enabled. this is also valid if only a synchronous write access is wanted. the enabling of the output alone does not effect an sti interrupt. 2) in order to enable the stov interrupts the output of the corresponding cda register has to be enabled. this is also valid if only a synchronous read access is wanted. the enabling of the input alone does not effect an interrupt.
isac-sx te psb 3186 description of functional blocks data sheet 79 2003-01-30 an stov interrupt is not generated if all stimulating sti interrupts are acknowledged. an stixy must be acknowledged by setting the ackxy bit in the asti register until two bcl clocks (for dps=?0?) or one bcl clocks (for dps=?1?) before the timeslot which is selected for the appropriate stixy. the interrupt structure of the synchronous transfer is shown in figure 43 . . figure 43 interrupt structure of the synchronous data transfer table 10 examples for synchronous transfer interrupts enabled interrupts (register msti) generated interrupts (register sti) sti stov sti stov xy 0 -xy 0 -example 1 -xy 0 --example 2 xy 0 xy 1 xy 0 xy 1 example 3 xy 0 xy 0 ; xy 1 xy 0 xy 0 ; xy 1 example 4 xy 0 ; xy 1 xy 0 ; xy 1 xy 0 xy 1 xy 0 xy 1 example 5 xy 0 ; xy 1 xy 1 xy 0 xy 1 - xy 1 example 6 xy 0 ; xy 1 xy 0 ; xy 1 ; xy 2 xy 0 xy 1 xy 0 ; xy 2 xy 1 ; xy 2 example 7 sti11 msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 ack11 asti ack10 ack20 ack21 st mos tran icd cic wov interrupt ista mask mos tran wov st icd cic
isac-sx te psb 3186 description of functional blocks data sheet 80 2003-01-30 figure 44 shows some examples based on the timeslot structure. figure a) shows at which point in time an sti and stov interrrupt is generated for a specific timeslot. figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. . figure 44 examples for the synchronous transfer interrupt control with one enabled stixy xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 a) interrupts for data access to time slot 0 (b1 after reset), msti.sti10 and msti.stov10 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '1' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 b) interrupts for data access to time slot 0 (b1 after reset), stov interrupt used as flag for "intermediate cda access"; msti.sti10 and msti.stov21 enabled c) interrupts for data access to time slot 0 and 5, msti.sti10, msti.stov10, msti.sti21 and msti.stov21 enabled sti_stov.vsd xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '0' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 d) interrupts for data access to time slot 0 (b1 after reset), stov21 interrupt used as flag for "intermiediate cda access", stov10 interrupt used as flag for "cda access failed"; msti.sti10, msti.stov10 and msti.stov21 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 : stov interrupt generated for a not acknowledged sti interrupt : sti interrupt generated
isac-sx te psb 3186 description of functional blocks data sheet 81 2003-01-30 restrictions concerning monitoring and shifting data due to the hardware design, there are some restrictions for the cda shifting data function and for the cda monitoring data function. the selection of the cda registers is restricted if other functional blocks of the isac-sx te (transceiver cores, hdlc controllers, ci handler, monitor handler, tic bus etc.) access the corresponding timeslot. if no functional block is assigned to a certain timeslot, any cda register can be used for monitoring or shifting it. if a timeslot is already occupied by a functional block in a certain transmission direction, only cda registers with odd numbers (cda11/21) can be assigned to odd timeslots and cda registers with even numbers (cda10/20) can be assigned to even timeslots in the same transmission direction. for the other transmission direction every cda register can be used. (example: if ts 5 is already occupied in dd direction, only cda11 and 21 can be used for monitoring it. for monitoring ts 5 in du direction, also cda10 or cda20 could be used.) if above guideline is not considered, data can be overwritten in corresponding timeslots. in this context no general rules can be derived in which way the data are overwritten. the usage of the looping data and switching data functions are unrestricted. restrictions concerning read/write access if data shall be read out from a certain transmission direction and other data shall be written in the opposite transmission direction in the same timeslot, only special cda register combinations can be used. the correct behavior can be achieved with the following cda register combinations: with other register combinations unintended loops or erroneous monitorings can occur or wrong data is written to the iom interface. unexpected write/read behavior of cda registers if inputs and outputs are disabled, the programmed values of cda10/11/20/21 registers cannot be read back. instead of the expected value the content of the previous programming can be read out. the programmed value (5a h in the following example) will be fetched if the output is enabled. table 11 cda register combinations with correct read/write access cda register combination 1234 data of the downstream timeslot is read by cda10 cda11 cda20 cda21 data is written to the upstream timeslot from cda20 cda21 cda10 cda11
isac-sx te psb 3186 description of functional blocks data sheet 82 2003-01-30 example: w cda1_cr = 00 h (inputs and outputs are disabled) w cda10 = 5a h (example) r cda10 = ff h (old value of previous programming) w cda1_cr = 02 h (output of cda10 is enabled) r cda10 = 5a h (the programmed value can be read back) 3.7.2 serial data strobe si gnal and strobed data clock for timeslot oriented standard devices connected to the iom-2 interface the isac-sx te provides an independent data strobe signal sds. instead of a data strobe signal a strobed iom-2 bit clock can be provided on pin sds. 3.7.2.1 serial data strobe signal the strobe signal can be generated with every 8-khz frame and is controlled by the register sds_cr. by programming the tss bits and three enable bits (ens_tss, ens_tss+1, ens_tss+3) a data strobe can be generated for the iom-2 timeslots ts, ts+1 and ts+3 and any combination of them. the data strobe for ts and ts+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for ts+3 is always 2 bits long (bit7, bit6). figure 45 shows three examples for the generation of a strobe signal. in example 1 the sds is active during channel b2 on iom-2 whereas in the second example during ic2 and mon1. the third example shows a strobe signal for 2b+d channels which can be used e.g. for an idsl (144kbit/s) transmission.
isac-sx te psb 3186 description of functional blocks data sheet 83 2003-01-30 figure 45 data strobe signal for all examples sds_conf.sds_bcl must be set to ?0?. fsc dd,du m r m x d ci0 sds (example1) sds (example2) sds (example3) tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' = '0' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' = '1' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 3: = '0 h ' = '1' = '1' = '1' ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 3186_02.vsd
isac-sx te psb 3186 description of functional blocks data sheet 84 2003-01-30 3.7.2.2 strobed iom-2 bit clock the strobed iom-2 bit clock is active during the programmed window. outside the programmed window a ?0? is driven. two examples are shown in figure 46 . figure 46 strobed iom-2 bit clock. register sds_conf programmed to 01 h the strobed bit clock can be enabled in sds_conf.sds_bcl. 3.7.3 iom-2 monitor channel the iom-2 monitor channel ( figure 47 ) is utilized for information exchange in the monitor channel between a master mode device and a slave mode device. the montior channel data can be controlled by the bits in the monitor control register (mon_cr). for the transmission of the monitor data one of the iom-2 channels (3 iom-2 channels in te mode) can be selected by setting the monitor channel selection bits (mcs) in the monitor control register (mon_cr). for all examples sds_conf.sds_bcl must be set to ?1?. fsc dd,du m r m x d ci0 sds (example1) sds (example2) ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 3186_03.vsd tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' = '0' = '0' = '1' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' = '1' = '1' = '0' setting of sds_cr:
isac-sx te psb 3186 description of functional blocks data sheet 85 2003-01-30 the dps bit in the same register selects between an output on du or dd respectively and with en_mon the monitor data can be enabled/disabled. the default value is monitor channel 0 (mon0) enabled and transmission on dd. figure 47 examples of monitor channel applications in iom -2 te mode the monitor channel of the isac-sx te can be used in following applications which are illustrated in figure 47 : as a master device the isac-sx te can program and control other devices attached to the iom-2 which do not need a parallel microcontroller interface e.g. arcofi-ba psb 2161. this facilitates redesigning existing terminal designs in which e.g. an interface of an expansion slot is realized with iom-2 interface and monitor programming. as a slave device the transceiver part of the isac-sx te is programmed and controlled from a master device on iom-2 (e.g. isar34 psb 7115). this is used in applications where no microcontroller is connected directly to the isac-sx te in order to simplify host interface connection. the hdlc controlling is processed by the master device therefore the hdlc data is transferred via iom-2 interface directly to the master device. for data exchange between two microcontroller systems attached to two different devices on one iom-2 backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between the two systems. this simplifies the system design of terminal equipment. 3086_08 monitor handler layer 1 v/d module (e.g. arcofi-ba) iom-2 monitor channel c monitor handler layer 1 v/d module (e.g. isar34) iom-2 monitor channel c master device monitor handler layer 1 v/d module (e.g. isar34) iom-2 monitor channel c data exchange between two c systems c slave device
isac-sx te psb 3186 description of functional blocks data sheet 86 2003-01-30 3.7.3.1 handshake procedure the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted once per 8-khz frame until the transfer is acknowledged via the mr bit. the monitor channel protocol is described in the following section and figure 48 illustrates this. the relevant control and status bits for transmission and reception are listed in table 12 and table 13 . table 12 transmit direction control/ status bit register bit function control mocr mxc mx bit control mie transmit interrupt enable status mosr mda data acknowledged mab data abort msta mac transmission active table 13 receive direction control/ status bit register bit function control mocr mrc mr bit control mre receive interrupt enable status mosr mdr data received mer end of reception
isac-sx te psb 3186 description of functional blocks data sheet 87 2003-01-30 figure 48 monitor channel protocol (iom-2) before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a ?0? in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to ?1?. this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates an mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to ?1? to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor interrupt enable (mie) to ?1?. itd10032 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mie = 1 mox = adr mxc = 1 mac = 1 mox = data1 mda int. mda int. mda int. mxc = 0 mdr int. rd mor (=adr) mrc = 1 mdr int. mdr int. mrc = 0 mer int. p p 125 s rd mor (=data1 ) rd mor (=data2 ) mox = data2 mac = 0
isac-sx te psb 3186 description of functional blocks data sheet 88 2003-01-30 as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to ?0?. this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mda interrupt status. this "mda interrupt ? write data ? mdr interrupt ? read data ? mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to ?0?. this enforces an inactive (?1?) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to ?0?. during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to ?0?. an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter. the monitor transfer protocol rules are summarized in the following section: a pair of mx and mr in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission . a start of a transmission is initiated by the transmitter by setting the mxc bit to ?1? enabling the internal mx control. the receiver acknowledges the received first byte by setting the mr control bit to ?1? enabling the internal mr control. the internal mx,mr control indicates or acknowledges a new byte in the mon slot by toggling mx,mr from the active to the inactive state for one frame. two frames with the mx-bit in the inactive state indicate the end of transmission . two frames with the mr-bit set to inactive indicate a receiver request for abort . the transmitter can delay a transmission sequence by sending the same byte continuously. in that case the mx-bit remains active in the iom-2 frame following the first byte occurrence. delaying a transmission sequence is only possible while the receiver mr-bit and the transmitter mx-bit are active.
isac-sx te psb 3186 description of functional blocks data sheet 89 2003-01-30 since a double last-look criterion is implemented the receiver is able to receive the mon slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. to control this handshake procedure a collision detection mechanism is implemented in the transmitter. this is done by making a collision check per bit on the transmitted monitor data and the mx bit. monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. two frames with the mx bit in the inactive state indicates the end of a message (eom). transmission and reception of monitor messages can be performed simultaneously. this feature is used by the isac-sx te to send back the response before the transmission from the controller is completed (the isac-sx te does not wait for eom from controller). 3.7.3.2 error treatment in case the isac-sx te does not detect identical monitor messages in two successive frames, transmission is not aborted. instead the isac-sx te will wait until two identical bytes are received in succession. a transmission is aborted of the isac-sx te if an error in the mr handshaking occurs a collision on the iom-2 bus of the monitor data or mx bit occurs the transmission time-out timer expires a reception is aborted by the device if an error in the mx handshaking occurs or an abort request from the opposite device occurs mx/mr treatment in error case in the master mode the mx/mr bits are under control of the microcontroller through mxc or mrc, respectively. an abort is indicated by an mab interrupt or mer interrupt, respectively. in the slave mode the mx/mr bits are under control of the device. an abort is always indicated by setting the mx/mr bit inactive for two or more iom-2 frames. the controller must react with eom. figure 49 shows an example for an abort requested by the receiver, figure 50 shows an example for an abort requested by the transmitter and figure 51 shows an example for a successful transmission.
isac-sx te psb 3186 description of functional blocks data sheet 90 2003-01-30 figure 49 monitor channel, transmission abort requested by the receiver figure 50 monitor channel, transmission abort requested by the transmitter figure 51 monitor channel, normal end of transmission mx (du) iom -2 frame no. 1 2 345 67 eom mr (dd) 1 0 1 0 mon_rec-abort.vsd abort request from receiver mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_tx-abort.vsd abort request from transmitter mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_norm.vsd 8
isac-sx te psb 3186 description of functional blocks data sheet 91 2003-01-30 3.7.3.3 monitor channel programming as a master device as a master device the isac-sx te can program and control other devices attached to the iom-2 interface. the master mode is selected by default if one of the possible microcontroller interfaces are selected. the monitor data is written by the microprocessor in the mox register and transmitted via iom-2 dd (du) line to the programmed/controlled device e.g. arcofi-ba psb 2161 or iec-q te psb 21911. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter chapter 3.7.3.1 . if the transmitted command was a read command the slave device responds by sending the requested data. the data structure of the transmitted monitor message depends on the device which is programmed. therefore the first byte of the message is a specific address code which contains in the higher nibble a monitor channel address to identify different devices. the length of the messages depends on the accessed device and the type of monitor command. 3.7.3.4 monitor channel programming as a slave device in applications without direct host controller connection the isac-sx te must operate in the monitor slave mode which can be selected by pinstrapping the microcontroller interface pins according table 3 respectively in chapter 3.2 . as a slave device the transceiver part of the isac-sx te is programmed and controlled by a master device at the iom-2 interface. all programming data required by the isac-sx te is received in the monitor timeslot on the iom-2 and is transferred in the mor register. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter 3.7.3.1 . the first byte of the monitor message must contain in the higher nibble the monitor channel address code which is ?1010? for the isac-sx te. the lower nibble distinguishes between a programming command or an identification command. identification command in order to be able to identify unambiguously different hardware designs of the isac-sx te by software, the following identification command is used: the isac-sx te responds to this dd identification sequence by sending a du identification sequence: design:six bit code, specific for each device in order to identify differences in operation dd 1st byte value 10100000 dd 2nd byte value 00000000
isac-sx te psb 3186 description of functional blocks data sheet 92 2003-01-30 e.g. 000001 isac-sx te psb 3186 v 1.4 this identification sequence is usually done once, when the terminal is connected for the first time. this function is used so that the software can distinguish between different possible hardware configurations. however this sequence is not compulsory. programming sequence the programming sequence is characterized by a ?1? being sent in the lower nibble of the received address code. the data structure after this first byte and the principle of a read/ write access to a register is similar to the structure of the serial control interface described in chapter 3.2.1.1 . for write access the header 43 h /47 h can be used and for read access the header 40 h /44 h . all registers can be read back when setting the r/w bit in the byte for the command/ register address. the isac-sx te responds by sending its iom-2 specific address byte (a1 h ) followed by the requested data. note: application hint: it is not allowed to disable the mx- and mr-control in the programming device at the same time! first, the mx-control must be disabled, then the c has to wait for an end of reception before the mr-control may be disabled. otherwise, the isac-sx te does not recognize an end of reception. 3.7.3.5 monitor time-out procedure to prevent lock-up situations in a monitor transmission a time-out procedure can be enabled by setting the time-out bit (tout) in the monitor configuration register (mconf). an internal timer is always started when the transmitter must wait for the reply of the addressed device. after 5 ms without reply the timer expires and the transmission will be aborted with a eom (end of message) command by setting the mx bit to ?1? for two consecutive iom-2 frames. du 1st byte value 10100000 du 2nd byte value 0 1 design dd 1st byte value 10100001 dd 2nd byte value header byte dd 3rd byte value r/w register address dd 4th byte value data 1 dd (nth + 3) byte value data n
isac-sx te psb 3186 description of functional blocks data sheet 93 2003-01-30 3.7.3.6 monitor interrupt logic figure 52 shows the monitor interrupt structure of the isac-sx te. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable ( mre ) and mr bit control ( mrc ). the monitor channel end of reception mer , monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie . mre prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is active (1) but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. (additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol.) figure 52 monitor interrupt structure 3.7.4 c/i channel handling the command/indication channel carries real-time status information between the isac-sx te and another device connected to the iom-2 interface. 1) one c/i channel (called c/i0) conveys the commands and indications between the layer-1 and the layer-2 parts of the isac-sx te. it can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. c/i0 channel access may be arbitrated via the tic bus acce ss protocol. in this case the arbitration is done in iom-2 channel 2 (see figure 36 ). the c/i0 channel is accessed via register cir0 (in receive direction, layer-1 to layer-2) and register cix0 (in transmit direction, layer-2 to layer-1). the c/i0 code is four bits long. a listing and explanation of the layer-1 c/i codes can be found in chapter 3.5.2 . in the receive direction, the code from layer-1 is continuously monitored, with an interrupt st mos tran icd cic wov interrupt ista mask st mos tran icd cic wov mre mdr mie mda mer mab mosr mocr
isac-sx te psb 3186 description of functional blocks data sheet 94 2003-01-30 being generated anytime a change occurs (ista.cic). a new code must be found in two consecutive iom-2 frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix0 is continuously transmitted in c/i0. 2) a second c/i channel (called c/i1) can be used to convey real time status information between the isac-sx te and various non-layer-1 peripheral devices e.g. psb 2161 arcofi-ba. the c/i1 channel consists of four or six bits in each direction.the width can be changed from 4bit to 6bit by setting bit cix1.cicw. in 4-bit mode 6-bits are written whereby the higher 2 bits must be set to ?1? and 6-bits are read whereby only the 4 lsbs are used fo r comparison and interrupt generation (i.e. the higher two bits are ignored). the c/i1 channel is accessed via registers cir1 and cix1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. cic interrupt logic figure 53 shows the cic interrupt structure. a cic interrupt may originate ? from a change in received c/i channel 0 code (cic0) or ? from a change in received c/i channel 1 code (cic 1). the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e in the cix1 register. in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. the cir0 is buffered with a fifo size of two. if a second code change occurs in the received c/i channel 0 before the first one has been read, immediately after reading of cir0 a new interrupt will be generated and the new code will be stored in cir0. if several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. for cir1 no fifo is available. the actual code of the received c/i channel 1 is always stored in cir1.
isac-sx te psb 3186 description of functional blocks data sheet 95 2003-01-30 figure 53 cic interrupt structure 3.7.5 d-channel access control d-channel access control is defined to guarantee all connected tes and hdlc controllers a fair chance to transmit data in the d-channel. collisions are possible on the iom-2 interface if there is more than one hdlc controller connected or on the s-interface when there is more than one terminal connected in a point to multipoint configuration (nt te1 ? te8). both arbitration mechanisms are implemented in the isac-sx te and will be described in the following two chapters. 3.7.5.1 tic bus d-channel access control the tic bus is imlemented to organize the access to the layer-1 functions provided in the isac-sx te (c/i-channel) and to the d-channel from up to 7 external communication controllers ( figure 54 ). note: if the tic bus feature is not used, it has to be switched off in order not to disturb the layer-1 control and the hdlc controller. this is done by setting bit dim 1 in register mode d and bit 4 in register iom_cr. for more details please refer to the application note ?reconfigurable pbx?. to this effect the outputs of the d-channel controllers (e.g. icc - isdn communication controller peb 2070) are wired-or (negative logic, i.e. a ?0? wins) and connected to pin du. the inputs of the iccs are connected to pin dd. external pull-up resistors on du/ dd are required. the arbitration mechanism must be activated by setting moded.dim2-0=00x. st mos tran icd cic wov interrupt ista mask cic1 ci1e cic0 cir0 cix1 mos tran wov st icd cic
isac-sx te psb 3186 description of functional blocks data sheet 96 2003-01-30 figure 54 applications of tic bus in iom-2 bus configuration the arbitration mechanism is implemented in the last octet in iom-2 channel 2 of the iom-2 interface ( figure 55 ). an access request to the tic bus may either be generated by software (p access to the c/i channel) or by the isac-sx te itself (transmission of an hdlc frame in the d-channel). a software access request to the bus is effected by setting the bac bit (cix0 register) to ?1?. in the case of an access request, the isac-sx te checks the bus accessed-bit bac (bit 5 of last octet of ch2 on du, figure 55 ) for the status "bus free?, which is indicated by a logical ?1?. if the bus is free, the isac-sx te transmits its individual tic bus address tad programmed in the cix0 register (cix0.tba2-0). the isac-sx te sends its tic bus address tad and compares it bit by bit with the value on du. if a sent bit set to ?1? is read back as ?0? because of the access of another d-channel source with a lower tad, the isac-sx te withdraws immediately from the tic bus, i.e. the remaining tad bits are not transmitted. the tic bus is occupied by the device which sends its address error- free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. this one will set bac=0 on tic bus and starts d-channel transmission in the same frame. 3086_09 icc (7) icc (2) icc (1) . . . d-channel control s- transceiver nt tic-bus on iom-2 s-interface u-interface
isac-sx te psb 3186 description of functional blocks data sheet 97 2003-01-30 figure 55 structure of last octet of ch2 on du when the tic bus is seized by the isac-sx te, the bus is identified to other devices as occupied via the du ch2 bus accessed-bit state ?0? until the access request is withdrawn. after a successful bus access, the isac-sx te is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. if none of the devices connected to the iom-2 interface request access to the d and c/ i channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. note: bit bac (cix0 register) should be reset by the p when access to the c/i channels is no more requested, to grant other devices access to the d and c/i channels. 3.7.5.2 s-bus priority mechanism for d-channel the s-bus access procedure specified in itu i.430 was defined to organize d-channel access with multiple tes connected to a single s-bus ( figure 57 ). to implement collision detection the d (channel) and e (echo) bits are used. the d-channel s-bus condition is indicated towards the iom-2 interface with the s/g bit, i.e. the availability of the s/t interface d channel is indicated in bit 5 "stop/go" (s/g) of the dd last octet of ch2 channel ( figure 56 ). s/g = 1 : stop s/g = 0 : go d u
isac-sx te psb 3186 description of functional blocks data sheet 98 2003-01-30 figure 56 structure of last octet of ch2 on dd the stop/go bit is available to other layer-2 devices connected to the iom-2 interface to determine if they can access the s/t bus d channel. the access to the d-channel is controlled by a priority mechanism which ensures that all competing tes are given a fair access chance. this priority mechanism discriminates among the kind of information exchanged and information exchange history: layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). furthermore, once a te having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. the te is given back its normal level within a priority class when all tes have had an opportunity to transmit information at the normal level of that priority class. the priority mechanism is based on a rather simple method: a te not transmitting layer-2 frames sends binary 1s on the d-channel. as layer-2 frames are delimited by flags consisting of the binary pattern ?01111110? and zero bit insertion is used to prevent flag imitation, the d-channel may be considered idle if more than seven consecutive 1s are detected on the d-channel. hence by monitoring the d echo channel, the te may determine if the d-channel is currently used by another te or not. a te may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. this number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. a te, when in the active condition, is monitoring the d echo channel, counting the number of consecutive binary 1s. if a 0 bit is detected, the te restarts counting the number of consecutive binary 1s. if the required number of 1s according to the actual level of priority has been detected, the te may start transmission of an hdlc frame. if a collision occurs, the te immediately shall cease transmission, return to the d-channel monitoring state, and send 1s over the d-channel. itd09693 d ci1 mon1 ic2 ic1 ci0 mon0 b2 b1 mr mx mx mr s/g a/b a/b s/g stop/go available/blocked dd e e
isac-sx te psb 3186 description of functional blocks data sheet 99 2003-01-30 figure 57 d-channel access control on the s-interface s-bus d-channel access control in the isac-sx te the above described priority mechanism is fully implemented in the isac-sx te. for this purpose the d-channel collission detection according to itu i.430 must be enabled by setting moded.dim2-0 to ?0x1?. in this case the transceiver continuously compares the received e-echo bits with its own transmitted d data bits. depending on the priority class selected, 8 or 10 consecutive ones (high priority level, priority 8) need to be detected before the transceiver sends valid d-channel data on the upstream d-bits on s. in low priority level (priority 10) 10 or 11 consecutive ones are required. the priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the command/indication (c/i) channel of the iom-2 interface to the transceiver. if the activation is initiated by a te, the priority class is selected implicitly by the choice of the activation command. if the s-interface is activated from the nt, an activation command selecting the desired priority class should be programmed at the te on reception of the activation indication (ai8 or ai10). in the activated state the priority class may be changed whenever required by simply programming the desired activation request command (ar8 or ar10). 3086_10 d-channel control s- transceiver d-channel control s- transceiver nt s-interface d-bits d-channel control s- transceiver e-bits u-interface . . . te 1 te 2 te 8
isac-sx te psb 3186 description of functional blocks data sheet 100 2003-01-30 3.7.6 activation/deactivation of iom-2 interface the iom-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. in this deactivated state is fsc = ?1?, dcl and bcl = ?0? and the data lines are ?1?. the iom-2 interface can be kept active while the s interface is deactivated by setting the cfs bit to "0" (mode1 register). this is the case after a hardware reset. if the iom-2 interface should be switched off while the s interface is deactivated, the cfs bit should be set to ?1?. in this case the internal oscillator is disabled when no signal (info 0) is present on the s bus and the c/i command is ?1111? = diu. if the te wants to activate the line, it has first to activate the iom-2 interface either by using the "software power up" function (iom_cr.spu bit) or by setting the cfs bit to "0" again. the deactivation procedure is shown in figure 58 . after detecting the code diu (deactivate indication upstream) the layer 1 of the isac-sx te responds by transmitting did (deactivate indication downstream) during subsequent frames and stops the timing signals synchronously with the end of the last c/i (c/i0) channel bit of the fourth frame. figure 58 deactivation of the iom-2 interface the clock pulses will be enabled again when the du line is pulled low (bit spu in the iom_cr register), i.e. the c/i command tim = "0000" is received by layer 1, or when a non-zero level on the s-line interface is detected (if tr_conf0.ldd=0). the clocks are turned on after approximately 0.2 to 4 ms depending on the oscillator. dcl is activated such that its first rising edge occurs with the beginning of the bit following the c/i (c/i0) channel. iom -2 deactivated dc dc dc dc di di di di di di di di di b1 b2 d cio d cio dcl dd du fsc iom -2 itd09655_s.vsd dr dr dr dr dr
isac-sx te psb 3186 description of functional blocks data sheet 101 2003-01-30 after the clocks have been enabled this is indicated by the pu code in the c/i channel and, consequently, by a cic interrupt. the du line may be released by resetting the software power up bit iom_cr =?0? and the c/i code written to cix0 before (e.g. tim or ar8) is output on du. the isac-sx te supplies iom-2 timing signals as long as there is no diu command in the c/i (c/i0) channel. if timing signals are no longer required and activation is not yet requested, this is indicated by programming diu in the cix0 register. figure 59 activation of the iom-2 interface itd09656 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ fsc du dd fsc du dd dcl spu = 1 spu = 0 cic : cixo = tim int. tim pu b1 b1 mx mr 0.2 to 4 ms 132 x dcl tim tim pu pu pu pu r iom -ch1 r iom -ch2 iom -ch2 r iom r -ch1
isac-sx te psb 3186 description of functional blocks data sheet 102 2003-01-30 3.8 hdlc controller the isac-sx te contains an hdlc controller for the layer-2 functions of the d- channel protocol (lapd). by setting the enable hdlc channel bits (d_en_x) in the dci_cr register the hdlc controller can access the d or b-channels on iom-2. it performs the framing functions used in hdlc based communication: flag generation/ recognition, bit stuffing, crc check and address recognition. the fifo has a size of 64 byte per direction and is implemented as cyclic buffers. the transceiver reads and writes data sequentially with constant data rate whereas the data transfer between fifo and microcontroller uses a block oriented protocol with variable block sizes. the configuration, control and status bits related to the hdlc controller are all assigned to the following address ranges: note: for d-channel access the address range 00 h -1f h is used (similar as in isac-s te psb 2186), however a single address from this range is sufficient to access the fifo as the internal fifo pointer is incremented automatically independent from the external address. 3.8.1 message transfer modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus the receive data flow and the address recognition features can be programmed in a flexible way to satisfy different system requirements. the structure of a d-channel two-byte address (lapd) is shown below: for address recognition on the d-channel the isac-sx te contains four programmable registers for individual sapi and tei values (sap1, 2 and tei1, 2), plus two fixed values for the ?group? sapi (sapg = ?fe? or ?fc?) and tei (teig = ?ff?). the received c/r bit is excluded from the address comparison. ea is the address field extension bit which must be set to ?1? according to hdlc lapd. table 14 hdlc controller address range fifo address config/ctrl/status registers d-channel hdlc 00 h -1f h 20 h -29 h high address byte low address byte sapi1, 2, sapg c/r 0 tei 1, 2, teig ea
isac-sx te psb 3186 description of functional blocks data sheet 103 2003-01-30 operating modes there are 5 different operating modes which can be selected via the mode selection bits mds2-0 in the moded registers: non-auto mode (mds2-0 = ?01x?) characteristics: full address recognition with one-byte (mds = ?010?) or two-byte (mds = ?011?) address comparison all frames with valid addresses are accepted and the bytes following the address are transferred to the p via rfifod. additional information is available in rstad. transparent mode 0 (mds2-0 = ?110?). characteristics: no address recognition every received frame is stored in rfifod (first byte after opening flag to crc field). additional information can be read from rstad. transparent mode 1 (mds2-0 = ?111?). characteristics: sapi recognition a comparison is performed on the first byte after the opening flag with sap1, sap2 and ?group? sapi (fe h /fc h ). in the case of a match, all the following bytes are stored in rfifod. additional information can be read from rstad. transparent mode 2 (mds2-0 = ?101?). characteristics: tei recognition a comparison is performed only on the second byte after the opening flag, with tei1, tei2 and group tei (ff h ). in case of a match the rest of the frame is stored in the rfifod. additional information is available in rstad. extended transparent mode (mds2-0 = ?100?). characteristics: fully transparent in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/ check, bitstuffing mechanism. this allows user specific protocol variations. also refer to chapter 3.8.5 .
isac-sx te psb 3186 description of functional blocks data sheet 104 2003-01-30 3.8.2 data reception 3.8.2.1 structure and control of the receive fifo the cyclic receive fifo buffer with a length of 64 byte has a variable fifo block size (threshold) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding rfbs bits in the exmd register. the variable block size allows an optimized hdlc processing concerning frame length, i/o throughput and interrupt load. the transfer protocol between hdlc fifo an d microcontroller is block oriented with the microcontroller as master. the control of the data transfer between the cpu and the isac-sx te is handled via interrupts (isac-sx te host) and commands (host isac-sx te). there are three different interrupt indication s in the istad registes concerned with the reception of data: ? rpf ( r eceive p ool f ull) interrupt, indicating that a data block of the selected length (exmd.rfbs) can be read from rfifod. the message which is currently received exceeds the block size so further blocks will be received to complete the message. ? rme ( r eceive m essage e nd) interrupt, indicating that the reception of one message is completed, i.e. either a short message is received (message length the defined block size (exmd.rfbs)) or the last part of a long message is received (message length the defined block size (exmd.rfbs)) and is stored in the rfifox. ? rfo ( r eceive f rame o verflow) interrupt, indicating that a complete frame could not be stored in rfifod and is therefore lost as the rfifod is occupied. this occurs if the host fails to respond quickly enough to rpf/rme interrupts since previous data was not read by the host. there are two control commands that are used with the reception of data: ? rmc ( r eceive m essage c omplete) command, telling the isac-sx te that a data block has been read from the rfifod and the corresponding fifo space can be released for new receive data. ? rres ( r eceiver r eset) command, resetting the hdlc receiver and clearing the receive fifo of any data (e.g. used before start of reception). it has to be used after a change of the message transfer mode. pending interrupt indications of the receiver are not cleared by rres, but have to be cleared by reading these interrupts. note: the significant interrupts and commands are underlined as only these are commonly used during a normal reception sequence. the following description of the receive fifo operation is illustrated in figure 60 for a rfifod block size (threshold) of 16 and 32 bytes.
isac-sx te psb 3186 description of functional blocks data sheet 105 2003-01-30 the rfifod requests service from the microcontroller by setting a bit in the istad register, which causes an interrupt (rpf, rme, rfo). the microcontroller then reads status information (rbchd,rbcld), data from the rfifod and then may change the receive fifo block size (exmd.rfbs). a block transfer is completed by the microcontroller via a receive message complete (cmdrd.rmc) command. this causes the space of the transferred bytes being released for new data and in case the frame was complete (rme) the reset of the receive byte counter rbc (rbchd,rbcld) 1) . the total length of the frame is contained in the rbchd and rbcld registers which contain a 12 bit number (rbc11...0), so frames up to 4095 byte length can be counted. if a frame is longer than 4095 bytes, the rbchd.ov (overflow) bit will be set. the least significant bits of rbcld contain the number of valid bytes in the last data block indicated by rme (length of last data block selected block size). table 15 shows which rbc bits contain the number of bytes in the last data block or number of complete data blocks respectively. if the number of bytes in the last data block is ?0? the length of the last received block is equal to the block size. the transfer block size (exmd.rfbs) is 32 bytes by default. if it is necessary to react to an incoming frame within the first few bytes the microcontroller can set the rfifod block size to a smaller value. each time a cmdrd.rmc or cmdrd.rres command is issued, the rfifod access controller sets its block size to the value specified in exmd.rfbs, so the microcontroller has to write the new value for rfbs before the rmc command. when setting an initial value for rfbs before the first hdlc activities, a rres command must be issued afterwards. the rfifod can hold any number of frames fitting in the 64 bytes. at the end of a frame, the rstad byte is always appended. all generated interrupts are inserted together with all additional information into a wait line to be individually passed to the host. for example if several data blocks have been received to be read by the host and the host acknowledges the current block, a new rpf or rme interrupt from the wait line is immediately generated to indicate new data. 1) if rmc is omitted, then no new interrupt can be generated. table 15 receive byte count with rbc1 1...0 in the rbchd/rbcld registers exmd1.rfbs selected block size number of complete data blocks in bytes in the last data block in ?00? 32 byte rbc11...5 rbc4...0 ?01? 16 byte rbc11...4 rbc3...0 ?10? 8 byte rbc11...3 rbc2...0 ?11? 4 byte rbc11...2 rbc1...0
isac-sx te psb 3186 description of functional blocks data sheet 106 2003-01-30 figure 60 rfifo operation hdlc receiver 32 16 8 4 rpf rfifo p rbc=4h ram hdlc receiver rfifo access controller 32 16 8 4 rfbs=01 ram exmd.rfbs=01 rmc exmd.rfbs=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt istad.rpf the p has read the 4 bytes, sets rfbs=01 (16 bytes) and completes the block transfer by an cmdrx.rmc command. following cmdrx.rmc the 4 bytes of the last block are deleted. rfacc rfacc is set. rfifo access controller rfbs=11 hdlc receiver 32 16 8 rpf rfifo p rbc=14h ram rsta rsta rsta the hdlc receiver has written further data into the fifo. when a frame is complete, a status byte (rstad) is appended. when the rfacc detects 16 valid bytes, it sets an rpf interrupt. the p reads the 16 bytes hdlc receiver 32 16 8 rme rfifo rbc=16h ram rsta rsta rsta after the rmc acknowledgement the the frame, therefore it asserts an rme interupt and increments the rbc counter by 2. rmc rfacc rfacc meanwhile two more short frames have been received. and acknowledges the transfer by setting cmdrd.rmc. this causes the space occupied by the 16 bytes being released. p rfifo access controller rfbs=01 rfifo access controller rfbs=01 rfacc detects an rsta byte, i.e. end of
isac-sx te psb 3186 description of functional blocks data sheet 107 2003-01-30 possible error conditions during reception of frames if parts of a frame get lost because the receive fifo is full, the receive data overflow (rdo) byte in the rstad byte will be set. if a complete frame is lost, i.e. if the fifo is full when a new frame is received, the receiver will assert a receive frame overflow (rfo) interrupt. the microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it reads the same data again and again. on the other hand, if it doesn?t read or doesn?t want to read all data, they are deleted anyway after the rmc command. if the microcontroller reads data without a pr ior rme or rpf interrupt, the content of the rfifod would not be corrupted, but new data is only transferred to the host as long as new valid data is available in the rfifod, otherwise the last data is read again and again. the general procedures for a data reception sequence are outlined in the flow diagram in figure 61 .
isac-sx te psb 3186 description of functional blocks data sheet 108 2003-01-30 figure 61 data reception procedures figure 62 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. the fifo threshold (block size) is set to 32 byte in this example: after 32 byte of frame 1 have been received an rpf interrupt is generated to indicate that a data block can be read from the rfifod. xx hdlc_rflow.vsd start receive message end rme ? receive pool full rpf ? read counter rd_count := rfbs or rd_count := rbc read rd_count bytes from rfifo receive message complete write rmc change block size write exmr.rfbs (optional) read rbc rd_count := rbc y y n n * 1) rbc = rbch + rbcl register rfbs: refer to exmr register in case of rme the last byte in rfifo contains the receive status information rsta * 1)
isac-sx te psb 3186 description of functional blocks data sheet 109 2003-01-30 the host reads the first data block from rfifod and acknowledges the reception by rmc. meanwhile the second data block is received and stored in rfifod. the second 32 byte block is indicated by rpf which is read and acknowledged by the host as described before. the reception of the remaining 4 bytes plus rstad are indicated by rme (i.e. the receive status is always appended to the end of the frame). the host gets the number of bytes (count = 5) from rbcld/rbchd and reads out the rfifod and optionally the status register rsta. the frame is acknowledged by rmc. the second frame is received and indicated by rme interrupt. the host gets the number of bytes (count = 13) from rbcld/rbchd and reads out the rfifod and optionally the status register. the rfifod is acknowledged by rmc. the third frame is transferred in the same way. figure 62 reception sequence example 3.8.2.2 receive frame structure the management of the received hdlc frames as affected by the different operating modes (see chapter 3.8.1 ) is shown in figure 63 . fifoseq_rec.vsd * 1) the last byte contains the receive status information rmc rpf rme rpf rmc rme rmc rmc rmc rme iom interface cpu interface receive frame 68 bytes 12 bytes 12 bytes 32 412 12 32 rd count rd 13 bytes * 1) rd count rd 13 bytes * 1) rd count rd 5 bytes * 1) rd 32 bytes rd 32 bytes
isac-sx te psb 3186 description of functional blocks data sheet 110 2003-01-30 figure 63 receive data flow the isac-sx te indicates to the host that a new data block can be read from the rfifod by means of an rpf interrupt (see previous chapter). user data is stored in the rfifod and information about the received frame is available in the rbcld and rbchd registers and the rsta d byte which are listed in table 16 . the rstad register is always appended in the rfifod as last byte to the end of a frame. note: the number of bytes received in rfifod depends on the selected receive fifo threshold (exmd.rfbs). i 3186_13 addr flag ctrl crc flag address control data status rstad rfifod *1) sap1 sap2 sapg *2) tei1 tei2 teig *2) non auto/16 mode 0 1 1 mds2 mds1 mds0 rfifod _ *3) non auto/8 0 1 0 tei1 tei2 *2) rfifod transparent 0 1 1 0 rfifod 1 1 1 transparent 1 sap1 sap2 sapg *2) rfifod tei1 tei2 teig *2) 1 0 1 transparent 2 compared with registers description of symbols: stored in fifo/registers *1) crc optionally stored in rfifod if exmd:rcrc=1 *2) address optionally stored in rfifod if exmd:sra=1 *3) start of the control field in case of an 8 bit address *4) content of rsta register appended at the frameend into rfifod *4) rstad *1) *4) rstad *1) *4) rstad *1) *4) rstad *1) *4)
isac-sx te psb 3186 description of functional blocks data sheet 111 2003-01-30 table 16 receive information at rme interrupt information register bit mode type of frame (command/ response) rstad c/r non-auto mode, 2-byte address field transparent mode 1 recognition of sapi rstad sa1, 0 non-auto mode, 2-byte address field transparent mode 1 recognition of tei rstad ta all except transparent mode 0 result of crc check (correct/incorrect) rstad crc all valid frame rstad vfr all abort condition detected (yes/no) rstad rab all data overflow during reception of a frame (yes/no) rstad rdo all number of bytes received in rfifo rbcl rbc4-0 all message length rbcld rbchd rbc11-0 all rfifo overflow rbchd ov all
isac-sx te psb 3186 description of functional blocks data sheet 112 2003-01-30 3.8.3 data transmission 3.8.3.1 structure and control of the transmit fifo the cyclic transmit fifo buffer with a length of 64 byte has a variable fifo block size (threshold) of 16 or 32 bytes (programmabl e) which can be selected by setting the corresponding xfbs bits in the exmd register. there are three different interrupt indications in the istad register concerned with the transmission of data: ? xpr ( t ransmit p ool r eady) interrupt, indicating that a data block of up to 16 or 32 byte can be written to the xfifod (fixed block size). an xpr interrupt is generated either after an xres (transmitter reset) command (which is issued for example for frame abort) or when a data block from the xfifod is transmitted and the corresponding fifo space is released to accept further data from the host. ? xdu ( t ransmit d ata u nderrun) interrupt, indicating that the transmission of the current frame has been aborted (seven consecutive ?1?s are transmitted) as the xfifod holds no further transmit data. this occurs if the host fails to respond to an xpr interrupt quickly enough. ? xmr ( t ransmit m essage r epeat) interrupt, indicating that the transmission of the complete last frame has to be repeated as a collision on the s bus has been detected and the xfifox does not hold the first data bytes of the frame (collision after the 16th/ 32nd byte or after the 32nd byte of the frame, respectively). the occurence of an xdu or xmr interrupt clears the xfifod and an xmr interrupt is issued together with an xdu or xmr interrupt, respectively. data cannot be written to the xfifod as long as an xdu/xmr interrupt is pending. three different control commands are used for transmission of data: ? xtf ( t ransmit t ransparent f rame) command, telling the isac-sx te that up to 16 or 32 byte have been written to the xfifod and should be transmitted. a start flag is generated automatically. ? xme ( t ransmit m essage e nd) command, telling the isac-sx te that the last data block written to the xfifod completes the corresponding frame and should be transmitted. this implies that according to the selected mode a frame end (crc + closing flag) is generated and appended to the frame. ? xres ( t ransmitter r eset) command, resetting the hdlc transmitter and clearing the transmit fifo of any data. after an xres command the transmitter always sends an abort sequence, i.e. this command can be used to abort a transmission. pending interrupt indications of the transmitter are not cleared by xres, but have to be cleared by reading these interutps. optionally two additional status conditions can be read by the host:
isac-sx te psb 3186 description of functional blocks data sheet 113 2003-01-30 ? xdov ( t ransmit d ata o verflow), indicating that the data block size has been exceeded, i.e. more than 16 or 32 byte were entered and data was overwritten. ? xfw ( t ransmit f ifo w rite enable), indicating that data can be written to the xfifod. this status flag may be polled instead of or in addition to xpr. note: the significant interrupts and commands are underlined as only these are usually used during a normal transmission sequence. the xfifod requests service from the microcontroller by setting a bit in the istad register, which causes an interrupt (xpr, xdu, xmr). the microcontroller can then read the status register stard (xfw, xdov), write data in the fifo and it can change the transmit fifo block size (exmd.xfbs) if required. the instant of the initiation of a transmit pool ready (xpr) interrupt after different transmit control commands is listed in table 17 . when setting xme the transmitter appends the crc and the endflag at the end of the frame. when xtf & xme has been set, the xfifod is locked until successful transmission of the current frame, so a consecutive xpr interrupt also indicates successful transmission of the frame whereas after xme or xtf the xpr interrupt is asserted as soon as there is space for one data block in the xfifod. the transfer block size is 32 bytes for d- and b-channel by default, but sometimes, if the microcontroller has a high computational load, it is useful to increase the maximum reaction time for an xpr interrupt. however, the threshold can only be changed for d-channel. the maximum reaction time is: t max = (xfifod size - xfbs) / data transmission rate with a selected block size of 16 bytes an xpr interrupt indicates when a transmit fifo space of at least 16 bytes is available to accept further data, i.e. there are still a maximum of 48 bytes (64 bytes - 16 bytes) to be transmitted. with a 32 bytes block size the xpr is initiated when a transmit fifo space of at least 32 bytes is available to accept further data, i.e. there are still a maximum of 32 bytes (64 bytes - 32 bytes) to be transmitted. the maximum reaction time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt load. with a selected block size an xpr always indicates the table 17 xpr interrupt (availability of xfifod) after xtf, xme commands cmdrd register transmit pool ready (xpr) interrupt initiated ... xtf as soon as the selected buffer size in the xfifod is available. xtf & xme after the successful transmission of the closing flag. the transmitter always sends an abort sequence. xme as soon as the selected buffer size in the fifo is available, two consecutive frames share flags.
isac-sx te psb 3186 description of functional blocks data sheet 114 2003-01-30 available space in the xfifod, so any number of bytes smaller than the selected xfbs may be stored in the fifo during one ?write block? access cycle. similar to rfbs for the receive fifo, a new setting of xfbs takes effect after the next xtf, xme or xres command. xres resets the xfifod. the xfifod can hold any number of frames fitting in the 64 bytes. possible error conditions during transmission of frames if the transmitter sees an empty fifo, i.e. if the microcontroller doesn?t react fast enough to an xpr interrupt, an xdu (transmit data underrun) interrupt will be generated. if the hdlc channel becomes unavailable during transmission the transmitter tries to repeat the current frame as specified in the lapd protocol. this is impossible after the first data block has been sent (16 or 32 bytes), in this case an xmr transmit message repeat interrupt is set and the microcontroller has to send the whole frame again. both xmr and xdu interrupts cause a reset of the xfifod. the xfifod is locked while an xmr or xdu interrupt is pending, i.d. all write actions of the microcontroller will be ignored as long as the microcontroller hasn?t read the istad register with the set xdu, xmr interrupts. if the microcontroller writes more data than allowed (block size), then the data in the xfifod will be corrupted and the stard.xdov bit is set. if this happens, the microcontroller has to abort the transmission by cmdrd.xres and start new. the general procedures for a data transmission sequence are outlined in the flow diagram in figure 64 .
isac-sx te psb 3186 description of functional blocks data sheet 115 2003-01-30 figure 64 data transmission procedure the following description gives an example for the transmission of a 76 byte frame with a selected block size of 32 byte: the host writes 32 bytes to the xfifod, issues an xtf command and waits for an xpr interrupt in order to continue with entering data. the isac-sx te immediately issues an xpr interrupt (as remaining xfifod space is not used) and starts transmission. due to the xpr interrupt the host writes the next 32 bytes to the xfifod, followed by the xtf command, and waits for xpr. as soon as the last byte of the first block is transmitted, the isac-sx te releases an xpr (xfifod space of first data block is free again) and continues transmitting the second block. the host writes the remaining 12 bytes of the frame to the xfifod and issues the xtf command together with xme to indicate that this is the end of frame. after the last byte of the frame has been transmitted the isac-sx te releases an xpr interrupt and the host may proceed with transmission of a new frame. 21150_25 start transmit pool ready xpr ? command xtf+xme write one data block to xfifo n y y n end of message ? end command xtf
isac-sx te psb 3186 description of functional blocks data sheet 116 2003-01-30 figure 65 transmission sequence example 3.8.3.2 transmit frame structure the transmission of transparent frames (xtf command) is shown in figure 66 . for transparent frames, the whole frame including address and control field must be written to the xfifod. the host confi gures whether the crc is generated and appended to the frame (default) or not (selected in exmd.xcrc). further, the host selects the interframe time fill signal which is transmitted between hdcl frames (exmd.itf). one option is to send continuous flags (?01111110?), however if d-channel access handling (collision resolution on the s bus) is required, the signal must be set to idle (continuous ?1?s are transmitted). reprogramming of itf takes effect only after the transmission of the current frame has been completed or after an xres command. figure 66 transmit data flow transmit frame 76 bytes fifoseq_tran.vsd iom interface cpu interface wr 32 bytes xtf 32 12 32 xpr xpr wr 32 bytes xtf wr 12 bytes xtf+xme xpr flag fifoflow_tran.vsd transmit transparent frame (xtf) ctrl crc flag i address control data checkram addr * 1) xfifo * 1) the crc is generated by default. if exmr.xcrc is set no crc is appended
isac-sx te psb 3186 description of functional blocks data sheet 117 2003-01-30 3.8.4 access to iom-2 channels by setting the enable hdlc data bits (d_en_d, d_en_b1, d_en_b2) in the dci_cr register the hdlc controller can access the d, b1 and b2 channels or any combination of them. in all modes (except extended transparent mode) transmission always works frame aligned, i.e. it starts with the first selected channel, whereas reception searches for a flag anywhere in the serial data stream. 3.8.5 extended transparent mode this non-hdlc mode is selected by setting mode2...0 to ?100?. in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/check, bitstuffing mechanism. this allows user specific protocol variations. transmitter the transmitter sends the data out of the fifo without manipulation. transmission is always iom-2 frame aligned and byte aligned, i.e. transmission starts in the first selected channel (b1, b2, d, according to the setting of register dci_cr in the iom-2 handler) of the next iom-2 frame. the fifo indications and commands are the same as in other modes. if the microcontroller sets xtf & xme the transmitter responds with an xpr interrupt after sending the last byte, then it returns to its idle state (sending continuous ?1?). if the collision detection is enabled in d-channel (mode.dim = ?0x1?) the stop go bit (s/ g) can be used as clear to send indication as in any other mode. if the s/g bit is set to ?1? (stop) during transmission the transmitter responds always with an xmr (transmit message repeat) interrupt. if the microcontroller fails to respond to a xpr interrupt in time and the transmitter runs out of data then it will assert an xdu (transmit data underrun) interrupt. receiver the reception is iom-2 frame aligned and byte aligned, like transmission, i.e. reception starts in the first selected channel (b1, b2, d, according to the setting of registers dci_cr in the iom-2 handler) of the next iom-2 frame. the fifo indications and commands are the same as in others modes. all incoming data bytes are stored in the rfifod and is additionally made available in rstad. if the fifo is full an rfo interrupt is asserted (exmd.sra = ?0?). note: in the extended transparent mode the exmd register has to be set to ?xxx00000?
isac-sx te psb 3186 description of functional blocks data sheet 118 2003-01-30 3.8.6 hdlc controller interrupts the cause of an interrupt related to the hdlc controller is indicated in the ista register by the icd bit. this bit points to the interrupt source of the d-channel hdlc controller in the istad register. the individual interrupt sources of the hdlc controllers during reception and transmission of data are explained in chapter 3.8.2.1 or chapter 3.8.3.1 respectively. figure 67 interrupt status registers of the hdlc controllers each interrupt source in the istad register can selectively be masked by setting the corresponding bit in maskd to ?1?. icd mos tran aux cic st icd mos tran aux cic st xdu xmr xpr rfo rpf rme maskd xdu xmr xpr rfo rpf rme istad mask ista 3186_16.vsd interrupt d-channel
isac-sx te psb 3186 description of functional blocks data sheet 119 2003-01-30 3.9 test functions the isac-sx te provides test and diagnostic functions for the s-interface and the d- channel: digital loop via tlp (test loop, tmd register) command bit ( figure 68 ): the tx path of layer 2 is internally connected with the rx path of layer 2. the output from layer 1 (s/t) on dd is ignored. this is used fo r testing isac-sx te functionality excluding layer 1 (loopback between xfifod and rfifod). figure 68 layer 2 test loops tmd.tlp = ?1? tmd.tlp = ?0?
isac-sx te psb 3186 description of functional blocks data sheet 120 2003-01-30 test of layer-2 functions while disabling all layer-1 functions and pins associated with them (including clocking) via bit tr_conf0.dis_tr. the hdlc controllers can still operate via iom-2. dcl and fsc pins become input. loop at the analog end of the s interface; transmission of special test signals on the s/t interface according to the modified ami code are initiated via a c/i command written in cix0 register. test loop 3 is activated with the c/i channel command activate request loop (arl). an s interface is not required since info3 is looped back internally to the receiver. when the receiver has synchronized itself to this signal, the message "test indication" (or "awake test indication") is delivered in the c/i channel. no signal is transmitted over the s interface. in the test loop mode the s interface awake detector is enabled, i.e. if a level is detected (e.g. info 2/info 4) this will be reported by the resynchronization indication (rsy). the loop function is not effected by this condition and the internally generated 192-khz line clock does not depend on the signal received at the s interface. two kinds of test signals may be sent by the isac-sx te: ? single pulses and ? continuous pulses. the single pulses are of alternating polarity, one s interface bit period wide, 0.25 ms apart, with a repetition frequency of 2 khz. single pulses can be sent in all applications. the corresponding c/i command in te applications is tm1. continuous pulses are likewise of alternating polarity, one s-interface bit period wide, but they are sent continuously. the repetition frequency is 96 khz. continuous pulses may be transmitted in all applications. this test mode is entered in te applications with the c/i command tm2.
isac-sx te psb 3186 detailed register description data sheet 121 2003-01-30 4 detailed register description the register mapping of the isac-sx te is shown in figure 69 . figure 69 register mapping of the isac-sx te the register address range from 00 h -2f h is assigned to the d-channel hdlc controller and the c/i-channel handler. the register set ranging from 30 h -3f h pertains to the transceiver registers. the address range from 40 h -5b h is assigned to the iom handler with the registers for timeslot and data port selection (tsdp) and the control registers (cr) for the transceiver data (tr), monitor data (mon), hdlc/ci data (hci) and controller access data (cda), serial data strobe signal (sds), iom interface (iom) and synchronous transfer interrupt (sti). the address range from 5c h -5f h pertains to the monitor handler. general interrupt and configuration regist ers are contained in the address range 60 h -65 h . 3186_04 d- and c/i-channel iom-2 and monitor handler (not used) 00h 40h 30h 70h ffh transceiver 60h interrupt, general configuration
isac-sx te psb 3186 detailed register description data sheet 122 2003-01-30 the register summaries of the isac-sx te are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (read/write). a detailed register description follows these register summaries. the register summaries and the description are sorted in ascending order of the register address. d-channel hdlc, c/i-channel handler name76543210addrr/wres rfifod d-channel receive fifo 00 h - 1f h r xfifod d-channel transmit fifo 00 h - 1f h w istad rme rpf rfo xpr xmr xdu 0 0 20 h r10 h maskd rme rpf rfo xpr xmr xdu 1 1 20 h wff h stard xdov xfw 0 0 raci 0 xaci 0 21 h r40 h cmdrd rmc rres 0 sti xtf 0 xme xres 21 h w00 h moded mds2 mds1 mds0 0 rac dim2 dim1 dim0 22 h r/w c0 h exmd1 xfbs rfbs sra xcrc rcrc 0 itf 23 h r/w 00 h timr1 cnt value 24 h r/w 00 h sap1 sapi1 0 mha 25 h wfc h sap2 sapi2 0 mla 26 h wfc h rbcld rbc7 rbc0 26 h r00 h rbchd 0 0 0 ov rbc11 rbc8 27 h r00 h tei1 tei1 ea1 27 h wff h tei2 tei2 ea2 28 h wff h rstad vfr rdo crc rab sa1 sa0 c/r ta 28 h r0f h tmd 0000000tlp29 h r/w 00 h
isac-sx te psb 3186 detailed register description data sheet 123 2003-01-30 reserved 2a-2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h transceiver name76543210 addrr/wres tr_ conf0 dis_ tr 0en_ icv 0 0 0 exlp ldd 30 h r/w 01 h tr_ conf1 0rpll_ adj en_ sfsc 00xx x31 h r/w tr_ conf2 dis_ tx pds 0 rlp 0 0 0 0 32 h r/w 80 h tr_sta rinf slip icv 0 fsyn 0 ld 33 h r00 h reserved 34 h sqrr1 msyn mfen 0 0 sqr11sqr12sqr13sqr14 35 h r40 h sqxr1 0 mfen 0 0 sqx11 sqx12sqx13 sqx14 35 h w4f h sqrr2 sqr21sqr22sqr23sqr24sqr31sqr32sqr33sqr34 36 h r00 h reserved 36 h w sqrr3 sqr41sqr42sqr43sqr44sqr51sqr52sqr53sqr54 37 h r00 h reserved 37 h w istatr 0 x x x ld ric sqc sqw 38 h r00 h masktr 1 1 1 1 ld ric sqc sqw 39 h r/w ff h reserved 3a h - 3b h
isac-sx te psb 3186 detailed register description data sheet 124 2003-01-30 acfg2 0 0 0 0 acl led 0 0 3c h r/w 00 h reserved 3d h - 3f h iom handler (timeslot , data port selection, cda data and cda control register) name76543210addrr/wres cda10 controller data access register (ch10) 40 h r/w ff h cda11 controller data access register (ch11) 41 h r/w ff h cda20 controller data access register (ch20) 42 h r/w ff h cda21 controller data access register (ch21) 43 h r/w ff h cda_ tsdp10 dps 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 tss 47 h r/w 81 h reserved 48 h - 4b h tr_ tsdp_ bc1 dps 0 0 tss 4c h r/w tr_ tsdp_ bc2 dps 0 0 tss 4d h r/w transceiver name76543210 addrr/wres
isac-sx te psb 3186 detailed register description data sheet 125 2003-01-30 cda1_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4e h r/w 00 h cda2_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4f h r/w 00 h iom handler (control registers, synchronous transfer interrupt control), monitor handler name76543210addrr/wres tr_cr (ci_cs=0) en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 50 h r/w trc_cr (ci_cs=1) 00000 cs2-0 50 h r/w reserved 51 h reserved 52 h dci_cr (ci_cs=0) dps_ ci1 en_ ci1 d_ en_d d_ en_b2 d_ en_b1 cs2-0 53 h r/w dcic_cr (ci_cs=1) 00000 cs2-0 53 h r/w mon_cr dps en_ mon 000 cs2-0 54 h r/w sds_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 55 h r/w 00 h reserved 56 h iom_cr spu 0 ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom 57 h r/w 08 h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0000ack 21 ack 20 ack 11 ack 10 58 h w00 h
isac-sx te psb 3186 detailed register description data sheet 126 2003-01-30 msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h sds_ conf 0000diom_ inv diom_ sds 0sds_ bcl 5a h r/w 00 h mcda mcda21 mcda20 mcda11 mcda10 5b h rff h mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosrmdrmermdamab00005d h r00 h mocrmremrcmiemxc00005e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h interrupt, general configuration registers name76543210 addrr/wres ista 0 0 st cic aux tran mos icd 60 h r00 h mask 1 1 st cic aux tran mos icd 60 h wff h auxi 0 0 eaw wov tin2 tin1 0 0 61 h r00 h auxm 1 1 eaw wov tin2 tin1 1 1 61 h wff h mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 62 h r/w 00 h mode20000int_ pol 0 0 ppsdx 63 h r/w 00 h id 0 0 design 64 h r01 h sres res_ ci 0 0 res_ mon res_ dch res_ iom res_ tr res_ rsto 64 h w00 h timr2 tmd 0 cnt 65 h r/w 00 h
isac-sx te psb 3186 detailed register description data sheet 127 2003-01-30 reserved 66 h - 6f h interrupt, general configuration registers name76543210 addrr/wres
isac-sx te psb 3186 detailed register description data sheet 128 2003-01-30 4.1 d-channel hdlc control and c/i registers 4.1.1 rfifod - receive fifo d-channel a read access to any address within the range 00h-1fh gives access to the ?current? fifo location selected by an internal pointer which is automatically incremented after each read access. this allows for the use of efficient ?move string? type commands by the microcontroller. the rfifod contains up to 32 bytes of received data. after an istad.rpf interrupt, a complete data block is available. the block size can be 4, 8, 16 or 32 bytes depending on the exmd2.rfbs setting. after an istad.rme interrupt, the number of received bytes can be obtained by reading the rbcld register. 4.1.2 xfifod - transmit fifo d-channel a write access to any address within the range 00-1f h gives access to the ?current? fifo location selected by an internal pointer which is automatically incremented after each write access. this allows the use of efficient ?move string? type commands by the microcontroller. depending on exmd2.xfbs up to 16 or 32 bytes of transmit data can be written to the xfifod following an istad.xpr interrupt. 4.1.3 istad - interrupt status register d-channel value after reset: 10 h 70 rfifod receive data rd (00-1f) 70 xfifod transmit data wr (00-1f) 70 istad rme rpf rfo xpr xmr xdu 0 0 rd (20)
isac-sx te psb 3186 detailed register description data sheet 129 2003-01-30 rme ... receive message end one complete frame of length less than or equal to the defined block size (exmd1.rfbs) or the last part of a frame of length greater than the defined block size has been received. the contents are available in the rfifod. the message length and additional information may be obtained from rbchd and rbcld and the rstad register. rpf ... receive pool full a data block of a frame longer than the defined block size (exmd1.rfbs) has been received and is available in the rfifod. the frame is not yet complete. rfo ... receive frame overflow the received data of a frame could not be stored, because the rfifod is occupied. the whole message is lost. this interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to an rpf or rme interrupt (istad). xpr ... transmit pool ready a data block of up to the defined block size 16 or 32 (exmd1.xfbs) can be written to the xfifod. an xpr interrupt will be generated in the following cases: after an xtf or xme command as soon as the 16 or 32 bytes in the xfifo are available and the frame is not yet complete after an xtf together with an xme command is issued, when the whole frame has been transmitted after a reset of the transmitter (xres) after a device reset xmr ... transmit message repeat the transmission of the last frame has to be repeated because a collision on the s bus has been detected after the 16 th /32 nd data byte of a transmit frame. if an xmr interrupt occurs the transmit fifo is locked until the xmr interrupt is read by the host (interrupt cannot be read if masked in maskd). xdu ... transmit data underrun the current transmission of a frame is aborted by transmitting seven ?1?s because the xfifod holds no further data. this interrupt occurs whenever the microcontroller has failed to respond to an xpr interrupt (istad register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete.
isac-sx te psb 3186 detailed register description data sheet 130 2003-01-30 if an xdu interrupt occurs the transmit fifo is locked until the xdu interrupt is read by the host (interrupt cannot be read if masked in maskd). 4.1.4 maskd - mask register d-channel value after reset: ff h each interrupt source in the istad register can selectively be masked by setting the corresponding bit in maskd to ?1?. masked interrupt status bits are not indicated when istad is read. instead, they remain internally stored and pending until the mask bit is reset to ?0?. 4.1.5 stard - status register d-channel value after reset: 40 h xdov ... transmit data overflow more than 16 or 32 bytes (according to selected block size) have been written to the xfifod, i.e. data has been overwritten. xfw ... transmit fifo write enable data can be written to the xfifod. this bit may be polled instead of (or in addition to) using the xpr interrupt. raci ... receiver active indication the d-channel hdlc receiver is active when raci = ?1?. this bit may be polled. the raci bit is set active after a begin flag has been received and is reset after receiving an abort sequence. 70 maskd rme rpf rfo xpr xmr xdu 1 1 wr (20) 70 stard xdov xfw 0 0 raci 0 xaci 0 rd (21)
isac-sx te psb 3186 detailed register description data sheet 131 2003-01-30 xaci ... transmitter active indication the d-channel hdlc-transmitter is active when xaci = ?1?. this bit may be polled. the xaci-bit is active when an xtf-command is issued and the frame has not been completely transmitted 4.1.6 cmdrd - command register d-channel value after reset: 00 h rmc ... receive message complete reaction to rpf (receive pool full) or rme (receive message end) interrupt. by setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the rfifod may be released. rres ... receiver reset hdlc receiver is reset, the rfifod is cleared of any data. sti ... start timer 1 the isac-sx te timer 1 is started when sti is set to one. the timer is stopped by writing to the timr1 register. note: timer 2 is controlled by the timr2 register only. xtf ... transmit transparent frame after having written up to 16 or 32 bytes (exmd1.xfbs) to the xfifod, the microcontroller initiates the transmission of a transparent frame by setting this bit to ?1?. the opening flag is automatically added to the message by the isac-sx te (except in the extended transparent mode where no flags are used). xme ... transmit message end by setting this bit to ?1? the microcontroller indicates that the data block written last to the xfifod completes the corresponding frame. the isac-sx te terminates the transmission by appending the crc (if exmd1.xcrc=0) and the closing flag sequence to the data (except in the extended transparent mode where no such framing is used). 70 cmdrd rmc rres 0 sti xtf 0 xme xres wr (21)
isac-sx te psb 3186 detailed register description data sheet 132 2003-01-30 xres ... transmitter reset the d-channel hdlc transmitter is reset and the xfifod is cleared of any data. this command can be used by the microcontroller to abort a frame currently in transmission. note: after an xpr interrupt further data has to be written to the xfifod and the appropriate transmit command (xtf) has to be written to the cmdrd register again to continue transmission, when the current frame is not yet complete (see also xpr in istad). during frame transmission, the 0-bit insertion according to the hdlc bit-stuffing mechanism is done automatically. 4.1.7 moded - mode register value after reset: c0 h mds2-0 ... mode select determines the message transfer mode of the hdlc controller, as follows: 70 moded mds2 mds1 mds0 0 rac dim2 dim1 dim0 rd/wr (22) mds2-0 mode number of address bytes address comparison remark 1.byte 2.byte 0 0 0 reserved 0 0 1 reserved 0 1 0 non-auto mode 1 tei1,tei2 ? one-byte address compare. 0 1 1 non-auto mode 2 sap1,sap2, sapg tei1,tei2,teig two-byte address compare. 1 0 0 extended transparent mode 1 1 0 transparent mode 0 ? ? ? no address compare. all frames accepted.
isac-sx te psb 3186 detailed register description data sheet 133 2003-01-30 note: sap1, sap2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); sapg = fixed value fc / fe h . tei1, tei2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; teig = fixed value ff h two different methods of the high byte and/or low byte address comparison can be selected by setting sap1.mha and/or sap2.mla. rac ... receiver active the d-channel hdlc receiver is activated when this bit is set to ?1?. if set to ?0? the hdlc data is not evaluated in the receiver. dim2-0 ... digital interface modes these bits define the characteristics of the iom data ports (du, dd). the dim0 bit enables/disables the collission detection. the dim1 bit enables/disables the tic bus access. the effect of the individual dim bits is summarized in the table below . 1 1 1 transparent mode 1 > 1 sap1,sap2,sa pg ? high-byte address compare. 1 0 1 transparent mode 2 > 1 ? tei1,tei2,teig low-byte address compare. dim2 dim1 dim0 characteristics 0 0 transparent d-channel, the collission detection is disabled 0 1 stop/go bit evaluated for d-channel access handling 0 0 last octet of iom channel 2 used for tic bus access 0 1 tic bus access is disabled 1 xxreserved mds2-0 mode number of address bytes address comparison remark 1.byte 2.byte
isac-sx te psb 3186 detailed register description data sheet 134 2003-01-30 4.1.8 exmd1- extended mode register d-channel 1 value after reset: 00 h xfbs ? transmit fifo block size 0 ? block size for the transmit fifo data is 32 byte 1 ? block size for the transmit fifo data is 16 byte note: a change of xfbs will take effect after a receiver command (cmdrd.xme, cmdrd.xres, cmdrd.xtf) has been written. rfbs ? receive fifo block size note: a change of rfbs will take effect after a transmitter command (cmdr.rmc, cmdr.rres,) has been written sra ? store receive address 0 ? receive address isn?t stored in the rfifod 1 ? receive address is stored in the rfifod xcrc ? transmit crc 0 ? crc is transmitted 1 ? crc isn?t transmitted rcrc? receive crc 0 ? crc isn?t stored in the rfifod 1 ? crc is stored in the rfifod 70 exmd1 xfbs rfbs sra xcrc rcrc 0 itf rd/wr (23) rfbs block size receive fifo bit 6 bit5 0 0 32 byte 0 1 16 byte 1 0 8 byte 1 1 4 byte
isac-sx te psb 3186 detailed register description data sheet 135 2003-01-30 itf? interframe time fill selects the inter-frame time fill signal which is transmitted between hdlc-frames. 0 ? idle (continuous ?1?) 1 ? flags (sequence of patterns: ?0111 1110?) note: itf must be set to ?0? for power down mode. in applications with d-channel access handling (collision resolution), the only possible inter-frame time fill is idle (continuous ?1?) . otherwise the d-channel on the s/t-bus cannot be accessed 4.1.9 timr1 - timer 1 register value after reset: 00 h cnt ... timer counter cnt together with value determines the time period t after which a auxi.tin1 interrupt will be generated: cnt=0...6:t = cnt x 2.048 sec + t1 with t1 = ( value+1 ) x 0.064 sec cnt=7:t = t1 = ( value+1 ) x 0.064 sec (generated periodically) the timer can be started by setting the sti-bit in cmdrd and will be stopped when a tin1 interrupt is generated or the timr1 register is written. note: if cnt is set to 7, a tin interrupt is indefinitely generated after every expiration of t1 (i.e. t = t1). value ... timer value determines the value of the timer value t1 = ( value + 1 ) x 0.064 sec . 4.1.10 sap1 - sapi1 register value after reset: fc h 754 0 timr1 cnt value rd/wr (24) 70 sap1 sapi1 0 mha wr (25)
isac-sx te psb 3186 detailed register description data sheet 136 2003-01-30 sapi1 ... sapi1 value value of the first programmable service access point identifier (sapi) according to the isdn lapd protocol. mha... mask high address 0 ?the sapi address of an incomming frame is compared with sap1, sap2, sapg. 1 ?the sapi address of an incomming frame is compared with sap1 and sapg. sap1 can be masked with sap2 thereby bit positions of sap1 are not compared if they are set to ?1? in sap2. 4.1.11 sap2 - sapi2 register value after reset: fc h sapi2 ... sapi2 value value of the second programmable service access point identifier (sapi) according to the isdn lapd-protocol. mla... mask low address 0 ?the tei address of an incomming frame is compared with tei1, tei2 and teig. 1 ?the tei address of an incomming frame is compared with tei1 and teig. tei1 can be masked with tei2 thereby bit positions of tei1 are not compared if they are set to ?1? in tei2. 4.1.12 rbcld - receive frame byte count low d-channel value after reset: 00 h rbc7-0 ... receive byte count eight least significant bits of the total number of bytes in a received message (see rbchd register). 70 sap2 sapi2 0 mla wr (26) 70 rbcld rbc7 rbc0 rd (26)
isac-sx te psb 3186 detailed register description data sheet 137 2003-01-30 4.1.13 rbchd - receive frame byte count high d-channel value after reset: 00 h . ov ... overflow a ?1? in this bit position indicates a message longer than (2 12 - 1) = 4095 bytes . rbc8-11 ... receive byte count four most significant bits of the total number of bytes in a received message (see rbcld register). note: normally rbchd and rbcld should be read by the microcontroller after an rme-interrupt in order to determine the number of bytes to be read from the rfifod, and the total message length. the contents of the registers are valid only after an rme or rpf interrupt, and remain so until the frame is acknowledged via the rmc bit or rres. 4.1.14 tei1 - tei1 register 1 value after reset: ff h tei1 ... terminal endpoint identifier in all message transfer modes except in transparent modes 0, 1 and extended transparent mode, tei1 is used by the isac-sx te for address recognition. in the case of a two-byte address field, it contains the value of the first programmable terminal endpoint identifier according to the isdn lapd-protocol. in non-automodes with one-byte address field, tei1 is a command address, according to x.25 lapb. ea1 ... address field extension bit this bit is set to ?1? according to hdlc/lapd. 70 rbchd 0 0 0 ov rbc11 rbc8 rd (27) 70 tei1 tei1 ea1 wr (27)
isac-sx te psb 3186 detailed register description data sheet 138 2003-01-30 4.1.15 tei2 - tei2 register value after reset: ff h tei2 ... terminal endpoint identifier in all message transfer modes except in transparent modes 0, 1 and extended transparent mode, tei2 is used by the isac-sx te for address recognition. in the case of a two-byte address field, it contains the value of the second programmable terminal endpoint identifier according of the isdn lapd-protocol. in non-auto-modes with one-byte address field, tei2 is a response address, according to x.25 lapd. ea2 ... address field extension bit this bit is to be set to ?1? according to hdlc/lapd. 4.1.16 rstad - receive status register d-channel value after reset: 0f h for general information please refer to chapter 3.8 . vfr... valid frame determines whether a valid frame has been received. the frame is valid (1) or invalid (0). a frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). rdo ... receive data overflow if rdo=1, at least one byte of the frame has been lost, because it could not be stored in rfifod. as opposed to the istad.rfo an rdo indicates that the beginning of a frame has been received but not all bytes could be stored as the rfifod was temporarily full. 70 tei2 tei2 ea2 wr (28) 70 rstad vfr rdo crc rab sa1 sa0 c/r ta rd (28)
isac-sx te psb 3186 detailed register description data sheet 139 2003-01-30 crc ... crc check the crc is correct (1) or incorrect (0). rab ... receive message aborted the receive message was aborted by the remote station (1), i.e. a sequence of seven 1?s was detected before a closing flag. sa1-0 ... sapi address identification ta ... tei address identification sa1-0 are significant in non-automode with a two-byte address field, as well as in transparent mode 3. ta is significant in all modes except in transparent modes 0 and 1. two programmable sapi values (sap1, sap2) plus a fixed group sapi (sapg of value fc h /fe h ), and two programmable tei values (tei1, tei2) plus a fixed group tei (teig of value ff h ), are available for address comparison. the result of the address comparison is given by sa1-0 and ta, as follows: note: if sap1 and sap2 contain identical values, the combination sap1,2-teig will only be indicated by sa1,0 = ?10? (i.e. the value ?00? will not occur in this case). address match with mds2-0 sa1 sa0 ta 1 st byte 2 nd byte 010 (non-auto/8 mode) x x x x 0 1 tei2 tei1 - - 011 (non-auto/16 mode) 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 sap2 sap2 sapg sapg sap1 sap1 teig tei2 teig tei1 or tei2 teig tei1 111 (transparent mode1) 0 0 1 0 1 0 x x x sap2 sapg sap1 - - - 101 (transparent mode 2) - - - - 0 1 - - teig tei1 or tei2 1 1 x reserved
isac-sx te psb 3186 detailed register description data sheet 140 2003-01-30 c/r ... command/response the c/r bit contains the c/r bit of the received frame (bit1 in the sapi address) note: the contents of rstad corresponds to the last received hdlc frame; it is duplicated into rfifod for every frame (last byte of frame) 4.1.17 tmd -test mode register d-channel value after reset: 00 h for general information please refer to chapter 3.9 . tlp ... test loop the tx path of layer-2 is internally connected with the rx path of layer-2. data coming from the layer 1 controller will not be forwarded to the layer 2 controller. the setting of tlp is only valid if the iom interface is active. 4.1.18 cir0 - command/indication receive 0 value after reset: f3 h codr0 ... c/i code 0 receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 ... c/i code 0 change a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. 70 tmd 0000000tlprd/wr (29) 70 cir0 codr0 cic0 cic1 s/g bas rd (2e)
isac-sx te psb 3186 detailed register description data sheet 141 2003-01-30 cic1 ... c/i code 1 change a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. s/g ... stop/go bit monitoring indicates the availability of the upstream d-channel on the s/t interface. 1: stop 0: go bas ... bus access status indicates the state of the tic-bus: 0: the isac-sx te itself occupies the d- and c/i-channel 1: another device occupies the d- and c/i-channel note: the codr0 bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code is made available in cir0 at the first and second read of that register, respectively. 4.1.19 cix0 - command/indication transmit 0 value after reset: fe h codx0 ... c/i-code 0 transmit code to be transmitted in the c/i-channel 0. the code is only transmitted if the tic bus is occupied. if tic bus is enabled but occupied by another device, only ?1s? are transmitted. tba2-0 ... tic bus address defines the individual address for the isac-sx te on the iom bus. this address is used to access the c/i- and d-channel on the iom interface. note: if only one device is liable to transmit in the c/i- and d-channels of the iom it should always be given the address value ?7?. 70 cix0 codx0 tba2 tba1 tba0 bac wr (2e)
isac-sx te psb 3186 detailed register description data sheet 142 2003-01-30 bac ... bus access control only valid if the tic-bus feature is enabled (moded.dim2-0). if this bit is set, the isac-sx te will try to access the tic-bus to occupy the c/i-channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the isac-sx te with tic-bus address (tba2-0, stcr register) ?7?, which has the lowest priority in a bus configuration. 4.1.20 cir1 - command/indication receive 1 value after reset: fe h codr1 ... c/i-code 1 receive cicw, ci1e ... c/i-channel width, c/i-channel 1 interrupt enable these two bits contain the read back values from cix1 register (see below). 4.1.21 cix1 - command/indication transmit 1 value after reset: fe h codx1 ... c/i-code 1 transmit bits 7-2 of c/i-channel 1. cicw... c/i-channel width cicw selects between a 4 bit (?0?) and 6 bit (?1?) c/i1 channel width. the c/i1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. however in write direction the full codx1 code is transmitted, i.e. the host must write the higher two bits to ?1?. 70 cir1 codr1 cicw ci1e rd (2f) 70 cix1 codx1 cicw ci1e wr (2f)
isac-sx te psb 3186 detailed register description data sheet 143 2003-01-30 ci1e ... c/i-channel 1 interrupt enable interrupt generation ista.cic of cir0.cic1 is enabled (1) or masked (0).
isac-sx te psb 3186 detailed register description data sheet 144 2003-01-30 4.2 transceiver registers 4.2.1 tr_conf0 - transceiver configuration register 0 value after reset: 01 h dis_tr ... disable transceiver setting dis_tr to ?1? disables the transceiver. in order to reenable the transceiver again, a transceiver reset must be issued (sres.res_tr = 1). the transceiver must not be reenabled by setting dis_tr from ?1? to ?0?. for general information please refer to chapter 3.3.9 . en_icv ... enable illegal code violation 0: normal operation 1: icv enabled. the receipt of at least one illegal code violation within one multi-frame is indicated by the c/i indication ?1011? (cvr) in two consecutive iom frames. exlp ... external loop in case the analog loopback is activated with c/i = arl the loop is a 0: internal loop next to the line pins 1: external loop which has to be closed between sr1/2 and sx1/sx2 note: the external loop is only useful if bit dis_tx of register tr_conf2 is set to ?0?. for general information please refer to chapter 3.3.10 . ldd ... level detection discard 0: automatic clock generation after detection of any signal on the line in power down state 1: no clock generation after detection of any signal on the line in power down state note: if an interrupt by the level detect circuitry is generated, the microcontroller has to set this bit to ?0? for an activation of the s/t interface. for general information please refer to chapter 3.3.8 and chapter 3.7.6 . 70 tr_ conf0 dis_ tr 0en_ icv 0 0 0 exlp ldd rd/wr (30)
isac-sx te psb 3186 detailed register description data sheet 145 2003-01-30 4.2.2 tr_conf1 - transceiver configuration register 1 value after reset: 0x h rpll_adj ... receive pll adjustment 0: dpll tracking step is 0.5 xtal period per s-frame 1: dpll tracking step is 1 xtal period per s-frame en_sfsc ... enable short fsc 0: no short fsc is generated 1: a short fsc is generated once per multi-frame (every 40th iom frame) x ... undefined the value of these bits depends on the selected mode. it is important to note that these bits must not be overwritten to a different value when accessing this register. 4.2.3 tr_conf2 - transmitter configuration register 2 value after reset: 80 h dis_tx ... disable line driver 0: transmitter is enabled 1: transmitter is disabled for general information please refer to chapter 3.3.9 . pds ... phase deviation select defines the phase deviation of the s-transmitter. 0: the phase deviation is 2 s-bits minus 7 oscillator periods plus analog delay plus delay of the external circuitry. 70 tr_ conf1 0rpll_ adj en_ sfsc 00xxxrd/wr (31) 70 tr_ conf2 dis_ tx pds0rlp0000rd/wr (32)
isac-sx te psb 3186 detailed register description data sheet 146 2003-01-30 1: the phase deviation is 2 s-bits minus 9 oscillator periods plus analog delay plus delay of the external circuitry. for general information please refer to chapter 3.3.7 . rlp ... remote line loop 0: remote line loop open 1: remote line loop closed for general information please refer to chapter 3.3.10 . 4.2.4 tr_sta - transceiver status register value after reset: 00 h rinf ... receiver info 00: received info 0 01: received any signal except info 0,2,4 10: reserved info 2 11: received info 4 slip ... slip detected a ?1? in this bit position indicates that a slip is detected in the receive or transmit path. icv ... illegal code violation 0: no illegal code violation is detected 1: llegal code violation (ansi t1.605) in data stream is detected fsyn ... frame synchronization state 0: the s/t receiver is not synchronized 1: the s/t receiver has synchronized to the framing bit f ld ... level detection 0: no receive signal has been detected on the line. 1: any receive signal has been detected on the line. 70 tr_sta rinf slip icv 0 fsyn 0 ld rd (33)
isac-sx te psb 3186 detailed register description data sheet 147 2003-01-30 4.2.5 sqrr1 - s/q-channel receive register 1 value after reset: 40 h for general information please refer to chapter 3.3.2 . msyn ... multi-frame synchronization state 0: the s/t receiver has not synchronized to the received f a and m bits 1: the s/t receiver has synchronized to the received f a and m bits mfen ... multiframe enable read-back of the mfen bit of the sqxr register sqr11-14 ... received s bits received s bits in frames 1, 6, 11 and 16 4.2.6 sqxr1- s/q-channel tx register 1 value after reset: 4f h mfen ... multiframe enable used to enable or disable the multiframe structure (see chapter 3.3.2 ) 0: s/t multiframe is disabled 1: s/t multiframe is enabled readback value in sqrr1. sqx1-4 ... transmitted s/q bits transmitted q bits (f a bit position) in frames 1, 6, 11 and 16. 70 sqrr msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 rd (35) 70 sqxr1 0 mfen 0 0 sqx1 sqx2 sqx3 sqx4 wr (35)
isac-sx te psb 3186 detailed register description data sheet 148 2003-01-30 4.2.7 sqrr2 - s/q-channel receive register 2 value after reset: 00 h sqr21-24, sqr31-34... received s bits received s bits in frames 2, 7, 12 and 17 (sqr21-24, subchannel 2), and in frames 3, 8, 13 and 18 (sqr31-34, subchannel 3). 4.2.8 sqrr3 - s/q-channel receive register 3 value after reset: 00 h sqr41-44, sqr51-54... received s bits received s bits in frames 4, 9, 14 and 19 (sqr41-44, subchannel 4), and in frames 5, 10, 15 and 20 (sqr51-54, subchannel 5). 4.2.9 istatr - interrupt status register transceiver value after reset: 00 h for all interrupts in the istatr register the following logical states are defined: 0: interrupt is not acitvated 1: interrupt is acitvated x ... reserved bits set to ?1? in this bit position must be ignored. 70 sqrr2 sqr21 sqr22 sqr23 sqr24 sqr31 sqr32 sqr33 sqr34 rd (36) 70 sqrr3 sqr41 sqr42 sqr43 sqr44 sqr51 sqr52 sqr53 sqr54 rd (37) 70 istatr x x x x ld ric sqc sqw rd (38)
isac-sx te psb 3186 detailed register description data sheet 149 2003-01-30 ld ... level detection any receive signal has been detected on the line. this bit is set to ?1? (i.e. an interrupt is generated if not masked) as long as any receiver signal is detected on the line. ric ... receiver info change ric is activated if one of the tr_sta bits rinf or icv has changed. this bit is reset by reading the tr_sta register. sqc ... s/q-channel change a change in the received s-channel has been detected. the new code can be read from the sqrxx bits of registers sqrr1-3 within the duration of the next multiframe (5 ms). this bit is reset by a read access to the corresponding sqrrx register. sqw ... s/q-channel writable the s/q channel data for the next multiframe is writable. the register for the q (s) bits to be transmitted (received) has to be written (read) within the duration of the next multiframe (5 ms). this bit is reset by writing register sqxrx. 4.2.10 masktr - mask transceiver interrupt value after reset: ff h the transceiver interrupts ld, ric, sqc and sqw are enabled (0) or disabled (1). 4.2.11 acfg2 - auxiliary configuration register value after reset: 00 h note: although no other auxiliary configuration registers are supported by isac-sx te, the name acfg2 for this register was chosen intentionally in compliance with isac-sx peb3086. 70 masktr 1 1 1 1 ld ric sqc sqw rd/wr (39) 70 acfg2 0 0 0 0 acl led 0 0 rd/wr (3d)
isac-sx te psb 3186 detailed register description data sheet 150 2003-01-30 acl ... acl function select 0: pin acl automatically indicates the s-bus activation status by a low level. 1: the output state of acl is programmable by the host in bit led. note: an led with preresistance my directly be connected to acl . led ... led control if enabled (acl = 1) the led with preresistance connected across vdd and acl is switched ... 0: ... off (high level on pin acl ) 1: ... on (low level on pin acl )
isac-sx te psb 3186 detailed register description data sheet 151 2003-01-30 4.3 iom-2 and monitor handler 4.3.1 cdaxy - controller data access register xy data registers cdaxy which can be accessed from the controller. 4.3.2 xxx_tsdpxy - time slot and data port selection for chxy this register determines the time slots and the data ports on the iom-2 interface for the data channels ?xy? of the functional units ?xxx? which are controller data access (cda) and transceiver (tr). 70 cdaxy controller data access register rd/wr (40-43) register register address value after reset cda10 40 h ff h cda11 41 h ff h cda20 42 h ff h cda21 43 h ff h 70 xxx_ tsdpxy dps 0 0 tss rd/wr (44-4d) register register address value after reset cda_tsdp10 44 h 00 h ( = output on b1-dd) cda_tsdp11 45 h 01 h ( = output on b2-dd) cda_tsdp20 46 h 80 h ( = output on b1-du) cda_tsdp21 47 h 81 h ( = output on b2-du) tr_tsdp_bc1 4c h 00 h ( = transceiver output on b1-dd) tr_tsdp_bc2 4d h 01 h ( = transceiver output on b2-dd)
isac-sx te psb 3186 detailed register description data sheet 152 2003-01-30 the position of b-channel data from the s-interface is programmed in tr_tsdp_bc1 and tr_tsdp_bc2. dps ... data port selection 0: the data channel xy of the functional unit xxx is output on dd. the data channel xy of the functional unit xxx is input from du. 1: the data channel xy of the functional unit xxx is output on du. the data channel xy of the functional unit xxx is input from dd. note: for the cda (controller data access) data the input is determined by the cda_crx.swap bit. if swap = ?0? the input for the cdaxy data is vice versa to the output setting for cdaxy. if the swap = ?1? the input from cdax0 is vice versa to the output setting of cdax1 and the input from cdax1 is vice versa to the output setting of cdax0. see controller data access description in chapter 3.7.1.1 tss ... timeslot selection selects one of 32 timeslots (0...31) on the iom-2 interface for the data channels. 4.3.3 cdax_cr - control register controller data access ch1x for general information please refer to chapter 3.7.1.1 . en_tbm ... enable tic bus monitoring 0: the tic bus monitoring is disabled 1: the tic bus monitoring with the cdax0 r egister is enabled. the tsdpx0 register must be set to 08 h for monitoring from du or 88 h for monitoring from dd, respectively (this selection is only valid if iom_cr.tic_dis = 0). 70 cdax_ cr 00en_ tbm en_i1 en_i0 en_o1 en_o0 swap rd/wr (4e-4f) register register address value after reset cda1_cr 4e h 00 h cda2_cr 4f h 00 h
isac-sx te psb 3186 detailed register description data sheet 153 2003-01-30 en_i1, en_i0 ... enable input cdax0, cdax1 0: the input of the cdax0, cdax1 register is disabled 1: the input of the cdax0, cdax1 register is enabled en_o1, en_o0 ... enable output cdax0, cdax1 0: the output of the cdax0, cdax1 register is disabled 1: the output of the cdax0, cdax1 register is enabled swap ... swap inputs 0: the time slot and data port for the input of the cdaxy register is defined by its own tsdpxy register. the data port for the cdaxy input is vice versa to the output setting for cdaxy. 1: the input (time slot and data port) of the cdax0 is defined by the tsdp register of cdax1 and the input of cdax1 is defined by the tsdp register of cdax0. the data port for the cdax0 input is vice versa to the output setting for cdax1. the data port for the cdax1 input is vice versa to the output setting for cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 to cdax0. the outputs are not affected by the swap bit. 4.3.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) value after reset: f8 h read and write access to this register is only possible if iom_cr.ci_cs = 0. en_d ... enable transceiver d-channel data en_b2r ... enable transceiver b2 receive data en_b1r ... enable transceiver b1 receive data en_b2x ... enable transceiver b2 transmit data en_b1x ... enable transceiver b1 transmit data this register is used to individually enable/disable the d-channel (both rx and tx direction) and the receive/transmit paths for the b-channel of the s-transceiver. 0: the corresponding data path to the transceiver is disabled. 1: the corresponding data path to the transceiver is enabled. 70 tr_cr en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 rd/wr (50)
isac-sx te psb 3186 detailed register description data sheet 154 2003-01-30 cs2-0 ... channel select for transceiver d-channel this register is used to select one of eight iom channels to which the transceiver d-channel data is related to. note: it should be noted that writing tr_cr.cs2-0 will also write to trc_cr.cs2-0 and therefore modify the channel selection for the transceiver c/i0 data. 4.3.4.1 trc_cr - control register transceiver c/i0 (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. cs2-0 ... channel select for the transceiver c/i0 channel this register is used to select one of eight iom channels to which the transceiver c/i0 channel data is related to. 4.3.5 dci_cr - control regi ster for d and ci1 handler (iom_cr.ci_cs=0) value after reset: a0 h read and write access to this register is only possible if iom_cr.ci_cs = 0. dps_ci1 ... data port selection ci1 handler data 0: the ci1 handler data is output on dd and input from du 1: the ci1 handler data is output on du and input from dd en_ci1 ... enable ci1 handler data 0: ci1 handler data access is disabled 1: ci1 handler data access is enabled 70 trc_cr 0 0 0 0 0 cs2-0 rd/wr (50) 70 dci_cr dps_ ci1 en_ ci1 d_ en_d d_ en_b2 d_ en_b1 cs2-0 rd/wr (53)
isac-sx te psb 3186 detailed register description data sheet 155 2003-01-30 note: the timeslot for the c/i1 handler cannot be programmed but is fixed to iom channel 1. d_en_d ... enable d-timeslot for d-channel controller d_en_b2 ... enable b2-timeslot for d-channel controller d_en_b1 ... enable b1-timeslot for d-channel controller these bits are used to select the timeslot length for the d-channel hdlc controller access as it is capable to access not only the d-channel timeslot. the host can individually enable two 8-bit timeslots b1- and b2-channel (d_en_b1, d_en_b2) and one 2-bit timeslot d-channel (d_en_d) on iom-2. the position is selected via cs2-0. 0: d-channel controller does not access timeslot data b1, b2 or d, respectively 1: d-channel controller does access timeslot data b1, b2 or d, respectively cs2-0 ... channel select for d-channel controller this register is used to select one of eight iom channels. if enabled, the d-channel data is connected to the corresponding timeslots of that iom channel. note: it should be noted that writing dci_cr.cs2-0 will also write to dcic_cr.cs2-0 and therefore modify the channel selection for the data of the c/i0 handler. 4.3.5.1 dcic_cr - control register for ci0 handler (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. cs2-0 ... channel select for c/i0 handler this register is used to select one of eight iom channels. if enabled, the data of the c/i0-handler is connected to the corresponding c/i0 timeslots of that iom channel. 70 dcic_cr 0 0 0 0 0 cs2-0 rd/wr (13)
isac-sx te psb 3186 detailed register description data sheet 156 2003-01-30 4.3.6 mon_cr - control register monitor data value after reset: 40 h for general information please refer to chapter 3.7.3 . dps ... data port selection 0: the monitor data is output on dd and input from du 1: the monitor data is output on du and input from dd en_mon ... enable output 0: the monitor data input and output is disabled 1: the monitor data input and output is enabled cs2-0 ... monitor channel selection 000: the monitor data is input/output on mon0 (3rd timeslot on iom-2) 001: the monitor data is input/output on mon1 (7th timeslot on iom-2) 010: the monitor data is input/output on mon2 (11th timeslot on iom-2) : 111: the monitor data is input/output on mon7 (31st timeslot on iom-2) 4.3.7 sds_cr - control register serial data strobe value after reset: 00 h this register is used to select position and length of the strobe signal. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). for general information please refer to chapter 3.7.2 and chapter 3.7.2.2 . 70 mon_cr dps en_ mon 000 cs2-0 rd/wr (54) 70 sds_cr ens_ tss ens_ tss+1 ens_ tss+3 tss rd/wr (55)
isac-sx te psb 3186 detailed register description data sheet 157 2003-01-30 ens_tss ... enable serial data strobe of timeslot tss ens_tss+1 ... enable serial data strobe of timeslot tss+1 0: the serial data strobe signal sdsx is inactive during tss, tss+1 1: the serial data strobe signal sdsx is active during tss, tss+1 ens_tss+3 ... enable serial data strobe of timeslot tss+3 (d-channel) 0: the serial data strobe signal sdsx is inactive during the d-channel (bit7, 6) of tss+3 1: the serial data strobe signal sdsx is active during the d-channel (bit7, 6) of tss+3 tss ... timeslot selection selects one of 32 timeslots on the iom-2 interface (with respect to fsc) during which sdsx is active high or provides a strobed bcl clock output (see sds_conf.sds_bcl). the data strobe signal allows standard data devices to access a programmable channel. 4.3.8 iom_cr - control register iom data value after reset: 08 h spu ... software power up 0: the du line is normally used for transmitting data 1: setting this bit to ?1? will pull the du line to low. this will enforce connected layer 1 devices to deliver iom-clocking. after a subsequent ista.cic-interrupt (c/i-code change) and reception of the c/i-code ?pu? (power up indication in te-mode) the microcontroller writes an ar or tim command as c/i-code in the cix0-register, resets the spu bit and waits for the following cic-interrupt. for general information please refer to chapter 3.7.6 . ci_cs ... c/i channel selection the channel selection for d-channel and c/i-channel is done in the channel select bits ch2-0 of register tr_cr (for the transceiver) and dci_cr (for the d-channel controller and c/i-channel controller). 70 iom_cr spu 0 ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom rd/wr (57)
isac-sx te psb 3186 detailed register description data sheet 158 2003-01-30 0: a write access to cs2-0 has effect on the configuration of d- and c/i-channel, whereas a read access delivers the d-channel configuration only. 1: a write access to cs2-0 has effect on the configuration of the c/i-channel only, whereas a read access delivers the c/i-channel configuration only. tic_dis ... tic bus disable 0: the last octet of iom channel 2 (12th timeslot) is used as tic bus. 1: the tic bus is disabled. the last octet of the last iom time slot (ts 11) can be used as every time slot. en_bcl ... enable bit clock bcl 0: the bcl clock is disabled 1: the bcl clock is enabled. clkm ... clock mode if the transceiver is disabled (dis_tr = ?1?) the dcl from the iom-2 interface is an input. 0: a double bit clock is connected to dcl 1: a single bit clock is connected to dcl for general information please refer to chapter 3.7 . dis_od ... disable open drain drivers 0: du/dd are open drain drivers 1: du/dd are push pull drivers dis_iom ... disable iom dis_iom should be set to ?1? if external devices connected to the iom interface should be ?disconnected? e.g. for power saving purposes or for not disturbing the internal iom connection between layer 1 and layer 2. however, the isac-sx te internal operation between s-transceiver, b-channel and d-channel controller is independent of the dis_iom bit. 0: the iom interface is enabled 1: the iom interface is disabled. the fsc, dcl clock outputs have high impedance; clock inputs are active; du, dd data line inputs are switched off and outputs have high impedance; except in te/lt-t mode the du line is input (?0?-level causes activation), so the du pin must be terminated (pull up resistor).
isac-sx te psb 3186 detailed register description data sheet 159 2003-01-30 4.3.9 sti - synchronous transfer interrupt value after reset: 00 h for all interrupts in the sti register the following logical states are applied: 0: interrupt is not activated 1: interrupt is activated the interrupts are automatically reset by reading the sti register. for general information please refer to chapter 3.7.1.1 . stovxy ... synchronous transfer overflow interrupt enabled stov interrupts for a certain stixy interrupt are generated when the stixy has not been acknowledged in time via the ackxy bit in the asti register. this must be one (for dps=?0?) or zero (for dps=?1?) bcl clocks before the time slot which is selected for the stov. stixy ... synchronous transfer interrupt depending on the dps bit in the corresponding tsdpxy register the synchronous transfer interrupt stixy is generated two (for dps=?0?) or one (for dps=?1?) bcl clock after the selected time slot (tsdpxy.tss). note: st0vxy and ackxy are useful for synchronizing microcontroller accesses and receive/transmit operations. one bcl clock is equivalent to two dcl clock cycles. 4.3.10 asti - acknowledge synchronous transfer interrupt value after reset: 00 h for general information please refer to chapter 3.7.1.1 . 70 sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd (58) 70 asti 0 0 0 0 ack 21 ack 20 ack 11 ack 10 wr (58)
isac-sx te psb 3186 detailed register description data sheet 160 2003-01-30 ackxy ... acknowledge synchronous transfer interrupt after an stixy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ackxy bit to ?1?. 4.3.11 msti - mask synchro nous transfer interrupt value after reset: ff h for the msti register the following logical states are applied: 0: interrupt is not masked 1: interrupt is masked for general information please refer to chapter 3.7.1.1 . stovxy ... synchronous transfer overflow for stixy mask bits for the corresponding stovxy interrupt bits. stixy ... synchronous transfer interrupt xy mask bits for the corresponding stixy interrupt bits. 4.3.12 sds_conf - configuration register for serial data strobe value after reset: 00 h for general information on sds_bcl please refer to chapter 3.7.2 . diom_inv ... du/dd on iom timeslot inverted 0: du/dd are active during sds high phase and inactive during the low phase. 1: du/dd are active during sds low phase and inactive during the high phase. this bit has only effect if diom_sds is set to ?1? otherwise diom_inv is don?t care. 70 msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd/wr (59) 70 sds_ conf 0000diom_ inv diom_ sds 0sds_ bcl rd/wr (5a)
isac-sx te psb 3186 detailed register description data sheet 161 2003-01-30 diom_sds ... du/dd on iom controlled via sds 0: the pin sds and its configuration settings are used for serial data strobe only. the iom-2 data lines are not affected. 1: the du/dd lines are deactivated during the during high/low phase (selected via diom_inv) of the sds signal. the sds timeslot is selected in sds_cr. sds_bcl ... enable iom bit clock for sds 0: the serial data strobe is generated in the programmed timeslot. 1: the iom bit clock is generated in the programmed timeslot. 4.3.13 mcda - monitoring cda bits value after reset: ff h mcdaxy ... monitoring cdaxy bits bit 7 and bit 6 of the cdaxy registers are mapped into the mcda register. this can be used for monitoring the d-channel bits on du and dd and the ?echo bits? on the tic bus with the same register 4.3.14 mor - monitor receive channel value after reset: ff h contains the monitor data received in the iom-2 monitor channel according to the monitor channel protocol. the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs. 70 mcda mcda21 mcda20 mcda11 mcda10 rd (5b) bit7 bit6 bit7 bit6 bit7 bit6 bit7 bit6 70 mor monitor receiver data rd (5c)
isac-sx te psb 3186 detailed register description data sheet 162 2003-01-30 4.3.15 mox - monitor transmit channel value after reset: ff h contains the monitor data to be transmitted in iom-2 monitor channel according to the monitor channel protocol.the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs 4.3.16 mosr - monitor interrupt status register value after reset: 00 h mdr ... monitor channel data received mer ... monitor channel end of reception mda ... monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab ... monitor channel data abort 4.3.17 mocr - monitor control register value after reset: 00 h mre ... monitor receive interrupt enable 0: monitor interrupt status mdr generation is masked 1: monitor interrupt status mdr generation is enabled 70 mox monitor transmit data wr (5c) 70 mosr mdr mer mda mab 0 0 0 0 rd (5d) 70 mocr mre mrc mie mxc 0 0 0 0 rd/wr (5e)
isac-sx te psb 3186 detailed register description data sheet 163 2003-01-30 mrc ... mr bit control determines the value of the mr bit: 0: mr is always ?1?. in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1: mr is internally controlled by the isac-sx te according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1). mie ... monitor interrupt enable monitor interrupt status mer, mda, mab generation is enabled (1) or masked (0). mxc ... mx bit control determines the value of the mx bit: 0: the mx bit is always ?1?. 1: the mx bit is internally controlled by the isac-sx te according to monitor channel protocol. 4.3.18 msta - monitor status register value after reset: 00 h mac ... monitor transmit channel active the data transmisson in the monitor channel is in progress. tout ... time-out read-back value of the tout bit. msta 00000mac0tout rd (5f)
isac-sx te psb 3186 detailed register description data sheet 164 2003-01-30 4.3.19 mconf - monitor configuration register value after reset: 00 h tout... time-out 0: the monitor time-out function is disabled 1: the monitor time-out function is enabled mconf0000000tout wr (5f)
isac-sx te psb 3186 detailed register description data sheet 165 2003-01-30 4.4 interrupt and general configuration 4.4.1 ista - interrupt status register value after reset: 00 h for all interrupts in the ista register following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated icd ... hdlc interrupt from d-channel an interrupt originated from the hdlc controller of the d-channel has been recognized. st ... synchronous transfer this interrupt is generated to enable the microcontroller to lock on to the iom timing for synchronous transfers. the source can be read from the sti register. cic ... c/i channel change a change in c/i channel 0 or c/i channel 1 has been recognized. the actual value can be read from cir0 or cir1. aux ... auxiliary interrupts signals an interrupt generated from external awake (pin eaw ), watchdog timer overflow, timer1 or timer2. the source can be read from the auxiliary interrupt register auxi. tran ... transceiver interrupt an interrupt originated in the transceiver in terrupt status register (istatr) has been recognized. mos ... monitor status a change in the monitor status register (mosr) has occured. note: a read of the ista register clears no ne of the interrupts. they are only cleared by reading the corresponding status register. 70 ista 0 0 st cic aux tran mos icd rd (60)
isac-sx te psb 3186 detailed register description data sheet 166 2003-01-30 4.4.2 mask - mask register value after reset: ff h for the mask register following logical states are applied: 0: interrupt is enabled 1: interrupt is disabled each interrupt source in the ista register can selectively be masked/disabled by setting the corresponding bit in mask to ?1?. masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to ?0?. note: in the event of a c/i channel change, cic is set in ista even if the corresponding mask bit in mask is set, but no interrupt is generated. 4.4.3 auxi - auxiliary interrupt status register value after reset: 00 h for all interrupts in the ista register the following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated eaw ... external awake interrupt an interrupt from the eaw pin has been detected. wov ... watchdog timer overflow signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits wtc1 and wtc2 (mode1 register) in the correct manner. a reset pulse has been generated by the isac-sx te. tin2, 1 ... timer interrupt 1, 2 an interrupt originated from timer 1 or timer 2 is recognized, i.e the timer has expired. 70 mask 1 1 st cic aux tran mos icd wr (60) 70 auxi 0 0 eaw wov tin2 tin1 0 0 rd (61)
isac-sx te psb 3186 detailed register description data sheet 167 2003-01-30 4.4.4 auxm - auxiliary mask register value after reset: ff h for the mask register following logical states are applied: 0: interrupt is enabled 1: interrupt is disabled each interrupt source in the auxi register can selectively be masked/disabled by setting the corresponding bit in auxm to ?1?. masked interrupt status bits are not indicated when auxi is read. instead, they remain internally stored and pending, until the mask bit is reset to ?0?. 4.4.5 mode1 - mode1 register value after reset: 00 h wtc1, 2 ... watchdog timer control 1, 2 after the watchdog timer mode has been selected (rss = ?11?) the watchdog timer is started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bit in the following sequence to reset and restart the watchdog timer. if wtc1/2 is not written fast enough in this way, the timer expires and a wov-interrupt (auxi register) together with a reset pulse is generated. cfs ... configuration select this bit determines clock relations and recovery on s/t and iom interfaces. 70 auxm 1 1 eaw wov tin2 tin1 1 1 wr (61) 70 mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 rd/wr (62) wtc1 wtc2 1. 2. 1 0 0 1
isac-sx te psb 3186 detailed register description data sheet 168 2003-01-30 0: the iom interface clock and frame signals are always active, "power down" state included. the states "power down" and "power up" are thus functionally identical except for the indication: pd = 1111 and pu = 0111. with the c/i command timing (tim) the microcontroller can enforce the "power up" state and with c/i command deactivation indication (di) the "power down" state is reached again. however, it is also possible to activate the s-interface directly with the c/i command activate request (ar 8/10/l) without the tim command. 1: the iom interface clock and frame signals are normally inactive ("power down"). for activating the iom-2 clocks the "power up" state can be induced by software (iom_cr.spu) or by resetting cfs again. after that the s-interface can be activated with the c/i command activate request (ar 8/10/l). the "power down" state can be reached again with the c/i command deactivation indication (di). note: after reset the iom interface is always active. to reach the "power down" state the cfs-bit has to be set. for general information please refer to chapter 3.3.8 . rss2, rss1... reset source selection 2,1 the isac-sx te reset sources for the rsto output pin can be selected according to the table below. if rss = ?00? no above listed reset source is selected and therefore no reset is generated at rsto . watchdog timer after the selection of the watchdog timer (rss = ?11?) the timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bits in two consecutive bit pattern (see description of the wtc1, 2 bits) otherwise the watchdog timer expires and a reset pulse of 125 s t 250 s is generated. deactivation of the watchdog timer is only possible with a hardware reset. rss c/i code change eaw watchdog timer bit 1 bit 0 0 0 -- -- -- 0 1 (reserved) 10xx-- 1 1 -- -- x
isac-sx te psb 3186 detailed register description data sheet 169 2003-01-30 if rss = ?10? is selected the following two reset sources generate a reset pulse of 125 s t 250s at the rsto pin: - external (subscriber) awake (eaw ) the eaw input pin serves as a request signal from the subscriber to initiate the awake function in a terminal and generates a reset pulse (in te mode only). - exchange awake (c/i code) a c/i code change generates a reset pulse. after a reset pulse generated by the isac-sx te and the corresponding interrupt (wov or cic) the actual reset source can be read from the ista. 4.4.6 mode2 - mode2 register value after reset: 00 h int_pol ... interrupt polarity selects the polarity of the interrupt pin int . 0: low active with open drain characteristic (default) 1: high active with push pull characteristic ppsdx ... push/pull output for sdx (sci interface) 0: the sdx pin has open drain characteristic 1: the sdx pin has push/pull characteristic 4.4.7 id - identification register value after reset: 01 h 70 mode2 0 0 0 0 int_ pol 0 0 ppsdx rd/wr (63) 70 id 0 0 design rd (64)
isac-sx te psb 3186 detailed register description data sheet 170 2003-01-30 design ... design number the design number allows to identify different hardware designs of the isac-sx te by software. 01 h : v 1.4 (all other codes reserved) 4.4.8 sres - software reset register value after reset: 00 h res_xx ... reset functional block xx a reset can be activated on the functional block c/i-handler, monitor channel, d-channel, iom handler, s-transceiver and to pin rsto . setting one of these bits to ?1? causes the corresponding block to be reset for a duration of 4 bcl clock cycles, except res_rsto which is activated for a duration of 125 ... 250s. the bits are automatically reset to ?0? again. 4.4.9 timr2 - timer 2 register value after reset: 00 h tmd ... timer mode timer 2 can be used in two different modes of operation. 0: count down timer. an interrupt is generated only once after a time period of 1...63 ms. 1: periodic timer. an interrupt is periodically generated every 1 ... 63 ms (see cnt). cnt ... timer counter 0: timer off. 1 ... 63:timer period = 1 ... 63 ms 70 sres res_ ci 0 0 res_ mon res_ dch res_ iom res_ tr res_ rsto wr (64) 70 timr2 tmd 0 cnt rd/wr (65)
isac-sx te psb 3186 detailed register description data sheet 171 2003-01-30 by writing ?0? to cnt the timer is immediately stopped. a value different from that determines the time period after which an interrupt will be generated. if the timer is already started with a certain cnt value and is written again before an interrupt has been released, the timer will be reset to the new value and restarted again. an interrupt is indicated to the host in auxi.tin2. note: reading back this value delivers back the current counter value which may differ from the programmed value if the counter is running.
isac-sx te psb 3186 electrical characteristics data sheet 172 2003-01-30 5 electrical characteristics 5.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. the supply voltage must show a monotonic rise. parameter symbol limit values unit min. max. ambient temperature under bias t a 0+70c storage temperature t stg ? 55 150 c input/output voltage on any pin with respect to ground v s ? 0.3 5.25 v maximum voltage on any pin with respect to ground v max 5.5 v
isac-sx te psb 3186 electrical characteristics data sheet 173 2003-01-30 5.2 dc characteristics v dd / v ss = 3.3 v 5%; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. h-input level (except pin sr1/2) v ih 2.0 5.5 v l-input level (except pin sr1/2) v il ? 0.3 0.8 v h-output level (except pin xtal2, sx1/ 2) v oh 2.4 v i oh = - 4.5 ma (ad0-7) i oh = - 400 a (all others) l-output level (except pin xtal2, sx1/ 2) v ol 0.45 v i ol = 6 ma (du, dd, c768) i ol = 4.5 ma (acl , aux7, aux6, ad0-7) i ol = 2 ma (all others) input leakage current output leakage current (all pins except sx1/2,sr1/2,xtal1/2, aux7/6) i li i lo 1 1 a a 0v< v in isac-sx te psb 3186 electrical characteristics data sheet 174 2003-01-30 5.3 capacitances t a = 25 c, v dd = 3.3 v 5% v ssa = 0 v, v ss = 0 v, f c = 1 mhz, unmeasured pins grounded. parameter symbol limit values unit remarks min. max. input capacitance i/o capacitance c in c i/o 7 7 pf pf all pins except sx1,2 and xtal1,2 output capacitance against v ss c out 10 pf pins sx1,2
isac-sx te psb 3186 electrical characteristics data sheet 175 2003-01-30 5.4 oscillator specification recommended oscillator circuits figure 70 oscillator circuits note: it is important to note that the load capacitance depends on the recommendation of the crystal specification. typical values are 22 ... 33 pf. xtal1 clock characteristics (external oscillator input) parameter symbol limit values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 40 pf oscillator mode fundamental parameter limit values min. max. duty cycle 1:2 2:1 its09659 7.68 mhz xtal1 xtal2 xtal2 xtal1 n.c. oscillator external signal crystal oscillator mode driving from external source 42 41 41 42 pf 33 33 pf c l l c
isac-sx te psb 3186 electrical characteristics data sheet 176 2003-01-30 5.5 ac characteristics t a = 0 to 70 c, v dd = 3.3 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.45 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 71. figure 71 input/output waveform for ac tests its09660 = 100 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf
isac-sx te psb 3186 electrical characteristics data sheet 177 2003-01-30 5.6 iom-2 interface timing data is transmitted with the rising edge of dcl and sampled with its falling edge. below figure shows double clock mode timing (the length of a timeslot is 2 dcl cycles), however, the timing parameters are valid both in single and double clock mode. figure 72 iom-2 timing (te mode) parameter symbol limit values unit min. max. iom output data delay t iod 60 ns iom input data setup t iis 4ns iom input data hold t iih 3ns fsc strobe delay (see note) t fsd -135 15 ns strobe signal delay t sdd 50 ns bcl / fsc delay t bcd 30 ns
isac-sx te psb 3186 electrical characteristics data sheet 178 2003-01-30 note: min. value in synchronous state, max. value in non-synchronous state. this results in a phase shift of fsc when the s-bus gets activated, this is the fsc signal is shifted by 135 ns. dcl clock output characteristics figure 73 definition of clock period and width dcl clock input characteristics note: in normal mode the iom clocks are output only. if the transceiver is disabled (dis_tr = 1) the iom clocks become input and e.g. the hdlc controller can still operate via the iom-2 interface. symbol limit values unit test condition min. typ. max. t p 585 651 717 ns osc 100 ppm t wh 260 325 391 ns osc 100 ppm t wl 260 325 391 ns osc 100 ppm parameter limit values unit min. max. duty cycle 40 60 % 2.3 v
isac-sx te psb 3186 electrical characteristics data sheet 179 2003-01-30 5.7 microcontroller interface timing 5.7.1 serial control interface (sci) timing figure 74 sci interface parameter sci interface symbol limit values unit min. max. scl cycle time t 1 200 ns scl high time t 2 100 ns scl low time t 3 100 ns cs setup time t 4 2ns cs hold time t 5 10 ns sdr setup time t 6 10 ns sdr hold time t 7 6ns sdx data out delay t 8 30 ns cs high to sdx tristate t 9 40 ns cs scl sdr sdx t 4 t 2 t 3 t 1 t 9 t 5 t 6 t 7 t 8
isac-sx te psb 3186 electrical characteristics data sheet 180 2003-01-30 5.7.2 parallel microcontroller interface timing siemens/intel bus mode the data read and write timing is the same for multiplexed and non multiplexed bus operation ( figure 75 and figure 76 ). figure 77 shows the corresponding address timing in multiplexed mode and figure 78 in non multiplexed mode. figure 75 microprocessor read cycle figure 76 microprocessor write cycle figure 77 multiplexed address timing
isac-sx te psb 3186 electrical characteristics data sheet 181 2003-01-30 figure 78 non-multiplexed address timing motorola bus mode the motorola bus is non multiplexed. the data timing is shown in figure 79 (read) and figure 80 (write). the corresponding address timing (for both read and write) is shown in figure 81 . figure 79 microprocessor read timing itt09661 wr x cs or a0-a7 t ah t as address rd x cs d0-7
isac-sx te psb 3186 electrical characteristics data sheet 182 2003-01-30 figure 80 microprocessor write cycle itt09679 cs x ds d0 - d7 t dw data t wd dsd t ww tt wi r / w t rwd d0-7
isac-sx te psb 3186 electrical characteristics data sheet 183 2003-01-30 figure 81 non-multiplexed address timing microprocessor interface timing parameter symbol limit values unit min. max. ale pulse width t aa 20 ns address setup time to ale t al 5ns address hold time from ale t la 3ns address latch setup time to wr , rd t als 10 ns address setup time t as 10 ns address hold time t ah 3ns ale guard time t ad 15 ns ds delay after r/w setup t dsd 3ns rd pulse width t rr 100 ns data output delay from rd t rd 80 ns data float from rd t df 25 ns rd control interval t ri 70 ns w pulse width t ww 10 ns data setup time to w x cs t dw 10 ns data hold time w x cs t wd 2ns w control interval t wi 70 ns r/w hold from cs x ds inactive t rwd 2ns itt09662 cs x ds ad0 - ad7 t ah t as a0-7
isac-sx te psb 3186 electrical characteristics data sheet 184 2003-01-30 5.8 reset figure 82 reset signal res parameter symbol limit values unit test conditions min. length of active low state t res 4 ms power on/power down to power up (standby) 2 x dcl clock cycles during power up (standby) 21150_26 res t res
isac-sx te psb 3186 electrical characteristics data sheet 185 2003-01-30 5.9 s-transceiver parameter symbol limit values unit test condition min. typ. max. v dd = 3.3 v 5%; v ss = 0 v; t a = 0 to 70 c absolute value of output pulse amplitude | vsx2 ? vsx1 | v x 1.17 v r l = transmitter output current i x 26 ma r l = 5.6 transmitter output impedance (sx1,2) z x 10 0 k inactive or during binary one; during binary zero r l = 50 receiver input impedance (sr1,2) z r 30 k v dd = 3.3 v
isac-sx te psb 3186 electrical characteristics data sheet 186 2003-01-30 5.10 recommended transformer specification note: in te mode, at the pulse shape measurement with a load of 400 (e.g. k 1403 approval test ?pulse shape?) overshots might occur with a leakage inductance greater than 6 h. parameter symbol limit values unit test condition min. typ. max. transformer ratio 1:1 main inductance l 25 20 mh mh no dc current, 10 khz 2.5 ma dc current, 10 khz leakage inductance l l 6 h te mode, 10 khz capacitance between primary and secondary side c80pf1 khz copper resistance r 1.7 2.0 2.3
isac-sx te psb 3186 electrical characteristics data sheet 187 2003-01-30 5.11 line overload protection the maximum input current for the s-transceiver lines (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. the desctruction limits are shown in figure 83 . figure 83 maximum line input current 21150_35 t [s] 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 i [a] 1 2 3 1.5 0.80 0.65 0.52 0.40
isac-sx te psb 3186 electrical characteristics data sheet 188 2003-01-30 5.12 emc / esd aspects to improve performance with respect to emc and esd requirements it is recommended to provide additional capacitors in the middle tap of the transformers (see figure 84 below). the values for c1 and c2 should be in the range 1 ... 10 nf. they can be located either on the chip side of the transformer (option 1) or on the s bus side (option 2), but not on both sides. this improves emc immunity acording to en55024 which is mandatory since 2001-07- 01. note: the figure does not show any other components required for protection circuit in receive and transmit direction as this is not affected by including c1 and c2. figure 84 transformer circuitry ac ac ac c k1 c p2 c p1 c p4 c p3 c k4 c 1 c 2 transmitter (nt) transmitter (te) sr1 sr2 sx1 sx2 c k2 c k3 test generator 0.15mhz - 80mhz carrier with 1 khz, 80% amplitude modulated signal couple capacity: c k1 c k2 c k3 c k4 parasitic capacity: c p1 c p2 c p3 c p4 test setup c1, c2 required to supress common mode signals (option 1) c 1 c 2 c1 and c2 are also possible at this position (option 2) 21150_34
isac-sx te psb 3186 package outlines data sheet 189 2003-01-30 6 package outlines p-mqfp-64-1 (plastic metric quad flat package) gpm05220 y ou can find all of the current packages, types of packing, and others on the infineon internet pag e ? products?: http://www.infineon.com/products . dimensions in mm s md = surface mounted device
isac-sx te psb 3186 package outlines data sheet 190 2003-01-30 p-tqfp-64-1 (plastic thin quad flat package) gpm05613 y ou can find all of the current packages, types of packing, and others on the infineon internet pag e ? products?: http://www.infineon.com/products . dimensions in mm s md = surface mounted device
isac-sx te psb 3186 appendix data sheet 191 2003-01-30 7appendix d-channel hdlc, c/i-channel handler name76543210addrr/wres rfifod d-channel receive fifo 00 h - 1f h r xfifod d-channel transmit fifo 00 h - 1f h w istad rme rpf rfo xpr xmr xdu 0 0 20 h r10 h maskd rme rpf rfo xpr xmr xdu 1 1 20 h wff h stard xdov xfw 0 0 raci 0 xaci 0 21 h r40 h cmdrd rmc rres 0 sti xtf 0 xme xres 21 h w00 h moded mds2 mds1 mds0 0 rac dim2 dim1 dim0 22 h r/w c0 h exmd1 xfbs rfbs sra xcrc rcrc 0 itf 23 h r/w 00 h timr1 cnt value 24 h r/w 00 h sap1 sapi1 0 mha 25 h wfc h sap2 sapi2 0 mla 26 h wfc h rbcld rbc7 rbc0 26 h r00 h rbchd 0 0 0 ov rbc11 rbc8 27 h r00 h tei1 tei1 ea1 27 h wff h tei2 tei2 ea2 28 h wff h rstad vfr rdo crc rab sa1 sa0 c/r ta 28 h r0f h tmd 0000000tlp29 h r/w 00 h reserved 2a-2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h
isac-sx te psb 3186 appendix data sheet 192 2003-01-30 cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h transceiver name76543210 addrr/wres tr_ conf0 dis_ tr 0en_ icv 0 0 0 exlp ldd 30 h r/w 01 h tr_ conf1 0rpll_ adj en_ sfsc 00xx x31 h r/w tr_ conf2 dis_ tx pds 0 rlp 0 0 0 0 32 h r/w 80 h tr_sta rinf slip icv 0 fsyn 0 ld 33 h r00 h reserved 34 h sqrr1 msyn mfen 0 0 sqr11sqr12sqr13sqr14 35 h r40 h sqxr1 0 mfen 0 0 sqx11 sqx12sqx13 sqx14 35 h w4f h sqrr2 sqr21sqr22sqr23sqr24sqr31sqr32sqr33sqr34 36 h r00 h reserved 36 h w sqrr3 sqr41sqr42sqr43sqr44sqr51sqr52sqr53sqr54 37 h r00 h reserved 37 h w istatr 0 x x x ld ric sqc sqw 38 h r00 h masktr 1 1 1 1 ld ric sqc sqw 39 h r/w ff h reserved 3a h - 3b h acfg2 0 0 0 0 acl led 0 0 3c h r/w 00 h reserved 3d h - 3f h
isac-sx te psb 3186 appendix data sheet 193 2003-01-30 iom handler (timeslot , data port selection, cda data and cda control register) name76543210addrr/wres cda10 controller data access register (ch10) 40 h r/w ff h cda11 controller data access register (ch11) 41 h r/w ff h cda20 controller data access register (ch20) 42 h r/w ff h cda21 controller data access register (ch21) 43 h r/w ff h cda_ tsdp10 dps 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 tss 47 h r/w 81 h reserved 48 h - 4b h tr_ tsdp_ bc1 dps 0 0 tss 4c h r/w tr_ tsdp_ bc2 dps 0 0 tss 4d h r/w cda1_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4e h r/w 00 h cda2_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4f h r/w 00 h
isac-sx te psb 3186 appendix data sheet 194 2003-01-30 iom handler (control registers, synchronous transfer interrupt control), monitor handler name76543210addrr/wres tr_cr (ci_cs=0) en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 50 h r/w trc_cr (ci_cs=1) 00000 cs2-0 50 h r/w reserved 51 h reserved 52 h dci_cr (ci_cs=0) dps_ ci1 en_ ci1 d_ en_d d_ en_b2 d_ en_b1 cs2-0 53 h r/w dcic_cr (ci_cs=1) 00000 cs2-0 53 h r/w mon_cr dps en_ mon 000 cs2-0 54 h r/w sds_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 55 h r/w 00 h reserved 56 h iom_cr spu 0 ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom 57 h r/w 08 h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0000ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h sds_ conf 0000diom_ inv diom_ sds 0sds_ bcl 5a h r/w 00 h mcda mcda21 mcda20 mcda11 mcda10 5b h rff h
isac-sx te psb 3186 appendix data sheet 195 2003-01-30 mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosrmdrmermdamab00005d h r00 h mocrmremrcmiemxc00005e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h interrupt, general configuration registers name76543210 addrr/wres ista 0 0 st cic aux tran mos icd 60 h r00 h mask 1 1 st cic aux tran mos icd 60 h wff h auxi 0 0 eaw wov tin2 tin1 0 0 61 h r00 h auxm 1 1 eaw wov tin2 tin1 1 1 61 h wff h mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 62 h r/w 00 h mode20000int_ pol 0 0 ppsdx 63 h r/w 00 h id 0 0 design 64 h r01 h sres res_ ci 0 0 res_ mon res_ dch res_ iom res_ tr res_ rsto 64 h w00 h timr2 tmd 0 cnt 65 h r/w 00 h reserved 66 h - 6f h
isac-sx te psb 3186 index data sheet 196 2003-01-30 a absolute maximum ratings 172 ac characteristics 176 acfg2 register 149 ackxy bits 159 acl bit 149 activation 67 activation indication - pin acl 38 activation led 38 activation/deactivation of iom-2 interface 100 appendix 191 applications 18 architecture 25 asti register 159 aux bit 165 auxi register 166 auxm register 167 b bac bit 141 bas bit 140 bus operation modes 31 c c/i channel 93 c/r bit 138 capacitances 174 cda_tsdpxy registers 151 cdax_cr register 152 cdaxy registers 151 cfs bit 167 ci_cs bit 157 ci1e bit 142 cic bit 165 cic1/0 bits 140 cicw bit 142 cir0 register 140 cir1 register 142 cix0 register 141 cix1 register 142 clkm bit 157 clock generation 54 cmdr register 131 cnt bits 135, 170 codr0 bits 140 codr1 bits 142 codx0 bits 141 codx1 bits 142 control of layer-1 57 controller data access 72 crc bit 138 d d_en_b2/1 bits 154 d_en_d bit 154 dc characteristics 173 d-channel access control s-bus priority mechanism 97 tic bus 95 dci_cr register 154 dcic_cr register 155 deactivation 67 delay between iom-2 and s 44 design bits 169 device architecture 25 dim2-0 bits 132 diom_inv bit 160 diom_sds bit 160 direct address mode 32 dis_iom bit 157 dis_od bit 157 dis_tr bit 144 dis_tx bit 145 dps bit 151, 156 dps_ci1 bit 154 e ea1 bit 137 ea2 bit 138 eaw bit 166 electrical characteristics 172 en_b2/1r bits 153 en_b2/1x bits 153 en_bcl bit 157
isac-sx te psb 3186 index data sheet 197 2003-01-30 en_ci1 bit 154 en_d bit 153 en_i0 bit 152 en_i1 bit 152 en_icv bit 144 en_mon bit 156 en_o0 bit 152 en_o1 bit 152 en_sfsc bit 145 en_tbm bit 152 ens_tssx bits 156 exchange awake 35 exlp bit 144 exmd1 register 134 extended transparent mode 117 external reset input 35 f features 15 fsyn bit 146 functional blocks 25 h hdlc controllers access to iom channels 117 data reception 104 data transmission 112 extended transparent mode 117 interrupts 118 receive frame structure 109 test functions 119 transmit frame structure 116 i icd bit 165 icv bit 146 id register 169 indirect address mode 32 int_pol bit 169 interrupt structure 33 iom_cr register 157 iom-2 68 frame structure (te) 69 handler 70 interface timing 177 monitor channel 84 ista register 165 istad register 128 istatr register 148 itf bit 134 j jitter 55 l ld bit 146, 148 ldd bit 144 led bit 149 led output 38 level detection 50 logic symbol 17 looping data 73 m mab bit 162 mac bit 163 mask register 166 maskd register 130 masktr register 149 mcda register 161 mcdaxy bits 161 mconf register 164 mda bit 162 mdr bit 162 mds2-0 bits 132 mer bit 162 mfen bit 147 mha bit 135 microcontroller interface timing 179 microcontroller interfaces 27 mie bit 162 mla bit 136 mocr register 162 mode1 register 167 mode2 register 169 moded register 132
isac-sx te psb 3186 index data sheet 198 2003-01-30 mon_cr register 156 monitor channel error treatment 89 handshake procedure 86 interrupt logic 93 master device 91 slave device 91 time-out procedure 92 monitoring data 77 mor register 161 mos bit 165 mosr register 162 mox register 162 mrc bit 162 mre bit 162 msta register 163 msti register 160 msyn bit 147 multiframing 42 mxc bit 162 o oscillator 175 oscillator clock output 56 ov bit 137 overview 12 p package outlines 189 parallel microcontroller interface 31 pds bit 145 pin configuration 19 ppsdx bit 169 r rab bit 138 rac bit 132 raci bit 130 rbc11-8 bits 137 rbc7-0 bits 136 rbchd register 137 rbcld register 136 rcrc bit 134 rdo bit 138 receive pll 55 register description 121 res_xxx bits 170 reset generation 34 reset source selection 34 reset timing 184 rfbs bits 134 rfifod register 128 rfo bit 128 ric bit 148 rinf bit 146 rlp bit 145 rmc bit 131 rme bit 128 rpf bit 128 rpll_adj bit 145 rres bit 131 rss2/1 bits 167 rstad register 138 s s/g bit 140 s/t-interface 39 circuitry 47 coding 40 delay compensation 50 external protection circuitry 47 multiframing 42 receiver characteristics 46 transceiver enable/disable 51 transmitter characteristics 45 sa1/0 bits 138 sap1 register 135 sap2 register 136 s-bus priority mechanism 97 sci - serial control interface 28 sci interface timing 179 sds 82 sds_bcl bit 160 sds_conf register 160 sdsx_cr registers 156 serial data strobe 82
isac-sx te psb 3186 index data sheet 199 2003-01-30 shifting data 73 slip bit 146 software reset 35 spu bit 157 sqc bit 148 sqr1-4 bits 147 sqr21-24 bits 148 sqr31-34 bits 148 sqr41-44 bits 148 sqr51-54 bits 148 sqrr1 register 147 sqrr2 register 148 sqrr3 register 148 sqw bit 148 sqx1-4 bits 147 sqxr1 register 147 sra bit 134 sres register 170 st bit 165 stard register 130 state machine te mode 59 sti bit 131 sti register 159 stixy bits 159, 160 stop/go bit 140 stovxy bits 159, 160 strobed data clock 82 subscriber awake 35 swap bit 152 synchronous transfer 78 t ta bit 138 tba2-0 bits 141 tei1 register 137 tei2 register 138 test functions 52 test signals 120 tic bus 95 tic_dis bit 157 timer 35 timer 1 36 timer 2 37 timr1 register 135 timr2 register 170 tin2/1 bits 166 tlp bit 140 tmd bit 170 tmd register 140 tout bit 163, 164 tr_conf0 register 144 tr_conf1 register 145 tr_conf2 register 145 tr_cr register 153 tr_sta register 146 tr_tsdp_bc1/2 registers 151 tran bit 165 transceiver enable/disable 51 transformer specification 186 trc_cr register 154 tss bits 151, 156 typical applications 18 v value bits 135 vfr bit 138 w watchdog timer 35 wov bit 166 wtc1/2 bits 167 x xaci bit 130 xcrc bit 134 xdov bit 130 xdu bit 128 xfbs bit 134 xfifod register 128 xfw bit 130 xme bit 131 xmr bit 128 xpr bit 128 xres bit 131 xtf bit 131
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