? 1/7 application where transient overvoltage protection in esd sensitive equipment is required, such as : computers printers communication systems and cellular phones video equipment this device is particularly adapted to the protection of symmetrical signals. description the ESDA14V2-4BF2 is a monolithic array designed to protect up to 4 lines in a bidirectional way against esd transients. the device is ideal for situations where board space saving is requested. features 4 bidirectional transil functions esd protection: iec61000-4-2 level 4 stand off voltage: 12 v min. low leakage current < 1 a 50 w peak pulse power (8/20 s) benefits high esd protection level high integration suitable for high density boards complies with the following standards: iec61000-4-2 15 kv (air discharge) 8 kv (contact discharge) mil std 883f- method 3015-7: class3 25 kv (human body model) ESDA14V2-4BF2 quad bidirectional transil? array for esd protection rev. 3 january 2006 flip-chip (5 bumps) figure 1: pin configuration (bump side) gnd a1 a3 c1 c3 tm: transil is a trademark of stmicroelectronics. table 1: order code part number marking ESDA14V2-4BF2 ea asd (application specific devices) figure 2: pin configuration (bump side) a b c 31 2
ESDA14V2-4BF2 2/7 table 2: absolute ratings (limiting values) table 3: electrical characteristics (t amb = 25 c) symbol parameter value unit v pp esd discharge mil std 883e - method 3015-7 iec61000-4-2 air discharge iec61000-4-2 contact discharge 25 15 8 kv p pp peak pulse power (8/20 s) 50 w t j junction temperature 125 c t stg storage temperature range -55 to +150 c t l lead solder temperature (10 seconds duration) 260 c t op operating temperature range -40 to +125 c symbol parameter v br breakdown voltage i rm leakage current @ v rm v rm stand-off voltage v cl clamping voltage r d dynamic impedance i pp peak pulse current c capacitance part number v br @ i r i rm @ v rm r d tc min. max. max. typ. max. max. note 1 note 2 0v bias v v ma a v ? 10 -4 /c pf ESDA14V2-4BF2 14.2 18 1 112 3.2 10 15 0.1 3 note 1: square pulse, i pp = 3a, tp = 2.5 s. note 2: ? v br = t (tamb -25 c) x v br (25 c) v cl v br v rm i pp i slope: 1 / r d v
ESDA14V2-4BF2 3/7 figure 3: clamping voltage versus peak pulse current (tj initial = 25 c) (rectangular waveform, t p = 2.5 s) figure 4: capacitance versus reverse applied voltage (typical values) figure 5: relative variation of leakage current versus junction temperature (typical values) figure 6: esd response to iec61000-4-2 (+15 kv air discharge) figure 7: esd response to iec61000-4-2 (-15 kv air discharge) figure 8: analog crosstalk 0.1 1.0 10.0 0 102030405060 v (v) cl i (a) pp tp = 2.5s 0 2 4 6 8 10 12 14 02468101214 v (v) r c(pf) f=1mhz v =30mv t =25c osc rms j 1 10 100 1000 25 50 75 100 125 t (c) j i [t ] / i [t =25c] rj rj v(i/o) v(i/o) 100.0k 1.0m 10.0m 100.0m 1.0g -100.0 -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 f/hz typical crosstalk response of esda14v2-4bf1 (a1/a3 line)
ESDA14V2-4BF2 4/7 figure 10: application example figure 11: aplac model figure 9: digital crosstalk v g1 21 g1 v rise time: t = 3ns 10-90% v= a1 v = 0-3v f = 5mhz in v= c3 out connector ic to be protected a1 a3 c1 c3 b2 100m 1.2pf 100m 50ph 50m 160ph 1.8 b2 1.2pf 100m 1.2pf 100m 1.2pf d02_r c3 a3 c1 b2 a1 d02_r bv = 16 ibv = 1m cjo = 200p m = 0.3333 rs = 1 vj = 0.6 tt = 100n d02_f bv = 16 ibv = 1m cjo = 10.4p m = 0.3333 rs = 2 vj = 0.6 tt = 100n
ESDA14V2-4BF2 5/7 figure 12: ordering information scheme figure 13: flip-chip package mechanical data figure 14: foot print recommendations figure 15: marking esda 14v2 - 4 b fx esd array number of line package breakdown voltage type 14v2 = 14.2 volts min. b = bidirectional 4 = 4 lines f = flip-chip x = 2: leadfree pitch = 500m, bump = 315m 1.12 mm 50m 1.12 mm 50m 315m 50 700m 50 650m 65 4 95 m 40 copper pad diameter : 250m recommended , 300m max solder stencil opening : 330m solder mask opening recommendation : 340m min for 315m copper pad diameter x y x w z w dot, st logo xx = marking yww = datecode (y = year ww = week) z = manufacturing location e
ESDA14V2-4BF2 6/7 figure 16: flip-chip tape and reel specification dot identifying pin a1 location user direction of unreeling all dimensions in mm 4 +/- 0.1 8 +/- 0.3 4 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 ? 1.5 +/- 0.1 0.73 +/- 0.05 xxz yww st xxz yww st xxz yww st e e e in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the inner box label, in compliance with jedec standard jesd97. the maximum ratings relat- ed to soldering conditions are also marked on the inner box label. ecopack is an st trademark. eco- pack specifications are available at: www.st.com. table 4: ordering information note: more informations are available in the application notes: an1235: ?flip-chip: package description and recommendations for use? ordering code marking package weight base qty delivery mode ESDA14V2-4BF2 ea flip-chip 2.1 mg 5000 tape & reel 7? table 5: revision history date revision description of changes 14-mar-2005 1 first issue. 18-oct-2005 2 dimension from center bump to corner bump changed in figure 13 to indicate diagonal instead of perpendicular measurement. no values changed. ecopack statement added. 17-jan-2006 3 die dimensions changed in figure 13. cavity depth changed in figure 16
ESDA14V2-4BF2 7/7 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered tr ademark of stmicroelectronics. all other names are the property of their respective owners ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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