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128-macrocell max? eplds fax id: 6104 cy7c346 cy7c346b cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 october 1989 C revised march 31, 1997 1cy 7 c34 6b features ? 128 macrocells in 8 labs ? 20 dedicated inputs, up to 64 bidirectional i/o pins ? programmable interconnect array ? 0.8-micron double-metal cmos eprom technology (cy7c346) ? advanced 0.65-micron cmos technology to increase performance (cy7c346b) ? available in 84-pin clcc, plcc, and 100-pin pga, pqfp functional description the cy7c346/cy7c346b is an erasable programmable log- ic device (epld) in which cmos eprom cells are used to configure logic functions within the device. the max architec- ture is 100% user configurable, allowing the devices to accom- modate a variety of independent logic functions. the 128 macrocells in the cy7c346/cy7c346b are divided into 8 logic array blocks (labs), 16 per lab. there are 256 expa nder product terms, 32 per lab, to be used and shared by the macrocells within each lab. each lab is interc onnected through the programmable inter- connect array, allowing all signals to be routed throughout the chip. the speed and density of the cy7c346/cy7c346b allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series ttl logic, to complex cont rollers and multifunction chips. with greater than 25 times the func- tional ity of 20-pin plds, the cy7c346/cy7c346b allows the replacement of over 50 ttl devices. by replacing large amounts of logic, the cy7c346/cy7c346b reduces board space, part count, and incre ases sy stem reliability. macrocell 49 macrocell 50 macrocell 51 macrocell 52 macrocell 53 macrocell 54 macrocell 55 macrocell 56 macrocell 33 macrocell 34 macrocell 35 macrocell 36 macrocell 37 macrocell 38 macrocell 39 macrocell 40 macrocell 104 macrocell 103 macrocell 102 macrocell 101 macrocell 100 macrocell 99 macrocell 98 macrocell 97 macrocell 120 macrocell 119 macrocell 118 macrocell 117 macrocell 116 macrocell 115 macrocell 114 macrocell 113 macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 21 macrocell 22 macrocell 23 macrocell 24 logic block diagram c346C1 macrocell 88 macrocell 87 macrocell 86 macrocell 85 macrocell 84 macrocell 83 macrocell 82 macrocell 81 macrocell 121C128 macrocell 105C112 macrocell 86C96 macrocell 41C48 macrocell 25C32 macrocell 9C16 system clock p i a input [59] (n4) 36 . input [60] (m5) 37 . input [61] (n5) 38 . input [64] (n6) 41 . input [65] (m7) 42 . input [66] (l7) 43 . input [67] (n7) 44 . input [70] (l8) 47 . input [71] (n9) 48 . input [72] (m9) 49 . [100] (c13) nc [99] (d12) nc [98] (d13) 77 [97] (e12) 76 [96] (e13) 75 [95] (f11) 74 [92] (g13) 73 [91] (g11) 72 [90] (g12) nc [89] (h13) nc [86] (j13) 71 [85] (j12) 70 [84] (k13) 69 [83] (k12) 68 [82] (l13) 67 [81] (l12) 64 [80] (m13) nc [79] (m12) nc [78] (n13) 63 [77] (m11) 60 [76] (n12) 59 [75] (n11) 58 [74] (m10) 57 [73] (n10) 56 [58] (m4) nc [57] (n3) nc [56] (m3) 55 [55] (n2) 54 [54] (m2) 53 [53] (n1) 52 [52] (l2) 51 [51] (m1) 50 8 (b13) [1] 9 (c12) [2] 10 (a13) [3] 11 (b12) [4] 12 (a12) [5] 13 (11) [6] nc (a11) [7] nc (b10) [8] 14 (a4) [23] 15 (b4) [24] 16 (a3) [25] 17 (a2) [26] 18 (b3) [27] 21 (a1) [28] nc (b2) [29] nc (b1) [30] 22 (c2) [31] 25 (c1) [32] 26 (d2) [33] 27 (d1) [34] 28 (e2) [35] 29 (e1) [36] nc (f1) [39] nc (g2) [40] 30 (g3) [41] 31 (g1) [42] 32 (h3) [45] 33 (j1) [46] 34 (j2) [47] 35 (k1) [48] nc (k2) [49] nc (l1) [50] lab h lab g lab f lab e lab a lab b lab c lab d 3, 20, 37, 54 (a6,b6,f12,f13,h1,h2,m8,n8) [18, 19, 43, 44, 68, 69, 93, 94] 16, 33, 50, 67 (b8,c8,f2,f3,h11,h12,l6,m6) [12, 13, 37, 38, 62, 63, 87, 88] v cc gnd ( ) C pertain to 100Cpin pga package 1 (c7) [16] input/clk .. 78 (a10) [9] input . ..... 79 (b9) [10] input . ..... 80 (a9) [11] input ..... 83 (a8) [14] input . ..... 84 (b7) [15] input . ..... 2 (a7) [17] input .. ..... 5 (c6) [20] input .. ..... 6 (a5) [21] input .. ..... 7 (b5) [22] input .. ..... macrocell 73C 80 macrocell 72 macrocell 71 macrocell 70 macrocell 69 macrocell 68 macrocell 67 macrocell 66 macrocell 65 macrocell 57C 64 [ ] C pertain to 100Cpin pqfp package .
cy7c346 cy7c346b 2 selection guide 7c346bC15 7c346bC20 7c346C25 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 maximum access time (ns) 15 20 25 30 35 maximum operating current (ma) commercial 250 250 250 250 250 military 320 325 320 320 industrial 320 320 320 320 320 maximum standby current (ma) commercial 225 225 225 225 225 military 275 275 275 275 industrial 275 275 275 275 275 shaded area contains preliminary information. pin configurations i/o top view plcc/clcc 7 64 53 11 12 10 98 43 42 44 45 46 21 22 24 23 25 13 14 41 40 21 26 27 18 19 17 16 15 20 28 29 31 30 32 33 36 35 37 38 39 34 52 51 49 50 48 47 7c346 c346C2 53 54 55 60 58 59 57 56 66 65 63 64 62 67 61 i/o i/o i/o v cc inp /clk inp gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc inp gnd inp i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pga bottom view 7c346 c346C3 inp inp i/o i/o i/o i/o i/o i/o l k j h g f e d c b a 1 2 3 4 5 6 7 9 10 11 7c346b 7c346b i/o i/o i/o inp 8 i/o i/o i/o i/o i/o i/o i/o v cc 12 13 n m inp i/o inp inp inp i/o i/o gnd gnd v cc v cc i/o i/o i/o inp gnd i/o i/o v cc v cc gnd gnd i/o i/o i/o inp gnd inp i/o inp inp i/o inp v cc inp inp inp 74 73 72 71 70 69 68 84 83 82 81 80 79 78 77 76 75 i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o v cc v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc v cc i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o
cy7c346 cy7c346b 3 pin configurations (continued) top view pqfp 72 71 69 70 68 2 3 1 36 35 12 13 15 14 16 4 5 34 33 67 66 17 26 9 10 8 7 6 11 27 28 30 29 31 32 61 60 58 59 57 65 64 56 i/o i/o i/o i/o i/o i/o input i/o input v cc v cc input input input i/o i/o i/o i/o i/o i/o input input input 62 63 i/o input input i/o i/o gnd gnd input input input i/o i/o i/o v cc v cc input input input i/o i/o i/o 18 19 20 21 22 23 24 25 55 54 53 52 51 50 49 48 47 46 45 37 38 39 40 41 42 43 44 80 79 77 78 76 75 74 73 95 96 97 98 100 99 81 82 83 84 85 86 94 93 92 91 90 89 88 87 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input gnd gnd input input/clk input c346C4 7c346 7c346b
cy7c346 cy7c346b 4 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................C65 c to+150 c ambient temperature with power applied..............................................C55 c to+125 c maximum junction temperature (under bias).................................................................. 150 c supply voltage to ground potential ................ C2.0v to+7.0v maximum power dissipation................................... 2500 mw dc v cc or gnd current ............................................ 500 ma dc output current per pin........................ C25 ma to+25 ma dc input voltage [1] ........................................C3.0v to + 7.0v dc program voltage .................................................... 13.0v static discharge voltage ........................................... >1100v (per mil-std-883, method 3015) operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial C40 c to +85 c 5v 10% military C55 c to +125 c (case) 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = C4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.45 v v ih input high voltage 2.2 v cc +0.3 v v il input low voltage C0.3 0.8 v i ix input current gnd < v in < v cc C10 +10 m a i oz output leakage current v o = v cc or gnd C40 +40 m a i os output short circuit current v cc = max., v out = 0.5v [3, 4] C30 C90 ma i cc1 power supply current (stand- by) v i = gnd (no load) coml 225 ma mil/ind 275 i cc2 power supply current [5] v i = v cc or gnd (no load) f = 1.0 mhz [4] coml 250 ma mil/ind 320 t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance [6] parameter description test conditions max. unit c in input capacitance v in = 2v, f = 1.0 mhz 10 pf c out output capacitance v out = 2v, f = 1.0 mhz 20 pf notes: 1. minimum dc input is C0.3v. during transitions, the inputs may undershoot to C3.0v for periods less than 20 ns. 2. typical values are for t a = 25 c and v cc = 5v. 3. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 4. guaranteed by design but not 100% tested. 5. this parameter is measured with device programmed as a 16-bit counter in each lab. 6. part (a) in ac test load and waveforms is used for all parameters except t er and t xz , which is used for part (b) in ac test load and waveforms. all external timing parameters are measured referenced to external pins of the device.
cy7c346 cy7c346b 5 logic array blocks there are 8 logic array blocks in the cy7c346/cy7c346b. each lab consists of a macrocell array containing 16 macro- cells, an ex pander product term array containing 32 expand- ers, and an i/o block. the lab is fed by the programmable interc onnect ar ray and the dedicated input bus. all macrocell feedbacks go to the macrocell array, the ex pander array, and the programmable interconnect array. ex panders feed them- selves and the macrocell array. all i/o feedbacks go to the programmable interconnect array so that they may be access- ed by macrocells in other labs as well as the macrocells in the lab in which they are situated. externally, the cy7c346/cy7c346b provides 20 dedicated inputs, one of which may be used as a system clock. there are 64 i/o pins that may be individually configured for input, output, or bidirectional data flow. programmable interconnect array the programmable interc onnect ar ray (pia) solves intercon- nect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. ac test loads and waveforms [6] 3.0v 5v output r1 464 w r2 250 w 50 pf including jigand scope gnd 90% 10% 90% 10% 6ns 6 ns 5v output r1 464 w r2 250 w 5pf including jigand scope (a) (b) output 1.75v equivalent to: thvenin equivalent(commercial/military) all input pulses c346C5 c346C6 163 w figure 1. cy7c346/cy7c346b internal timing model logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in register output delay t od t xz t zx logic array delay t lad feedback delay t fd output input c346C7 systemclockdelay t ics t rh t rsu t pre t clr pia delay t pia i/o delay t io
cy7c346 cy7c346b 6 timing delays timing delays within the cy7c346/cy7c346b may be easily determined using warp2 a or warp3 a software or by the mod- el shown in or figure 1 . the cy7c346 /cy7c346b has fixed internal delays, allowing the user to determine the worst case timing delays for any design. for complete timing information, warp3 software provides a timing simulator. design recommendations operation of the devices descr ibed herein with conditions above those listed under maximum ratings may cause per- manent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this datasheet is not implied. ex posure to absolute maximum rat- ings conditions for extended periods of time may affect device reliability. the cy7c346/cy7c346b contains ci rcuitry to pro- tect device pins from high static voltages or elect ric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. for proper operation, input and output pins must be con- strained to the range gnd (vin or vout) vcc. unused inputs must always be tied to an appropriate logic level (ei- ther vcc or gnd). each set of vcc and gnd pins must be connected together directly at the device. power supply de- coupling capacitors of at least 0.2 m f must be connected between vcc and gnd. for the most effective decoupling, each vcc pin should be separately decoupled to gnd di- rectly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types have. design security the cy7c346/cy7c346b contains a programmable design security feature that controls the access to the data pro- grammed into the device. if this programmable feature is used, a proprietary design implemented in the device cannot be cop- ied or retrieved. this enables a high level of design control to be obtained since programmed data wi thin eprom cells is invisible. the bit that controls this function, along with all other program data, may be reset simply by erasing the entire de- vice. the cy7c346/cy7c346b is fully functionally tested and guar- anteed through complete testing of each programmable eprom bit and all internal logic elements thus ensuring 100% programming yield. the erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. the devices also contain on-board logic test circuitry to allow verification of function and ac speci fication once enca psulat- ed in non-windowed packages. typical i cc vs. f max output drive current 400 300 200 100 1 khz 10 khz 100 khz 1 mhz maximum frequency 10 mhz 0 50 mhz 100 hz v cc =5.0v roomtemp. c346C8 01 2 3 4 v o output voltage (v) 100 80 60 40 20 5 i oh i ol v cc =5.0v roomtemp. 0.45 c346C9
cy7c346 cy7c346b 7 timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum ex- pander delay t exp to the overall delay. similarly, there is an additional t pia delay for an input from an i/o pin when com- pared to a signal from straight input pin. when calculating synchronous frequencies, use t s1 if all in- puts are on dedicated input pins. the parameter t s2 should be used if data is applied at an i/o pin. if t s2 is greater than t co1 , 1/t s2 becomes the limiting frequency in the data path mode unless 1/(t wh + t wl ) is less than 1/t s2 . when expander logic is used in the data path, add the appro- priate maximum ex pander delay, t exp to t s1 . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t s1 ) is the lowest fre- quency. the lowest of these frequencies is the maximum data path frequency for the synchronous configuration. when calculating external asynchronous frequencies, use t as1 if all inputs are on the dedicated input pins. if any data is applied to an i/o pin, t as2 must be used as the required set-up time. if (t as2 + t ah ) is greater than t aco1 , 1/(t as2 + t ah ) becomes the limiting frequency in the data path mode unless 1/(t awh + t awl ) is less than 1/(t as2 + t ah ). when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the asynchronous config- uration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchro- nous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the de- vices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. the parameter t aoh indicates the system compatibility of this device when driving subsequent registered logic with a pos- itive hold time and using the same asynchronous clock as the cy7c346/cy7c346b. in general, if t aoh is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchro- nous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage condi- tions, provided the clock signal source is the same. this also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. this is due to the expander logic in the second devices clock signal path adding an additional delay (t exp ) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following devices register.
cy7c346 cy7c346b 8 commercial and industrial external synchronous switching characteristics [6] over operating range 7c346bC15 7c346bC20 7c346C25 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. min. max. unit t pd1 dedicated input to combinatorial output delay [7] 15 20 25 30 35 ns t pd2 i/o input to combinatorial output delay [8] 25 32 40 45 55 ns t pd3 dedicated input to combinatorial output delay with expander delay [9] 23 30 37 44 55 ns t pd4 i/o input to combinatorial output delay with expander delay [4,10] 33 42 52 59 75 ns t ea input to output enable delay [4, 7] 15 20 25 30 35 ns t er input to output disable delay [4, 7] 15 20 25 30 35 ns t co1 synchronous clock input to output delay 7 8 14 16 20 ns t co2 synchronous clock to local feedback to combinatorial output [4,11] 17 20 30 35 42 ns t s1 dedicated input or feedback set-up time to synchronous clock input [7, 12] 10 13 15 20 25 ns t s2 i/o input set-up time to synchronous clock input [7] 20 24 30 36 45 ns t h input hold time from synchronous clock input [7] 0 0 0 0 0 ns t wh synchronous clock input high time 5 7 8 10 12.5 ns t wl synchronous clock input low time 5 7 8 10 12.5 ns t rw asynchro nous clear width [4, 7] 16 22 25 30 35 ns t rr asynchro nous clear recovery time [4,7] 16 22 25 30 35 ns t ro asynchro nous clear to regis- tered output delay [7] 15 20 25 30 35 ns t pw asynchronous preset width [4, 7] 15 20 25 30 35 ns t pr asynchronous preset recovery time [4,7] 15 20 25 30 35 ns t po asynchronous preset to regis- tered output delay [7] 15 20 25 30 35 ns t cf synchronous clock to local feedback input [4, 13] 3 3 3 3 6 ns t p external synchronous clock period (1/(f max3 )) [4] 12 15 16 20 25 ns f max1 external feed back maximum frequency (1/(t co1 + t s1 )) [4, 14] 58.8 47.6 34.5 27.7 22.2 mhz f max2 internal local feedback maximum frequency, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 15] 76.9 62.5 55.5 43.4 32.2 mhz shaded area contains preliminary information.
cy7c346 cy7c346b 9 f max3 data path maximum frequency, lesser of (1/(t wl + t wh )), (1/(t s1 + t h )) or (1/t co1 ) [4, 16] 100 71.4 62.5 50 40 mhz f max4 maximum register toggle frequency (1/(t wl + t wh )) [4, 17] 100 71.4 62.5 50 40 mhz t oh output data stable time from synchronous clock input [4, 18] 3 3 3 3 3 ns shaded area contains preliminary information. notes: 7. this specification is a measure of the delay from input signal applied to a dedicated input (68-pin plcc input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. this delay assumes no expander terms are used to form the logic function. when this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous c lear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) e mploys expander logic. if an input signal is applied to an i/o pin an additional delay equal to t pia should be added to the comparable delay for a dedicated input. if expanders are used, add the maximum expander delay t exp to the overall delay for the comparable delay without expanders. 8. this specification is a measure of the delay from input signal applied to an i/o macrocell pin to any output. this de lay assumes no expander terms are used to form the logic function. 9. this specification is a measure of the delay from an input signal applied to a dedicated input (68-pin plcc input pin 1, 2, 3 2, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. this delay assumes expander terms are used to form the logic function and includes the wors t-case exp ander logic delay for one pass through the expander logic. 10. this specification is a measure of the delay from an input signal applied to an i/o macrocell pin to any output. this delay assumes expander terms are used to form the logic function and includes the wors t-case expander logic delay for one pass through the expander logic. this parameter is tested periodically by sampling production material. 11. this specification is a measure of the delay from synchronous register clock to internal feedback of the register output sig nal to the input of the lab logic ar ray and then to a combinatorial output. this delay assumes no expanders are used, register is synchronously clocked and all feedbac k is within the same lab. this parameter is tested periodically by sampling production material. 12. if data is applied to an i/o input for capture by a macrocell register, the i/o pin input set-up time minimums should be observed. these parame ters are t s2 for synchronous operation and t as2 for asynchronous operation. 13. this specification is a measure of the d elay associated with the internal register feedback path. this is the delay from synchronous clock to lab logic ar ray input. this delay plus the regi ster set-up time, t s1 , is the minimum internal period for an internal synchronous state machine configuration. this delay is for feedback within the same lab. this parameter is tested periodically by sampling production material. 14. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration w ith external feedback can operate. it is assumed that all data inputs and external feedback signals are applied to dedicated inputs. 15. this specification indicates the guaranteed maximum frequency at which a state machine with internal-only feed back can operate. if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t co1 . all feedback is assumed to be local originating within the same lab. 16. this frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated i nput pin to output pin). this assumes data input signals are applied to dedicated input pins and no expander logic is used. if any of the data inputs are i/o pins, t s2 is the appropriate t s for calculation. 17. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock si gnal applied to the dedica ted clock input pin. 18. this parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. commercial and industrial external synchronous switching characteristics [6] over operating range 7c346bC15 7c346bC20 7c346C25 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. min. max. unit
cy7c346 cy7c346b 10 commercial and industrial external asynchronous sw itching characteristics [6] over operating range 7c346bC15 7c346bC20 7c346C25 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. min. max. unit t aco1 asynchronous clock input to output delay [7] 15 20 25 30 35 ns t aco2 asynchronous clock input to local fe edback to combinatorial output [19] 25 32 39 46 55 ns t as1 dedicated input or feedback set-up time to asynchronous clock input [7] 5 5 5 6 8 ns t as2 i/o input set-up time to asynchronous clock input [7] 14.5 17 19 22 28 ns t ah input hold time from asynchronous clock input [7] 5 6 6 8 10 ns t awh asynchronous clock input high time [7] 9 10 11 14 16 ns t awl asynchronous clock input low time [7, 20] 7 8 9 11 14 ns t acf asynchronous clock to local feedback input [4, 21] 11 13 15 18 22 ns t ap external as ynchron ous clock period (1/(f maxa4 )) [4] 16 18 20 25 30 ns f maxa1 external f eedback maximum frequency in as ynchronous mode (1/(t aco1 + t as1 )) [4, 22] 50 40 33.3 27.7 23.2 mhz f maxa2 maximum internal asynchronous frequency [4,23] 62.5 55.5 50 40 33.3 mhz f maxa3 data path maximum freq uency in asynchronous mode [4, 24] 66.6 50 40 33.3 28.5 mhz f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4, 25] 62.5 55.5 50 40 33.3 mhz t aoh output data stable time from asynchronous clock input [4,26] 12 12 15 15 15 ns shaded area contains preliminary information. notes: 19. this specification is a measure of the delay from an as ynchronous register clock input to internal feedback of the register output signal to the input of the lab logic array and then to a comb inatorial output. this delay assumes no expan ders are used in the logic of combinatorial output or the asynchronous clock inp ut. the clock signal is applied to the dedicated clock input pin and all feed back is within a single lab. this parameter is tested periodically by sampling production material. 20. this parameter is measured with a positive-edge triggered clock at the register. for n egative edge triggering, the t awh and t awl parameters must be swapped. if a given input is used to clock multiple registers with both positive and negative polarity, t awh should be used for both t awh and t awl . 21. this specification is a m easure of the delay associated with the internal register feedback path for an asynchronous clock to lab logic array in put. this delay plus the asynchronous register set-up time, t as1 , is the minimum internal period for an internal asynchronously clocked state machine configuration. this delay is for feedback within the same lab, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. this parameter is tested periodically by sampling production material. 22. this specification indicates the guaranteed maximum freq uency at which an async hronously clocked state machine configuration with external feedback can operate. it is assumed that all data inputs, clock inputs, and feedback si gnals are a pplied to dedicated i nputs and that no expander logic is e mployed in the clock si gnal path or data path. 23. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. this parameter is determined by the les ser of (1/(t acf + t as1 )) or (1/(t awh + t awl )). if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t aco1 . this specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single lab. this parameter is tested periodically by sampling production material. 24. this frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. this specifica tion is determined by the lesser of 1/(t awh + t awl ), 1/(t as1 + t ah ) or 1/t aco1 . it assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. this specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked m ode by a clock signal applied to an external dedicated input pin. 26. this parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin.
cy7c346 cy7c346b 11 commercial and industrial internal switching characteristics over operating range 7c346bC15 7c346bC20 7c346C25 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. min. max. unit t in dedicated input pad and buffer delay 3 4 5 7 9 ns t io i/o input pad and bu ffer de- lay 3 4 6 6 9 ns t exp expander array delay 8 10 12 14 20 ns t lad logic array data delay 8 10 12 14 16 ns t lac logic array control delay 5 7 10 12 13 ns t od output buffer and pad delay 3 3 5 5 6 ns t zx output buffer enable de- lay [27] 5 5 10 11 13 ns t xz output buffer disable delay 5 5 10 11 13 ns t rsu register set-up time relative to clock signal at register 4 5 6 8 10 ns t rh register hold time relative to clock signal at register 4 5 6 8 10 ns t latch flow through latch delay 1 2 3 4 4 ns t rd register delay 1 1 1 2 2 ns t comb transparent mode delay [28] 1 2 3 4 4 ns t ch clock high time 4 6 8 10 12.5 ns t cl clock low time 4 6 8 10 12.5 ns t ic asynchronous clock logic delay 6 8 14 16 18 ns t ics synchronous clock delay 0.5 0.5 1 1 1 ns t fd feedback delay 1 1 1 1 2 ns t pre asynchronous register preset time 3 3 5 6 7 ns t clr asynchronous register clear time 3 3 5 6 7 ns t pcw asynchronous pre set and clear pulse width 3 4 5 6 7 ns t pcr asynchronous pre set and clear recovery time 3 4 5 6 7 ns t pia programmable interconnect array delay time 10 12 14 16 20 ns shaded area contains preliminary information. notes: 27. sample tested only for an output change of 500 mv. 28. this specification guarantees the maximum combinatorial delay associ ated with the macrocell register bypass when the macrocell is configured for combi- natorial operation.
cy7c346 cy7c346b 12 military external synchronous switching characteristics [6] over operating range 7c346bC20 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. unit t pd1 dedicated input to combinatorial output delay [7] 20 25 30 35 ns t pd2 i/o input to combinatorial output delay [8] 32 39 45 55 ns t pd3 dedicated input to combinatorial output delay with expander delay [9] 30 37 44 55 ns t pd4 i/o input to combinatorial output delay with expander delay [4,10] 42 51 59 75 ns t ea input to output enable delay [4, 7] 20 25 30 35 ns t er input to output disable delay [4, 7] 20 25 30 35 ns t co1 synchronous clock input to output delay 8 14 16 20 ns t co2 synchronous clock to local feedback to combinatorial output [4,11] 20 30 35 42 ns t s1 dedicated input or feedback set-up time to synchronous clock input [7,12] 13 15 20 25 ns t s2 i/o input set-up time to synchronous clock input [7] 24 29 36 45 ns t h input hold time from synchronous clock input [7] 0 0 0 0 ns t wh synchronous clock input high time 7 8 10 12.5 ns t wl synchronous clock input low time 7 8 10 12.5 ns t rw asynchronous clear width [4,7] 20 25 30 35 ns t rr asynchronous clear recovery time [4,7] 20 25 30 35 ns t ro asynchronous clear to registered output delay [7] 20 25 30 35 ns t pw asynchronous pre set width [4,7] 20 25 30 35 ns t pr asynchronous pre set recovery time [4,7] 20 25 30 35 ns t po asynchronous pre set to registered output delay [7] 20 25 30 35 ns t cf synchronous clock to local feedback input [4,13] 3 3 3 6 ns t p external synchronous clock period (1/(f max3 )) [4] 14 16 20 25 ns f max1 external feedback maximum frequency (1/(t co1 + t s1 )) [4,14] 47.6 34.5 27.7 22.2 mhz shaded area contains preliminary information.
cy7c346 cy7c346b 13 military external synchronous switching characteristics [6] over operating range (continued) 7c346bC20 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. unit f max2 internal local f eedback maximum frequency, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 15] 62.5 55.5 43.4 32.2 mhz f max3 data path maximum frequency, lesser of (1/(t wl + t wh )), (1/(t s1 + t h )) or (1/t co1 ) [4, 16] 71.4 62.5 50 40 mhz f max4 maximum register toggle frequency (1/(t wl + t wh )) [4, 17] 71.4 62.5 50 40 mhz t oh output data stable time from synchronous clock input [4,18] 3 3 3 3 ns shaded area contains preliminary information. military external asynchronous switching characteristics [6] over operating range 7c346bC20 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. unit t aco1 asynchronous clock in put to output delay [7] 20 25 30 35 ns t aco2 asynchronous clock in put to local feedback to combinatorial output [19] 32 39 46 55 ns t as1 dedicated input or feedback set-up time to asy nchronous clock input [7] 6 5 6 8 ns t as2 i/o input set-up time to asynchronous clock input [7] 17 19 22 28 ns t ah input hold time from asynchronous clock input [7] 6 6 8 10 ns t awh asynchronous clock input high time [7] 10 11 14 16 ns t awl asynchronous clock input low time [7, 20] 8 9 11 14 ns t acf asynchronous clock to lo cal feedback input [4, 21] 13 15 18 22 ns t ap external asynchronous clock period (1/(f maxa4 )) [4] 18 20 25 30 ns f maxa1 external feedback maximum frequency in asynchronous mode (1/(t aco1 + t as1 )) [4,22] 40 33.3 27.7 23.2 mhz f maxa2 maximum internal asynchronous frequency [4, 23] 55.5 50 40 33.3 mhz f maxa3 data path maximum frequency in asynchronous mode [4,24] 50 40 33.3 28.5 mhz f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4,25] 55.5 50 40 33.3 mhz t aoh output data stable time from asynchronous clock input [4, 26] 12 15 15 15 ns shaded area contains preliminary information.
cy7c346 cy7c346b 14 military typical internal switching characteristics over operating range 7c346bC20 7c346bC25 7c346C30 7c346bC30 7c346C35 7c346bC35 parameter description min. max. min. max. min. max. min. max. unit t in dedicated input pad and buffer delay 4 5 7 9 ns t io i/o input pad and buffer delay 4 6 6 9 ns t exp expander array delay 10 12 14 20 ns t lad logic array data delay 10 12 14 16 ns t lac logic array control delay 7 10 12 13 ns t od output buffer and pad delay 3 5 5 6 ns t zx output buffer enable delay [27] 5 10 11 13 ns t xz output buffer disable delay 5 10 11 13 ns t rsu register set-up time relative to clock signal at register 5 6 8 10 ns t rh register hold time relative to clock signal at register 5 6 8 10 ns t latch flow through latch delay 2 3 4 4 ns t rd register delay 1 1 2 2 ns t comb transparent mode delay [28] 2 3 4 4 ns t ch clock high time 6 8 10 12.5 ns t cl clock low time 6 8 10 12.5 ns t ic asynchronous clock logic delay 8 14 16 18 ns t ics synchronous clock delay 0.5 2 2 3 ns t fd feedback delay 1 1 1 2 ns t pre asynchronous register preset time 3 5 6 7 ns t clr asynchronous register clear time 3 5 6 7 ns t pcw asynchronous pre set and clear pulse width 4 5 6 7 ns t pcr asynchronous pre set and clear recovery time 4 5 6 7 ns t pia programmable interconnect array delay time 12 14 16 20 ns shaded area contains preliminary information.
cy7c346 cy7c346b 15 switching waveforms external asynchronous t aco1 external combinatorial external synchronous t pd1 /t pd2 t er t ea valid output dedicated input/ i/o input combinatorial output combinatorial or registered output c346C10 high-impedance three-state high-impedance three-state t h t s1 t wh t wl t rr /t pr t rw /t pw t oh t co1 t ro /t po t co2 c346C11 dedicated inputs or registered feedback synchronous clock asynchronous clear/preset registered outputs combinatorial output from registered feedback t ah t as1 t awh t awl t rr /t pr t rw /t pw t aoh t ro /t po t aco2 asynchronous clock input asynchronous registered outputs dedicated inputs or registered feedback asynchronous clear/preset combinatorial output from asynchronous registered feedback c346C12 [7] [7] [7] [8] [7] [7] [7]
cy7c346 cy7c346b 16 switching waveforms (continued) internal combinatorial internal asynchronous internal synchronous t in t io t pia t exp t lac ,t lad c346C13 input pin expander i/o pin logic array t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd array delay output logic array input clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array c346C14 t r t ch t cl t in t ics t rsu t rh c346C15 system cl ock pin system cl ock at register data from logic array
cy7c346 cy7c346b 17 switching waveforms (continued) internal synchro nous c346C16 t xz t zx t od high impedance clock from logic array logic array data from output pin t rd state ordering information speed (ns) ordering code package name package type operating range 15 cy7c346bC15hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346bC15jc/ji j83 84-lead plastic leaded chip carrier cy7c346bC15nc/ni n100 100-lead plastic quad flatpack cy7c346bC15rc/ri r100 100-pin windowed ceramic pin grid array 20 cy7c346bC20hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346bC20jc/ji j83 84-lead plastic leaded chip carrier cy7c346bC20nc/ni n100 100-lead plastic quad flatpack cy7c346bC20rc/ri r100 100-pin windowed ceramic pin grid array cy7c346bC20hmb h84 84-pin windowed leaded chip carrier military cy7c346bC20rmb r100 100-pin windowed ceramic pin grid array 25 cy7c346C25hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346C25jc/ji j83 84-lead plastic leaded chip carrier cy7c346C25nc/ni n100 100-lead plastic quad flatpack cy7c346C25rc/ri r100 100-pin windowed ceramic pin grid array cy7c346bC25hc/hi h84 84-pin windowed leaded chip carrier cy7c346bC25jc/ji j83 84-lead plastic leaded chip carrier cy7c346bC25nc/ni n100 100-lead plastic quad flatpack cy7c346bC25rc/ri r100 100-pin windowed ceramic pin grid array cy7c346bC25hmb h84 84-pin windowed leaded chip carrier military cy7c346bC25rmb r100 100-pin windowed ceramic pin grid array 30 cy7c346C30hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346C30jc/ji j83 84-lead plastic leaded chip carrier cy7c346C30nc/ni n100 100-lead plastic quad flatpack cy7c346bC30hc/hi h84 84-pin windowed leaded chip carrier cy7c346bC30jc/ji j83 84-lead plastic leaded chip carrier cy7c346bC30nc/ni n100 100-lead plastic quad flatpack cy7c346bC30rc/ri r100 100-pin windowed ceramic pin grid array cy7c346C30hmb h84 84-pin windowed leaded chip carrier military cy7c346C30rmb r100 100-pin windowed ceramic pin grid array cy7c346bC30hmb h84 84-pin windowed leaded chip carrier cy7c346bC30rmb r100 100-pin windowed ceramic pin grid array shaded area contains preliminary information.
cy7c346 cy7c346b 18 military specifications group a subgroup testing document #: 38C00244Cd max is a registered trademark of altera corporation. warp2 and warp3 are registered trademarks of cypress semiconductor corporation. ordering information (continued) speed (ns) ordering code package name package type operating range 35 cy7c346C35jc/ji j83 84-lead plastic leaded chip carrier commercial/industrial cy7c346C35nc/ni n100 100-lead plastic quad flatpack cy7c346C35rc/ri r100 100-pin windowed ceramic pin grid array cy7c346bC35hc/hi h84 84-pin windowed leaded chip carrier cy7c346bC35jc/ji j83 84-lead plastic leaded chip carrier cy7c346bC35nc/ni n100 100-lead plastic quad flatpack cy7c346bC35rc/ri r100 100-pin windowed ceramic pin grid array cy7c346C35hmb h84 84-pin windowed leaded chip carrier military cy7c346C35rmb r100 100-pin windowed ceramic pin grid array cy7c346bC35hmb h84 84-pin windowed leaded chip carrier cy7c346bC35rmb r100 100-pin windowed ceramic pin grid array shaded area contains preliminary information. dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc1 1, 2, 3 switching characteristics parameter subgroups t pd1 7, 8, 9, 10, 11 t pd2 7, 8, 9, 10, 11 t pd3 7, 8, 9, 10, 11 t co1 7, 8, 9, 10, 11 t s1 7, 8, 9, 10, 11 t s2 7, 8, 9, 10, 11 t h 7, 8, 9, 10, 11 t wh 7, 8, 9, 10, 11 t wl 7, 8, 9, 10, 11 t ro 7, 8, 9, 10, 11 t po 7, 8, 9, 10, 11 t aco1 7, 8, 9, 10, 11 t aco2 7, 8, 9, 10, 11 t as1 7, 8, 9, 10, 11 t ah 7, 8, 9, 10, 11 t awh 7, 8, 9, 10, 11 t awl 7, 8, 9, 10, 11
cy7c346 cy7c346b 19 package diagrams 84-lead windowed leaded chip carrier h84
cy7c346 cy7c346b 20 package diagrams (continued) 84-lead plastic leaded chip car rier j83
cy7c346 cy7c346b 21 package diagrams (continued) 100-lead plastic quad flatpack n100
cy7c346 cy7c346b ? cypress s emiconduc tor corporation, 1997. the information contained herein is s ubject to change without notice. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. package diagrams (continued) 100-pin windowed ceramic pin g rid array r100

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