1 ps8527 03/01/01 product description pericom semiconductor?s pi74avc+ series of logic circuits are produced using the company?s advanced submicron cmos technology, achieving industry leading speed. the pi74alvch16374 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. this device can be used as two 8-bit flip-flops or one 16-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels set up at the data (d) inputs. oe can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in that state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect internal operations of the flip-flop. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2.5v 16-bit edge triggered d-type flip-flop with 3-state outputs logic block diagram product features ? pi74avc+16374 is designed for low voltage operation, v cc = 1.65v to 3.6v ? true 24ma balanced drive @ 3.3v ? compatible with philips and t.i. avc logic family ?i off supports partial power-down operation ? 3.6v i/o tolerant inputs and outputs ? all outputs contain a patented ddc (dynamic drivecontrol) circuit that reduces noise without degrading propagation delay. ? industrial operation at ?40c to +85c ? available packages: ? 48-pin 240-mil wide plastic tssop ? 48-pin 173-mil wide plastic tvsop pi74avc+16374 1clk 1q1 1d c1 1d1 to seven other channels 1oe 1 48 47 2 2clk 2q1 1d c1 2d1 to seven other channels 25 36 13 24 2oe
2 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc ............................................. ?0.5v to +4.6v input voltage range, v i ................................................... ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) ...................... ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) ......................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) .................................................... ?50ma output clamp current, i ok (v o <0) .............................................. ?50ma continuous output current, i o .................................................... 50ma continuous current through each v cc or gnd ......................... 100ma package thermal impedance, q ja (3) : package a ......................... 64c/w package k ......................... 48c/w storage temperature range, t stg .................................... ?65c to 150c 1. input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. output positive-voltage rating may be exceeded up to 4.6v maximum if the output current rating is observed. 3. the package thermal impedance is calculated in accor- dance with jesd 51. notes: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. s t u p n is t u p t u o e ok l cdq l - hh l - ll ll r o hxq 0 hxx z pin name description oe 3-state output enable inputs (active low) clk clock input (active high) dx data inputs qx 3-state outputs gnd ground v cc power product pin description truth table (1) product pin configuration notes: 1. h = high signal level l = low signal level x = don't care or irrelevant z = high impedance 1 2 3 4 5 6 7 8 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 32 31 30 29 28 27 26 25 1oe 1clk 1q1 1d1 1q2 1d2 gnd gnd 1q3 1d3 1q4 1d4 v 1q5 1d5 1q6 1d6 gnd gnd 1q7 1d7 1q8 1d8 2q1 2d1 2q2 2d2 gnd gnd 2q3 2d3 2q4 2d4 2q5 2d5 2q6 2d6 gnd gnd 2q7 2d7 2q8 2d8 2oe 2clk cc v cc v cc v cc 48-pin a,k
3 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs recommended operating conditions (1) . n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o4 . 16 . 3 v y l n o n o i t n e t e r a t a d2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i h v c c v 2 . 1 =v c c v c c v 6 . 1 o t v 4 . 1 =v x 5 6 . 0 c c v c c v 5 9 . 1 o t v 5 6 . 1 =v x 5 6 . 0 c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 =2 v l i e g a t l o v t u p n i l e v e l - w o l v c c v 2 . 1 =d n g v c c v 6 . 1 o t v 4 . 1 =v x 5 3 . 0 c c v c c v 5 9 . 1 o t v 5 6 . 1 =v x 5 3 . 0 c c v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u o e t a t s e v i t c a0v c c e t a t s - 306 . 3 i s h o t n e r r u c t u p t u o l e v e l - h g i h v c c v 6 . 1 o t v 4 . 1 =4 ? a m v c c v 5 9 . 1 o t v 5 6 . 1 =6 ? v c c v 7 . 2 o t v 3 . 2 =2 1 ? v c c v 6 . 3 o t v 3 =4 2 ? i s l o t n e r r u c t u p t u o l e v e l - w o l v c c v 6 . 1 o t v 4 . 1 =4 v c c v 5 9 . 1 o t v 5 6 . 1 =6 v c c v 7 . 2 o t v 3 . 2 =2 1 v c c v 6 . 3 o t v 3 =4 2 d t d e t a r l l a f r o e s i r n o i t i s n a r t t u p n i vv c c v 6 . 3 o t v 4 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o 0 4 ?5 8c notes: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation.
4 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs s r e t e m a r a ps n o i t i d n o c t s e t ) 1 ( v c c . n i m. p y t. x a ms t i n u v h o i h o 0 0 1 ? =a v 6 . 3 o t v 4 . 1v c c v 2 . 0 ? v i s h o 4 ? =m v a h i v 1 9 . 0 =v 4 . 15 0 . 1 i s h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i s h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i s h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i s l o 0 0 1 =a v 6 . 3 o t v 4 . 12 . 0 i s l o 4 =m v a l i v 9 4 . 0 =v 4 . 14 . 0 i s l o 6 =m v a l i v 7 5 . 0 =v 5 6 . 15 4 . 0 i s l o 2 1 =m v a l i v 7 . 0 =v 3 . 25 5 . 0 i s l o 4 2 =m v a l i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 a i f f o v i v r o o v 6 . 3 =0 0 1 i z o v o v = c c d n g r ov 6 . 30 1 i c c v i v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o c v i v = c c d n g r o v 5 . 25 . 3 f p v 3 . 35 . 3 s t u p n i a t a d v 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r o v 5 . 25 . 6 v 3 . 35 . 6 note: typical values are measured at t a = 25c. dc electrical characteristics (over the operating range, t a = -40c +85c)
5 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs switching characteristics over recommended operating free-air temperature range (unless otherwise noted, see figures 1 thru 4) operating characteristics, t a = 25 c s r e t e m a r a ps n o i t i d n o c t s e t v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t n o i t a p i s s i d r e w o p d p c e c n a t i c a p a c d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f g n i h c t i w s s t u p t u o 2 4 71 89 8 f p d e l b a s i d s t u p t u o2 57 53 6 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . p y t. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 6 10 0 20 0 2 s n t d p k l cq 3 . 75 . 14 . 82 . 17 . 68 . 01 . 47 . 03 . 3 t n e e oq 4 . 76 . 15 . 86 . 17 . 69 . 03 . 47 . 04 . 3 t s i d e oq 4 . 85 . 24 . 93 . 28 . 712 . 45 . 19 . 3 v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c0 6 10 0 20 0 2 s n t w w o l r o h g i h k l c , n o i t a r u d e s l u p1 . 35 . 25 . 2 t u s k l c e r o f e b a t a d , e m i t p u t e s - 1 . 47 . 29 . 14 . 14 . 1 t h r e t f a a t a d , e m i t d l o hk l c - 7 . 13 . 12 . 11 . 11 . 1 timing requirements over recommended operating free-air temperature range (unless otherwise noted, see figures 1 thru 4)
6 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
7 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k w 1 k w 0.15v 0.15v 30
8 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 30
9 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 0.3v 0.3v 30
10 ps8527 03/01/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16374 2.5v 16-bit edge triggered d-type flip flop with 3-state outputs pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com packaging mechanical - 48-pin tssop (a-package) packaging mechanical - 48-pin tvsop (tssop) (k-package) n o i t a m r o f n i g n i r e d r on o i t p i r c s e d a 4 7 3 6 1 + c v a 4 7 i pp o s s t c i t s a l p e d i w l i m - 0 4 2 , n i p - 8 4 k 4 7 3 6 1 + c v a 4 7 i pp o s v t c i t s a l p e d i w l i m - 3 7 1 , n i p - 8 4 .378 .386 .047 .031 .041 seating plane .0051 .009 .016 bsc 1 48 .169 .177 9.60 9.80 4.30 4.50 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 .252 bsc 6.4 max. 1.20 .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc
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