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16mb lw r-r, rev 1.0 1 / 22 june 24, 2002 CXK77P36R160GB / cxk77p18r160gb sony 3/33/4 16mb lw r-r hstl high speed synchronous srams (512k x 36 or 1m x 18) preliminary description the CXK77P36R160GB (organized as 524,288 words by 36 bits) and the cxk77p18r160gb (organized as 1,048,576 words by 18 bits) are high speed cmos synchronous static rams with common i/o pins. these synchronous srams integrate input registers, high speed ram, output registers, and a one-deep write buffer onto a single monolithic ic. register - register (r-r) read operations and late write (lw) write operations are supported, providing a high-performance user interface. all address and control input signals except g (output enable) and zz (sleep mode) are registered on the rising edge of the k differential input clock. during read operations, output data is driven valid from the rising edge of k, one full clock cycle after address is registered. during write operations, input data is registered on the rising edge of k, one full clock cycle after address is registered. sleep (power down) capability is provided via the zz input signal. output drivers are series terminated, and output impedance is programmable via the zq input pin. by connecting an external control resistor rq between zq and v ss , the impedance of all data output drivers can be precisely controlled. 333 mhz operation is obtained from a single 2.5v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol. features ? 3 speed bins cycle time / access time -3 3.0ns / 1.8ns -33 3.3ns / 1.9ns -4 4.0ns / 2.0ns ? single 2.5v power supply (v dd ): 2.5v 5% ? dedicated output supply voltage (v ddq ): 1.8v 0.1v ? hstl-compatible i/o interface with dedicated input reference voltage (v ref ): 0.9v typical ? register - register (r-r) read protocol ? late write (lw) write protocol ? full read/write coherency ? byte write capability ? differential input clocks (k/ k ) ? asynchronous output enable ( g ) ? sleep (power down) mode via dedicated mode pin (zz) ? programmable output driver impedance ? jtag boundary scan (subset of ieee standard 1149.1) ? 119 pin (7x17), 1.27mm pitch, 14mm x 22mm ball grid array (bga) package
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 2 / 22 june 24, 2002 512k x 36 pin assignment (top view) notes : 1. pad location 3r is defined as an m1 mode pin in lw srams. however, it must be tied ?low? in this device. 2. pad location 5r is defined as an m2 mode pin in lw srams. however, it must be tied ?high? in this device. 3. pad location 6u must be left unconnected. it is used by sony for internal test purposes. 1 2 3 4 5 6 7 a v ddq sa sa nc sa sa v ddq b nc sa sa nc (32m) sa sa nc c nc sa sa v dd sa sa nc d dqc dqc v ss zq v ss dqb dqb e dqc dqc v ss ss v ss dqb dqb f v ddq dqc v ss g v ss dqb v ddq g dqc dqc sbw c nc sbw b dqb dqb h dqc dqc v ss nc v ss dqb dqb j v ddq v dd v ref v dd v ref v dd v ddq k dqd dqd v ss k v ss dqa dqa l dqd dqd sbw d k sbw a dqa dqa m v ddq dqd v ss sw v ss dqa v ddq n dqd dqd v ss sa v ss dqa dqa p dqd dqd v ss sa v ss dqa dqa r nc sa m1 (1) v dd m2 (2) sa nc t nc nc (x18) sa sa (x36) sa nc (x18) zz u v ddq tms tdi tck tdo rsvd (3) v ddq
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 3 / 22 june 24, 2002 1m x 18 pin assignment (top view) notes : 1. pad location 3r is defined as an m1 mode pin in lw srams. however, it must be tied ?low? in this device. 2. pad location 5r is defined as an m2 mode pin in lw srams. however, it must be tied ?high? in this device. 3. pad location 6u must be left unconnected. it is used by sony for internal test purposes. 1 2 3 4 5 6 7 a v ddq sa sa nc sa sa v ddq b nc sa sa nc (32m) sa sa nc c nc sa sa v dd sa sa nc d dqb nc v ss zq v ss dqa nc e nc dqb v ss ss v ss nc dqa f v ddq nc v ss g v ss dqa v ddq g nc dqb sbw b nc v ss nc dqa h dqb nc v ss nc v ss dqa nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb v ss k v ss nc dqa l dqb nc v ss k sbw a dqa nc m v ddq dqb v ss sw v ss nc v ddq n dqb nc v ss sa v ss dqa nc p nc dqb v ss sa v ss nc dqa r nc sa m1 (1) v dd m2 (2) sa nc t nc sa (x18) sa nc (x36) sa sa (x18) zz u v ddq tms tdi tck tdo rsvd (3) v ddq
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 4 / 22 june 24, 2002 pin description symbol type description sa input synchronous address inputs - registered on the rising edge of k. dqa, dqb dqc, dqd i/o synchronous data inputs / outputs - registered on the rising edge of k during write operations. driven from the rising edge of k during read operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d k, k input differential input clocks ss input synchronous select input - registered on the rising edge of k. ss = 0 enables the device to accept read and write commands ss = 1 disables the device sw input synchronous global write enable input - registered on the rising edge of k. sw = 0 specifies a write operation when the device is enabled sw = 1 specifies a read operation when the device is enabled sbw a, sbw b, sbw c, sbw d input synchronous byte write enable inputs - registered on the rising edge of k. sbw a = 0 specifies write data byte a during a write operation sbw b = 0 specifies write data byte b during a write operation sbw c = 0 specifies write data byte c during a write operation sbw d = 0 specifies write data byte d during a write operation g input asynchronous output enable input - deasserted (high) disables the data output drivers. zz input asynchronous sleep mode input - asserted (high) forces the sram into low-power mode. m1, m2 input read operation protocol select - these mode pins must be tied ?low? and ?high? respectively to select register - register read operations. zq input output driver impedance control resistor input - this pin must be connected to v ss through an external resistor rq to program data output driver impedance. see the programmable output driver impedance section for further information. v dd 2.5v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ref input reference voltage - input buffer threshold voltage. v ss ground tck input jtag clock tms input jtag mode select - weakly pulled ?high? internally. tdi input jtag data in - weakly pulled ?high? internally. tdo output jtag data out rsvd reserved - this pin is used for sony test purposes only. it must be left unconnected. nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd , v ddq , or v ss .
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 5 / 22 june 24, 2002 ? clock truth table notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?. 2. ?***? indicates that the input requirement or output state is determined by the previous operation. 3. dqs are tri-stated in response to write and deselect commands, one cycle after the command is sampled. ? sleep (power down) mode sleep (power down) mode is provided through the asynchronous input signal zz. when zz is asserted (high), the output drivers are disabled and the sram begins to draw standby current. contents of the memory array are preserved. an enable time (t zze ) must be met before the sram is guaranteed to be in sleep mode, and a recovery time (t zzr ) must be met before the sram can resume normal operation. ? programmable impedance output drivers these devices have programmable impedance output drivers. the output impedance is controlled by an external resistor rq connected between the sram?s zq pin and v ss , and is equal to one-fifth the value of this resistor, nominally. see the dc electrical characteristics section for further information. output driver impedance power-up requirements output driver impedance will reach the programmed value within 8192 cycles after power-up. consequently, it is recom- mended that read operations not be initiated until after the initial 8192 cycles have elapsed. output driver impedance updates output impedance is updated during write and deselect operations when the output driver is disabled. ? power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq should never exceed v dd . if this power supply sequence cannot be met, a large bypass diode may be re- quired between v dd and v ddq . please contact sony memory application department for further information. k zz ss (t n ) sw (t n ) sbw x (t n ) g operation dq (t n ) dq (t n+1 ) x 1 x x x x sleep (power down) mode hi - z hi - z - 0 1 x x x deselect *** hi - z - 0 0 1 x 1 read hi - z hi - z - 0 0 1 x 0 read *** q(t n ) - 0 0 0 0 x write all bytes *** d(t n ) - 0 0 0 x x write bytes with sbw x = 0 *** d(t n ) - 0 0 0 1 x abort write *** hi - z
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 6 / 22 june 24, 2002 ? absolute maximum ratings note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ? bga package thermal characteristics ? i/o capacitance (t a = 25 o c, f = 1 mhz) note : these parameters are sampled and are not 100% tested. item symbol rating units supply voltage v dd -0.5 to +3.0 v output supply voltage v ddq -0.5 to +2.3 v input voltage (address, control, data, clock) v in -0.5 to v ddq + 0.5 (2.3v max.) v input voltage (m1, m2) v min -0.5 to v dd + 0.5 (3.0v max.) v input voltage (tck, tms, tdi) v tin -0.5 to v dd + 0.5 (3.0v max.) v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c item symbol rating units junction to case temperature q jc 1.0 c/w item symbol test conditions min max units input capacitance address c in v in = 0v --- 4.2 pf control c in v in = 0v --- 4.2 pf clock c kin v kin = 0v --- 3.5 pf output capacitance data c out v out = 0v --- 4.8 pf
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 7 / 22 june 24, 2002 ? dc recommended operating conditions (v ss = 0v, t a = 0 to 85 o c) 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component. 2. v ih (max) ac = v ddq + 0.9v for pulse widths less than one-quarter of the cycle time (t cyc /4). 3. v il (min) ac = -0.9v for pulse widths less than one-quarter of the cycle time (t cyc /4). item symbol min typ max units notes supply voltage v dd 2.37 2.5 2.63 v output supply voltage v ddq 1.7 1.8 1.9 v input reference voltage v ref 0.8 0.9 1.0 v 1 input high voltage (address, control, data) v ih v ref + 0.1 --- v ddq + 0.3 v 2 input low voltage (address, control, data) v il -0.3 --- v ref - 0.1 v 3 input high voltage (m1, m2) v mih 1.3 --- v dd + 0.3 v input low voltage (m1, m2) v mil -0.3 --- 0.4 v clock input signal voltage v kin -0.3 --- v ddq + 0.3 v clock input differential voltage v dif 0.2 --- v ddq + 0.6 v clock input common mode voltage v cm 0.8 0.9 1.0 v
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 8 / 22 june 24, 2002 ? dc electrical characteristics (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 o c) 1. for maximum output drive (i.e. minimum impedance), the zq pin can be tied directly to v ss . 2. for minimum output drive (i.e. maximum impedance), the zq pin can be left unconnected or tied to v ddq . item symbol test conditions min typ max units notes input leakage current (address, control, clock) i li v in = v ss to v ddq -5 --- 5 ua input leakage current (m1, m2) i mli v min = v ss to v dd -10 --- 10 ua output leakage current i lo v out = v ss to v ddq g = v ih -10 --- 10 ua average power supply operating current i dd-3 i dd-33 i dd-4 i out = 0 ma ss = v il , zz = v il --- --- --- --- --- --- 780 730 650 ma power supply standby current i sb i out = 0 ma zz = v ih --- --- 250 ma output high voltage v oh i oh = -6.0 ma rq = 250 w v ddq - 0.4 --- --- v output low voltage v ol i ol = 6.0 ma rq = 250 w --- --- 0.4 v output driver impedance r out v oh , v ol = v ddq /2 rq < 150 w --- --- 35 (30*1.15) w 1 v oh , v ol = v ddq /2 150 w rq 300 w (rq/5)* 0.85 rq/5 (rq/5)* 1.15 w v oh , v ol = v ddq /2 rq > 300 w 51 (60*0.85) --- --- w 2
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 9 / 22 june 24, 2002 ? ac electrical characteristics (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 o c) 1. these parameters are sampled and are not 100% tested. 2. these parameters are measured at 50mv from steady state voltage. parameter symbol -3 -33 -4 units notes min max min max min max k cycle time t khkh 3.0 --- 3.3 --- 4.0 --- ns k clock high pulse width t khkl 1.2 --- 1.3 --- 1.5 --- ns k clock low pulse width t klkh 1.2 --- 1.3 --- 1.5 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 0.5 --- 0.5 --- 0.5 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 0.5 --- 0.5 --- 0.5 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 0.5 --- 0.5 --- 0.5 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 0.5 --- 0.5 --- 0.5 --- ns k clock high to output valid t khqv --- 1.8 --- 1.9 --- 2.0 ns k clock high to output hold t khqx 0.7 --- 0.7 --- 0.7 --- ns 1 k clock high to output low-z t khqx1 0.7 --- 0.7 --- 0.7 --- ns 1,2 k clock high to output high-z t khqz 0.7 1.8 0.7 1.9 0.7 2.0 ns 1,2 output enable low to output valid t glqv --- 1.8 --- 1.9 --- 2.0 ns output enable low to output low-z t glqx 0.3 --- 0.3 --- 0.3 --- ns 1,2 output enable high to output high-z t ghqz --- 1.8 --- 1.9 --- 2.0 ns 1,2 sleep mode enable time t zze --- 15 --- 15 --- 15 ns 1 sleep mode recovery time t zzr 20 --- 20 --- 20 --- ns 1
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 10 / 22 june 24, 2002 ? ac test conditions (v dd = 2.5v 5%, v ddq = 1.8v 0.1v, t a = 0 to 85 c ) item symbol conditions units notes input reference voltage v ref 0.9 v input high level v ih 1.4 v input low level v il 0.4 v input rise & fall time 2.0 v/ns input reference level 0.9 v clock input high voltage v kih 1.4 v v dif = 1.0v clock input low voltage v kil 0.4 v v dif = 1.0v clock input common mode voltage v cm 0.9 v clock input rise & fall time 2.0 v/ns clock input reference level k/ k cross v output reference level 0.9 v output load conditions rq = 250 w see figure 1 below dq 0.9 v figure 1: ac test output load (v ddq = 1.8v) 50 w 50 w 5 pf 16.7 w 0.9 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 11 / 22 june 24, 2002 read-write-read timing diagram synchronously controlled via ss and deselect operations ( g = low) note : in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the applica- tion, one deselect operation may be sufficient. a4 a6 a7 sa sw g = v il dq q1 d5 d6 q2 q3 d4 t khdx t dvkh a1 q7 read read read deselect deselect write write write read read read figure 2 k k a2 a5 ss t khqx t khqz t khqx1 t khqv t khwx t wvkh sbw x t khax t avkh t khwx t wvkh t khsx t svkh a3 a8 a9 t khkh t klkh t khkl
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 12 / 22 june 24, 2002 read-write-read timing diagram asynchronously controlled via g and dummy read operations ( ss = low) note : in the diagram above, two dummy read operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one dummy read operation may be sufficient. a4 a6 a7 sa sw g dq q1 d5 d6 q2 q3 d4 a1 q7 read read read read read write write write read read read figure 3 k k a2 a5 ss = v il t khqx t khqz t khqx1 t khqv sbw x a3 t glqx t glqv t ghqz dummy dummy a8 a9 t khdx t dvkh t khwx t wvkh t khax t avkh t khwx t wvkh t khkh t klkh t khkl
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 13 / 22 june 24, 2002 sleep (power-down) mode timing diagram notes : 1: this can be any operation. the depiction of a read operation here is provided only as an example. 2: before zz is asserted, at least two (2) deselect operations must be initiated after the last read or write operation is ini- tiated, in order to ensure the successful completion of the last read or write operation. 3: while zz is asserted, all of the sram?s address, control, data, and clock inputs are ignored. 4: after zz is deasserted, deselect operations must be initiated until the specified recovery time (t zzr ) has been met. read and write operations may not be initiated during this time. 5: this can be any operation. the depiction of a read operation here is provided only as an example. k k sa zz dq a1 figure 4 a4 t zzr t zze begin i sb ss q1 a2 a3 q2 sw sbw x deselect read read read read deselect (note 1) (note 2) (note 5) deselect (note 4) (note 3) g = v il
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 14 / 22 june 24, 2002 ? test mode description these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, con- troller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied ?low? to prevent clocking the sram. tms and tdi should either be tied ?high? through a pull-up resistor or left unconnected. tdo should be left unconnected. note : operation of the tap does not interfere with normal sram operation except when the sample-z instruction is se- lected. consequently, tck, tms, and tdi can be controlled any number of ways without adversely affecting the function- ality of the device. jtag dc recommended operating conditions (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 c ) jtag ac test conditions (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 c ) parameter symbol test conditions min max units jtag input high voltage v tih --- 1.4 v dd + 0.3 v jtag input low voltage v til --- -0.3 0.8 v jtag output high voltage (cmos) v toh i toh = -100ua v dd - 0.1 --- v jtag output low voltage (cmos) v tol i tol = 100ua --- 0.1 v jtag output high voltage (ttl) v toh i toh = -8.0ma v dd - 0.4 --- v jtag output low voltage (ttl) v tol i tol = 8.0ma --- 0.4 v jtag input leakage current i tli v tin = v ss to v dd -10 10 ua parameter symbol conditions units notes jtag input high level v tih 2.5 v jtag input low level v til 0.0 v jtag input rise & fall time 1.0 v/ns jtag input reference level 1.25 v jtag output reference level 1.25 v jtag output load condition see fig.1 (page 10)
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 15 / 22 june 24, 2002 jtag ac electrical characteristics jtag timing diagram parameter symbol min max unit tck cycle time t thth 100 ns tck high pulse width t thtl 40 ns tck low pulse width t tlth 40 ns tms setup time t mvth 10 ns tms hold time t thmx 10 ns tdi setup time t dvth 10 ns tdi hold time t thdx 10 ns tck low to tdo valid t tlqv 20 ns tck low to tdo hold t tlqx 0 ns figure 5 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 16 / 22 june 24, 2002 tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the operations associated with each tap instruction. state transitions are controlled by tms and occur on the rising edge of tck . the tap controller enters the ?test-logic reset? state in one of two ways: 1. at power up. 2. when a logic ?1? is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. the tdo output driver is active only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. tap controller state diagram figure 6 test-logic reset run-test / idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 17 / 22 june 24, 2002 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) from the falling edge of tck. they are divided into two groups: ?instruction registers? (ir), which are manipulated via the ?ir? states in the tap controller, and ?data registers? (dr), which are manipulated via the ?dr? states in the tap controller. instruction register (ir - 3 bits) the instruction register stores the various tap instructions supported by these devices. it is loaded with the idcode in- struction at power-up, and when the tap controller is in the ?test-logic reset? and ?capture-ir? states. it is inserted be- tween tdi and tdo when the tap controller is in the ?shift-ir? state, at which time it can be loaded with a new instruction. however, newly loaded instructions are not executed until the tap controller has reached the ?update-ir? state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. code (2:0) instruction description 000 bypass see code ?111?. 001 idcode loads a predefined device- and manufacturer-specific identification code into the id register when the tap controller is in the ?capture-dr? state, and inserts the id register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the id register description for more information. 010 sample-z loads the individual logic states of all signals composing the sram?s i/o ring into the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the boundary scan register between tdi and tdo when the tap controller is in the ?shift- dr? state. also disables the sram?s data output drivers. see the boundary scan register description for more information. 011 private do not use. reserved for manufacturer use only. 100 sample loads the individual logic states of all signals composing the sram?s i/o ring into the boundary scan register when the tap controller is in the ?capture-dr? state, and inserts the boundary scan register between tdi and tdo when the tap controller is in the ?shift- dr? state. see the boundary scan register description for more information. 101 private do not use. reserved for manufacturer use only. 110 private do not use. reserved for manufacturer use only. 111 bypass loads a logic ?0? into the bypass register when the tap controller is in the ?capture-dr? state, and inserts the bypass register between tdi and tdo when the tap controller is in the ?shift-dr? state. see the bypass register description for more information.
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 18 / 22 june 24, 2002 bypass register (dr - 1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic ?0? when the bypass instruction has been loaded in the instruction register and the tap controller is in the ?cap- ture-dr? state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction reg- ister and the tap controller is in the ?shift-dr? state. id register (dr - 32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the id register is 32 bits wide, and contains the following information: bit 0 is the lsb and bit 31 is the msb. when the id register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. boundary scan registers (dr - 70 bits for x36, 51 bits for x18) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for functional and/or density upgrades. it is loaded with the individual logic states of all signals composing the sram?s i/o ring when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?shift- dr? state. the boundary scan register contains the following bits: note : for deterministic results, all signals composing the sram?s i/o ring must meet setup and hold times with respect to tck (same as tdi and tms) when sampled. note : k and k are connected to a differential input receiver that generates a single-ended input clock signal to the device. therefore, in order to capture deterministic values for these signals in the boundary scan register, they must be at opposite logic levels when sampled. note : when an external resistor rq is connected between the zq pin and v ss , the value of the zq signal captured in the boundary scan register is non-deterministic. device revision number (31:28) part number (27:12) sony id (11:1) start bit (0) 512kb x 36 xxxx 0000 0000 0100 1010 0000 1110 001 1 1mb x 18 xxxx 0000 0000 0100 1011 0000 1110 001 1 512kb x 36 1mb x 18 dq 36 dq 18 sa 19 sa 20 k, k 2 k, k 2 ss , sw , sbw x 6 ss , sw , sbw x 4 g , zz 2 g , zz 2 zq, m1, m2 3 zq, m1, m2 3 place holder 2 place holder 2
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 19 / 22 june 24, 2002 boundary scan register bit order assignments the table below depicts the order in which the bits are arranged in the boundary scan register. bit 1 is the lsb and bit 70 (for x36) or bit 51 (for x18) is the msb. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. note 1 : nc pins at pad locations 4g and 4h are connected to v ss internally, regardless of pin connection externally. 512kb x 36 1mb x 18 bit signal pad bit signal pad bit signal pad bit signal pad 1 m2 5r 36 sa 3b 1 m2 5r 36 sbw b 3g 2 sa 4p 37 sa 2b 2 sa 6t 37 zq 4d 3 sa 4t 38 sa 3a 3 sa 4p 38 ss 4e 4 sa 6r 39 sa 3c 4 sa 6r 39 nc (1) 4g 5 sa 5t 40 sa 2c 5 sa 5t 40 nc (1) 4h 6 zz 7t 41 sa 2a 6 zz 7t 41 sw 4m 7 dqa 6p 42 dqc 2d 7 dqa 7p 42 dqb 2k 8 dqa 7p 43 dqc 1d 8 dqa 6n 43 dqb 1l 9 dqa 6n 44 dqc 2e 9 dqa 6l 44 dqb 2m 10 dqa 7n 45 dqc 1e 10 dqa 7k 45 dqb 1n 11 dqa 6m 46 dqc 2f 11 sbw a 5l 46 dqb 2p 12 dqa 6l 47 dqc 2g 12 k 4l 47 sa 3t 13 dqa 7l 48 dqc 1g 13 k 4k 48 sa 2r 14 dqa 6k 49 dqc 2h 14 g 4f 49 sa 4n 15 dqa 7k 50 dqc 1h 15 dqa 6h 50 sa 2t 16 sbw a 5l 51 sbw c 3g 16 dqa 7g 51 m1 3r 17 k 4l 52 zq 4d 17 dqa 6f 18 k 4k 53 ss 4e 18 dqa 7e 19 g 4f 54 nc (1) 4g 19 dqa 6d 20 sbw b 5g 55 nc (1) 4h 20 sa 6a 21 dqb 7h 56 sw 4m 21 sa 6c 22 dqb 6h 57 sbw d 3l 22 sa 5c 22 dqb 7g 58 dqd 1k 22 sa 5a 24 dqb 6g 59 dqd 2k 24 sa 6b 25 dqb 6f 60 dqd 1l 25 sa 5b 26 dqb 7e 61 dqd 2l 26 sa 3b 27 dqb 6e 62 dqd 2m 27 sa 2b 28 dqb 7d 63 dqd 1n 28 sa 3a 29 dqb 6d 64 dqd 2n 29 sa 3c 30 sa 6a 65 dqd 1p 30 sa 2c 31 sa 6c 66 dqd 2p 31 sa 2a 32 sa 5c 67 sa 3t 32 dqb 1d 33 sa 5a 68 sa 2r 33 dqb 2e 34 sa 6b 69 sa 4n 34 dqb 2g 35 sa 5b 70 m1 3r 35 dqb 1h
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 20 / 22 june 24, 2002 ? ordering information part number v dd i/o type size speed (cycle time / access time) CXK77P36R160GB-3 2.5v hstl 512k x 36 3.0ns / 1.8ns CXK77P36R160GB-33 2.5v hstl 512k x 36 3.3ns / 1.9ns CXK77P36R160GB-4 2.5v hstl 512k x 36 4.0ns / 2.0ns cxk77p18r160gb-3 2.5v hstl 1m x 18 3.0ns / 1.8ns cxk77p18r160gb-33 2.5v hstl 1m x 18 3.3ns / 1.9ns cxk77p18r160gb-4 2.5v hstl 1m x 18 4.0ns / 2.0ns sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illus - trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuit s.
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 21 / 22 june 24, 2002 13.0 a x4 b 2.5 max 0.6 0.1 s 7.62 1.27 119 - f 0.75 0.15 s ab (7x17) 119 pin bga package dimensions s 14.0 s a 0.15 1 2 3 4 5 6 7 a b c d e f g h j k l m n p r t u f 0.15 m 0.15 0.20 p r e l i m i n a r y p r e l i m i n a r y 4 - c 0 . 7 4 - c 1 . 0 1 9 . 0 2 2 . 0 0 . 1 5 s b 0 . 3 5 s 2 0 . 3 2 sony code eiaj code jedec code package material borad treatment lead material package mass solder package structure bga-119p-021 bga119-p-1422 epoxy resin copper-clad laminate 1.3g
sony ? CXK77P36R160GB / cxk77p18r160gb preliminary 16mb lw r-r, rev 1.0 22 / 22 june 24, 2002 ? revision history rev. # rev. date description of modification rev 1.0 06/24/02 initial version

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