corecontrol tm data she et tda21102 rev. 2.0 page 1 aug 31, 2004 number name description 1 pwm1 input for the pwm1 controller signal 2 pwm2 input for the pwm2 controller signal 3 gnd ground 4 gate ls1 gate drive output for the n-channel low side mosfet 1. 5 pvcc input to adjust the high side gate drive 6 pgnd power ground return for the low side drivers 7 gate ls2 gate drive output for the n-channel low side mosfet 2. 8 phase2 to be connected to the junction of the high side and the low side mosfet 2 9 gate hs2 gate drive output for the n-channel high side mosfet 2. 10 boot2 floating bootstrap pin. to be connected to the external bootstrap capacitor to generate the gate drive voltage for the high side n-channel mosfet 2. 11 boot1 floating bootstrap pin. to be connected to the external bootstrap capacitor to generate the gate drive voltage for the high side n-channel mosfet 1. 12 gate hs1 gate drive output for the n-channel high side mosfet 1. 13 phase1 to be connected to the junction of the high side and the low side mosfet 1 14 vcc supply voltage ? fast rise and fall times fo r frequencies up to 2 mhz ? capable of sinking more th an 4 a peak current for lowest switching losses ? charges the high side and low side mosfet s gate to 5..12 v according to pvcc setting. ? adjustable high side and low side mosfet gate drive voltage via pvcc pin for optimizing on losses an d gate drive losses ? integrates the bootstrap diode for reducing the part count ? prevents from cross-conducting by adaptive gate drive control ? high voltage rating on phase node ? supports shut-down mode for very low qu iescent current through three-state input ? compatible to standard pwm controller ics (intersil, analog devices) ? floating high side mosfet drive ? ideal for multi-phase desk top cpu supplies on m otherboards and vrms type package marking ordering code tda21102 p-dso-14-3 21102 q67042-s4244 p-dso-14-3 high speed driver with bootstrapping for dual power mosfets features pinout & descri p tion pwm1 vcc pwm2 phase1 gnd gatgate hs1 gate ls1 boot1 pvcc boot2 pgnd gate hs2 gate ls2 phase2 top view
corecontrol tm data she et tda21102 rev. 2.0 page 2 aug 31, 2004 general description the dual high speed driver is designed to drive a wide range of n-channel lo w side and n-channel high side mosfets with varying gate charges. it has a sm all propagation delay from input to output, short rise and fall times and the same pin configuration as the hip6602b. in addition it provides several protection features as well as a shut down mode for efficiency reasons. the high breakdown voltage makes it suitable for mobile applications. target application the dual high speed driver is designed to work well in half-bridge type circuits where dual n-channel mosfets are utilized. a circuit designer can fully take advantage of the drivers capabilities in high- efficiency, high-density synchronous dc/dc converters that operate at high switching frequencies, e.g. in multi-phase converters for cpu supplies on motherboards and vrms but also in motor drive and class-d amplifier type applications. block diagram shoot through protection gnd pvcc phase boot gate ls gate hs ls driver hs driver shoot through protection gnd pvcc phase boot gate ls gate hs ls driver hs driver control logic control logic bias pwm pwm vcc
corecontrol tm data she et tda21102 rev. 2.0 page 3 aug 31, 2004 absolute maximum ratings at tj = 25 c, unless otherwise specified value parameter symbol min. max. unit voltage supplied to ?vcc? pin v vcc -0.3 25 voltage supplied to ?pvcc? pin v pvcc -0.3 25 voltage supplied to ?pwm? pin v pwm -0.3 5.5 voltage supplied to ?boot? pin referenced to ?phase? v boot ? v phase -0.3 25 voltage rating at ?phase? pin, dc v phase -1 25 voltage rating at ?phase? pin, t pulse_max =500ns max duty cycle = 2% -20 30 voltage supplied to gate hs pin referenced to ?phase? t pulse_max < 100ns, e < 2uj v gatehs -3.5 v boot +0.3 voltage supplied to gate ls pin referenced to ?gnd? t pulse_max < 100ns, e < 2uj v gatels -5 v vcc +0.3 v junction temperature t j -25 150 storage temperature t s -55 150 c esd rating; human body model 4 kv iec climatic category; din en 60068-1 55/150/56 - thermal characteristic values unit parameter symbol min. typ. max. thermal resistance, junction-solder joint ( pin 4 ) rth-js 40.5 thermal resistance, junction-case rth-jc 44.7 thermal resistance, junction-ambient rth-ja 116.2 k/w
corecontrol tm data she et tda21102 rev. 2.0 page 4 aug 31, 2004 electrical characteristic at tj = 25 c, unless otherwise specified values parameter symbol conditions min. typ. max. unit supply characteristic bias supply current i vcc f = 1 mhz, no load v pvcc = v vcc = 12 v 1.3 1.8 quiescent current i vccq 1.8 v v pwm 3.0 v 3.8 4.9 power supply current i pvcc f = 1 mhz, no load v pvcc = v vcc = 12 v 25 33 ma under-voltage lockout v vcc rising threshold 9.7 10.1 10.5 v under-voltage lockout v vcc falling threshol d 7.3 7.6 8.0 v input characteristic current in ?pwm? pin i pwm_l v _pwm = 0.4 v -80 115 -150 current in ?pwm? pin i pwm_h v _pwm = 4.5 v 120 180 250 a shut down window v in_shut t_ shut > 350 ns 1.7 3.1 v shut down hold-off time t_ shut 1.7 v v pwm 3.1 v 100 200 320 ns pwm pin open v pwm_o 1.8 2.0 2.2 pwm low level threshold (falling) v pwm_l 1.4 pwm high level threshold (rising) v pwm_h 3.7 v pulse width high side t _p = pulse with on pwm pin 40 ns at tj = 25 c , unless otherwise specified dynamic characteristic turn-on propagation delay high side* t d(on)_hs 18 35 turn-off propagation delay high side t d(off)_hs 18 25 rise time high side t r_hs 14 28 fall time high side t f_hs 14 22 turn-on propagation delay low side t d(on)_ls 17 23 turn-off propagation delay low side t d(off)_ls 14 20 rise time low side t r_ls 22 29 fall time low side t f_ls p pvcc = v vcc = 12 v c iss = 3000 pf 14 22 ns
corecontrol tm data she et tda21102 rev. 2.0 page 5 aug 31, 2004 at tj = 125 c , unless otherwise specified dynamic characteristic turn-on propagation delay high side* t d(on)_hs 22 turn-off propagation delay high side t d(off)_hs 22 rise time high side t r_hs 16 fall time high side t f_hs 16 turn-on propagation delay low side t d(on)_ls 20 turn-off propagation delay low side t d(off)_ls 18 rise time low side t r_ls 23 fall time low side t f_ls p pvcc = v vcc = 12 v c iss = 3000 pf 16 ns measurement timing diagram pwm @ 50% pwm @ 50% phase @ 2v gate ls @ 2v gate ls @ 90% gate ls @ 10% gate hs @ 90% t d(on)_hs t d(off)_ls t f_ls t r_hs t d(off)_hs gate hs @ 10% t f_hs t d(on)_ls t r_ls pwm @ 50% pwm @ 50% phase @ 2v gate ls @ 2v gate ls @ 90% gate ls @ 10% gate hs @ 90% t d(on)_hs t d(off)_ls t f_ls t r_hs t d(off)_hs gate hs @ 10% t f_hs t d(on)_ls t r_ls gate h s gate l s phase
corecontrol tm data she et tda21102 rev. 2.0 page 6 aug 31, 2004 operating conditions at tj = 25 c, unless otherwise specified values parameter symbol conditions min. typ. max. unit voltage supplied to ?vcc? pin v vcc 10.8 13.2 v voltage supplied to ?pvcc? pin v pvcc 5 13.2 v input signal transition frequency f 0.1 2 mhz power dissipation p tot t a = 25 c, t j = 125 c 0.9 w junction temperature t j -25 150 c at tj = 25 c, unless otherwise specified values parameter conditions min. typ. max. unit output characteristic high side (hs) a nd low side (ls), ensured by design output resistance hs; source p pvcc = v vcc = 12 v i _hs_src = 2 a 1 (1) ? hs; sink v vcc = 12 v , p pvcc = 5v 1 1.3 ? hs; sink p pvcc = v vcc = 12 v 0.9 1.2 ? ls; source p pvcc = v vcc = 12 v i _hs_src = 2 a 1.4 (2) ? ls; sink v vcc = 12 v , p pvcc = 5v 1 1.3 ? ls; sink p pvcc = v vcc = 12 v 1 1.25 ? hs; source 4 hs; sink 4 ls; source 4 peak output- current ls; sink p pvcc = v vcc = 12 v t_ p_hs / pulse < 20 ns t_ p_ls / pulse < 40 ns d _hs < 2%, d _ls < 4% 4 a 1 incremental resistance v boot -v hs = 4.3v @ i source =2a 2 incremental resistance v vcc ?v ls = 4.4v @ i source =2a
corecontrol tm data she et tda21102 rev. 2.0 page 7 aug 31, 2004 package drawing p-dso-14-3 layout footprints e a l b 1,27 mm 5,69 mm 1,31 mm 0,65 mm
corecontrol tm data she et tda21102 rev. 2.0 page 8 aug 31, 2004 published by infineon technologies ag, bereichs kommunikation st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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