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features applications tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 low-power, highly-integrated, programmable 16-bit, 26-ksps mono codec ? analog and digital sidetone mono 16-bit oversampling sigma-delta a/d ? antialiasing filter (aaf) converter ? programmable input and output gain mono 16-bit oversampling sigma-delta d/a control (pga) converter ? microphone/handset/headset amplifiers support maximum master clock of 100 mhz to ? aic12k has an 8- w speaker driver allow the dsp output clock to be used as a ? power management with master clock hardware/software power-down modes selectable fir/iir filter with bypassing 30 w option separate software control for adc and dac programmable sampling rate up to: power down ? max 26 ksps with on-chip iir/fir filter fully compatible with common tms320? ? max 104 ksps with iir/fir bypassed dsp family and microcontroller power supplies on-chip fir produced 84-db snr for adc and 92-db snr for dac ? 1.65 v - 1.95 v digital core power smart time division multiplexed ? 1.1 v - 3.6 v digital i/o ( smartdm?) serial port ? 2.7 v - 3.6 v analog ? glueless 4-wire interface to dsp power dissipation (p d ) ? automatic cascade detection (acd) ? 11.2 mw at 3.3 v in standard operation self-generates master/slave device ? 17.8 mw at 3.3 v with headphone drivers addresses internal reference voltage (v ref ) ? programming mode to allow on-the-fly 2s complement data format reconfiguration test modes which include digital loopback ? continuous data transfer mode to and analog loopback minimize bit clock speed ? support different sampling rate for each device digital still cameras ? turbo mode to maximize bit clock for wireless accessories faster data transfer and allow multiple hands-free car kits serial devices to share the same bus voip ? allows up to 16 devices to be connected cable modem to a single serial port host port ? 2-wire interface ? selectable i 2 c or s 2 c differential and single-ended analog input/output built-in analog functions: please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. smartdm, tms320c5000, tms320c6000 are trademarks of texas instruments. tms320 is a trademark of texas instrument. production data information is current as of publication date. copyright ? 2001?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com
description tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. the tlv320aic1x is a true low-cost, low-power, high-integrated, high-performance, mono voice codec. it features one 16-bit analog-to-digital (a/d) channel and one 16-bit digital-to-analog (d/a) channel. the tlv320aic1x provides high-resolution signal conversion from digital-to-analog (d/a) and from analog-to-digital (a/d) using oversampling sigma-delta technology with programmable sampling rate. the tlv320aic1x implements the smart time division multiplexed serial port (smartdm?). the smartdm port is a synchronous 4-wire serial port in tdm format for glue-free interface to ti dsps (i.e. tms320c5000?, tms320c6000?) and microcontrollers. the smartdm supports both continuous data transfer mode and on-the-fly reconfiguration programming mode. the tlv320aic1x can be gluelessly cascaded to any smartdm-based device to form multichannel codec and up to 16 tlv320aic1x codecs can be cascaded to a single serial port. the tlv320aic1x also provides a flexible host port. the host port interface is a two-wire serial interface that can be programmed to be either an industrial standard i 2 c or a simple s 2 c (start-stop communication protocol). the tlv320aic1x also integrates all of the critical functions needed for most voice-band applications including mic preamplifier, handset amplifier, headset amplifier, antialiasing filter (aaf), input/output programmable gain amplifier (pga), and selectable low-pass iir/fir filters. the aic12k also includes an 8- w speaker driver. the tlv320aic1x implements an extensive power management; including device power-down, independent software control for turning off adc, dac, operational-amplifiers, and iir/fir filter (bypass) to maximize system power conservation. the tlv320aic1x consumes only 11.2 mw at 3.3 v. the tlv320aic1x low power operation from 2.7 v to 3.6 v power supplies, along with extensive power management, make it ideal for portable applications including wireless accessories, hands free car kits, voip, cable modem, and speech processing. its low group delay characteristic makes it suitable for single or multichannel active control applications. the tlv320aic1x is characterized for commercial operation from 0 c to 70 c and industrial operation from -40 c to 85 c. the tlv320aic1xk is characterized for industrial operation from -40 c to 85 c. ordering information operating package ordering transport media, product package (1) temperature designator number quantity range, t a tlv320aic1xcdbt tape and reel, 250 tlv320aic1xc tssop-30 dbt 0 c to 70 c tlv320aic1xcdbtr tape and reel, 3000 tlv320aic1xidbt tape and reel, 250 tlv320aic1xi tssop-30 dbt -40 c to 85 c tlv320aic1xidbtr tape and reel, 3000 tlv320aic12kirhbt tape and reel, 250 tlv320aic12k qfn-32 rhb -40 c to 85 c tlv320aic12kirhbr tape and reel, 3000 tlv320aic14kirhbt tape and reel, 250 tlv320aic14k qfn-32 rhb -40 c to 85 c tlv320aic14kirhbr tape and reel, 3000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . 2 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 aic12/13/12k dbt package aic14/15/14k dbt package (top view) (top view) aic12k rhb package aic14k rhb package (top view) (top view) note: for the rhb package, connect the device thermal pad to drvdd. 3 submit documentation feedback www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iovss iovdd fsd fs dout din m/s pwrdn outm1 n/c n/c drvdd drvss outp2 outmv outp3 dvss dvdd sclk sda scl mclk reset inp1 inm1 bias inm2 inp2 micin avss avdd outp1 30 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iovss iovdd fsd fs dout din m/s pwrdn outm1 n/c n/c drvdd drvss n/c n/c n/c dvss dvdd sclk sda scl mclk reset inp1 inm1 bias inm2 inp2 micin avss avdd outp1 30 31 12 3 4 5 6 7 8 9 10 11 12 13 14 15 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 iovss iovdd fsd fs dout din m/s pwrdn outm1 outp1 drvdd drvss ncnc nc dvssdvdd sclk sda scl mclk reset inp1inm1 bias inm2 inp2 micin avdd avss 12 3 4 5 6 7 8 9 10 11 12 13 14 15 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 iovss iovdd fsd fs dout din m/s pwrdn outm1 outp1 drvdd drvss outp2 outmv outp3 dvssdvdd sclk sda scl mclk reset inp1inm1 bias inm2 inp2 micin avdd avss
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 terminal functions terminal name aic12/13/12k aic14/15/14k aic12k aic14k i/o description dbt dbt rhb rhb no. no. no. no. iovss 1 1 5 5 i digital i/o ground iovdd 2 2 6 6 i digital i/o power supply frame sync delayed output. the fsd output synchronizes a slave device to the frame sync of the master device. fsd is applied to the slave fs input and is the same duration as the master fs signal. this fsd 3 3 7 7 o pin must be pulled low if aic1x is a stand-alone slave. it must be pulled high if the aic1x is a stand-alone master or the last slave in the cascade. frame sync. when fs goes low, din begins receiving data bits and fs 4 4 8 8 i/o dout begins transmitting data bits. in master mode, fs is internally generated. in slave mode, fs is externally generated. data output. dout transmits the adc output bits and registers data, dout 5 5 9 9 o and is synchronized to sclk and fs. data is sent out at the rising edge of sclk. outside data/control frame, dout is put in 3-state. data input. din receives the dac input data and register data from the din 6 6 10 10 i external dsp (digital signal processor) and is synchronized to sclk and fs. data is latched at the falling edge of sclk. master/slave select input. when m/s is high, the device is the master, m/s 7 7 11 11 i and when low it is a slave. power down. when pwrdn is pulled low, the device goes into a power-down mode, the serial interface is disabled, and most of the high-speed clocks are disabled. however, all the register values are pwrdn 8 8 12 12 i sustained and the device resumes full-power operation without reinitialization when pwrdn is pulled high again. pwrdn resets the counters only and preserves the programmed register contents. inverting output of the dac. outm1 is functionally identical with and complementary to outp1. this differential output can drive a outm1 9 9 13 13 o maximum load of 600 w . this output can also be used alone for single-ended operation. noninverting output of the dac. this differential output can drive a outp1 10 10 14 14 o maximum load of 600 w . this output can also be used alone for single-ended operation. drvdd 11 11 15 15 i analog power supply for the 16- w drivers outp2 and outp3 drvss 12 12 17 17 i analog ground for the 16- w drivers outp2 and outp3 analog output number 2 from the 16- w driver. this output can drive a outp2 13 ? 18 ? o maximum load of 16 w , and also can be configured as either single-ended output or differential output by the control register 6. programmable virtual ground for the output of outp2 and outp3 outmv 14 ? 19 ? o (see the register map). analog output number 3 from the 16- w driver. this output can drive a outp3 15 ? 20 ? o maximum load of 16 w , and also be configured as either single-ended output or differential output by the control register 6. avss 16 16 21 21 i analog ground avdd 17 17 22 22 i analog power supply micin 18 18 23 23 i mic preamplifier input. it must be connected to avss if not used. inp2 19 19 24 24 i noninverting analog input 2. it must be connected to avss if not used. inm2 20 20 25 25 i inverting analog input 2. it must be connected to avss if not used. bias output voltage is software selectable between 1.35 v and 2.35 v. bias 21 21 27 27 o its output current is 5 ma. inm1 22 22 28 28 i inverting analog input 1. it must be connected to avss if not used. inp1 23 23 29 29 i noninverting analog input 1. it must be connected to avss if not used. hardware reset. the reset function is provided to initialize all of the reset 24 24 30 30 i internal registers to their default values. the serial port is configured to the default state accordingly. master clock. mclk derives the internal clocks of the sigma-delta mclk 25 25 31 31 i analog interface circuit. scl 26 26 32 32 i programmable host port (i 2 c or s 2 c) clock input. sda 27 27 1 1 i/o programmable host port (i 2 c or s 2 c) data line. 4 submit documentation feedback www.ti.com
electrical characteristics absolute maximum ratings tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 terminal functions (continued) terminal name aic12/13/12k aic14/15/14k aic12k aic14k i/o description dbt dbt rhb rhb no. no. no. no. shift clock. sclk signal clocks serial data into din and out of dout during the frame-sync interval. when configured as an output (m/s high), sclk is generated internally by multiplying the frame-sync signal sclk 28 28 2 2 i/o frequency by 16 and the number of codecs in cascade in standard and continuous mode. when configured as an input (m/s low), sclk is generated externally and must be synchronous with the master clock and frame sync. dvdd 29 29 3 3 i digital power supply dvss 30 30 4 4 i digital ground 16, 18, 19, 20, nc ? 13, 14, 15 16, 26 no connection 26 aic12, aic13, aic14, aic15, aic12k, aic14k: over recommended operating free-air temperature range avdd = 3.3 v, dvdd = 1.8 v, iovdd = 3.3 v (unless otherwise noted) over operating free-air temperature range (unless otherwise noted) (1) units v cc supply voltage range: dvdd (2) -0.3 v to 2.25 v avdd, drvdd, iovdd (2) -0.3 v to 4 v v o output voltage range, all digital output signals -0.3 v to iovdd + 0.3 v v i input voltage range, all digital input signals -0.3 v to iovdd + 0.3 v t a operating free-air temperature range -40 c to 85 c t j junction temperature 105 c t stg storage temperature range -65 c to 150 c power dissipation (t j max - t a ) / q ja q ja thermal impedance 44 c/w case temperature for 10 seconds: package 260 c aic12, aic13, aic14, aic15, aic12k and aic14k all cdm 500 v pins aic12, aic13, aic14, aic15, aic12k and aic14k all hbm 2 kv esd characteristics pins except for the following: dvdd, sda hbm 1.3 kv dout hbm 1.9 kv (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to v ss . 5 submit documentation feedback www.ti.com
recommended operating conditions tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 min nom max min nom max unit aic12/13/14/15 aic12k/14k supply voltage for analog, avdd 2.7 3.3 3.6 2.7 3.3 3.6 v supply voltage for analog output driver, drvdd 2.7 3.6 2.7 3.6 v ss supply voltage for digital core, dvdd 1.65 1.8 1.95 1.65 1.8 1.95 v supply voltage for digital i/o, iovdd 1.1 3.3 3.6 1.1 3.3 3.6 v v i(analog) analog single-ended peak-to-peak input voltage 2 2 v between outp1 and 600 600 outm1 (differential) between outp2 and 16 16 outmv (single-ended) between outp3 and r l output load resistance, 16 16 w outmv (single-ended) between outp2 and 32 32 outmv (differential) between outp3 and 32 32 outmv (differential) c l analog output load capacitance 20 20 pf digital output capacitance 20 20 pf master clock 100 100 mhz adc or dac conversion rate 26 26 khz t a operating free-air temperature -40 85 -40 85 c 6 submit documentation feedback www.ti.com
digital inputs and outputs adc path filter tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 f s = 8 khz, outputs not loaded parameter (1) min typ max unit v oh high-level output voltage, dout 0.8 iovdd v v ol low-level output voltage, dout 0.1 iovdd v i ih high-level input current, any digital input 0.5 a i il low-level input current, any digital input 0.5 a c i input capacitance 3 pf c o output capacitance 5 pf (1) for v ih (input high level), when iovdd < 1.6 v, minimum v ih is 1.1v. fs = 8 khz (1) (2) test parameter min typ max min typ max unit conditions fir filter iir filter 0 hz to 30 hz -0.5 0.2 -0.5 0.2 300 hz to 3 hz -0.5 0.25 -0.5 0.25 3.3 hz -0.5 0.3 -1.5 0.3 filter gain relative to gain db at 1020 hz 3.6 khz -3 -3 4 khz -35 -20 3 4.4 khz -74 -60 (1) the filter gain outside of the passband is measured with respect to the gain at 1020 hz. the analog input test signal is a sine wave with 0 db = 4 v i(pp) as the reference level for the analog input signal. the pass band is 0 to 3600 hz for an 8-khz sample rate. this pass band scales linearly with the sample rate. (2) the filter characteristics are specified by design and are not tested in production. 7 submit documentation feedback www.ti.com
adc dynamic performance adc channel characteristics tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 fs = 8 khz (1) test parameter min typ max min typ max unit conditions aic12/13/14/15 aic12k/14k v i = -1 db 82 88 75 88 snr signal-to-noise ratio v i = -9 db 78 82 82 v i = -40 db 46 v i = -1 db 84 90 75 90 thd total harmonic distortion v i = -9 db 82 88 88 db v i = -40 db 67 v i = -1 db 79 87 87 signal-to-harmonic thd+n v i = -9 db 73 79 79 distortion + noise v i = -40 db 48 (1) the test condition is a differential 1020-hz input signal with an 8-khz conversion rate. input and output common mode is 1.35 v. test parameter min typ max min typ max unit conditions aic12/13/14/15 aic12k/14k preamplifier gain = 6 v i(pp) single-ended input level 2 2 v db v io input offset voltage micin, inpx, inmx 10 10 mv i b input bias current micin, inpx, inmx 34 34 a common-mode voltage 1.35 1.35 v dynamic range v i = -1 db 85 85 db mute attenuation pga = mute 80 80 db intrachannel isolation 87 87 db e g gain error v i = -1 db at 1020 hz 0.6 0.6 db e o(adc) adc converter offset error 10 10 mv common-mode rejection cmrr v i = -1 db at 1020 hz 50 50 db ratio at inmx and inpx idle channel noise v (inp,inm,micin) = 0 v 50 100 50 vrms r i input resistance t a = 25 c 30 30 k w c i input capacitance t a = 25 c 2 2 pf iir 5/f s 5/f s s channel delay fir 17/f s 17/f s s 8 submit documentation feedback www.ti.com
dac path filter dac dynamic performance tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 fs = 8 khz (1) (2) test parameter min typ max min typ max unit conditions fir filter iir filter 0 hz to 30 hz -0.5 0.2 -0.5 0.2 300 hz to 3 hz -0.25 0.25 -0.25 0.35 3.3 hz -0.35 0.3 -0.75 0.3 filter gain relative to gain db at 1020 hz 3.6 khz -3 -3 4 khz -40 -20 3 4.4 khz -74 -60 (1) the filter gain outside of the passband is measured with respect to the gain at 1020 hz. the input signal is the digital equivalent of a sine wave (digital full scale = 0 db). the nominal differential dac channel output with this input condition = 4 v i(pp) . the pass band is 0 to 3600 hz for an 8-khz sample rate. this pass band scales linearly with the sample rate. (2) the filter characteristics are specified by design and are not tested in production. test parameter min typ max min typ max unit conditions aic12/13/14/15 aic12k/14k dac line output (outp1, outm1) (1) v i = 0 db 80 92 75 92 snr signal-to-noise ratio v i = -9 db 75 83 83 v i = -40 db 51 v i = 0 db 78 85 70 85 total harmonic thd v i = -9 db 74 83 83 db distortion v i = -40 db 62 v i = 0 db 75 82 82 signal-to-total harmonic thd+n v i = -9 db 70 77 77 distortion + noise v i = -40 db 44 dac headphone output (outp2, outp3) (1) (2) v i = 0 db 78 89 89 snr signal-to-noise ratio db v i = -9 db 71 81 81 v i = 0 db 78 82 82 total harmonic thd db distortion v i = -9 db 73 80 80 v i = 0 db 75 80 80 signal-to-total harmonic thd+n db distortion + noise v i = -9 db 69 78 78 dac speaker output (outp2, outmv) (1) (3) snr signal-to-noise ratio v i = 0 db 91 db total harmonic thd v i = 0 db 80 db distortion (1) the test condition is the digital equivalent of a 1020 hz input signal with an 8-khz conversion rate. the test is measured at output of application schematic low-pass filter. the test is conducted in 16-bit mode. (2) the dac headphone output spec between outp2, outp3, and outmv is valid only for the aic12/13 and the aic12k (3) the dac speaker output spec between outp2, outp3, and outmv is valid only for the aic12k. 9 submit documentation feedback www.ti.com
dac channel characteristics bias amplifier characteristics outmv amplifier characteristics tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 parameter test conditions min typ max unit dynamic range v i = 0 db at 1020 hz 92 db interchannel isolation 120 db e g gain error, 0 db v o = 0 db at 1020 hz 0.5 db common mode voltage 1.35 v idle channel narrow band noise 0 khz-4 khz (1) 80 125 (2) vrms v oo output offset voltage at out (differential) din = all zeros 10 mv v o analog output voltage, (3.3 v) outp 0.35 2.35 v 600 w load at 3.3 v between 6.7 outp1 and outm1 16 w load at 3.3 v between single-ended outp2/outmv and 62.5 outp3/outmv (3) p (o) maximum output power mw 16 w load at 3.3 v between differential outp2/outp3 and 125 outmv (4) 8 w load at 3.3 v between differential outp2/outp3 and 190 outmv (4) iir 5/f s channel delay s fir 18/f s (1) the conversion rate is 8 khz. (2) the max value is valid only for the aic12/13/14/15. (3) the specification for maximum power output for single ended load between outp2/outmv and outp3/outmv is valid only for the aic12/13 and aic12k. (4) the specification for maximum power output for differential load between outp2/outp3 and outmv is valid only for the aic12/13 and aic12k. parameter test conditions min typ max min typ max unit aic12/13/14/15 aic12k/14k v o output voltage 2.2 2.35 2.4 2.35 v integrated noise 300 hz-13 khz 20 20 v offset voltage 10 10 mv current drive 10 10 ma unity gain bandwidth 1 1 mhz dc gain 140 120 db parameter test conditions min typ max min typ max unit aic12/13/14/15 aic12k/14k v o output voltage 1.3 1.35 1.4 1.35 v integrated noise 300 hz-13 khz 20 20 v offset voltage 10 10 mv current drive 62.5 62.5 ma unity gain bandwidth 1 1 mhz dc gain 120 120 db 10 submit documentation feedback www.ti.com
power-supply rejection (1) power supply tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 parameter test conditions min typ max unit differential 75 av dd supply-voltage rejection ratio, analog supply (f j = 0 to f s /2) at 1 khz db single-ended 50 dac channel 95 dv dd supply-voltage rejection ratio, dac channel f j = 0 khz to 30 khz db adc channel 86 (1) power supply rejection measurements are made with both the adc and dac channels idle and a 200 mv peak-to-peak signal applied to the appropriate supply. parameter test conditions min typ max min typ max unit aic12/13/14/15 aic12k/14k all sections on 17.8 23.1 17.8 p d power dissipation (1) mw without 16- w drivers 11.2 16.5 11.2 all sections on 5.4 7 5.4 ma i (total) total current (1) without 16- w drivers 3.4 5 3.4 power down 0.01 0.01 ma adc 2 2 dac 1 1 analog i dd supply current ref 0.4 0.4 ma 16- w drivers 2 2 digital (2) coarse sampling 1 1 i dd analog 1.4 1.4 ma i dd supply current, pll i dd digital 1 1 (1) excludes digital (2) all section on except the pll condition. 11 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional block diagram aic12/13/12k 12 submit documentation feedback www.ti.com s2d mux analog loopback (600 w driver) (16 w driver) d2s (16 w driver) d2s micin inp2 inm2 inp1 inm1 outp1 outm1 outp2outp3 outmv bias pga - 42 db to 20 dbstep size = 1 db low pass filter sigma- delta dac anti- aliasing filter sigma- delta adc sinc filter fir filter iir filter decimation filter sinc filter fir filter iir filter interpolation filter digital loopback w/ sidetone control and mute m/sdout din fs sclk fsd scl sda host port div 16xmxnxp internal clock circuit mclk pga - 42 db to 20 dbstep size = 1 db smartdm preamplifier 24, 12, 6, 0 db -3 db to -21 db 1.35 v/2.35 v @ 5 ma max serial port v ref
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional block diagram aic14/15/14k 13 submit documentation feedback www.ti.com mux analog loopback (600 w driver) micin inp2 inm2 inp1 inm1 outp1 outm1 bias pga ? 42 db to 20 dbstep size = 1 db low-pass filter sigma- delta dac anti- aliasing filter sigma- delta adc sinc filter fir filter iir filter decimation filter sinc filter fir filter iir filter interpolation filter digital loopback w/ sidetone control and mute m/sdout din fs sclk fsd scl sda host port div 16xmxnxp internal clock circuit mclk pga ? 42 db to 20 dbstep size = 1 db smartdm preamplifier 24, 12, 6, 0 db ?3 db to ?21 db 1.35 v/2.35 v @ 5 ma max serial port v ref s 2 d
definitions and terminology tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 term definition data transfer the time during which data is transferred from dout and to din. the interval interval is 16 shift clocks and the data transfer is initiated by the falling edge of the fs signal in standard and continuous mode. signal data this refers to the input signal and all of the converted representations through the adc channel and the signal through the dac channel to the analog output. this is contrasted with the purely digital software control data. frame sync frame sync refers only to the falling edge of the signal fs that initiates the data transfer interval frame sync and sampling frame sync and sampling period is the time between falling edges of period successive fs signals. f s the sampling frequency adc channel adc channel refers to all signal processing circuits between the analog input and the digital conversion result at dout. dac channel dac channel refers to all signal processing circuits between the digital data word applied to din and the differential output analog signal available at outp and outm. dxx bit position in the primary data word (xx is the bit number) dsxx bit position in the secondary data word (xx is the bit number) pga programmable gain amplifier iir infinite impulse response fir finite impulse response 14 submit documentation feedback www.ti.com
timing requirements tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 1. hardware reset timing figure 2. serial communication timing test conditions min typ max unit t wh pulse duration, mclk high 5 t wl pulse duration, mclk low 5 setup time, reset, before mclk high t su1 3 (see figure 1 ) t h1 hold time, reset, after mclk high (see figure 1 ) 2 t d1 delay time, sclk - to fs/fsd c l = 20 pf 5 ns t d2 delay time, sclk - to fs/fsd - 5 t d3 delay time, sclk - to dout 15 t en enable time, sclk - to dout 15 t dis disable time, sclk - to dout 15 t su2 setup time, din, before sclk 10 t h2 hold time, din, after sclk 10 15 submit documentation feedback www.ti.com t h1 2.4 v mclk reset 2.4 v t su1 2.4 v t wl t wh t d1 t d2 t d1 t d2 t en t d3 t dis t su2 t h2 d15d15 sclk fs fsd dout din
parameter measurement information tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 3. i 2 c / s 2 c timing test conditions min max unit t scl scl clock frequency 0 900 khz t hd;sta hold time (repeated start condition. after this 100 ns period, the first clock pulse is generated. t low low period of the scl clock 560 ns t high high period of the scl clock 560 ns t su;sta set-up time for a repeated start condition c l = 20 pf 100 ns t hd;dat data hold time 50 ns t su;dat data set-up time 50 ns t r rise time of both sda and scl signals 300 ns t f fall time of both sda and scl signals 100 ns t su;sto set-up time for stop condition 100 ns t buf bus free time between a stop and start condition 500 ns figure 4. fft?adc channel (-1 db input) 16 submit documentation feedback www.ti.com sda scl t su;sto t buf t r t hd;sta t su;sta t high t hd;dat t hd;sta t low t f t r t f t su;oat -160 -140 -120 -100 -80 -60 -40 -20 0 0 1000 2000 3000 amplitude - db f - frequency - hz 500 1500 2500 3500 4000 sampling rate at 8 khz
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 parameter measurement information (continued) figure 5. fft?adc channel (-9 db input) figure 6. fft?dac channel (0 db input) figure 7. fft?dac channel (-9 db input) 17 submit documentation feedback www.ti.com -160 -140 -120 -100 -80 -60 -40 -20 0 0 1000 2000 3000 amplitude - db f - frequency - hz 500 1500 2500 3500 4000 sampling rate at 8 khz -160 -140 -120 -100 -80 -60 -40 -20 0 0 1000 2000 3000 amplitude - db f - frequency - hz 500 1500 2500 3500 4000 sampling rate at 8 khz -160 -140 -120 -100 -80 -60 -40 -20 0 0 1000 2000 3000 amplitude - db f - frequency - hz 500 1500 2500 3500 4000 sampling rate at 8 khz
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 parameter measurement information (continued) figure 8. fft?adc channel in fir/iir bypass mode (-1 db input) figure 9. fft?dac channel in fir/iir bypass mode (0 db input) 18 submit documentation feedback www.ti.com -140 -120 -100 -80 -60 -40 -20 0 0 4000 8000 12000 amplitude - db f - frequency - hz 2000 6000 10000 14000 16000 adc at 8 khzfs = 32 khz -140 -120 -100 -80 -60 -40 -20 0 0 4000 8000 12000 amplitude - db f - frequency - hz 2000 6000 10000 14000 16000 dac at 8 khzfs = 32 khz
typical characteristics tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 adc filter gain adc filter gain vs vs frequency response (fir) frequency response (iir) figure 10. figure 11. adc iir filter group delay dac iir filter group delay vs vs frequency frequency response figure 12. figure 13. 19 submit documentation feedback www.ti.com ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 500 1000 1500 2000 2500 3000 3500 4000 filter gain ? db f ? frequency ? hz ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 500 1000 1500 2000 2500 3000 3500 4000 filter gain ? db f ? frequency ? hz ?45 0 3 4 5 6 7 8 9 0 500 1000 1500 2000 2500 3000 3500 4000 group delay - fs f - frequency - hz 1 2 0 3 4 5 6 7 8 9 0 500 1000 1500 2000 2500 3000 3500 4000 group delay - fs f - frequency - hz 1 2
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 typical characteristics (continued) adc filter gain dac filter gain vs vs frequency (fir/iir bypass) frequency (fir/iir bypass) figure 14. figure 15. dac iir dac fir vs vs frequency response frequency response figure 16. figure 17. 20 submit documentation feedback www.ti.com -14 -8 -6 -4 -2 0 2 4 0 2000 4000 6000 8000 10 k 12 k 14 k 16 k filter gain - db f - frequency - hz -12 -10 -14 -8 -6 -4 -2 0 2 4 0 2000 4000 6000 8000 10 k 12 k 14 k 16 k filter gain - db f - frequency - hz -12 -10 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 1000 2000 3000 4000 5000 6000 7000 8000 filter gain ? db f ? frequency ? hz osr = 512 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 1000 2000 3000 4000 5000 6000 7000 8000 filter gain ? db f ? frequency ? hz osr = 128
functional description operating frequencies (see notes) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 typical characteristics (continued) dac fir dac fir vs vs frequency response frequency response figure 18. figure 19. the sampling frequency is the frequency of the frame sync (fs) signal whose falling edge starts digital-data transfer for both adc and dac. the sampling frequency is derived from the master clock (mclk) input by the following equations: coarse sampling frequency (default): ? the coarse sampling is selected by programming p = 8 in the control register 4, which is the default configuration of aic1x on power-up or reset. ? fs = sampling (conversion) frequency = mclk ? (16 m n 8) fine sampling frequency (see step 5): ? fs = sampling (conversion) frequency = mclk ? (16 m n p) notes: 1. use control register 4 to set the following values of m, n, and p 2. m = 1, 2, . . . , 128 3. n = 1, 2,..., 16 4. p = 1, 2, ..., 8 5. the fine sampling rate needs an on-chip phase lock loop (frequency multiplier) to generate internal clocks. the pll requires the relationship between mclk and p to meet the following condition: 10 mhz (mclk ? p) 25 mhz. the output of the pll is only used to generate internal clocks that are needed by the data converters. other clocks such as the serial interface clocks in master mode are not generated from the pll output. the clock generation scheme is as shown in figure 20 . 21 submit documentation feedback www.ti.com ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 1000 2000 3000 4000 5000 6000 7000 8000 filter gain ? db f ? frequency ? hz osr = 256 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 1000 2000 3000 4000 5000 6000 7000 8000 filter gain ? db f ? frequency ? hz osr = 128
internal architecture analog low-pass filter sigma-delta adc tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional description (continued) figure 20. aic1x clock tree architecture 6. both equation of fs require that the following conditions be met: ? (m n p) 3 (devnum mode) if the fir/iir filter is not bypassed. ? [integer (m ? 4) n p] 3 (devnum mode) if the fir/iir filter is bypassed. where: ? devnum is the number of codec channels connecting in cascade mode. ? mode is equal to 1 for continuous data transfer mode and 2 for programming mode. 7. if the dac osr is set to 512, then m needs to be a multiple of 4. if the dac osr is set to 256, then m needs to be a multiple of 2. m can take any value between 1 and 128 if the osr is set to 128. example: the mclk that comes from the dsp 'c5402 clkout equals to 20.48 mhz, and the conversion rate of 8 khz is desired. first, set p = 1 to satisfy condition step 5 above so that (mclk ? p) = 20.48 mhz ? 1 = 20.48 mhz. next, pick m = 10 and n = 16 to satisfy step 6 above and derive 8 khz for fs. the built-in analog low-pass filter is a two-pole filter that has a 20-db attenuation at 1 mhz. the analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. the adc provides high-resolution, low-noise performance using oversampling techniques. due to the oversampling employed, only single pole r-c filters are required on the analog inputs. 22 submit documentation feedback www.ti.com mclk 1/p x 8 (dll) 1/(mn) 128 fs (no_dev x mode) / (mnp) sclk 1 / (16 x mode x no_dev) fs en_dll m = 1 - 128n = 1 - 16 p = 1- 8 when p = 8, dll(pll) is enabled devnum = number of devices in cascade mode = 1 (for continious data tranfer mode) sclk may not be an uniform clock depending upon values of devnum, mode, and mnp digital mode = 2 (for programming mode) * * fs 20.48 mhz (16 10 16 1) 8 khz
decimation filter sigma-delta dac interpolation filter analog/digital loopback side-tone loopback adc pga dac pga analog input/output tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional description (continued) the decimation filters are either fir filters or iir filters selected by bit d5 of the control register 1. the fir filter provides linear-phase output with 17/f s group delay, whereas the iir filter generates nonlinear phase output with negligible group delay. the decimation filters reduce the digital data rate to the sampling rate. this is accomplished by decimating with a ratio of 1:128. the output of the decimation filter is a 16-bit 2s-complement data word clocking at the sample rate selected. the bw of the filter is (0.45 fs) and scales linearly with the sample rate. the digital-to-analog converter is a sigma-delta modulator with 128/256/512-x oversampling. the dac provides high-resolution, low-noise performance using oversampling techniques. the oversampling ratio in dac is programmable to 256/512 using bits d4-d3 of control register 3, the default being 128. oversampling ratio of 512 can be used when fs is a maximum of 8 ksps and an oversampling ratio of 256 can be used when fs is a maximum of a 16 ksps. m should be a multiple of 2 for an oversampling ratio of 256 and 4 for oversampling ratio of 512. the interpolation filters are either fir filters or iir filters selected by bit d5 of the control register 1. the fir filter provides linear-phase output with 18/f s group delay, whereas the iir filter generates nonlinear phase output with negligible group delay. the interpolation filter resamples the digital data at a rate of 128/256/512 times the incoming sample rate, based on the oversampling rate of dac. the high-speed data output from the interpolation filter is then used in the sigma-delta dac. the bw of the filter is (0.45 fs) and scales linearly with the sample rate. the analog and digital loopbacks provide a means of testing the data adc/dac channels and can be used for in-circuit system level tests. the analog loopback always has the priority to route the dac low pass filter output into the analog input where it is then converted by the adc to a digital word. the digital loopback routes the adc output to the dac input on the device. analog loopback is enabled by writing a 1 to bit d2 in the control register 1. digital loopback is enabled by writing a 1 to bit d1 in control register 1. the side-tone digital loopback attenuates the adc output and mixes it with the input of the dac. the level of the side tone is set by dstg, bits d5-d3 of the control register 5c. tlv320aic1x has a built-in pga for controlling the signal levels at adc outputs. adc pga gain setting can be selected by writing into bits d5-d0 of register 5a. the pga range of the adc channel is 20 db to -42 db in steps of 1 db and mute. to avoid sudden jumps in signal levels with pga changes, the gains are applied internally with zero-crossovers. tlv320aic1x has a built-in pga for controlling the analog output signal levels in dac channel. dac pga gain setting can selected by writing into bits d5-d0 of register 5b. the pga range of the dac channel is 20 db to -42 db in steps of 1 db, and mute. to avoid sudden pop-sounds with power-up/down and gain changes the power-up/down and gain changes for dac channel are applied internally with zero-crossovers. the tlv320aic1x has three programmable analog inputs and three programmable analog outputs. bits d2-d1 of control register 6 select the analog input source from micin, inp1/m1, or inp2/m2. all analog i/o are either single-ended or differential. all analog input signals are self-biased to 1.35 v. the three analog outputs are configured by bits d7, d6, d5, and d4-d3 of control register 6. 23 submit documentation feedback www.ti.com
mic input inp and inm input single-ended analog input tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional description (continued) tlv320aic1x supports single ended microphone input. this can be used by connecting the external single ended source through ac coupling to the micin pin. this channel is selected by writing 01 or 10 into bits d2-d1 in control register 6. the single ended input is supported in two modes. writing 01 into bits d2-d1 chooses self biased micin mode. in this mode, the device internally self-biases the input at 1.35v. for best noise performance, the user should bias the microphone circuit using the bias voltage generated by the device as shown in figure 21 . writing 10 into bits d2-d1 chooses pseudo-differential micin mode. in this mode, the single ended input is connected through ac-coupling to micin and the bias voltage used to generate the signal is also ac coupled to inm1 as shown in figure 22 . for best noise performance, the micin and inm1 lines must be routed in similar fashion from the microphone to the device for noise cancellation. for high quality performance, the single ended signal is converted internally into differential signal before being converted. to improve the dynamic range with different types of microphones, the device supports a preamplifier with gain settings of 0/6/12/24 db. this can be chosen by writing into bits d1-d0 of control register 5c. figure 21. microphone interface to produce common-mode rejection of unwanted signal performance, the analog signal is processed differentially until it is converted to digital data. the signal applied to the terminals inm1/2 and inp1/2 are differential to preserve device specifications (see figure 22 ). the signal source driving analog inputs (inp1/2 and inm1/2) should have low source impedance for lowest noise performance and accuracy. to obtain maximum dynamic range, the signal should be ac-coupled to the input terminal. figure 22. inp and inm internal self-biased circuit the two differential inputs of (inp1/m1 and inp2/m2) can be configured to work as single-ended inputs by connecting inp to the analog input and inm to ground (see figure 23 ). 24 submit documentation feedback www.ti.com tlv320aic12 tlv320aic12 biasmicin 10 k w 0.1 m f electret microphone biasmicin inm1 0.1 m f 10 k w 0.1 m f electret microphone (a) single ended (b) pseudo -differential (high quality) inp1 or inp2 inm1 or inm2 1.35 v tlv320aic12 v (inp) v (inm)
analog output tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional description (continued) figure 23. single-ended input the outp and outm are differential output from the dac channel. the outp1 and outm1 can drive a load of 600- w directly and be either differential or single-ended (see figure 24 ). the outp2 and outp3 are output from two audio amplifiers to drive low-voltage speakers like those in the handset and headset. they can drive a load of 16- w directly and be configured as either differential output or single-ended output as by bit d7 of the control register 6 (see figure 25 ). if outp2 and outp3 are differential output, the outmv pin becomes the common inverting output. both outp2 and outp3 can be used simultaneously if each differential load r l > 32 w . this is because outmv amplifier can drive a maximum load of 16 w only (only one driver used) or a parallel combination of two 32- w loads (both drivers used). if both outp2 and outp3 are used simultaneously, they are muted at the same time if mute is selected. otherwise, the outmv pin is configured as the virtual ground for single-ended output and equal to the common mode voltage at 1.35 v. figure 24. outp1/outm1 output figure 25. single-ended/differential connection of outp2/outp3 output analog output configuration speaker driver configuration no. of speaker drivers on min load single-ended 1 16- w single-ended 2 32- w differential 1 16- w 25 submit documentation feedback www.ti.com inp1 or inp2 inm1 or inm2 c c analog input outp1outm1 rl differential output outp/outm outp1outm1 rl single-ended output outp/outm c outp2outp3 rl outmv rl
iir/fir control overflow flags iir/fir bypass mode system reset and power management software and hardware reset tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 functional description (continued) analog output configuration (continued) speaker driver configuration no. of speaker drivers on min load differential 2 32- w the decimation iir/fir filter sets an overflow flag (bit d7) of control register 1 indicating that the input analog signal has exceeded the range of internal decimation filter calculations. the interpolation iir/fir filter sets an overflow flag (bit d4) of control register 1 indicating that the digital input has exceeded the range of internal interpolation filter calculations. when the iir/fir overflow flag is set in the register, it remains set until the user reads the register. reading this value resets the overflow flag. these flags need to be reset after power-up by reading the register. if fir/iir overflow occurs, the input signal is attenuated by either the pga or some other method. an option is provided to bypass iir/fir filter sections of the decimation filter and the interpolation filter. this mode is selected through bit d6 of control register 2 and effectively increases the frequency of the fs signal to four times normal output rate of the iir/fir-filter. for example, for a normal sampling rate of 8 ksps (i.e., fs = 8 khz) with iir/fir, if the iir/fir is bypassed, the frequency of fs is readjusted to 4 8 khz = 32 khz. the sinc filters of the two paths can not be bypassed. a maximum of eight devices in cascade can be supported in the iir/fir bypassed mode. in this mode , the adc channel outputs data which has been decimated only until 4fs. similarly dac channel input needs to be preinterpolated to 4fs before being given to the device. this mode allows users the flexibility to implement their own filter in dsp for decimation and interpolation. m should be a multiple of 4 during iir/fir bypass mode. the frequency responses of the iir/fir bypass modes are shown in figure 14 and figure 15 . the tlv320aic1x resets internal counters and registers in response to either of two events: a low-going reset pulse is applied to terminal reset a 1 is written to the programmable software reset bits (d5 of control register 3) note: the tlv320aic1x requires a power-up reset applied to the reset pin before normal operation is started. either event resets the control registers and clears all sequential circuits in the device. the h/w reset (active low) signal is at least 6 master clock periods long. as soon as the reset input is applied, the tlv320aic1x enters the initialization cycle that lasts for 132 mclks, during which the serial port of the dsp must be tristated. the initialization sequence performed by the 'aic1x is known as auto cascade detection (acd). acd is a mechanism that allows a device to know its address in a cascade chain. up to 16 'aic1x devices can be cascaded together. the master device is the first device on the chain (i.e. the fs of the master is connected to the fs of the dsp). during acd, each device gets to know the number of devices in the chain as well as its relative position in the chain. this is done on hardware reset. therefore, after power up, a hardware reset must be done. acd requires 132 mclks after reset to complete operation. the number of mclks is independent of the number of devices in the chain. adjacent devices in the chain have their fs and fsd pins connected to each other. the master device fs is connected to the fs pin of the dsp. the fsd pin on the last device in the chain is pulled high. the master device has the highest address (i.e. 0, the next device in the chain has an address of 1, followed by 2 etc.). during the first 64 mclks, fs is configured as an output and fsd as an input. during the next 64 mclks, fs is configured as an input and fsd as an output. the master device always has fs configured as an output and the last slave in the cascade (i.e. channel with address 0) always has fsd configured as an input. 26 submit documentation feedback www.ti.com
power management software power-down hardware power-down host port interface tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 to calculate the channel address, during the first 64 mclks, the device counts the number of clocks between acd starting (reset) and the fsd going high. during the next 64 mclks, the device counts the number of clocks till fs is pulled low. the sum total of the counts in the first phase and the second phase is the number of devices in the channel. for a cascaded system, the rise time of h/w reset needs to be less than the mclk period and should satisfy setup time requirement of 2 ns with respect to mclk rise-edge. in stand-alone-slave mode sclk must be running during reset. if more than one codec is cascaded, reset must be synchronized to mclk. additionally, all devices must see the same edge of mclk within a window of 0.5 ns the reset signal need not be synchronized with mclk when the codec is in stand-alone master or slave configuration. most of the device (all except the digital interface) enters the power-down mode when d7 and d6, in control register 3, are set to 1. when the pwrdn pin is low, the entire device is powered down. in either case, register contents are preserved. the amount of power drawn during software power down is higher than during a hardware power down because of the current required to keep the digital interface active. additional differences between software and hardware power-down modes are detailed in the following paragraphs. data bits d7 and d6 of control register 3 are used by tlv320aic1x to turn on or off the software power-down mode, which takes effect in the next frame fs. the adc and dac can be powered down individually. in the software power-down, the digital interface circuit is still active while the internal adc and dac channel and differential outputs outpx and outmx are disabled, and dout is put in 3-state in the data frame only. register data in the control frame is still accepted via din, but data in the data frame is ignored. the device returns to normal operation when d7 and d6 of control register 3 are reset. the tlv320aic1x requires the pwrdn signal to be synchronized with mclk. when pwrdn is held low, the device enters hardware power-down mode. in this state, the internal clock control circuit and the differential outputs are disabled. all other digital i/os are disabled and din cannot accept any data input. the device can only be returned to normal operation by holding pwrdn high. getting out of the power-down mode (i.e. bringing pwrdn from low to high state) requires that the low-to-high transition of pwrdn be synchronous to the rising edge of mclk. if there is no need for the hardware power-down mode feature of the device, the pwrdn pin must be tied high. the host port uses a 2-wire serial interface (scl, sda) to program the aic1x's six control registers and selectable protocol between s 2 c mode and i 2 c mode. the s 2 c is a write-only mode and the i 2 c is a read-write mode selected by setting the bits d1 and d0 of control register 2 to 00 or 01. if the host interface is not needed the two pins of scl and sda can be programmed to become general-purpose i/os by setting the bits d1 and d0 of control register 2 to 10 or 11. if selected to be used as i/o pins, the sda and scl pins become output and input pins respectively, determined by d1 and d0. both s 2 c and i 2 c require a smartdm device address to communicate with the aic1x. one of smartdms advanced features is the automatic cascade detection (acd) that enables smartdm to automatically detect the total number of codecs in the serial connection and use this information to assign each codec a distinct smartdm device address. table 1 lists device addresses assigned to each codec in the cascade by the smartdm. the master always has the highest position in the cascade. for example, if there is a total of 8 codecs in the cascade (i.e., one master and 7 slaves), then the device addresses in row 8 are used in which the master is codec 7 with a device address of 0111. table 1. smartdm device addresses total codec position in cascade codecs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0000 27 submit documentation feedback www.ti.com
s 2 c (start-stop communication) i 2 c tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 table 1. smartdm device addresses (continued) total codec position in cascade codecs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 0001 0000 3 0010 0001 0000 4 0011 0010 0001 0000 5 0100 0011 0010 0001 0000 6 0101 0100 0011 0010 0001 0000 7 0110 0101 0100 0011 0010 0001 0000 8 0111 0110 0101 0100 0011 0010 0001 0000 9 1000 0111 0110 0101 0100 0011 0010 0001 0000 10 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 11 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 12 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 13 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 14 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 15 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 16 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 the s 2 c is a write-only interface selected by programming bits d1-d0 of control register 2 to 01. the sda input is normally in a high state, pulled low (start bit) to start the communication, and pulled high (stop bit) after the transmission of the lsb. sclk and fs must be active during register programming. figure 26 shows the timing diagram of s 2 c. the s 2 c also supports a broadcast mode in which the same register of all devices in cascade is programmed in a single write. to use s 2 cs broadcast mode, execute the following steps: 1. write 111 1000 1111 1111 after the start bit to enable the broadcast mode. 2. write data to program control register as specified in figure 26 with bits d14-d11 = xxxx (don't care). 3. write 111 1000 0000 0000 after the start bit to disable the broadcast mode. figure 26. s 2 c programming each i 2 c read-from or write-to 'aic1xs control register is given by index register address. read/write sequence always starts with the first byte as i 2 c address followed by 0. during the second byte, default/broadcast mode is set and the index register address is initialized. for write operation control register, data to be written is given from the third byte onwards. for read operation, stop-start is performed after the second byte. now the first byte is i 2 c address followed by 1. from the second byte onwards, control register data appears. each time read/write is performed, the index register address is incremented so that next read/write is performed on the next control register. during the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues ack to the i 2 c. 28 submit documentation feedback www.ti.com d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 scl sda start bit = 0 stop bit = 1 smartdm device address (see t able 1) registeraddress register content
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 27. i 2 c write sequence figure 28. i 2 c read sequence each aic has an index register address. to perform a write operation, make the lsb of the first byte as 0 (write) (see figure 29 ). during the second byte, the index register address is initialized and mode (broadcast/default) is set. from the third byte onwards, write data to the control register (given by index register) and increment the index register until stop or repeated start occurs. for operation, make the lsb of the first byte as 1 (read). from the second byte onwards, aic starts transmitting data from the control register (given by the index register) and increments the index register. for setting the index register perform operation the same as write case for 2 bytes, and then give a stop or repeated start. s/sr -> start/repeated start. 29 submit documentation feedback www.ti.com i 2 c write sequence scl sda a5 a4 a3 a2 a1 a0 0 ack b7 b6 b5 b4 b3 r2 r1 r0 i2c 6 a6 i2c 5 i2c 4 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack ack programmable i c device address 2 set by control register 2 start bit = 0 smartdm device address (see table 1) 00000 = default 11111 = broadcast mode index register address (index) control register data for write (index) control register data for write (index+1) sclsda a5 a4 a3 a2 a1 a0 0 ack b7 b6 b5 b4 b3 r2 r1 r0 i2c 6 a6 ack i2c 5 i2c 4 scl sda a5 a4 a3 a2 a1 a0 1 ack d7 d6 d5 d4 d3 d2 d1 d0 i2c 6 a6 i2c 5 i2c 4 d7 d6 d5 d4 d3 d2 d1 d0 ack ack start bit = 0 programmable 12c device address set by control register 2 smartdm device address (see table 1) index register address (index) stop bit = 1 xxxxx = don't care start bit = 0 programmable 12c device address set by control register 2 smartdm device address (see table 1) control register data (index) control register data (index+1) i 2 c read sequence
smart time division multiplexed serial port (smartdm) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 29. index register addresses the smart time division multiplexed serial port (smartdm) uses the 4 wires of dout, din, sclk, and fs to transfer data into and out of the aic1x. the tlv320aic1x's smartdm supports three serial interface configurations (see table 2 ): stand-alone master, stand-alone slave, and master-slave cascade, employing a time division multiplexed (tdm) scheme (a cascade of only-slaves is not supported). the smartdm allows for a serial connection of up to 16 codecs to a single serial port. data communication in the three serial interface configurations can be carried out in either standard operation (default) or turbo operation. each operation has two modes; programming mode (default mode) and continuous data transfer mode. to switch from the programming mode to the continuous data transfer mode, set bit d6 of control register 1 to 1, which is reset automatically after switching back to programming mode. the tlv320aic1x can be switched back from the continuous data transfer mode to the programming mode by setting the lsb of the data on din to 1, only if the data format is (15+1), as selected by bit 0 of control register 1. the smartdm automatically adjusts the number of time slots per frame sync (fs) to match the number of codecs in the serial interface so that no time slot is wasted. both the programming mode and the continuous data transfer mode of the tlv320aic1x are compatible with the tlv320aic10. the tlv320aic1x provides primary/secondary communication and continuous data transfer with improvements and eliminates the requirements for hardware and software requests for secondary communication as seen in other devices. the tlv320aic1x continuous data transfer mode now supports both master/slave stand alone and cascade. table 2. serial interface configurations m/s pin fsd pin tlv320aic1x connections comments master slave master slave stand-alone master high na pull high na stand-alone slave na low na pull-low connect to the next slave's fs master-slave cascade high low last slave's fsd pin is pulled high (see figure 32 ) slave-slave cascade na na na na not supported 30 submit documentation feedback www.ti.com s/sr i 2 c device address (3 bit)+ dtdmsp device address (+) r/w = 0 mode (5 bit) + index reg address (3 bit) ack ack control reg. data (write) ack control reg. data (write) 7 bit 1 bit 8 bit 8 bit 8 bit increment index reg. address default/broadcast (00000/11111) w rite mode t o the address given by index reg. address t o the address given by index reg. address s/sr i 2 c device address (3 bit)+ dtdmsp device address (+) r/w = 1 control reg. data(read) ack ack control reg. data(read) ack 7 bit 1 bit 8 bit 8 bit read mode from the address givenby index reg. address from the address givenby index reg. address increment index reg. address increment index reg. address s/sr i 2 c device address (3 bit)+ dtdmsp device address (+) r/w = 0 mode (5 bit) + index reg. address (3 bit) ack ack 7 bit 1 bit 8 bit for initializing index reg address stop
digital interface tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 clock source (mclk, sclk) mclk is the external master clock input. the clock circuit generates and distributes necessary clocks throughout the device. sclk is the bit clock used to receive and transmit data synchronously. when the device is in the master mode, sclk and fs are output and derived from mclk in order to provide clocking the serial communications between the device and a digital signal processor (dsp). when in the slave mode, sclk and fs are inputs. in the non-turbo mode (turbo = 0), sclk frequency is defined by: sclk = (16 fs #devices mode) where: fs is the frame-sync frequency. #device is the number of the device in cascade. mode is equal to 1 for continuous data transfer mode and 2 for programming mode. in turbo mode, see the turbo mode operation section of this data sheet. serial data out (dout) dout is placed in the high-impedance state after transmission of the lsb is completed. in data frame, the data word is the adc conversion result. in the control frame, the data is the register read results when requested by the read/write (r/w) bit. if a register read is not requested, the low eight bits of the secondary word are all zeroes. valid data on dout is taken from the high-impedance state by the falling edge of frame-sync (fs). the first bit transmitted on the falling edge of fs is the msb of valid data. serial data in (din) the data format of din is the same as that of dout, in which msb is received first on the falling edge of fs. in a data frame, the data word is the input digital signal to the dac channel. if (15+1)-bit data format is used, the lsb (d0) is set to 1 to switch from the continuous data transfer mode to the programming mode. in a control frame, the data is the control and configuration data that sets the device for a particular function as described in the control register programming section. frame-sync fs the frame-sync signal (fs) indicates the device is ready to send and receive data. the fs is an output if the m/s pin is connected to hi (master mode), and an input if the m/s pin is connected to lo (slave mode). the start of valid data is synchronized on the falling edge of the fs signal. in nonturbo mode, the fs signal must be present every (16 sclk mode). however, in turbo mode, the number of sclk per fs cycle can vary. the frequency of fs is defined as the sampling rate of the tlv320aic1x and derived from the master clock, mclk, as follows (see operating frequencies section for details): fs = mclk ? (16 p n m) figure 30. timing diagram of fs cascade mode and frame-sync delayed (fsd) in cascade mode, the dsp should be in slave mode, it receives all frame-sync pulses from the master though 31 submit documentation feedback www.ti.com sclk fs din/dout (16 bit) msb lsb d15 d14 d1 d0 0 1 15 16 14 d15 16 sclks
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 the master's fs. the master fsd is output to the first slave and the first slave's fsd is output to the second slave device and so on. when the codecs are configured in cascade mode, mclk must be connected in star configuration to ensure that mclk can propagate simultaneously to all the codecs in the chain in less then 2 ps. figure 32 shows the cascade of 4 tlv320aic1xs in which the closest one to dsp is the master and the rest are slaves. the fsd output of each device is input to the fs terminal of the succeeding device. figure 30 shows the fsd timing sequence in the cascade. stand-alone slave in the stand-alone slave connection, the fs and sclk are input in which they need to be synchronized to each other and programmed according to the operating frequencies section of this data sheet. the fs and sclk input are not required to synchronize to the mclk input but must remain active at all times to assure continuous sampling in the data converter. fs is output for initial 132 mclk and it is kept low. dsp needs to keep fs low or high-impedance state for this period to avoid contention on fs. in addition, sclk must be running at all times when the device is put into reset when in slave mode. 32 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 asynchronous sampling (codecs in cascade are sampled at different sampling frequency) the 'aic1x smartdm supports a different sampling frequency between the codecs in cascade connecting to a single serial port. all codecs are required to have a common frame synch frequency. the fs signal is calculated using step 1. the desired sampling frequencies of the individual codecs are then calculated using bits d2-d0 of control register 3 as shown in step 2 and step 3. 1. fs = mclk ? (16 m n p) 2. fs = n1 fs1 (n1 = 1,2, 8 defined in the control register 3 of codec1) 3. fs = n2 fs2 (n2 = 1,2, 8 defined in the control register 3 of codec2) the dsp should transfer data at the common fs rate used by the serial interface. the task of decimating and interpolating the data suitably for each codec is left to the dsp. figure 31. timing diagram for fsd output figure 32. cascade connection (to dsp interface) 33 submit documentation feedback www.ti.com sclk fsd (output) din/dout (16 bit) msb lsb d15 d14 d2 d1 0 1 14 15 13 d0 fs 16 sclks mclkdin dout fs sclk mclkdin dout fs sclk mclkdin dout fs sclk slave 2 slave 1 slave 0 master mclk din dout fsd sclk fsd fsd fs clkout dx dr fsx fsr clkx clkr tms320c5x m/s m/s m/s m/s fsd iovdd 1 k w 100 mhz max iovdd
programming mode tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 a. note: slave 0 fsd should be pulled high for stand-alone-master or cascade configuration. fsd must be pulled low for stand-alone-slave configuration. figure 33. master-slave frame-sync timing in continuous data transfer mode in the programming mode, the fs signal starts the input/output data stream. each period of fs contains two frames as shown in figure 34 and figure 35 : data frame and control frame. the data frame contains data transmitted from the adc or to the dac. the control frame contains data to program the aic1xs control registers. the smartdm automatically sets the number of time slots per frame equal to 2 times the number of aic1x codecs in the interface. each time slot contains 16-bit data. the sclk is used to perform data transfer for the serial interface between the aic1x codecs and the dsp. the frequency of sclk varies depending on the selected mode of serial interface. in the stand alone-mode, there are 32 sclks (or two time slots) per sampling period. in the master-slave cascade mode, the number of slcks equals 32 x (number of codecs in the cascade). the digital output data from the adc is taken from dout. the digital input data for the dac is applied to din. the synchronization clock for the serial communication data and the frame-sync is taken from sclk. the frame-sync signal that starts the adc and dac data transfer interval is taken from fs. the smartdm also provides a turbo mode, in which the fs's frequency is always the device's sampling frequency, but sclk is running at a much higher speed. thus, there are more than 32 sclks per sampling period, in which the data frame and control frame occupy only the first 32 sclks from the falling edge of the frame-sync fs (see the digital interface section for more details). figure 34. standard operation/programming mode: stand-alone timing 34 submit documentation feedback www.ti.com master slave2 slave1 slave0 slave2 master master fs din/dout master fsd, slave 2 fs slave 2 fsd, slave 1 fs slave 1 fsd, slave 0 fs slave 0 fsd, (see note) sclk fs din dout 16-bit dac data register data w rite 16-bit adc data register data read slot number 0 slot number 1
continuous data transfer mode tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 35. standard operation/programming mode: master-slave cascade timing the continuous data transfer mode, selected by setting bit d6 of the control register 1 to 1, contains conversion data only. in continuous data transfer mode, the control frame is eliminated and the period of fs signal contains only the data frame in which the 16-bit data is transferred contiguously, with no inactivity between bits. the control frame can be reactivated by setting the lsb of din data to 1 if the data is in the 15+1 format. to return the programming mode in the 16-bit dac data format mode, write 0 in bit d6 of control register 1 using i 2 c or s 2 c, or do a hardware reset to come out of continuous data transfer mode. if continuous data transfer mode is used with the turbo mode, the codec should first be set in turbo mode before it is switched from the default programming mode to the continuous data transfer mode. figure 36. standard operation/continuous data transfer mode: stand-alone timing 35 submit documentation feedback www.ti.com sclk fs din/ dout 0 1 2 2n-1 2n-2 2n-3 master slave n-2 slave 1 slave 2 slave n-3 slave 0 master slave n-2 slave n-3 slave 2 slave 1 slave 0 data frame control frame (register r/w) 16 sclks per slot slot number note: n is the total number of aic12s in the cascade sclk fs din dout 16-bit dac data (sample 1) 16-bit adc data (sample 1) slot number 0 slot number 0 16-bit dac data (sample 2) 16-bit adc data (sample 2) (sample 3)(sample 3) data frame data frame
turbo operation (sclk) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 37. standard operation/continuous data transfer mode: master-slave cascade timing setting turbo = 1 (bit d7) in control register 2 enables the turbo mode that requires the following condition to be met: for master with sclk as output, m n > #devices mode where: m, n, and p are clock divider values defined in the control register 4. #device is the number of the device in cascade. mode is equal to 1 for continuous data transfer mode and 2 for programming mode. for slave, sclk is the input with max allowable speed of 25 mhz (no condition is required). the number of sclks per fs can be 3 (16 mode). the turbo operation is useful for applications that require more bandwidth for multitasking processing per sampling period. in the turbo mode (see figure 38 ), the fss frequency is always the device's sampling frequency but the sclk is running at much higher speed than that described in section 3.6.1. the output sclk frequency is equal to (mclk/p) in master mode and up to a maximum speed of 25 mhz for both master and slave aic1x. the data/control frame is still 16-sclk long and the fs is one-sclk pulse. if the 'aic1x is in slave mode, and the device is not set to turbo mode, only the first fs is used to synchronize the data transfer. the 'aic1x ignores all subsequent fs signals and utilizes an internally generated fs. however, if the 'aic1x is set to turbo mode while in slave mode, then the data transfer synchronizes on every fs signal. therefore, it is recommended that if the 'aic1x is set to slave mode, then turbo mode is used. also note that in turbo mode, it is recommended that sclk be a multiple of 32 x fs 36 submit documentation feedback www.ti.com sclk fs din/ dout 0 1 2 n-1 n-2 n-3 0 1 2 n-1 n-2 n-3 data frame / sample 1 note: n is the total number of aic12s in the cascade 16 sclks per t ime slot data frame / sample 2 slot number master slave n-2 slave 1 slave 2 slave n-3 slave 0 master slave n-2 slave n-3 slave 2 slave 1 slave 0
control register programming tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 38. turbo programming mode (sclk is not drawn to scale) the tlv320aic1x contains six control registers that are used to program available modes of operation. all register programming occurs during the control frame through din. new configuration takes effect after a delay of one frame sync fs except the software reset, which happens after 6 mclks from the falling edge of the next frame sync fs. the tlv320aic1x is defaulted to the programming mode upon power up. set bit 6 in control register 1 to switch to continuous data transfer mode. if the 15+1 data format of din has been selected, the lsb of the din to 1 to switch from continuous data transfer mode to programming set mode. otherwise, either the device needs to be reset or the host port writes 0 to bit d6 of control register 1 during the continuous data transfer mode to switch back to the programming mode. 37 submit documentation feedback www.ti.com ... ... ... 15 14 1 0 14 15 1 0 14 15 1 0 one sclk data frame control frame hi-z fs t urbo sclk fs din / dout din / dout sampling period data frame control frame data frame control frame data frame hi-z stand-alone case: cascade case (master + 4 slaves): ... ... 15 14 1 0 14 15 1 0 one sclk data frame hi-z fs din / dout data frame stand-alone case:cascade case (master + 4 slaves): t urbo sclk fs din / dout sampling period data frame hi-z data frame turbo programming modeturbo continuous da t a transfer mode sampling period sampling period control frame hi-z ... 14 15 1 0 hi-z t urbo sclk t urbo sclk ? ????????????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? ?????????????????????????????????????????????????
data frame format control frame format (programming mode) broadcast register write tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 39. data frame format during the control frame, the dsp sends 16-bit words to the smartdm through din to read or write control registers shown in table 4 . the upper byte (bits d15-d8) of the 16-bit control-frame word defines the read/write command. bits d15-d13 define the control register address with register content occupied the lower byte d7-d0. bit d12 is set to 0 for a write or to 1 for a read. bit d11 in the write command is used to perform the broadcast mode. during a register write, the register content is located in the lower byte of din. during a register read, the register content is output in the lower byte of dout in the same control frame, whereas the lower byte of din is ignored. broadcast operation is very useful for a cascading system of smartdm dsp codecs in which all register programming can be completed in one control frame. during the control frame and in any register-write time slot, if the broadcast bit (d11) is set to 1, the register content of that time slot is written into the specified register of all devices in cascade (see figure 40 ). this reduces the dsp's overhead of doing multiple writes to program same data into cascaded devices. figure 40. control frame data format 38 submit documentation feedback www.ti.com d0 d15 - d1 a/d and d/a data d15 - d0d15 - d0 a/d and d/a data d15 - d0 din (15+1) bit mode (continuous data t ransfer mode only) dout (16 bit a/d data) din 16 bit mode dout 16 bit mode control framerequest 1 1 1 d11 0 1 1 1 0 1 din (read) din (w rite) don't care d15 d15 d13 d14 d13 d14 0 d9 d10 d11 dout (read) d15 d13 d14 d12 data to be w ritten into register d7 - d0d7 - d0 d7 - d0 r/w broadcast registeraddress registeraddress smartdm device address register content
register map tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 a. note: in this example, the broadcast operation (d11 = 1) is used to program the four control registers of reg.1, reg.2, reg.4, and reg.6 in all 4 dsp codecs (master, slave2, slave1, and slave0) shown in figure 33 . these registers are programmed during the same frame. figure 41. control frame data format bits d15 through d13 represent the control register address that is written with data carried in d7 through d0. bit d12 determines a read or a write cycle to the addressed register. when d12 = 0, a write cycle is selected. when d12 = 1, a read cycle is selected. bit d11 controls the broadcast mode as described above, in which the broadcast mode is enabled if d11 is set to 1. always write 1s to the bits d10 through d8. table 3 shows the register map. table 3. register map d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register address rw bc 1 1 1 control register content table 4. register addresses register no. d15 d14 d13 register name 0 0 0 0 no operation 1 0 0 1 control 1 2 0 1 0 control 2 3 0 1 1 control 3 4 1 0 0 control 4 5 1 0 1 control 5 6 1 1 0 control 6 39 submit documentation feedback www.ti.com master fs din master slave2 slave1 slave0 master slave2 slave1 slave0 master slave2 slave1 slave0 slave0 write command reg addr (d15-d13) r/w (d12) broadcast (d1 1) d10-d8 001(1) 01 111 010(2) 01 111 100(4) 01 111 110(6) 01 111 data frame control frame t ime slot
control register content description control register 1 (1) control register 2 (1) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 d7 d6 d5 d4 d3 d2 d1 d0 adovf cx iir daovf biasv alb dlb dac16 r r/w r/w r r/w r/w r/w r/w (1) note: r = read, w = write control register 1 bit summary reset bit name function value d7 adovf 0 adc over flow. this bit indicates whether the adc is overflow. adovf = 0 no overflow. adovf = 1 a/d is overflow. d6 cx 0 continuous data transfer mode. this bit selects between programming mode and continuous data transfer mode. cx = 0 programming mode. cx = 1 continuous data transfer mode. d5 iir 0 iir filter. this bit selects between fir and iir for decimation/interpolation low-pass filter. iir = 0 fir filter is selected. iir = 1 iir filter is selected. d4 daovf 0 dac over flow. this bit indicates whether the dac is overflow daovf = 0 no overflow. daovf = 1 dac is overflow d3 biasv 0 bias voltage. this bit selects the output voltage for bias pin biasv = 0 bias pin = 2.35 v biasv = 1 bias pin = 1.35 v d2 alb 0 analog loop back dlb = 0 analog loopback disabled dlb = 1 analog loopback enabled d1 dlb 0 digital loop back dlb = 0 digital loopback disabled dlb = 1 digital loopback enabled d0 dac16 0 dac 16-bit data format. this bit applies to the continuous data transfer mode only to enable the 16-bit data format for dac input. dac16 = 0 dac input data length is 15 bits. writing a 1 to the lsb of the dac input to switch from continuous data transfer mode to programming mode. dac16 = 1 dac input data length is 16 bit. d7 d6 d5 d4 d3 d2 d1 d0 turbo difbp i 2 c6 i 2 c5 i 2 c4 gpo hpc r/w r/w r/w r/w r/w r/w r/w r/w (1) note: r = read, w = write control register 2 bit summary reset bit name function value d7 turbo 0 turbo mode. this bit is used to set the sclk rate. turbo = 0 sclk = (16 fs #device mode) turbo = 1 sclk = mclk/p (p is determined in register 4) (mclk/p is valid only for master mode) d6 difbp 0 decimation/interpolation filter bypass. this bit is used to bypass both decimation and interpolation filters. difbp = 0 decimation/interpolation filters are operated. difbp = 1 decimation/interpolation filters are bypassed. d5-d3 i 2 cx 100 i 2 c device address. these three bits are programmable to define three msbs of the i 2 c device address (reset value is 100). these three bits are combined with the 4-bit smartdm device address to form 7-bit i 2 c device address. 40 submit documentation feedback www.ti.com
control register 3 (1) control register 4 (1) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 control register 2 bit summary (continued) reset bit name function value d2 gpo 0 general-purpose output d1-d0 hpc 00 host port control bits. write the following values into d1-d0 to select the appropriate configuration for two pins sda and scl. the sda pin is set to be equal to d2 if d1-d0 = 10. d1-d0 0 0 sda and scl pins are used for i 2 c interface 0 1 sda and scl pins are used for s 2 c interface 1 0 sda pin = d2, input going into scl pin is output to dout 1 1 sda pin = control frame flag. d7 d6 d5 d4 d3 d2 d1 d0 pwdn swrs osr-option asrf r/w r/w r/w r/w (1) note: r = read, w = write control register 3 bit summary reset bit name function value d7-d6 pwdn 00 power down, pwdn = 00 no power down pwdn = 01 power-down a/d pwdn = 10 power-down d/a pwdn = 11 software power down the entire device d5 swrs 0 software reset. set this bit to 1 to reset the device. d4-d3 osr 00 osr option. option d4 - d3 = x1 osr for dac channel is 512 ( max fs = 8 ksps) d4 - d3 = 10 osr for dac channel is 256 ( max fs = 16 ksps) d4 - d3 = 00 osr for dac channel is 128 (max fs = 26 ksps) d2-d0 asrf 001 asynchronous sampling rate factor. these three bits define the ratio n between fs frequency and the desired sampling frequency fs (applied only if different sampling rate between codec1 and codec2 is desired) asrf = 001 n = fs/fs = 1 asrf = 010 n = fs/fs = 2 asrf = 011 n = fs/fs = 3 asrf = 100 n = fs/fs = 4 asrf = 101 n = fs/fs = 5 asrf = 110 n = fs/fs = 6 asrf = 111 n = fs/fs = 7 asrf = 000 n = fs/fs = 8 d7 d6 d5 d4 d3 d2 d1 d0 fsdiv mnp r/w r/w r/w r/w r/w r/w r/w r/w (1) note: r = read, w = write control register 4 bit summary reset bit name function value d7 fsdiv 0 frame sync division factor fsdiv = 0 to write value of p to bits d2-d0 and value of n to bits d6-d3 fsdiv = 1 to write value of m to bits d6-d0 41 submit documentation feedback www.ti.com
control register 5a (5) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 control register 4 bit summary (continued) reset bit name function value d6-d0 mnp (1) (2) ? divider values of m, n, and p to be used in junction with the fsdiv bit for calculation of fs frequency (3) (4) according to the formula fs = mclk / (16 x m x n x p) m = 1,2, ? ,128 determined by d6-d0 with fsdiv = 1 d7-d0 = 10000000 m = 128 d7-d0 = 10000001 m = 1 to d7-d0 = 11111111 m = 127 n = 1,2, ? ,16 determined by d6-d3 with fsdiv = 0 d7-d0 = 00000xxx n = 16 d7-d0 = 00001xxx n = 1 to d7-d0 = 01111xxx n = 15 p = 1,2, ? ,8 determined by d2-d0 with fsdiv = 0 d7-d0 = 0xxxx000 p = 8 d7-d0 = 0xxxx001 p = 1 to d7-d0 = 0xxxx111 p = 7 (1) it takes 2 sampling periods to update new values of m, n, and p. (2) in register read operation, first read receives n and p values and second read receives m value. (3) m(default) = 16, n(default) = 6, p(default) = 8 (4) if p = 8, the device enters the coarse sampling mode as described in operating frequencies section. d7 d6 d5 d4 d3 d2 d1 d0 0 0 adgain r/w r/w r/w r/w r/w r/w r/w r/w (5) note: r = read, w = write control register 5a bit summary (1) (2) reset bit name function value d7-d6 control 00 adc programmable gain amplifier register 5a d5-d0 adgain 101010 a/d converter gain (see table 5 ) (1) in register read operation, first read receives adc gain value, second read receives dac gain value, third read receives register 5c contents, and fourth read receives register 5d contents. (2) pga default value = 101010 b (0db) for both adc and dac. table 5. a/d pga gain d7 d6 d5 d4 d3 d2 d1 d0 description 0 0 1 1 1 1 1 1 adc input pga gain = mute 0 0 1 1 1 1 1 0 adc input pga gain = 20 db 0 0 1 1 1 1 0 1 adc input pga gain = 19 db 0 0 1 1 1 1 0 0 adc input pga gain = 18 db 0 0 1 1 1 0 1 1 adc input pga gain = 17 db 0 0 1 1 1 0 1 0 adc input pga gain = 16 db 0 0 1 1 1 0 0 1 adc input pga gain = 15 db 0 0 1 1 1 0 0 0 adc input pga gain = 14 db 0 0 1 1 0 1 1 1 adc input pga gain = 13 db 0 0 1 1 0 1 1 0 adc input pga gain = 12 db 0 0 1 1 0 1 0 1 adc input pga gain = 11 db 0 0 1 1 0 1 0 0 adc input pga gain = 10 db 0 0 1 1 0 0 1 1 adc input pga gain = 9 db 42 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 table 5. a/d pga gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 description 0 0 1 1 0 0 1 0 adc input pga gain = 8 db 0 0 1 1 0 0 0 1 adc input pga gain = 7 db 0 0 1 1 0 0 0 0 adc input pga gain = 6 db 0 0 1 0 1 1 1 1 adc input pga gain = 5 db 0 0 1 0 1 1 1 0 adc input pga gain = 4 db 0 0 1 0 1 1 0 1 adc input pga gain = 3 db 0 0 1 0 1 1 0 0 adc input pga gain = 2 db 0 0 1 0 1 0 1 1 adc input pga gain = 1 db 0 0 1 0 1 0 1 0 adc input pga gain = 0 db 0 0 1 0 1 0 0 1 adc input pga gain = -1 db 0 0 1 0 1 0 0 0 adc input pga gain = -2 db 0 0 1 0 0 1 1 1 adc input pga gain = -3 db 0 0 1 0 0 1 1 0 adc input pga gain = -4 db 0 0 1 0 0 1 0 1 adc input pga gain = -5 db 0 0 1 0 0 1 0 0 adc input pga gain = -6 db 0 0 1 0 0 0 1 1 adc input pga gain = -7 db 0 0 1 0 0 0 1 0 adc input pga gain = -8 db 0 0 1 0 0 0 0 1 adc input pga gain = -9 db 0 0 1 0 0 0 0 0 adc input pga gain = -10 db 0 0 0 1 1 1 1 1 adc input pga gain = -11 db 0 0 0 1 1 1 1 0 adc input pga gain = -12 db 0 0 0 1 1 1 0 1 adc input pga gain = -13 db 0 0 0 1 1 1 0 0 adc input pga gain = -14 db 0 0 0 1 1 0 1 1 adc input pga gain = -15 db 0 0 0 1 1 0 1 0 adc input pga gain = -16 db 0 0 0 1 1 0 0 1 adc input pga gain = -17 db 0 0 0 1 1 0 0 0 adc input pga gain = -18 db 0 0 0 1 0 1 1 1 adc input pga gain = -19 db 0 0 0 1 0 1 1 0 adc input pga gain = -20 db 0 0 0 1 0 1 0 1 adc input pga gain = -21 db 0 0 0 1 0 1 0 0 adc input pga gain = -22 db 0 0 0 1 0 0 1 1 adc input pga gain = -23db 0 0 0 1 0 0 1 0 adc input pga gain = -24 db 0 0 0 1 0 0 0 1 adc input pga gain = -25 db 0 0 0 1 0 0 0 0 adc input pga gain = -26 db 0 0 0 0 1 1 1 1 adc input pga gain = -27 db 0 0 0 0 1 1 1 0 adc input pga gain = -28 db 0 0 0 0 1 1 0 1 adc input pga gain = -29 db 0 0 0 0 1 1 0 0 adc input pga gain = -30 db 0 0 0 0 1 0 1 1 adc input pga gain = -31 db 0 0 0 0 1 0 1 0 adc input pga gain = -32 db 0 0 0 0 1 0 0 1 adc input pga gain = -33 db 0 0 0 0 1 0 0 0 adc input pga gain = -34 db 0 0 0 0 0 1 1 1 adc input pga gain = -35 db 0 0 0 0 0 1 1 0 adc input pga gain = -36 db 0 0 0 0 0 1 0 1 adc input pga gain = -37 db 0 0 0 0 0 1 0 0 adc input pga gain = -38 db 43 submit documentation feedback www.ti.com
control register 5b (1) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 table 5. a/d pga gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 description 0 0 0 0 0 0 1 1 adc input pga gain = -39 db 0 0 0 0 0 0 1 0 adc input pga gain = -40 db 0 0 0 0 0 0 0 1 adc input pga gain = -41 db 0 0 0 0 0 0 0 0 adc input pga gain = -42 db d7 d6 d5 d4 d3 d2 d1 d0 0 1 dagain r/w r/w r/w r/w r/w r/w r/w r/w (1) note: r = read, w = write control register 5b bit summary (1) (2) reset bit name function value d7-d6 control na register 5b d5-d0 dagain 101010 d/a converter gain (see table 6 ) (1) in register read operation, first read receives adc gain value, second read receives dac gain value, third receives register 5c and fourth receives register 5d. (2) pga default value = 101010 b (0db) for both adc and dac. table 6. d/a pga gain d7 d6 d5 d4 d3 d2 d1 d0 description 0 1 1 1 1 1 1 1 dac input pga gain = mute 0 1 1 1 1 1 1 0 dac input pga gain = 20 db 0 1 1 1 1 1 0 1 dac input pga gain = 19 db 0 1 1 1 1 1 0 0 dac input pga gain = 18 db 0 1 1 1 1 0 1 1 dac input pga gain = 17 db 0 1 1 1 1 0 1 0 dac input pga gain = 16 db 0 1 1 1 1 0 0 1 dac input pga gain = 15 db 0 1 1 1 1 0 0 0 dac input pga gain = 14 db 0 1 1 1 0 1 1 1 dac input pga gain = 13 db 0 1 1 1 0 1 1 0 dac input pga gain = 12 db 0 1 1 1 0 1 0 1 dac input pga gain = 11 db 0 1 1 1 0 1 0 0 dac input pga gain = 10 db 0 1 1 1 0 0 1 1 dac input pga gain = 9 db 0 1 1 1 0 0 1 0 dac input pga gain = 8 db 0 1 1 1 0 0 0 1 dac input pga gain = 7 db 0 1 1 1 0 0 0 0 dac input pga gain = 6 db 0 1 1 0 1 1 1 1 dac input pga gain = 5 db 0 1 1 0 1 1 1 0 dac input pga gain = 4 db 0 1 1 0 1 1 0 1 dac input pga gain = 3 db 0 1 1 0 1 1 0 0 dac input pga gain = 2 db 0 1 1 0 1 0 1 1 dac input pga gain = 1 db 0 1 1 0 1 0 1 0 dac input pga gain = 0 db 0 1 1 0 1 0 0 1 dac input pga gain = -1 db 0 1 1 0 1 0 0 0 dac input pga gain = -2 db 0 1 1 0 0 1 1 1 dac input pga gain = -3 db 44 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 table 6. d/a pga gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 description 0 1 1 0 0 1 1 0 dac input pga gain = -4 db 0 1 1 0 0 1 0 1 dac input pga gain = -5 db 0 1 1 0 0 1 0 0 dac input pga gain = -6 db 0 1 1 0 0 0 1 1 dac input pga gain = -7 db 0 1 1 0 0 0 1 0 dac input pga gain = -8 db 0 1 1 0 0 0 0 1 dac input pga gain = -9 db 0 1 1 0 0 0 0 0 dac input pga gain = -10 db 0 1 0 1 1 1 1 1 dac input pga gain = -11 db 0 1 0 1 1 1 1 0 dac input pga gain = -12 db 0 1 0 1 1 1 0 1 dac input pga gain = -13 db 0 1 0 1 1 1 0 0 dac input pga gain = -14 db 0 1 0 1 1 0 1 1 dac input pga gain = -15 db 0 1 0 1 1 0 1 0 dac input pga gain = -16 db 0 1 0 1 1 0 0 1 dac input pga gain = -17 db 0 1 0 1 1 0 0 0 dac input pga gain = -18 db 0 1 0 1 0 1 1 1 dac input pga gain = -19 db 0 1 0 1 0 1 1 0 dac input pga gain = -20 db 0 1 0 1 0 1 0 1 dac input pga gain = -21 db 0 1 0 1 0 1 0 0 dac input pga gain = -22 db 0 1 0 1 0 0 1 1 dac input pga gain = -23db 0 1 0 1 0 0 1 0 dac input pga gain = -24 db 0 1 0 1 0 0 0 1 dac input pga gain = -25 db 0 1 0 1 0 0 0 0 dac input pga gain = -26 db 0 1 0 0 1 1 1 1 dac input pga gain = -27 db 0 1 0 0 1 1 1 0 dac input pga gain = -28 db 0 1 0 0 1 1 0 1 dac input pga gain = -29 db 0 1 0 0 1 1 0 0 dac input pga gain = -30 db 0 1 0 0 1 0 1 1 dac input pga gain = -31 db 0 1 0 0 1 0 1 0 dac input pga gain = -32 db 0 1 0 0 1 0 0 1 dac input pga gain = -33 db 0 1 0 0 1 0 0 0 dac input pga gain = -34 db 0 1 0 0 0 1 1 1 dac input pga gain = -35 db 0 1 0 0 0 1 1 0 dac input pga gain = -36 db 0 1 0 0 0 1 0 1 dac input pga gain = -37 db 0 1 0 0 0 1 0 0 dac input pga gain = -38 db 0 1 0 0 0 0 1 1 dac input pga gain = -39 db 0 1 0 0 0 0 1 0 dac input pga gain = -40 db 0 1 0 0 0 0 0 1 dac input pga gain = -41 db 0 1 0 0 0 0 0 0 dac input pga gain = -42 db 45 submit documentation feedback www.ti.com
control register 5c (1) control register 5d (1) tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 d7 d6 d5 d4 d3 d2 d1 d0 1 0 dstg reserved inbg r/w r/w r/w r/w r/w r r/w r/w (1) note: r = read, w = write digital sidetone gain d5 d4 d3 dstg 1 1 1 digital sidetone gain = mute (default) 1 1 0 digital sidetone gain = -21 db 1 0 1 digital sidetone gain = -18 db 1 0 0 digital sidetone gain = -15 db 0 1 1 digital sidetone gain = -12 db 0 1 0 digital sidetone gain = -9 db 0 0 1 digital sidetone gain = -6 db 0 0 0 digital sidetone gain = -3 db input buffer gain d1 d0 inbg 1 1 input buffer gain = 24 db 1 0 input buffer gain = 12 db 0 1 input buffer gain = 6 db 0 0 input buffer gain = 0 db (default) d7 d6 d5 d4 d3 d2 d1 d0 1 1 reserved chip version-id r/w r/w r r r r r r (1) note: r = read, w = write 46 submit documentation feedback www.ti.com
control register 6 tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 d7 d6 d5 d4 d3 d2 d1 d0 psdo mute2 mute3 odrct ainsel reserved r/w r/w r/w r/w r/w r/w r/w r/w control register 6 bit summary reset bit name function value d7 psdo 0 programmable single-ended/differential output. this bit configures the two pins of outp2 and outp3 as single-ended or differential output. if the outp2 and outp3 are single-ended, the outmv is the virtual ground. if the outp2 and outp3 are differential, the outmv is the common inverting output. psdo = 0 outp2 and outp3 are two differential output (1) psdo = 1 outp2 and outp3 are two single-ended output (2) note: (1) the outp2 and outp3 pins are the noninverting output with common inverting output. the outmv is their common inverting output (2) the virtual ground pin outmv and the common mode of outp2 and outp3 are the same at 1.35 v. d6 mute2 0 analog output2 mute control. this bit sets mute for outp2 mute2 = 0 outp2 is not mute mute2 = 1 outp2 is mute d5 mute3 0 analog output2 mute control. this bit sets mute for outp3 mute3 = 0 outp3 is not mute mute3 = 1 outp3 is mute d4-d3 odrct 00 analog driver control. these two bits enable/disable the analog output drivers for the analog output pins of outp2 and outp3 odrct =00 outp3 = off, outp2 = off odrct =01 outp3 = off, outp2 = on odrct =10 outp3 = on, outp2 = off odrct =11 outp3 = on, outp2 = on d2-d1 ainsel 00 analog input select. these bits select the analog input for the adc ainsel = 00 the analog input is inp/m1 ainsel = 01 the analog input is micin self-biased at 1.35 v ainsel =10 the analog input is micin with external common mode ainsel = 11 the analog input is inp/m2 note: for ainsel = 10, the external common mode is connected to inm1 via an ac-coupled capacitor. d0 reserved 47 submit documentation feedback www.ti.com
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 42. single-ended microphone input (internal common mode) 48 submit documentation feedback www.ti.com bias 0.1 m f 0.1 m f 0.1 m f micin inp1inm1 inp2 inm2 0.1 m f microphone 0.1 m f outp1 outm1 600 w outp2outmv outp3 avdd 0.1 m f avss 3.3 v analog supply analog gnd 0.1 m f 3.3 v analog supply analog gnd drvdd drvss iovdd 1 k w 1 k w iovdd m/s fsd fs din dout sclk from dsp orother clock source from dsp from dsp mclk reset pwrdn sda iovdd 1 k w scl 0.01 m f 0.1 m f 1 m f 0.01 m f 0.1 m f 1 m f dvdd dvss iovdd iovss t o 1.8 v digital supply t o digital gnd t o 3.3 v digital supply t o digital gnd tlv320aic12 fskfsr dx dr clkr clkx tlv320c5x i 2 c master s 2 c
tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 figure 43. pseudo-differential microphone input (external common mode) 49 submit documentation feedback www.ti.com bias 0.1 m f 0.1 m f 0.1 m f micin inp1inm1 inp2 inm2 0.1 m f microphone 0.1 m f 1 m f outp1 1 m f outm1 600 w 600 w outp2outmv outp3 avdd 0.1 m f avss 3.3 v analog supply analog gnd 0.1 m f 3.3 v analog supply analog gnd drvdd drvss iovdd 1 k w 1 k w iovdd m/s fsd fs din dout sclk from dsp orother clock source from dsp from dsp mclk reset pwrdn sda iovdd 1 k w from dsp scl 0.01 m f 0.1 m f 1 m f 0.01 m f 0.1 m f 1 m f dvdd dvss iovdd iovss t o 1.8 v digital supply t o digital gnd t o 3.3 v digital supply t o digital gnd tlv320aic12 fskfsr dx dr clkr clkx tlv320c5x
layout and grounding guidelines for tlv320aic1x tlv320aic12, tlv320aic13 tlv320aic14, tlv320aic15 tlv320aic12k, tlv320aic14k slws115e ? october 2001 ? revised january 2007 tlv320aic1x has an in-built analog antialias filter, which provides rejection to external noise at high frequencies that may couple into the device. digital filters with high out-of-band attenuation also reject the external noise. if the differential inputs are used for the adc channel, then the noise in the common-mode signal is also rejected by the high cmrr of tlv320aic1x. using external common-mode for microphone inputs also helps rejecting the external noise. however to extract the best performance from tlv320aic1x, care must be taken in board design and layout to avoid coupling of external noise into the device. tlv320aic1x supports clock frequencies as high as 100 mhz. to avoid coupling of fast switching digital signals to analog signals, the digital and analog sections should be separated on the board. in tlv320aic1x the digital and analog pins are kept separated to aid such a board layout. a separate analog ground plane should be used for the analog section of the board. the analog and digital ground planes should be shorted at only one place as close to tlv320aic1x as possible. no digital trace should run under tlv320aic1x to avoid coupling of external digital noise into the device. it is suggested to have the analog ground plane running below the tlv320aic1x. the power-supplies should be decoupled close to the supply pins, preferably, with a 0.1 f-ceramic capacitor and a 10-f tantalum capacitor following. the ground pin should be connected to the ground plane as close as possible to the tlv320aic1x, so as to minimize any inductance in the path. since the mclk is expected to be a high frequency signal, it is advisable to shield it with digital ground. for best performance of adc in differential input mode, the differential signals should be routed close to each other in similar fashion, so that the noise coupling on both the signals is same and can be rejected by the device. extra care has to be taken for the speaker driver outputs, as any trace resistance can cause a reduction in the maximum swing that can be seen at the speaker. for devices in the rhb package, connect the device thermal pad to drvss. 50 submit documentation feedback www.ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tlv32012kidbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv32014kidbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12cdbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12cdbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12cdbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12cdbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12idbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12idbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12idbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12idbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12kidbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12kidbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12kidbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12kirhbr active qfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic12kirhbt active qfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic13cdbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic13cdbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic13cdbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic13cdbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLV320AIC13IDBT active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLV320AIC13IDBTg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLV320AIC13IDBTr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLV320AIC13IDBTrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14cdbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14cdbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year package option addendum www.ti.com 16-mar-2007 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tlv320aic14cdbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14cdbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14idbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14idbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14idbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14idbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14kidbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14kidbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic14kidbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15cdbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15cdbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15cdbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15cdbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15idbt active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15idbtg4 active sm8 dbt 30 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15idbtr active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic15idbtrg4 active sm8 dbt 30 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20cpfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20cpfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20cpfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20cpfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20ipfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20ipfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20ipfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic20ipfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21cpfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year package option addendum www.ti.com 16-mar-2007 addendum-page 2
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tlv320aic21cpfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21cpfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21cpfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21ipfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21ipfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21ipfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic21ipfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24cpfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24cpfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24cpfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24cpfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24ipfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24ipfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24ipfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic24ipfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25cpfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25cpfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25cpfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25cpfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25ipfb active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25ipfbg4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25ipfbr active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlv320aic25ipfbrg4 active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlvaic12kirhbrg4 active qfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tlvaic12kirhbtg4 active qfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: package option addendum www.ti.com 16-mar-2007 addendum-page 3
active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-mar-2007 addendum-page 4
tape and reel information package materials information www.ti.com 17-may-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv320aic12kirhbr rhb 32 mla 330 12 5.3 5.3 1.5 8 12 pkgorn t2tr-ms p tlv320aic12kirhbt rhb 32 mla 180 12 5.3 5.3 1.5 8 12 pkgorn t2tr-ms p tlv320aic20cpfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic20ipfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic21cpfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic21ipfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic24cpfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic24ipfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic25cpfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tlv320aic25ipfbr pfb 48 tai 330 16 9.6 9.6 1.5 12 16 none tape and reel box information device package pins site length (mm) width (mm) height (mm) tlv320aic12kirhbr rhb 32 mla 346.0 346.0 29.0 tlv320aic12kirhbt rhb 32 mla 190.0 212.7 31.75 tlv320aic20cpfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic20ipfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic21cpfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic21ipfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic24cpfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic24ipfbr pfb 48 tai 341.0 159.0 123.5 package materials information www.ti.com 17-may-2007 pack materials-page 2
device package pins site length (mm) width (mm) height (mm) tlv320aic25cpfbr pfb 48 tai 341.0 159.0 123.5 tlv320aic25ipfbr pfb 48 tai 341.0 159.0 123.5 package materials information www.ti.com 17-may-2007 pack materials-page 3

mechanical data mtqf019a january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 pfb (s-pqfp-g48) plastic quad flatpack 4073176 / b 10/96 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony low power www.ti.com/lpw video & imaging www.ti.com/video wireless wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2007, texas instruments incorporated

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