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| ? symbios? SYM53C140 ultra2 scsi bus expander order number s14006 technical manual june 1999 version 1.0
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000087-00, first edition (june 1999) this document describes version 1.0 of lsi logic corporations SYM53C140 ultra2 scsi bus expander and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. the products in this manual are not intended for use in life-support appliances, devices, or systems. use of these products in such applications without the written consent of the appropriate lsi logic corporation of?cer is prohibited. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1998, 1999 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, lvdlink, symbios, and tolerant are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. sr preface iii preface this manual provides a description and electrical characteristics of the SYM53C140 ultra2 scsi bus expander chip that supports all combinations of single-ended, low-voltage differential, and high- voltage differential scsi bus conversions. audience this manual assumes some prior knowledge of current and proposed scsi standards. for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 iv preface ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic (storage components) electronic bulletin board (719) 533-7235 scsi electronic bulletin board (719) 533-7950 lsi logic world wide web home page www.lsil.com lsi logic internet anonymous ftp site ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi organization this document has the following chapters and appendixes: chapter 1, introduction , contains the general information about the SYM53C140 product. chapter 2, functional descriptions , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. chapter 3, speci?cations , contains the pin diagram, signal descriptions, electrical characteristics, ac timing diagrams, and mechanical drawing of the SYM53C140. appendix a, wiring diagrams , contain wiring diagrams that show typical SYM53C140 usage. appendix b, glossary , contains commonly used terms and their de?nitions. revision record page no. date version remarks all 5/98 0.5 first draft of complete data manual. all 6/99 1.0 misc. changes / corrections for product introduction. contents v contents chapter 1 introduction 1.1 general description 1-1 1.1.1 applications 1-2 1.1.2 features 1-4 1.1.3 speci?cations 1-5 1.2 bene?ts of lvdlink 1-6 chapter 2 functional descriptions 2.1 interface signal descriptions 2-1 2.1.1 scsi a side and b side control blocks 2-2 2.1.2 retiming logic 2-4 2.1.3 state machine control 2-4 2.1.4 precision delay control 2-4 2.1.5 diffsens receiver 2-5 2.1.6 dynamic transmission mode changes 2-5 2.1.7 scsi signal descriptions 2-6 2.1.8 scsi termination 2-13 chapter 3 speci?cations 3.1 signal descriptions 3-1 3.2 electrical characteristics 3-7 3.2.1 dc characteristics 3-7 3.2.2 tolerant technology electrical characteristics 3-11 3.2.3 ac characteristics 3-15 3.2.4 scsi interface timing 3-15 3.3 mechanical drawings 3-17 3.3.1 SYM53C140 160-pin pqfp mechanical drawing 3-18 vi contents appendix a wiring diagrams a.1 SYM53C140 wiring diagrams a-1 appendix b glossary index customer feedback figures 1.1 SYM53C140 scsi bus modes 1-1 1.2 SYM53C140 server clustering 1-3 1.3 SYM53C140 scsi bus device 1-4 2.1 SYM53C140 block diagram 2-2 2.2 SYM53C140 signal grouping 2-6 2.3 scsi termination 2-14 3.1 SYM53C140 160-pin pqfp pin diagram 3-2 3.2 SYM53C140 functional signal grouping 3-3 3.3 lvd driver 3-8 3.4 lvd receiver 3-9 3.5 external reset circuit 3-11 3.6 rise and fall time test conditions 3-13 3.7 scsi input filtering 3-13 3.8 hysteresis of scsi receivers 3-13 3.9 input current as a function of input voltage 3-14 3.10 output current as a function of output voltage 3-14 3.11 clock timing 3-15 3.12 input/output timing 3-16 3.13 SYM53C140 160 pin pqfp (pf) mechanical drawing 3-18 a.1 SYM53C140 wiring diagram 1 of 4 a-2 tables 1.1 types of operation 1-2 1.2 scsi bus distance requirements 1-3 1.3 transmission mode distance requirements 1-4 contents vii 2.1 diffsens voltage levels 2-5 2.2 direction control signal polarities 2-11 2.3 hvd_mode control signal polarity 2-11 2.4 reset/ control signal polarity 2-12 2.5 mode sense control voltage levels 2-12 2.6 ws_enable signal polarity 2-13 2.7 xfer_active signal polarity 2-13 3.1 scsi a side interface pins 3-4 3.2 scsi b side interface pins 3-5 3.3 chip interface control pins 3-5 3.4 power and ground pins 3-6 3.5 absolute maximum stress ratings 3-7 3.6 operating conditions 3-8 3.7 lvd driver scsi signals b_sd[15:0] ,b_sdp[1:0] , b_scd ,b_sio ,b_smsg ,b_sreq ,b_sack , b_sbsy ,b_satn ,b_ssel ,b_srst 3-8 3.8 lvd receiver scsi signals b_sd[15:0] ,b_sdp[1:0] , b_scd ,b_sio ,b_smsg ,b_sreq ,b_sack , b_sbsy ,b_satn ,b_ssel ,b_srst 3-9 3.9 diffsens scsi signal 3-9 3.10 input capacitance 3-9 3.11 bidirectional scsi signals a_sd[15:0]/, a_sdp[1:0]/, a_sreq/, a_sack/, b_sd[15:0] ,b_sdp[1:0] , b_sreq ,b_sack 3-10 3.12 bidirectional scsi signals a_scd/, a_sio/, a_smsg/, a_sbsy/, a_satn/, a_ssel/, a_srst/, b_scd , b_sio ,b_smsg ,b_sbsy ,b_satn ,b_ssel ,b_srst 3-10 3.13 input control signals clock, reset/, ws_enable 3-10 3.14 output control signals bsy_led, xfer_active 3-11 3.15 tolerant technology electrical characteristics 3-11 3.16 clock timing 3-15 3.17 input timing 3-15 3.18 output timing 3-16 viii contents symbios SYM53C140 ultra2 scsi bus expander 1-1 chapter 1 introduction 1.1 general description the SYM53C140 ultra2 scsi bus expander is a single chip solution allowing the extension of scsi device connectivity and/or cable length limits. a scsi bus expander couples bus segments together without any impact to the scsi protocol, software, or ?rmware. the SYM53C140 ultra2 scsi bus expander connects single-ended (se) ultra, low- voltage differential (lvd) ultra2 or high-voltage differential (hvd) peripherals together in any combination. the SYM53C140 is capable of supporting any combination of bus mode se, hvd, or lvd on either the a or b side port. this provides the system designer with maximum ?exibility in designing scsi backplanes to accommodate any scsi bus mode. figure 1.1 SYM53C140 scsi bus modes figure 1.1 shows the three scsi bus modes available on the a or b side. lvdlink ? transceivers provide the multimode lvd, se, or hvd capability. the SYM53C140 operates either as a expander or converter. in both scsi bus expander and converter modes, cable segments are electrically isolated from each other. this feature maintains the signal integrity of each cable segment. SYM53C140 scsi expander 160 pqfp a-side b-side lv d hvd (*) se lv d hvd (*) se 1-2 introduction as shown in table 1.1, the SYM53C140 operates in all modes: single- ended, low-voltage differential, and high-voltage differential. the SYM53C140 provides additional control capability through the pin level electrical isolation mode. this feature permits logical disconnection of both the a side bus and the b side bus without disrupting scsi transfers currently in progress. for example, devices on the logically disconnected b side can be swapped out while the a side bus remains active. the SYM53C140 is based on bus expander technology resulting in some signal ?ltering and re-timing to maintain signal skew budgets. the SYM53C140 is independent of software. 1.1.1 applications server clustering environments expanders creating distinct scsi cable segments which are electrically isolated from each other table 1.1 types of operation signal type mode speed lvd to lvd repeater ultra2 hvd to hvd 1 1. all hvd requires external differential transceivers and terminations. repeater ultra se to se repeater ultra or any combination above for repeater. lvdtohvd 1 converter ultra lvd to se converter ultra hvd 1 to se converter ultra or any combination above for converter. general description 1-3 figure 1.2 SYM53C140 server clustering figure 1.2 demonstrates how scsi bus expanders are used to couple bus segments together without any impact of the scsi protocol or software. con?gurations that use the SYM53C140 scsi bus expander in the ultra2 mode (lvd to lvd) allow the system designer to take advantage of the inherent cable distance, device connectivity, data reliability, and increased transfer rate bene?ts of lvd signaling with ultra2 scsi peripherals. in figure 1.2 example, the SYM53C140 is con?gured as a three port expander board. this con?guration allows segments a and b to be treated as a point-to-point segment. segment c is treated as a load segment with at least 8 inches between every node. table 1.2 shows the various distance requirements for each scsi bus mode. table 1.2 scsi bus distance requirements segment mode length limit a, b lvd (ultra2) 25 meters se (ultra) 20 meters hvd (ultra) 25 meters segment c lvd (ultra2) 12 meters se (ultra) 1.5 meters hvd (ultra) 25 meters segment a segment b segment c primary server secondary server shared disk subsystem scsi bus expander scsi bus expander 1-4 introduction in the second example, figure 1.3, the SYM53C140 is cascaded to achieve four distinct scsi segments. segments a and d can be treated as point-to-point segments. segments b and c are treated as load segments with at least 8 inch spacing between every node. table 1.3 shows the various distance requirements for each transmission mode. figure 1.3 SYM53C140 scsi bus device 1.1.2 features a ?exible scsi bus expander that supports any combination of low- voltage differential (lvd), single-ended (se), or high-voltage differential transceivers (hvd) creates distinct scsi bus segments that are electrically isolated from each other table 1.3 transmission mode distance requirements segment mode length limit a, d lvd (ultra2) 25 meters se (ultra) 20 meters hvd (ultra) 25 meters b, c lvd (ultra2) 12 meters se (ultra) 1.5 meters hvd (ultra) 25 meters segment a segment b segment c primary secondary shared disk scsi bus expander scsi bus expander server server scsi bus expander segment d subsystem shared disk subsystem general description 1-5 integrated lvdlink transceivers for direct attachment to either lvd, se, or hvd bus segments operates as a scsi bus expander C lvd to lvd (ultra2 scsi) C hvd to hvd (ultra scsi) C se to se (ultra scsi) operates as a scsi bus converter C lvd to hvd (ultra scsi) C lvd to se (ultra scsi) C hvd to se (ultra scsi) targets and initiators may be located on either the a or b side of the device accepts any asynchronous or synchronous transfer speed up to ultra2 scsi (for lvd to lvd mode only) supports dynamic addition/removal of scsi bus segments via the electrical isolation mode does not consume a scsi id propagates the reset/ signal from one side to the other regardless of the scsi bus state noti?es initiator(s) of changes in transmission mode (se/lvd/hvd) on a or b side segments via scsi bus reset scsi busy led driver for activity indicator up to four SYM53C140s may be cascaded completely independent of software 1.1.3 speci?cations 40 mhz input clock 160-pin plastic quad flat pack (pqfp) compliant with the scsi parallel interconnect 2(spi-2) compliant with scsi enhanced parallel interface (epi) speci?cations 1-6 introduction 1.2 bene?ts of lvdlink the SYM53C140 supports low-voltage differential (lvd) technology for scsi, a signaling technology that increases the reliability of scsi data transfers over longer distances than those supported by single-ended scsi technology. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high-voltage differential (hvd) scsi technology without the added cost of external differential transceivers. lvd allows a longer scsi cable and more devices on the bus. lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. for backward compatibility to existing single-ended devices, the SYM53C140 features multimode lvdlink transceivers that can switch between lvd and single-ended modes. integrated lvdlink multimode transceivers C supports single-ended, lvd, or hvd technology (hvd must have external transceivers) C allows greater device connectivity and longer cable length C lvdlink transceivers save the cost of external differential transceivers C supports a long-term performance migration path symbios SYM53C140 ultra2 scsi bus expander 2-1 chapter 2 functional descriptions 2.1 interface signal descriptions the SYM53C140 has no programmable registers, and therefore, no software requirements. scsi control signals control all SYM53C140 functions. this chapter describes all signals, their groupings and their functions. figure 2.1 shows a block diagram of the SYM53C140 device divided into the following blocks: a side scsi control block C lvd, se, and hvd drivers and receivers b side scsi control block C lvd, se, and hvd drivers and receivers retiming logic precision delay control state machine control 2-2 functional descriptions figure 2.1 SYM53C140 block diagram in its simplest form, the SYM53C140 passes data and parity from a source bus to a load bus. the side asserting, deasserting, or releasing the scsi signals is the source side. the model of the SYM53C140 is pieces of wire that allow corresponding scsi signals to ?ow from one side to the other side. the SYM53C140 needs to know which signals are being driven by another device so it can enable the proper drivers to pass the signals along. in addition, the SYM53C140 does some signal retiming to maintain the signal skew budget from the source bus to the load bus as if the source was a local bus member. 2.1.1 scsi a side and b side control blocks the scsi a side pins are connected internally to the corresponding scsi b side pins, forming bidirectional connections to the scsi bus. in the lvd/lvd mode, the scsi a side and b side control blocks connect to both targets and initiators and accept any asynchronous or synchronous data transfer rates up to the 80 mbytes/s rate of wide ultra2 scsi. tolerant ? and lvdlink technologies are part of both the a side and b side control blocks. retiming logic precision delay control state machine control lv d diffsens receiver lv d diffsens receiver scsi control block scsi control bloc k lvdink? transceivers lvdink? transceivers control signals lvd, single-ended, hvd wide ultra scsi bus (a side) lvd, single-ended, hvd wide ultra scsi bus (b side) a_diffsens b_diffsens 40 mhz clock input interface signal descriptions 2-3 2.1.1.1 SYM53C140 requirements for synchronous negotiation the SYM53C140 builds a table of information regarding devices on the bus in on-chip ram. the sdtr and wdtr information for each device is taken from the msg byte during negotiation. for all devices in the con?guration to communicate accurately with each other through the SYM53C140 at ultra2 (fast 40) rates, it is necessary for a complete synchronous negatiation to take place between the initatiator(s) and target(s) prior to any data transfer. otherwise, the SYM53C140 defaults to fast 20 rates. 2.1.1.2 tolerant technology in the single-ended mode, the SYM53C140 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation causes the scsi request, acknowledge, data, and parity signals to be actively driven high rather than passively pulled up by terminators. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions without the long signal delays associated with rc- type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. the bene?ts of tolerant technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved scsi transfer rates. in addition, tolerant scsi devices prevent glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. 2.1.1.3 lvdlink technology to support greater device connectivity and longer scsi cables, the SYM53C140 features lvdlink technology, the lsi logic implementation of multimode lvd scsi. lvdlink transceivers provide the inherent reliability of differential scsi, and a long-term migration path of faster scsi transfer rates. 2-4 functional descriptions lvdlink technology is based on current drive. its low output current reduces the power needed to drive the scsi bus. therefore, the i/o drivers can be integrated directly onto the chip. this reduces the cost and complexity compared to traditional (high power) differential designs. lvdlink lowers the amplitude of noise re?ections and allows higher transmission frequencies. the lvdlink transceivers in side a and side b operate in the lvd, hvd (external differential transceivers), or single-ended modes. the SYM53C140 automatically detects the type of signal connected, based on the voltages detected by a_diffsens and b_diffsens. 2.1.2 retiming logic the scsi signals, as they propagate from one side of the SYM53C140 to the other side, are processed by logic circuits that re-time the bus signals, as needed, to guarantee or improve the required scsi timings. the logic circuitry is governed by the state machine controls that keep track of scsi phases, the location of initiator and target devices, and various timing functions. in addition, the logic circuitry contains numerous delay elements that are periodically calibrated by the precision delay control block in order to guarantee speci?ed timing such as output pulse widths, setup and hold times, and others. 2.1.3 state machine control the state machine control keeps track of the scsi bus phase protocol and other internal operating conditions. this block provides signals to the retiming logic that identify how to properly handle scsi bus signal retiming and protocol, based on observed bus conditions. 2.1.4 precision delay control the precision delay control block provides calibration information to the precision delay elements in the retiming logic block in order to maintain precise timing as signals propagate through the device. as the SYM53C140 operating conditions (such as voltage and temperature) vary over time, the precision delay control block will periodically update the delay settings in the retiming logic to maintain constant and precise control over bus timing. interface signal descriptions 2-5 2.1.5 diffsens receiver the SYM53C140 contains lvd diffsens receivers that detect the voltage level on the a side or b side diffsens lines to inform the SYM53C140 of the transmission mode being used by the scsi buses. the lvd diffsens receivers are capable of detecting the voltage level of incoming scsi signals to determine whether it is from a single-ended, lvd, or hvd device. a device will not change its present signal driver or receiver mode based on the diffsens voltage levels unless a new mode is sensed continuously for at least 100 ms. transmission mode detection for se, lvd, or hvd is accomplished through the use of the diffsens lines. table 2.1 shows the voltages on the diffsens lines and modes they will cause. 2.1.6 dynamic transmission mode changes any dynamic mode change (se/lvd/hvd) on a bus segment is considered to be a catastrophic event that requires the initiator to determine whether the mode change meets the requirements for that bus segment. the SYM53C140 supports dynamic transmission mode changes by notifying the initiator(s) of changes in transmission mode (se/lvd/hvd) on a or b side segments via scsi bus reset. the diffsens line is used to detect a valid mode switch on the bus segments. after the diffsens state is present for 100 ms, the SYM53C140 generates a scsi reset on the opposite bus from the one that the transmission mode change occurred on. this reset is used to inform any initiators residing on the opposite segment about the change in the transmission mode. the initiator(s) will then renegotiate synchronous transfer rates with each device on that segment to ensure that there is a valid bus segment for that mode. table 2.1 diffsens voltage levels voltage mode -0.35 to +0.5 se +0.7 to +1.9 lvd +2.4 to +5.5 hvd 2-6 functional descriptions 2.1.7 scsi signal descriptions figure 2.2 shows the SYM53C140 signal grouping. a description of the signal groups follow. for a description of a speci?c signal, see section 3.1, signal descriptions in chapter 3 . for a signal electrical characteristics, see section 3.2, electrical characteristics in chapter 3 . for scsi bus signal timing, see section 3.2.4, scsi interface timing in chapter 3 . figure 2.2 SYM53C140 signal grouping 2.1.7.1 data and parity (sd and sdp) the signals named a_sd[15:0] and a_sdp[1:0] are the data and parity signals from the a side, and b_sd[15:0] and b_sdp[1:0] are the data and parity signals from the b side of the SYM53C140. these signals are sent and received from the SYM53C140 via scsi compatible drivers and receiver logic designed into the SYM53C140 interfaces. this logic provides the necessary drive, sense thresholds, and input hysteresis to function correctly in a scsi bus environment. a_ssel+ a_ssel- a_sbsy+ a_sbsy- a_srst+ a_srst- a_sreq+ a_sreq- a_sack+ a_sack- a_smsg+ a_smsg- a_scd+ a_scd- a_sio+ a_sio- a_satn+ a_satn- a_sdp[1:0]+ a_sdp[1:0]- a_sd[15:0]+ a_sd[15:0]- a_diffsens a_hvd_mode reset/ ws_enable xfer_active clock b_ssel+ b_ssel- b_sbsy+ b_sbsy- b_srst+ b_srst- b_sreq+ b_sreq- b_sack+ b_sack- b_smsg+ b_smsg- b_scd+ b_scd- b_sio+ b_sio- b_satn+ b_satn- b_sdp[1:0]+ b_sdp[1:0]- b_sd[15:0]+ b_sd[15:0]- b_diffsens b_hvd_mode bsy_led a-side lvd, hvd, or se scsi interface b-side lvd, hvd, or se scsi interface control signals SYM53C140 interface signal descriptions 2-7 the SYM53C140 receives data and parity signals and passes them from the source bus to the load bus and provides any necessary edge shifting to guarantee the skew budget for the load bus. either side of the SYM53C140 may be the source bus or the load bus. the side that is asserting, deasserting or releasing the scsi signals is the source side. the following steps describe the SYM53C140 data processing: 1. asserted data is accepted from the receiver logic as soon as it is received. once the clock signal has been received, data is gated from the receiver latch. 2. the path is next tested to be sure the data was not driven by the SYM53C140. this is because valid data needs to be generated by another node on the source bus to be passed through the SYM53C140 to the load bus. 3. the data is then leading edge ?ltered. the assertion edge is held for a speci?ed time to prevent any signal bounce. the duration is controlled by the input signal. 4. the next stage uses a latch to sample the signal. this provides a stable data window for the load bus. 5. the ?nal step develops pull-up and pull-down controls for the scsi i/o logic, including 3-state controls for the pull-up. 6. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.2 scsi bus activity led (bsy_led) internal logic is used to detect scsi bus activity and generate a signal that will produce an active high output. this output can be used to drive a led to indicate scsi activity. the internal circuitry is a digital one shot that is an active high with a minimum pulse width of 16 ms. the bsy_led output current is 8 ma. this output may have an led attached to it with the other lead of the led grounded through a suitable resistor. 2.1.7.3 busy control (sbsy) a_sbsy and b_sbsy signals are propagated from the source bus to the load bus. these signals go through the following process: 2-8 functional descriptions 1. the bus is tested to be sure the data lines were not driven by the SYM53C140. this is because valid data needs to be generated by another node on the source bus to be passed through the SYM53C140 to the load bus. 2. the data is then leading edge ?ltered. the assertion edge is held for a speci?ed time to prevent any signal bounce. the duration is controlled by the input signal. 3. the next stage has two modes. one mode simply passes data through. the other mode behaves like a large ?lter. the mode is selected by the current state in the SYM53C140 state machine that tracks scsi phases. the large ?lter mode is used when the busy (sbsy) and select (ssel) sources switch from side to side. this output is then fed to the output driver which is a pull-down open collector only. 4. a parallel function ensures that bus (transmission line) recovery is available for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.4 request and acknowledge control (sreq and sack) a_sreq, a_sack, b_sreq, and b_sack are clock and control signals. their signal paths contain controls to guarantee minimum pulse widths, ?lter edges, and does some retiming when used as data transfer clocks. sreq and sack have paths from the a side to the b side and from the b side to the a side. the received signal goes through the following processing steps before being sent to the opposite bus: 1. the asserted input signal is sensed and forwarded to the next stage if the direction control permits it. the direction controls are developed from state machines that are driven by the sequence of bus control signals. 2. the signal must then pass the test of not being generated by the SYM53C140. 3. in the a side to b side direction, the next stage is a leading edge ?lter. this ensures that the output will not switch during the speci?ed hold time after the leading edge. the duration of the input signal determines the duration of the output after the hold time. in the b side to a side direction, the circuit guarantees a minimum pulse width. interface signal descriptions 2-9 4. the next stage passes the signal if it is not a data clock. if sreq or sack is a data clock, it delays the leading edge to improve data output setup times. the duration is again controlled by the input signal. 5. the following stage is a trailing edge signal ?lter. when the signal deasserts, the ?lter will not permit any signal bounce. the output signal deasserts at the ?rst deasserted edge of the input signal. 6. the last stage develops pull-up and pull-down signals with drive and 3-state control. 7. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.5 reset control (srst) a_srst and b_srst are also passed from the source to the load bus. this output has pull-down control for an open collector driver. these reset signals are processed using the following steps: 1. the input signal is blocked if it is already being driven by the SYM53C140. 2. the next stage is a leading edge ?lter. this ensures that the output will not switch during a speci?ed time after the leading edge. the duration of the input signal then determines the duration of the output. 3. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.6 control/data, input/output, message, and attention controls (scd, sio, smsg, and satn) a_scd, a_sio, a_smsg, a_satn, b_scd, b_sio, b_smsg and b_satn are control signals that have the following processing steps: 1. the input signal is blocked if it is being driven by the SYM53C140. 2. the next stage is a leading edge ?lter. this ensures the output will not switch for a speci?ed time after the leading edge. the duration of the input signal determines the duration of the output. 2-10 functional descriptions 3. the ?nal stage develops pull-up and pull-down controls for the scsi i/o logic, including 3-state controls for the pull-up. 4. a parallel function ensures that bus (transmission line) recovery is for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.7 select control (ssel) a_ssel and b_ssel are control signals used during bus arbitration and selection. whichever side asserts, ssel propagates it to the other side. if both signals are asserted at the same time, the a side receives ssel and sends it to the b side. this output has pull-down control for an open collector driver. the signal goes through the following processing steps: 1. the input signal is blocked if it is being driven by the SYM53C140. 2. the next stage is a leading edge ?lter. this ensures that the output will not switch for a speci?ed time after the leading edge. the duration of the input signal then determines the duration of the output. 3. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.8 differential direction controls a_sd[15:0], a_sdp[1:0], a_sbsy, a_ssel, a_scd, a_sio, a_smsg, a_sreq, a_sack, a_satn, a_srst, b_sd[15:0], b_sdp[1:0], b_sbsy, b_ssel, b_scd, b_sio, b_smsg, b_sreq, b_sack, b_satn, and b_srst are all multimode signals. the mode is controlled by the hvd_mode input pins and the voltage is sensed at the diffsens inputs. when high-voltage differential signaling is selected and the diffsens line sees the proper voltage input, all the minus signal leads become single-ended inputs/outputs to hvd drivers/receivers. all plus signals interface signal descriptions 2-11 become the hvd driver/receiver direction control signals. the a and b sides are independently controlled. when the single-ended mode is selected by the lack of hvd_mode and the correct diffsens voltage, the plus signal leads are internally tied to ground and the minus scsi signals become the single-ended input/outputs. when the low-voltage differential mode is selected by the lack of hvd_mode and the correct diffsens voltage, the plus and minus signal leads are differential signal pairs. 2.1.7.9 clock (clock) this is the 40 mhz oscillator input to the SYM53C140. it is the clock source for the protocol control state machines and timing generation logic. this clock is not used in any bus signal transfer paths. 2.1.7.10 a and b high-voltage differential mode (a_hvd_mode and b_hvd_mode) these inputs inform the SYM53C140 that external drivers and receivers are used in this particular application. the effect of this control is to disable the lvd and single-ended modes of operation from the corresponding port. table 2.2 direction control signal polarities signal level state effect low = 0 deasserted input signals into the SYM53C140 high = 1 asserted drive the SYM53C140 signals onto the bus table 2.3 hvd_mode control signal polarity signal level state effect low = 0 deasserted SYM53C140 drivers function in single-ended or lvd mode. high = 1 asserted high-voltage differential signals and controls are enabled from the port. 2-12 functional descriptions 2.1.7.11 chip reset (reset/) this general purpose chip reset is intended to force all of the internal elements of the SYM53C140 into a known state. it will bring the state machine to an idle state and force all controls to a passive state. the minimum reset/ input asserted pulse width is 100 ns. the SYM53C140 also contains an internal power on reset (por) function that is ored with the chip reset pin. this eliminates the need for an external chip reset. 2.1.7.12 a and b differential sense (a_diffsens and b_diffsens) these control pins are used to determine the mode of scsi bus signaling that will be expected. for example, if a differential source is plugged into the b side that has been con?gured to run in the differential mode and if a single-ended source is detected, then the b side is disabled and no b side signals will be driven. this is a protection mechanism for single-ended interfaces that are connected to differential drivers. 2.1.7.13 warm swap enable (ws_enable) this input is used to remove the chip from an active bus without disturbing the current scsi transaction (for warm swap). when asserted table 2.4 reset/ control signal polarity signal level state effect low = 0 asserted reset is forced to all internal SYM53C140 elements. high = 1 deasserted SYM53C140 is not in a forced reset state. table 2.5 mode sense control voltage levels voltage mode -0.35 to +0.5 se +0.7 to +1.9 lvd +2.4 to +5.5 hvd interface signal descriptions 2-13 low, the chip will wait until the next scsi bus free state, then reset internally. once reset, all scsi activity will be ignored until the ws_enable pin is deasserted high and both scsi busses enter the bus free state. as an indication that the chip is idle, or ready to be warm swapped, the xfer_active signal will deassert low. an led or some other indicator could be connected to the xfer_active signal. 2.1.7.14 transfer active (xfer_active) this output is an indication that the chip has ?nished its internal testing, the scsi bus has entered a bus free state, and scsi traf?c can now pass from one bus to the other. the signal is asserted high when the chip is active. 2.1.8 scsi termination the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of each scsi segment, and only at the ends. no scsi segment should ever have more or less than two terminators installed and active. scsi host adapters should provide a table 2.6 ws_enable signal polarity signal level state effect high = 1 asserted the SYM53C140 performs normal transfers through the device low = 0 deasserted the SYM53C140 discontinues transfers through the device (off-line) upon detection of a scsi bus fee state table 2.7 xfer_active signal polarity signal level state effect high = 1 asserted indicates normal operation, transfers through the SYM53C140 are enabled low = 0 deasserted the SYM53C140 has detected a bus free state do to ws_enable being low disabling transfers through the device 2-14 functional descriptions means of accommodating terminators. the terminators should be socketed, so they may be removed if not needed. or, there should be a means of disabling them with software. multi-mode terminators are required because they provide both lvd and single-ended termination, depending on what mode of operation is detected by the diffsens pins. hvd requires a different termination con?guration. the use of active termination is highly recommended. figure 2.3 scsi termination 4 line1+ 5 line1- 6 line2+ 7 line2- 11 line3+ 12 line3- 13 line4+ 14 line4- 15 line5+ 17 discnct 16 line5- 32 line9+ 31 line9- 30 line8+ 29 line8- 25 line7+ 24 line7- 23 line6+ 22 line6- 33 se 21 diff b 34 lv d 35 hvd 20 diffsens ucc5630 sd0+ sd0- sd1+ sd1- sd2+ sd2- sd3+ sd3- sd4+ sd4- sdp0+ sdp0- sd7+ sd7- sd6+ sd6- sd5+ sd5- 22k 0.1 m f to led drivers diffsens connects to the scsi bus diffsens line to detect what type of devices (single-ended, lvd, or high-voltage differential) are connected to the scsi bus. discnct shuts down the terminator when it is not at the end of the bus. the disconnect pin low enables the terminator. *use additional ucc5630 terminators to terminate the scsi control signals and wide scsi data byte as needed. symbios SYM53C140 ultra2 scsi bus expander 3-1 chapter 3 speci?cations 3.1 signal descriptions the SYM53C140 is packaged in a 160-pin plastic quad flat pack (pqfp) shown in figure 3.1. the SYM53C140 signal grouping is shown in figure 3.2 and tables 3.1 through 3.4 list the signal descriptions grouped by function: scsi a side interface pins (table 3.1) scsi b side interface pins (table 3.2) chip interface control pins (table 3.3) power and ground pins (table 3.4) 3-2 speci?cations the decoupling capacitor arrangement shown below is recommended to maximize the bene?ts of the internal split ground system. capacitor values should be between 0.01 fand 0.1 f . figure 3.1 SYM53C140 160-pin pqfp pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 top view 98.SYM53C140 1. nc pins are not connected. bsd11+ bsd11 - bsd10+ bsd10 - bsd9+ bsd9 - vss scsi bsd8+ bsd8 - vdd scsi bsio+ bsio - bsreq+ bsreq - vss scsi bscd+ bscd - bssel+ bssel - bsmsg+ bsmsg - vss scsi vss core bsrst+ bsrst - vdd core vdd scsi bsack+ bsack - bsbsy+ bsbsy - vss scsi bsatn+ bsatn - bsdp0+ bsdp0 - vdd scsi rbias bsd7+ bsd7 - vss scsi asd4 - asd4+ asd5 - asd5+ asdd6 - asd6+ vdd scsi asd7 - asd7+ vss scsi asdp0 - asdp0+ asatn - asatn+ asbsy - asbsy+ vss core vss scsi asack - asack+ vdd scsi vdd core asrst - asrst+ vss scsi asmsg - asmsg+ assel - assel+ ascd - ascd+ vss scsi asreq - asreq+ asio - asio+ asd8 - asd8+ vdd scsi vss scsi bsd6+ bsd6 - bsd5+ bsd5 - bsd4+ bsd4 - vss scsi bsd3+ bsd3 - vdd scsi bsd2+ bsd2 - bsd1+ bsd1 - vss scsi bsd0+ bsd0 - bsdp1+ bsdp1 - bsd15+ bsd15 - vss scsi bsd14+ bsd14 - vdd scsi bsd13+ bsd13 - bsd12+ bsd12 - vss scsi vss scsi asd11+ asd11 - vdd scsi asd10+ asd10 - asd9+ asd9 - vss scsi vss scsi b_diffsens vdd io b_hvd_mode nc nc nc nc nc nc ws_enable xfer_active bsy_led clock reset/ a_hvd_mode vss io a_diffsens asd12 - asd12+ asd13 - asd13+ asd14 - asd14+ vss scsi asd15 - asd15+ vdd scsi asdp1 - asdp1+ asd0 - asd0+ vss scsi asd1 - asd1+ asd2 - asd2+ asd3 - asd3+ vdd scsi signal descriptions 3-3 figure 3.2 SYM53C140 functional signal grouping a_ssel+ a_ssel- a_sbsy+ a_sbsy- a_srst+ a_srst- a_sreq+ a_sreq- a_sack+ a_sack- a_smsg+ a_smsg- a_scd+ a_scd- a_sio+ a_sio- a_satn+ a_satn- a_sdp[1:0]+ a_sdp[1:0]- a_sd[15:0]+ a_sd[15:0]- a_diffsens a_hvd_mode reset/ ws_enable xfer_active clock b_ssel+ b_ssel- b_sbsy+ b_sbsy- b_srst+ b_srst- b_sreq+ b_sreq- b_sack+ b_sack- b_smsg+ b_smsg- b_scd+ b_scd- b_sio+ b_sio- b_satn+ b_satn- b_sdp[1:0]+ b_sdp[1:-0]- b_sd[15:0]+ b_sd[15:0]- b_diffsens b_hvd_mode bsy_led a-side lvd, hvd, or se scsi interface b-side lvd, hvd, or se scsi interface control signals SYM53C140 3-4 speci?cations table 3.1 scsi a side interface pins scsi a pin type description a_ssel+,- 91, 92 i/o a side scsi bus select control signal. a_sbsy+,- 104, 105 i/o a side scsi bus busy control signal. a_srst+,- 96, 97 i/o a side scsi bus reset control signal. a_sreq+,- 86, 87 i/o a side scsi bus request control signal. a_sack+,- 100, 101 i/o a side scsi bus acknowledge control signal. a_smsg+,- 93, 94 i/o a side scsi bus message control signal. a_scd+,- 89, 90 i/o a side scsi bus control and data control signal. a_sio+,- 84, 85 i/o a side scsi bus input and output control signal. a_satn+,- 106, 107 i/o a side scsi bus attention control signal. a_sdp[1:0]+,- 108, 109, 131, 132 i/o a side scsi bus data parity signal. a_sd[15:0]+,- 73, 74, 76C79, 82, 83, 111, 112, 114C119, 122C127, 129, 130, 134, 135, 137C142 i/o a side scsi bus data signals. a_diffsens 143 i a side scsi bus differential sense signal. a_hvd_mode 145 i a side scsi bus hvd mode control signal. signal descriptions 3-5 table 3.2 scsi b side interface pins scsi b pin type description b_ssel+,- 18, 19 i/o b side scsi bus select control signal. b_sbsy+,- 30, 31 i/o b side scsi bus busy control signal. b_srst+,- 24, 25 i/o b side scsi bus reset control signal. b_sreq+,- 13, 14 i/o b side scsi bus request control signal. b_sack+,- 28, 29 i/o b side scsi bus acknowledge control signal. b_smsg+,- 20, 21 i/o b side scsi bus message control signal. b_scd+,- 16, 17 i/o b side scsi bus control and data control signal. b_sio+,- 11, 12 i/o b side scsi bus input and output control signal. b_satn+,- 33, 34 i/o b side scsi bus attention control signal. b_sdp[1:0]+,- 59, 60, 35, 36 i/o b side scsi bus data parity signal. b_sd[15:0]+,- 1-6, 8, 9, 39, 40, 42C47, 49, 50, 52C55, 57, 58, 61, 62, 64, 65, 67C70, i/o b side scsi bus data signals. b_diffsens 159 i b side scsi bus differential sense signal. b_hvd_mode 157 i b side scsi bus hvd mode control signal. table 3.3 chip interface control pins control pin type description reset/ 146 i master reset for SYM53C140, active low. ws_enable 150 i/o enable/disable scsi transfers through the SYM53C140. xfer_active 149 i/o transfers through the SYM53C140 are enabled/disabled. clock 147 i oscillator input for SYM53C140 (40 mhz). bsy_led 148 o scsi activity led output, 8 ma. 3-6 speci?cations table 3.4 power and ground pins power and ground pin type description vdd scsi 10, 27, 37, 51, 66, 75, 81, 99, 113, 121, 133 i power supplies to the scsi bus i/o pins. vss scsi 7, 15, 22, 32, 41, 48, 56, 63, 71, 72, 80, 88, 95, 102, 110, 120, 128, 136, 160 i ground for the scsi bus i/o pins. vdd core 26, 98 i power supplies to the core logic. vss core 23, 103 i ground for the core logic. vdd io 158 i power supplies to the i/o logic. vss io 144 i ground for the i/o logic. rbias 38 i receiver bias control, r = 9.76 k w 1%. nc 151C156 n/a no connections. note: all v dd pins must be supplied 3.3 v. the SYM53C140 output signals drive 3.3 v. if the power supplies to the vdd io and vdd core pins in a chip testing environment are separated, either power up the pins simultaneously or power up vdd core before vdd io . the vdd io pin must always power down before the vdd core pin. electrical characteristics 3-7 3.2 electrical characteristics this section speci?es the dc and ac electrical characteristics of the SYM53C140. these electrical characteristics are in the following four categories: dc characteristics tolerant technology electrical characteristics ac characteristics scsi interface timing 3.2.1 dc characteristics table 3.5 absolute maximum stress ratings 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature -55 150 cC v dd supply voltage -0.5 4.5 v C v in input voltage v ss - 0.3 v dd + 0.3 v C i lp 2 2. -2 v < vpin < 8 v. latch-up current 150 C ma C esd electrostatic discharge C 2k v mil-std 883c, method 3015.7 3-8 speci?cations figure 3.3 lvd driver table 3.6 operating conditions 1 1. conditions that exceed the operating limits may cause the device to function incorrectly. symbol parameter min max unit test conditions v dd supply voltage 3.13 3.47 v C i dd supply current (dynamic se) C 130 ma C supply current (dynamic lvd) C 600 ma rbias = 9.76 k w 1% v dd = 3.3 v supply current (static) C 1 ma C t a operating free air 0 70 ?c C q ja thermal resistance (junction to ambient air) C 35 ?c/ w C table 3.7 lvd driver scsi signals b_sd[15:0], b_sdp[1:0], b_scd, b_sio, b_smsg, b_sreq, b_sack, b_sbsy, b_satn, b_ssel, b_srst 1 1. v cm = 0.7 - 1.8 v, r l = 0 - 110 w, r bias = 9.76 k w. symbol parameter min max units test conditions i o + source (+) current 7 12 ma asserted state i o - sink (-) current -7 -12 ma asserted state i o + source (+) current -3.5 -6 ma negated state i o - sink (-) current 3.5 6 ma negated state i oz 3-state leakage -20 20 m aC + - r l 2 v cm + i o + r l 2 i o - - electrical characteristics 3-9 figure 3.4 lvd receiver table 3.8 lvd receiver scsi signals b_sd[15:0], b_sdp[1:0] , b_scd, b_sio, b_smsg, b_sreq, b_sack, b_sbsy, b_satn, b_ssel, b_srst 1 1. v cm = 0.7 - 1.8 v symbol parameter min max units test conditions v i lvd receiver voltage asserting 60 C mv C v i lvd receiver voltage negating C -60 mv C table 3.9 diffsens scsi signal symbol parameter min max unit test conditions v ih high-voltage differential sense voltage 2.4 v dd + 0.3 v C v s lvd sense voltage 0.7 1.9 v C v il single-ended sense voltage v ss -0.3 0.5 v C i oz 3-state leakage -10 10 m aC table 3.10 input capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C 10 pf C v cm + - + + + - - - v i 2 v i 2 3-10 speci?cations table 3.11 bidirectional scsi signals a_sd[15:0]/, a_sdp[1:0]/, a_sreq/, a_sack/, b_sd[15:0], b_sdp[1:0], b_sreq, b_sack symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd vC v il input low voltage v ss 1.0 v C v oh 1 1. tolerant active negation enabled. output high voltage 2.0 v dd vi oh = 7.0 ma v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage -10 10 m aC table 3.12 bidirectional scsi signals a_scd/, a_sio/, a_smsg/, a_sbsy/, a_satn/, a_ssel/, a_srst/, b_scd, b_sio, b_smsg, b_sbsy, b_satn, b_ssel, b_srst symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd vC v il input low voltage v ss 1.0 v C v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage -10 10 m aC table 3.13 input control signals clock, reset/, ws_enable symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd vC v il input low voltage v ss 0.8 v C i oz 3-state leakage -10 10 m aC electrical characteristics 3-11 figure 3.5 external reset circuit 3.2.2 tolerant technology electrical characteristics input 3.3 v 0.1 m f reset pin 146 3.3 v table 3.14 output control signals bsy_led, xfer_active symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage C10 10 m aC table 3.15 tolerant technology electrical characteristics 1 symbol parameter min max units test conditions v oh 2 output high voltage 2.0 v dd + 0.3 v i oh =7ma v ol output low voltage v ss 0.5 v i ol =48ma v ih input high voltage 2.0 v dd + 0.3 v C v il input low voltage v ss C 0.3 0.8 v referenced to v ss v ik input clamp voltage C0.66 C0.77 v v dd = 4.75; i i = C20 ma v th threshold, high to low 1.0 1.2 v C v tl threshold, low to high 1.4 1.6 v C v th -v tl hysteresis 300 500 mv C i oh 2 output high current 2.5 24 ma v oh = 2.5 v (sheet 1 of 2) 3-12 speci?cations i ol output low current 100 200 ma v ol = 0.5 v i osh 2 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 3 i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 20 m a - 0.5 3-14 speci?cations figure 3.9 input current as a function of input voltage figure 3.10 output current as a function of output voltage +40 +20 0 -20 -40 -4 0 4 8 12 16 -0.7 v 8.2 v hi-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) 0 -200 -400 -600 -800 012345 output voltage (volts) output source current (milliamperes) output voltage (volts) 0123 45 100 80 60 40 20 0 electrical characteristics 3-15 3.2.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to dc characteristics in this chapter). chip timing is based on simulation at worst case voltage, temperature, and processing. the SYM53C140 requires a 40 mhz clock input. figure 3.11 clock timing 3.2.4 scsi interface timing table 3.16 clock timing symbol parameter min max units t 1 clock period 24.75 25.25 ns t 2 clock low time 10 15 ns t 3 clock high time 10 15 ns t 4 clock rise time 1 C v/ns clock t 1 t 3 t 4 t 2 table 3.17 input timing symbol parameter min max units t 1 input data setup 1 C ns t 2 input data hold 4.75 C ns t 3 input req/ack assertion pulse width 11 C ns t 4 input req/ack deassertion pulse width 11 C ns 3-16 speci?cations figure 3.12 input/output timing table 3.18 output timing symbol parameter min max units t 5 output data setup min [t 1 + 17ns, t 4 +5] C ns t 6 output data hold max [24, (t 2 - 20), t 3 ]Cns t 7 output req/ack pulse width max [20 ns, t 3 -5] max [30 ns, t 3 +5] ns t 8 req/ack transport delay 25 ns if req/ack is clock for input data, 10 ns if not 50 ns if req/ack is clock for input data, 30 ns if not ns t 9 data transport delay 6 [t 3 +35] ns input timing req or ack data output timing req or ack data t 3 t 4 t 1 t 2 valid data t 8 t 7 t 9 t 5 t 6 valid data mechanical drawings 3-17 3.3 mechanical drawings lsi logic component dimensions conform to a current revision of the jedec publication 95 standard package outline, using ansi 14.5y dimensioning and tolerancing interpretations. as jedec drawings are balloted and updated, changes may have occurred. to ensure the use of a current drawing, the jedec drawing revision level should be veri?ed. visit www.eia.org/jedec for review of publication 95 drawings and revision levels. for printed circuit board land patterns that will accept lsi logic components, it is recommended that customers refer to the ipc standards (institute for interconnecting and packaging electronic circuits). speci?cation number ipc-sm-782, surface mount design and land pattern standard is an established method of designing land patterns. feature size and tolerances are industry standards based on ipc assumptions. 3-18 speci?cations 3.3.1 SYM53C140 160-pin pqfp mechanical drawing the SYM53C140 is packaged in a 160-pin metric plastic quad flat pack (pqfp). figure 3.13 SYM53C140 160 pin pqfp (pf) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pf. mechanical drawings 3-19 figure 3.13 SYM53C140 pin 160 pqfp (pf) mechanical drawing (cont.) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pf. 3-20 speci?cations symbios SYM53C140 ultra2 scsi bus expander a-1 appendix a wiring diagrams a.1 SYM53C140 wiring diagrams the following four pages of wiring diagrams are of a typical SYM53C140 in a evaluation test board application. a-2 SYM53C140 wiring diagrams figure a.1 SYM53C140 wiring diagram 1 of 4 SYM53C140 wiring diagrams a-3 figure a.1 SYM53C140 wiring diagram 2 of 4 a-4 SYM53C140 wiring diagrams figure a.1 SYM53C140 wiring diagram 3 of 4 SYM53C140 wiring diagrams a-5 figure a.1 SYM53C140 wiring diagram 4 of 4 test circuit switch only. test circuit switch only. connector page a-6 wiring diagrams symbios SYM53C140 ultra2 scsi bus expander b-1 appendix b glossary ack/ acknowledge C driven by an initiator, ack/ indicates an acknowledgment or a scsi data transfer. in the target mode, ack/ is received as a response to the req/ signal. ansi american national standards institute. arbitration the process of selecting one respondent from a collection of several candidates that request service concurrently. asserted a signal is asserted when it is in the state that is indicated by the name of the signal. opposite of negated or deasserted. assertion the act of driving a signal to the true state. asynchronous transmission transmission in which each byte of the information is synchronized individually through the use of request (req/) and acknowledge (ack/) signals. atn/ attention C driven by an initiator, indicates an attention condition. in the target role, atn/ is received and is responded to by entering the message out phase. block a block is the basic 512 byte size of storage that the storage media is divided into. the logical block address protocol uses sequential block addresses to access the media. bsy/ busy C indicates that the scsi bus is being used. bsy/ can be driven by the initiator or the target device. bus a collection of unbroken signal lines that interconnect computer modules. the connections are made by taps on the lines. bus expander bus expander technology permits the extension of a bus by providing some signal ?ltering and retiming to maintain signal skew budgets. b-2 glossary cable skew delay cable skew delay is the minimum difference in propagation time allowed between any two scsi bus signals measured between any two scsi devices. c_d/ control/data C driven by a target. when asserted, indicates control or data information is on the scsi bus. this signal is received by the initiator. connect the function that occurs when an initiator selects a target to start an operation, or a target reselects an initiator to continue an operation. control signals the set of nine lines used to put the scsi bus into its different phases. the combinations of asserted and negated control signals de?ne the phases. controller a computer module that interprets signals between a host and a peripheral device. often, the controller is a part of the peripheral device, such as circuitry on a disk drive. db[7:0]/ scsi data bits C these eight data bits (db[7:0]/), plus a parity bit (dbp/), form the scsi bus. db7/ is the most signi?cant bit and has the highest priority id during the arbitration phase. data parity is odd. parity is always generated and optionally checked. parity is not valid during arbitration. deasserted the act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). a signal is deasserted or negated when it is in the state opposite to that which is indicated by the name of the signal. opposite of asserted. device a single unit on the scsi bus, identi?able by a scsi address. it can be a processor unit, a storage unit (such as a disk or tape controller or drive), an output unit (such as a controller or printer), or a communications unit. differential a signaling alternative that employs differential drivers and receivers to improve signal-to-noise ratios and increase maximum cable lengths. disconnect the function that occurs when a target releases control of the scsi bus, allowing the bus to go to the bus free phase. driver when used in the context of electrical con?guration, driver is the circuitry that creates a signal on a line. b-3 external con?guration all scsi peripheral devices are external to the host enclosure. external terminator the terminator that exists on the last peripheral device that terminates the end of the external scsi bus. free in the context of bus free phase, free means that no scsi device is actively using the scsi bus and, therefore, the bus is available for use. host a processor, usually consisting of the central processing unit and main memory. typically, a host communicates with other devices, such as peripherals and other hosts. on the scsi bus, a host has a scsi address. host adapter circuitry that translates between a processor's internal bus and a different bus, such as scsi. on the scsi bus, a host adapter usually acts as an initiator. initiator a scsi device that requests another scsi device (a target) to perform an operation. usually, a host acts as an initiator and a peripheral device acts as a target. internal con?guration all scsi peripheral devices are internal to the host enclosure. internal terminator the terminator that exists within the host that terminates the internal end of the scsi bus. i/o/ input/output C driven by a target. i/o controls the direction of data transfer on the scsi bus. when active, this signal indicates input to the initiator. when inactive, this signal indicates output from the initiator. this signal is also used to distinguish between the selection and reselection phases. i/o cycle an i/o cycle is an input (i/o read) operation or output (i/o write) operation that accesses the pc cards i/o address space. logical unit the logical representation of a physical or virtual device, addressable through a target. a physical device can have more than one logical unit. low (logical level) a signal is at the low logic level when it is below approximately 0.5 volts. b-4 glossary lsb abbreviation for least signi?cant bit or least signi?cant byte. that portion of a number, address or ?eld that occurs right-most when its value is written as a single number in conventional hexadecimal or binary notation. the portion of the number having the least weight in a mathematical calculation using the value. lun logical unit number. used to identify a logical unit. mandatory a characteristic or feature that must be present in every implementation of the standard. mhz megahertz C measurement in millions of hertz per second. used as a measurement of data transfer rate. microsecond ( m s) one millionth of a second. msb abbreviation for most signi?cant bit or most signi?cant byte. that portion of a number, address or ?eld that occurs left-most when its value is written as a single number in conventional hexadecimal or binary notation. the portion of the number having the most weight in a mathematical calculation using the value. msg/ message C driven active by a target during the message phase. this signal is received by the initiator. nanosecond (ns) one billionth of a second. negated a signal is negated or deasserted when it is in the state opposite to that which is indicated by the name of the signal. opposite of asserted. negation the act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state. parity a method of checking the accuracy of binary numbers. an extra bit, called a parity bit, is added to a number. if even parity is used, the sum of all 1s in the number and its corresponding parity is always even. if odd parity is used, the sum of the 1s and the parity bit is always odd. peripheral device a device that can be attached to the scsi bus. typical peripheral devices are disk drives, tape drives, printers, cd roms, or communications units. phase one of the eight states to which the scsi bus can be set. during each phase, different communication tasks can be performed. port a connection into a bus. b-5 priority the ranking of the devices on the bus during arbitration. protocol a convention for data transmission that encompasses timing control, formatting, and data representation. receiver the circuitry that receives electrical signals on a line. reconnect the function that occurs when a target reselects an initiator to continue an operation after a disconnect. release the act of allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). req/ request C driven by a target, indicates a request for a scsi data-transfer handshake. this signal is received by the initiator. reselect a target can disconnect from an initiator in order to perform a time- consuming function, such as a disk seek. after performing the operation, the target can reselect the initiator. reset reset C clears all internal registers when active. it does not assert the scsi rst/ signal and therefore does not reset the scsi bus. rst reset C indicates a scsi bus reset condition. scsi address the octal representation of the unique address ([7:0]) assigned to an scsi device. this address is normally assigned and set in the scsi device during system installation. scsi id (identi?cation) or scsi device id the bit-signi?cant representation of the scsi address referring to one of the signal lines db7/ through db0/. scsi small computer system interface. scam an acronym for scsi con?gured automatically. scam is the new scsi automatic id assignment protocol. scam frees scsi users from locating and setting scsi id switches and jumpers. scam is the key part of plug and play scsi. sel/ select C used by an initiator to select a target, or by a target to reselect an initiator. single-ended con?guration an electrical signal con?guration that uses a single line for each signal, referenced to a ground path common to the other signal lines. the advantage of a single-ended con?guration is that it uses half the pins, chips, and board area that differential/low-voltage differential b-6 glossary con?gurations require. the main disadvantage of single-ended con?gurations is that they are vulnerable to common mode noise. also, cable lengths are limited. synchronous transmission transmission in which the sending and receiving devices operate continuously at the same frequency and are held in a desired phase relationship by correction devices. for buses, synchronous transmission is a timing protocol that uses a master clock and has a clock period. target a scsi device that performs an operation requested by an initiator. termination the electrical connection at each end of the scsi bus, composed of a set of resistors. m s microsecond. one millionth of a second. symbios SYM53C140 ultra2 scsi bus expander ix-1 index symbol m s b-6 numerics 160-pin plastic quad flat pack 1-5 3-state 2-7 leakage 3-10 a a_sack 2-8 , 3-4 a_satn 2-9 , 3-4 a_sbsy 2-7 , 3-4 a_scd 2-9 , 3-4 a_sd[15:0] 2-6 , 3-4 a_sdp[1:0] 2-6 , 3-4 a_sio 2-9 , 3-4 a_smsg 2-9 , 3-4 a_sreq 2-8 , 3-4 a_srst 2-9 a_ssel 2-10 absolute maximum stress ratings 3-7 ac characteristics 3-15 ack b-1 acknowledge 2-3 (ack) 2-8 active negation 2-3 ansi b-1 applications 1-2 arbitration b-1 asserted b-1 assertion b-1 asynchronous transmission b-1 atn b-1 attention (satn) 2-9 b b_sack 2-8 , 3-5 b_satn 2-9 b_sbsy 2-7 , 3-5 b_scd 2-9 , 3-5 b_sd[15:0] 2-6 , 3-5 b_sdp[1:0] 2-6 , 3-5 b_sio 2-9 , 3-5 b_smsg 2-9 , 3-5 b_sreq 2-8 b_srst 2-9 b_ssel 2-10 , 3-5 backward compatibility 1-6 balanced duty cycles 2-3 bidirectional connections 2-2 scsi signals 3-10 block b-1 bsy b-1 bsy_led 2-7 bus b-1 timing 2-4 bus expander b-1 busy (bsy) 2-7 c c_d b-2 cable skew delay b-2 calibration 2-4 chip reset (reset/) 2-12 clock (clock) 2-11 signal 2-7 timing 3-15 ix-2 index connect b-2 control signals b-2 control/data (scd) 2-9 controller b-2 d data 2-3 , 2-6 db[7:0] b-2 dc characteristics 3-7 deasserted b-2 delay settings 2-4 device b-2 differential transceivers 1-6 differntial b-2 diffsens 2-4 , 2-5 , 3-9 receiver 2-5 direction control signal polarities 2-11 disconnect b-2 double clocking of data 2-3 driver b-2 e electrical characteristics 3-7 electrostatic discharge 3-7 enable/disable scsi transfers 3-5 esd 3-7 external configuration b-3 external terminator b-3 f filter edges 2-8 free b-3 g glitches 2-3 h high-voltage differential scsi 1-6 host b-3 adapter b-3 hvd_mode control signal polarity 2-11 hysteresis 2-6 i i/o b-3 cycle b-3 identification b-5 initiator b-3 input capacitance 3-9 i/o pads 3-9 input pads 3-9 control signals 3-10 high voltage 3-10 low voltage 3-10 timing 3-15 voltage 3-7 input/output (sio) 2-9 internal configuration b-3 internal terminator b-3 l latch-up current 3-7 leading edge filter 2-7 , 2-9 load bus 2-7 logical unit b-3 low (logical level) b-3 lsb b-4 lun b-4 lvd diffsens 2-5 driver scsi signals 3-8 receiver scsi signals 3-9 lvdlink 1-6 benefits 1-6 technology 2-4 transceivers 1-6 , 2-4 m mandatory b-4 master reset 3-5 message (smsg) 2-9 mhz b-4 microsecond b-4 migration path 1-6 msb b-4 index ix-3 msg b-4 n nanosecond b-4 negated b-4 negation b-4 o operating conditions 3-8 operating free air 3-8 output control signals 3-11 high voltage 3-10 low voltage 3-10 timing 3-16 p parallel function 2-8 , 2-9 parity 2-3 , 2-6 , b-4 peripheral device b-4 phase b-4 plastic quad flat pack (pqfp) 3-1 port b-4 power down 2-3 on reset (por) 2-12 up 2-3 pqfp 1-5 precision delay control 2-1 , 2-4 priority b-5 protocol b-5 pull-down 2-7 , 2-10 pull-up 2-7 , 2-10 pulse width 2-8 r rc-type input filters 2-3 receiver b-5 latch 2-7 reconnect b-5 recovery 2-9 release b-5 reliability issue 2-3 req b-5 request 2-3 (req) 2-8 reselect b-5 reserved b-5 reset b-5 reset (rst) 2-9 reset/ 2-12 , 3-5 control signal polarity 2-12 retiming 2-8 logic 2-1 , 2-4 rst b-5 s sack 2-8 , 2-9 scam b-5 scsi b-5 address b-5 bus protocol 2-4 device id b-5 i/o logic 2-10 id b-5 interface timing 3-15 parallel interconnect 2 1-5 phases 2-4 signal description 3-4 tolerant technology 2-3 scsi bus free state 2-13 sel b-5 select (ssel) 2-10 server clustering 1-2 signal descriptions 3-1 groupings 2-6 , 3-1 skew 2-2 single-ended configuration b-5 source bus 2-2 , 2-7 sreq 2-8 , 2-9 ssel 2-10 state machine 2-8 control 2-1 , 2-4 storage temperature 3-7 supply voltage 3-7 ix-4 index SYM53C140 scsi bus expander 1-1 synchronous transmission b-6 t target b-6 temperature 2-4 termination b-6 thermal resistance 3-8 tolerant drivers and receivers 2-3 receiver technology 2-3 scsi 2-3 technology 2-3 benefits 2-3 v vdd_core 3-6 vdd_scsi 3-6 voltage 2-4 vss_core 3-6 vss_scsi 3-6 w warm start enable 2-12 wide ultra2 scsi 2-2 ws_enable 2-12 , 3-5 signal polarity 2-13 x xfer_active 2-13 , 3-5 signal polarity 2-13 customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your name, phone number, fax number, and company address so that we may contact you directly for clari?cation or additional information. thank you for your help in improving the quality of our documents. customer feedback readers comments fax your comments to: lsi logic corporation technical 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