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ht36a0 8-bit music controller mcu block diagram rev. 1.00 1 september 3, 2002 features operating voltage: 3.6v~5.0v operating frequency: 3.58mhz~12mhz for crystal or rc oscillator 28 bidirectional i/o lines two 16-bit programmable timer/event counters with overflow interrupts watchdog timer built-in 8 bit mcu with 208 8 bits ram built-in 64k 16 bit rom for program/data shared digital output pins for external dac single data format with 16 bits digital stereo audio output two high d/a converter resolution: 16 bits polyphonic up to 16 notes independent pan and volume mix can be assigned to each sound component sampling rate of 50khz, 12.8mhz for system frequency eight-level subroutine nesting halt function and wake-up feature to reduce power consumption bit manipulation instructions 16-bit table read instructions 63 powerful instructions all instructions in 1 or 2 machine cycles 48-pin dip package general description the ht36a0 is an 8-bit high performance risc-like microcontroller specifically designed for music applica - tions. it provides an 8-bit mcu and a 16 channel wavetable synthesizer. the program rom is composed of both program control codes and wavetable voice codes, and can be easily programmed. the ht36a0 has a built-in 8-bit microprocessor which programs the synthesizer to generate the melody by setting the special register from 20h~2ah. a halt fea - ture is provided to reduce power consumption.
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pad coordinates unit: m pad no. x y pad no. x y 1 1365.58 1008.20 20 1273.90 1415.28 2 1365.58 748.60 21 1367.30 1106.75 3 1365.58 489.00 22 1367.30 847.15 4 1365.58 229.40 23 1367.30 587.55 5 1365.58 30.2 24 1367.30 327.95 6 1365.58 289.80 25 1367.30 68.35 7 1365.58 549.40 26 1367.30 191.25 8 1365.58 809.00 27 1367.30 450.85 9 1365.58 1068.60 28 1367.30 710.45 10 1365.58 1328.20 29 1367.30 970.05 11 1062.50 1415.28 30 1172.575 1414.78 12 802.90 1415.28 31 965.075 1414.78 13 543.30 1415.28 32 705.475 1414.78 14 283.70 1415.28 33 497.925 1414.78 15 24.10 1415.28 34 349.436 1396.935 16 235.50 1415.28 35 328.416 1396.935 17 495.10 1415.28 36 481.370 1368.13 18 754.70 1415.28 37 611.375 1368.13 19 1014.30 1415.28 38 741.385 1368.13 pad description pad no. pad name i/o internal connection function 1~8 pa0~pa7 i/o pull-high or none bidirectional 8-bit input/output port, wake-up by mask option 9~16 pb0~pb7 i/o pull-high or none bidirectional 8-bit input/output port 17~24 pc0~pc7 i/o pull-high or none bidirectional 8-bit input/output port 25 pd0 i/o pull-high or none bidirectional 8-bit input/output port 26 pd1/dout i/o pull-high or none bidirectional 8-bit input/output port dac data out 27 pd2/load i/o pull-high or none bidirectional 8-bit input/output port dac word clock 28 pd3/dclk i/o pull-high or none bidirectional 8-bit input/output port dac bit clock 29 res i reset input, active low 30 vss negative power supply of dac, ground 31 rch o cmos r channel audio output 32 lch o cmos l channel audio output 33 vcca1 dac power supply 35 34 osc1 osc2 i o osc1 and osc2 are connected to an rc network or a crystal (by mask option) for the internal system clock. in the case of rc opera - tion, osc2 is the output terminal for 1/4 system clock. the system clock may come from the crystal, the two pins cannot be floating. 36, 37 gnd negative power supply, ground 38 vdd positive power supply ht36a0 rev. 1.00 3 september 3, 2002
absolute maximum ratings supply voltage ........................................... 0.3v to 6v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0 . 3v to v dd +0.3v operating temperature .......................... 25 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3.6 5 6 v i dd operating current 5v no load f osc =11.0592mhz 816ma i stb standby current (wdt disabled) 5v no load system halt 0 a i ol i/o ports sink current 5v v ol =0.5v 9.7 16.2 ma i oh i/o ports source current 5v v oh =4.5v 5.2 8.7 ma r ph pull-high resistance of i/o ports 5v v il =0v 11 22 44 k v ih1 input high voltage for i/o ports 5v 3.5 5v v il1 input low voltage for i/o ports 5v 0 1.5 v v ih2 input high voltage (res )5v 4 v v il2 input low voltage (res )5v 2.5 v a.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions mcu interface f osc system frequency 5v 12mhz crystal 12 mhz f sys system clock 5v 4 16 mhz t wdt watchdog time-out period (rc) without wdt prescaler 9 17 35 ms t res external reset low pulse width 1 s t int interrupt pulse width 1 s symbol parameter figure min. typ. max. unit dac interface f bc dck bit clock frequency fig 1 f sys /16 mhz t ch dck bit clock h level time fig 1 600 ns t dos data output setup time fig 1 200 ns t doh data output hold time fig 1 200 ns t lcs load clock setup time fig 1 200 ns t lch load clock hold time fig 1 200 ns ht36a0 rev. 1.00 4 september 3, 2002
characteristics curves v vs f characteristics curve r vs f characteristics curve ht36a0 rev. 1.00 5 september 3, 2002 0 % $ % $ & % " $ % $ & & " $ % $ & & % & " & 1 1 " fig 1. audio output timing * 2 * 2 ) 2 2 ) 2 2 ) 2 2 ) ! 2 ! 2 ! 2
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ht36a0 rev. 1.00 6 september 3, 2002 function description execution flow the system clock for the ht36a0 is derived from either a crystal or an rc oscillator. the oscillator frequency di - vided by 2 is the system clock for the mcu and it is inter - nally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in one cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted and its contents specify a maximum of 8192 ad - dresses for each bank. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to retrieve the proper instruction. other - wise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. once a control transfer takes place, an additional dummy cycle is required. program rom ht36a0 provides 16 address lines wa[15:0] to read the program rom which is up to 1m bits, and is commonly used for the wavetable voice codes and the program memory. it provides two address types, one type is for program rom, which is addressed by a bank pointer pf2~0 and a 13-bit program counter pc 12~0; and the ' ' ' ! '
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( 6 . 1 + " ' . , / # ; 6 . 1 + " ' . , / ( 6 . 1 + " ' . , < / # ; 6 . 1 + " ' . , / ( 6 . 1 + " ' . , < / # ; 6 . 1 + " ' . , < / < < " 7 = . 3 6 : . 3 0 . , " 7 = . 3 6 : / execution flow mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 0 0 0000000000 timer/event counter 0 overflow 0 0 0 0000001000 timer/event counter 1 overflow 0 0 0 0000001100 skip pc+2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: bits of program counter @7~@0: bits of pcl #12~#0: bits of instruction code s12~s0: bits of stack register @7~@0: bits of pcl
ht36a0 rev. 1.00 7 september 3, 2002 other type is for wavetable code, which is addressed by the start address st15~0. on the program type, wa15~0= pf2~0 2 13 + pc12~0. on the wave table rom type, wa15~0=st15~0 2 5 . program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192 16 bits, addressed by the bank pointer, program counter and table pointer. certain locations in the program memory of each bank are reserved for special usage: location 000h on bank0 this area is reserved for the initialization program. af - ter chip reset, the program always begins execution at location 000h on bank0. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program on each bank. if timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h corresponding to its bank. location 00ch this area is reserved for the timer/event counter 1 interrupt service program on each bank. if a timer in- terrupt results from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00ch corre- sponding to its bank. table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the cur - rent page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table lo - cation. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruc - tion, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in this case, using the ta - ble read instruction in the main routine and the isr si - multaneously should be avoided. however, if the table read instruction has to be applied in both the main rou - tine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related in- structions need 2 cycles to complete the operation. these areas may function as normal program mem- ory depending upon user requirements. bank pointer the program memory is organized into 8 banks and each bank into 8192 16 bits program rom. pf[2~0] to be bank pointer only when pfc is configured as output mode. pfc is the control register of pf used to control the input/output configuration. to function as an output, the corresponding bit of the control register must be 0 . it will jump to the selection bank at the next program counter whenever there is data moved to the pf register. it should be note that the pf regis - ter has to be cleared before setting to output mode. % % ' = > . 3 . . . ? 3 3 4 = . ? & 3 3 : . ? . , ) . @ 3 a / % & 3 3 : . ? . , ) . @ 3 a / ( ( ( % + 3 b . . 4 . 0 3 = . . 3 . ( 2 ( ( % ' = > . 3 . . . ? 3 % > 6 . 8 3 . 3 4 = program memory for each bank instruction(s) table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: bits of table location @7~@0: bits of table pointer p12~p8: bits of current program counter
ht36a0 rev. 1.00 8 september 3, 2002 wavetable rom the st[15~0] is used to defined the start address of each sample on the wavetable and read the waveform data from the location. ht36a0 provides 21 output ad - dress lines from wa[16~0], the st[15~0] is used to lo - cate the major 16 bits i.e. wa[16:5] and the undefined data from wa[4~0] is always set to 00000b. so the start address of each sample have to be located at a multiple of 32. otherwise, the sample will not be read out cor - rectly because it has a wrong starting code. stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is subse- quently executed, a stack overflow occurs and the first entry will be lost (only the most recent eight return ad- dress are stored). data memory ram the data memory is designed with 256 8 bits. the data memory is divided into three functional groups: special function registers, wavetable function register, and gen - eral purpose data memory (208 8). most of them are read/write, but some are read only. the special function registers include the indirect ad - dressing register 0 (00h), the memory pointer register 0 (mp0;01h), the indirect addressing register 1 (02h), the memory pointer register 1 (mp1;03h), the accumulator (acc;05h), the program counter lower-byte register (pcl;06h), the table pointer (tblp;07h), the table higher-order byte register (tblh;08h), the watchdog timer option setting register (wdts;09h), the status register (status;0ah), the interrupt control register (intc;0bh), the timer/event counter 0 higher-order byte register (tmr0h;0ch), the timer/event counter 0 lower-order byte register (tmr0l;0dh), the timer/event counter 0 control register (tmr0c;0eh), the timer/ event counter 1 higher-order byte register (tmr1h;0fh), the timer/event counter 1 lower-order byte register (tmr1l;10h), the timer/event counter 1 control register (tmr1c;11h), the i/o registers (pa;12h, pb;14h, pc;16h, pd;18h, pf;1ch) and the i/o control registers (pac;13h, pbc;15h, pcc;17h, " 6 . 3 ' . # c % % % ! %
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ht36a0 rev. 1.00 9 september 3, 2002 pdc;19h, pfc;1dh). the wavetable function registers is defined between 20h~2ah. the remaining space be - fore the 30h is reserved for future expanded usage and reading these locations will return the result 00h. the general purpose data memory, addressed from 30h to ffh, is used for data and control information under instruc tion command. all data memory areas can handle arithmetic, logic, in - crement, decrement and rotate operations directly. ex - cept for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indirectly accessible through memory pointer registers (mp0;01h, mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h directly will return the result 00h. and writing directly results in no operation. the function of data movement between two indirect ad - dressing registers, is not supported. the memory pointer registers, mp0 and mp1, are 8-bit register which can be used to access the data memory by combining corresponding indirect addressing registers. accumulator the accumulator closely relates to alu operations. it is mapped to location 05h of the data memory and it can operate with immediate data. the data movement be- tween two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment & decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can also change the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd) and watchdog time-out flag (to). it also records the status information and controls the oper - ation sequence. with the exception of the to and pd flags, bits in the status register can be altered by instructions like any other register. any data written into the status register will not change the to or pd flags. in addition it should be noted that operations related to the status register may give different results from those intended. the to and pd flags can only be changed by system power up, watchdog timer overflow, executing the halt instruc - tion and clearing the watchdog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of status are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. interrupt the ht36a0 provides two internal timer/event counter interrupts on each bank. the interrupt control register (intc;0bh) contains the interrupt control bits that sets the enable/disable and the interrupt request flags. labels bits function c0 c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. also it is affected by a rotate through carry instruction. ac 1 ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov 3 ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared by either a system power-up or executing the clr wdt instruction. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status register
ht36a0 rev. 1.00 10 september 3, 2002 once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt needs servicing within the service routine, the pro - grammer may set the emi bit and the corresponding bit of the intc to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified locations in the program memory. only the program counter is pushed onto the stack. if the contents of the register and status register (status) are altered by the interrupt service program which may corrupt the desired control se - quence, then the programmer must save the contents first. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 5 of intc), caused by a timer/event counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt re- quest flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the timer/event counter 1 interrupt is operated in the same manner as timer/event counter 0. the related in- terrupt control bits et1i and t1f of the timer/event counter 1 are bit 3 and bit 6 of the intc respectively. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, the ret or reti in - struction may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the priorities in the following table apply. these can be masked by resetting the emi bit. no. interrupt source priority vector a timer/event counter 0 overflow 1 08h b timer/event counter 1 overflow 2 0ch the timer/event counter 0/1 interrupt request flag (t0f/t1f), external interrupt request flag (eif), enable timer/event counter 0/1 bit (et0i/et1i), enable external interrupt bit (eei) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is lo - cated at 0bh in the data memory. emi, et0i, et1i are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (t0f, t1f, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. be- cause interrupts often occur in an unpredictable manner or need to be serviced immediately in some applica- tions, if only one stack is left and enabling the interrupt is not well controlled, once the call subroutine operates in the interrupt subroutine, it may damage the original control sequence. register bit no. label function intc (0bh) 0 emi controls the master (global) interrupt (1=enabled; 0=disabled) 1 unused bit, read as 0 2 et0i controls the timer/event counter 0 interrupt (1=enabled; 0=disabled) 3 et1i controls the timer/event counter 1 interrupt (1=enabled; 0=disabled) 4 unused bit, read as 0 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc register
ht36a0 rev. 1.00 11 september 3, 2002 oscillator configuration the ht36a0 provides two types of oscillator circuit for the system clock, i.e., rc oscillator and crystal oscilla - tor. no matter what type of oscillator, the signal divided by 2 is used for the system clock. the halt mode stops the system oscillator and ignores external signal to con - serve power. if the rc oscillator is used, an external re - sistor between osc1 and vss is required, and the range of the resistance should be from 30k to 680k . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscilla - tion may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 78 s. the wdt oscillator can be disabled by mask option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys- tem clock of the mcu divided by 4), determined by mask options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown loca - tion with unpredictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 78 s normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of ap - proximately 20ms. this time-out period may vary with temperature, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real - ized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, ws0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user defined flags, and the programmer may use these flags to indicate some specified status. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset only the pc and sp are reset to zero. to clear the wdt contents (including the wdt prescaler ), 3 methods are implemented; external reset (a low level to res ), soft - ware instructions, or a halt instruction. the software instructions include clr wdt and the other set clr 7 . 6 3 . 6 3 " " " 0 " c "
" $ system oscillator " 7 = . 3 6 :
? . 3 e ' . 6 ? . 3 3 . f e ' . ' = 3 e " e " : 3 " 6 e ' " watchdog timer
ht36a0 rev. 1.00 12 september 3, 2002 wdt1 and clr wdt2. of these two types of instruc - tions, only one can be active depending on the mask op - tion clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are cho - sen (i.e. clrwdt times equal two), these two instruc - tions must be executed to clear the wdt; otherwise, the wdt may reset the chip because of time-out. power down operation halt the halt mode is initialized by a halt instruction and results in the following... the system oscillator will turn off but the wdt oscilla - tor keeps running (if the wdt oscillator is selected). watchdog timer wdt the contents of the on-chip ram and registers remain unchanged the wdt and wdt prescaler will be cleared and starts to count again (if the clock comes from the wdt oscillator). all i/o ports maintain their original status. the pd flag is set and the to flag is cleared. the halt pin will output a high level signal to disable the external rom. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig- nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per- forms a warm reset . by examining the to and pd flags, the cause for a chip reset can be determined. the pd flag is cleared when there is a system power-up or by execut- ing the clr wdt instruction and it is set when a halt in- struction is executed. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc and sp, the others remain in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by mask option. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if awakening from an interrupt, two sequences may occur. if the related interrupts is disabled or the in - terrupts is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, a regular interrupt re - sponse takes place. once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume to normal operation. in other words, a dummy cycle period will be inserted after the wake-up. if the wake-up results from an interrupt ac - knowledge, the actual interrupt subroutine will be de - layed by one more cycle. if the wake-up results in next instruction execution, this will execute immediately after a dummy period has finished. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are 3 ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that just resets the pc and sp, leaving the other cir - cuits to maintain their state. some registers remain un - changed during any other reset conditions. most registers are reset to the initial condition when the re - set conditions are met. by examining the pd and to flags, the program can distinguish between different chip resets . " " ' # " $ " " ' . ' = 3 . reset timing chart # " $ reset circuit e ' % & ' e ' ' = 3 # " 3 a e = . 3 @ 3 . 6 4 " " ' 4 . 3 " 1 reset configuration
ht36a0 rev. 1.00 13 september 3, 2002 the registers status is summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* program counter 0000h 0000h 0000h 0000h 0000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pf ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- --uu pfc ---- 1111 ---- 1111 ---- 1111 ---- 1111 uuuu uuuu chan 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu freqnh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu freqnl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu addrh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu addrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu reh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rel xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu env xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu lvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rvc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown
ht36a0 rev. 1.00 14 september 3, 2002 to pd reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses during system power up or when the system awakes from a halt state. when a system power-up occurs, the sst delay is added during the reset period. but when the reset co - mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional units chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter (0/1) off input/output ports input mode sp points to the top of stack timer/event counter two timer/event counters are implemented in the ht36a0. the timer/event counter 0 and timer/event counter 1 contain 16-bit programmable count-up coun - ters and the clock comes from the system clock divided by 4. there are three registers related to timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh). writing tmr0l only writes the data into a low byte buffer, and writing tmr0h will write the data and the contents of the low byte buffer into the timer/event counter 0 preload register (16-bit) simultaneously. the timer/event counter 0 preload register is changed by writing tmr0h operations and writing tmr0l will keep the timer/event counter 0 preload register unchanged. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid a false timing problem. reading tmr0l returns the contents of the low byte buffer. in other words, the low byte of the timer/event counter 0 cannot be read directly. it must read the tmr0h first to make the low byte contents of the timer/event counter 0 latched into the buffer. there are three registers related to the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). the timer/event counter 1 operates in the same man - ner as timer/event counter 0. the tmr0c is the timer/event counter 0 control regis - ter, which defines the timer/event counter 0 options. the timer/event counter 1 has the same options with timer/event counter 0 and is defined by tmr1c. the timer/event counter control registers define the op - erating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the instruction clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the instruction clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register and simulta - neously generates the corresponding interrupt request flag (t0f/t1f; bit 5/6 of intc). label bits function 0~2 unused bit, read as 0 te 3 define the tmr active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) ton 4 enable/disable timer counting (0=disable; 1=enable) 5 unused bit, read as 0 tm0 tm1 6 7 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c/tmr1c register
ht36a0 rev. 1.00 15 september 3, 2002 in pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a transient from low to high (or high to low; if the te bit is 0) it will start counting until the tmr returns to the original level and resets the ton. the measured result will remain in the even if the activated transient occurs again. in other words, only one cycle measurements can be done. until setting the ton, the cycle measurement will function again as long as it receives further transient pulse. note that, in this operating mode, the timer/event counter starts counting not according to the logic level but ac - cording to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instruction. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i/et1i can dis - able the corresponding interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr0h/tmr1h) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the program - mer. the two timer counters of ht36a0 are internal clock mode only, so only timer mode can be selected. there - fore the (tm1, tm0) bits can only be set to (tm1,tm0) = (1,0), and the other clock modes are invalid. input/output ports there are 28 bidirectional input/output lines labeled from pa to pd, which are mapped to the data memory of [12h], [14h], [16h], [18h] respectively. all these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h or 18h). for output oper - ation, all data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pfc) to control the input/output configura - tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor (mask op - tion) structures can be reconfigured dynamically under software control. to function as an input, the corre - sponding latch of the control register must write a 1 . the pull-high resistance will exhibit automatically if the pull-high option is selected. the input source also de - pends on the control register. if the control register bit is 1 , input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in read-modify-write instruc - tion. for output function, cmos is the only configura - tion. these control registers are mapped to locations 13h, 15h, 17h and 19h. after a chip reset, these input/output lines remain at high levels or floating (mask option). each bit of these in- put/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h, 16h or 18h) instruction. some instructions first input data and then follow the output operations. for example, the set [m].i, clr [m].i, cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability to wake-up the de - vice.

!
" #
$
%
& ' (
% # # $ $ ) " timer/event counter 0/1
ht36a0 rev. 1.00 16 september 3, 2002 16 channel wavetable synthesizer wavetable function memory mapping special register for wavetable synthesizer ram b7 b6 b5 b4 b3 b2 b1 b0 20h vm fr ch3 ch2 ch1 ch0 21h bl3 bl2 bl1 bl0 fr11 fr10 fr9 fr8 22h fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 23h st15 st14 st13 st12 st11 st10 st9 st8 24h st7 st6 st5 st4 st3 st2 st1 st0 25h wbs re14 re13 re12 re11 re10 re9 re8 26h re7 re6 re5 re4 re3 re2 re1 re0 27h a_r vl9 vl8 env1 env0 vr9 vr8 29h vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 2ah vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0 wavetable function register table register name register function b7 b6 b5 b4 b3 b2 b1 b0 20h channel number selection ch3 ch2 ch1 ch0 20h change parameter selection vm fr 21h block number selection bl3 bl2 bl1 bl0 21h frequency number selection fr11 fr10 fr9 fr8 22h fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 23h start address selection st15 st14 st13 st12 st11 st10 st9 st8 24h st7 st6 st5 st4 st3 st2 st1 st0 25h waveform format selection wbs 25h repeat number selection re14 re13 re12 re11 re10 re9 re8 26h re7 re6 re5 re4 re3 re2 re1 re0 27h envelope type selection env1 env0 27h attach and release selection a_r 27h left volume controller vl9 vl8 29h vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 27h right volume controller vr9 vr8 2ah vr7 vr6 vr5 vr4 vr3 vr2 vr1 vr0 * " + * * " + * , - " #

! '

! & & . , ' / 0
1 . ' 0 2 0 3 # 2 # 3 '
'
2 3 " 2 " 4 5 " " 5 " " input/output ports
ht36a0 rev. 1.00 17 september 3, 2002 ch[3~0] channel number selection the ht36a0 has a built-in 16 output channels and ch[3~0] is used to define which channel is selected. when this register is written to, the wavetable synthe - sizer will automatically output the dedicated pcm code. so this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined. change parameter selection these two bits, vm and fr, are used to define which register will be updated on this selected channel. there are two modes that can be selected to reduce the process of setting the register. please refer to the statements of the following table: vm fr function 0 0 update all the parameter 0 1 only update the frequency number 1 0 only update the volume output frequency definition the data on bl3~0] and fr[11~0] are used to define the output speed of the pcm file, i.e. it can be used to generate the tone scale. when the fr[11:0] is 800h and bl[3:0] is 6h, each sample data of the pcm code will be sent out sequentially. when the f osc is 12mhz, the formula of a tone fre- quency is: f out =f record 50khz sr fr [11 ~ 0] 2 (17 bl [3~0]) where f out is the output signal frequency, f record and sr is the frequency and sampling rate on the sample code, respectively. so if a voice code of c3 has been recorded which has the f record of 261hz and the sr of 11025hz, the tone frequency (f out ) of g3: f out =196hz. can be obtained by using the fomula: 196hz= 261hz 50khz 11025hz fr[11 ~ 0] 2 (17 bl [3~0]) a pair of the values fr[11~0] and bl[3~0] can be de - termined when the f osc is 12mhz. start address definition the ht36a0 provides two address types for extended use, one is the program rom address which is pro - gram counter corresponding with pf value, the other is the start address of the pcm code. the st[15~0] is used to define the start address of each pcm code and reads the waveform data from this location. the ht36a0 provides 16 input data lines from wa[15~0], the st[15~0] is used to locate the major 16 bits i.e. wa[15~5] and the undefined data from wa[4~0] is always set as 00000b. in other words, the wa[15~0]=st[15~0] 2 5 . so each pcm code has to be located at a multiple of 32. otherwise, the pcm code will not be read out correctly because it has a wrong start code. waveform format definition the ht36a0 accepts two waveform formats to ensure a more economical data space. wbs is used to define the sample format of each pcm code. wbs=0 means the sample format is 8-bit wbs=1 means the sample format is 12-bit the 12-bit sample format allocates location to each sample data. please refer to the waveform format statement as shown below. repeat number definition the repeat number is used to define the address which is the repeat point of the sample. when the re - peat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80h) until the volume become close. the re[14~0] is used to calculate the repeat address of the pcm code. the process for setting the re[14~0] is to write the 2 s complement of the repeat length to re[14~0], with the highest carry ignored. the ht36a0 will get the repeat address by adding the re[14~0] to the address of the end code, then jump to the address to repeat this range. left and right volume control the ht36a0 provides the left and right volume control independently. the left and right volume are con - trolled by vl[9~0] and vr[9~0] respectively. the chip provides 1024 levels of controllable volume, the 000h is the maximum and 3ffh is the minimum output vol - ume. envelope type definition the ht36a0 provides a function to easily program the envelope by setting the data of env[1~0] and a_r. it forms a vibrato effect by a change of the volume to at - tach and release alternately. the a_r signal is used to define the volume change in attach mode or release mode and env[1~0] is used to define which volume control bit will be changeable. on the attach mode, the control bits will be sequen - tially signaled down to 0. on the release mode, the control bits will be sequentially signaled up to 1. the relationship is shown in the following table. # 6 # 4 # # 7 # 8 # 3 # 9 # : ( 6 ( 6 : 6 4 : 4 0 ' !
; #
< = 9 . # 6 . # 4 (
> ? : ? : ! < < ? ? < < ? ( ? (
% < < 0 ' !
waveform format
ht36a0 rev. 1.00 18 september 3, 2002 the pcm code definition the ht36a0 can only solve the voice format of the signed 8-bit raw pcm. and the mcu will take the voice code 80h as the end code. so each pcm code section must be ended with the end code 80h. d/a converter interface ht36a0 provides the iis serial data format to support the multiple d/a converters, one bit clock output and a word clock signal for left/right stereo serial data transmission. clock signal the bit clock output signals dck are used to synchronize the iis serial data. the word clock signal load divides the serial data into left channel and right channel data for two-way audio out- put. load the word clock signal load is used for iis serial data. the stereo serial data consists of 16-channel sound generator. on iis format, a h state on load is used for the right channel, and a l state is used for the left channel. dck dck bit clock is the clock source for the signal. stereo serial data format the audio output data is in serial mode with 16 bit digi - tal signal and lsb first output. there is a high sam - pling rate of 50khz when the system clock is 12.8mhz and with two channel outputs for right/left channel. ht36a0 provides only one serial data format as iis mode. the user could directly connect a d/a con - verter which can accept the iis serial data format, like ht82v731. mask option no. mask option function 1 wdt source on-chip rc/instruction clock/ disable wdt 2 clrwdt times one time, two times (clr wdt1/wdt2) 3 wake-up pa only 4 pull-high pa, pb, pc, pd input 5 osc mode crystal or resistor type 6 i/o dac pin pd1~3 dac pin selection 7 lvr option low voltage reset option # + " 0 0 ( # # ' ! ( $ d/a converter timing a_r env1 env0 volume control bit control bit final value mode 0 0 0 vl2~0, vr2~0 111b release mode 0 0 1 vl1~0, vr1~0 11b 0 1 0 vl0, vr0 1b x 1 1 no bit unchanged no change mode 1 0 0 vl2~0, vr2~0 000b attach mode 1 0 1 vl1~0, vr1~0 00b 1 1 0 vl0, vr0 0b envelope type definition
application circuit normal ht36a0 rev. 1.00 19 september 3, 2002 # " ! % $ " 1 " $
( 2 ( $ 0 ( 1 + $ $ " " # ' . + ' . " : 2 ( & % # " $ " 1 " % 8 ' ! & &
package information 48-pin dip outline dimensions symbol dimensions in mil min. nom. max. a 2435 2445 b 535 555 c 145 155 d 125 145 e16 20 f50 70 g 100 h 595 615 i 635 670 0 15 ht36a0 rev. 1.00 20 september 3, 2002
)
# ( % 1
ht36a0 rev. 1.00 21 september 3, 2002 copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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