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1 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary general description EM73A83 is an advanced single chip cmos 4-bit micro-controller. it contains 16k-byte rom, 500-nibble ram, 4-bit alu, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. EM73A83 also equipped with 6 interrupt sources, 3 i/o ports (including 1 input port and 2 bidirection ports), lcd display (40x16), built-in sound generator and speech synthesizer. it's low power consumption and high speed feature are further strengten with dual, slow, idle and stop operation mode for optimized power saving. features ? operation voltage : 2.2v to 4.8v. clock source : dual clock system. low-frequency oscillator is 32 khz crystal oscillator or rc oscillator by mask option and high-frequency oscillator is a built-in internal oscillator (4.6 mhz). instruction set : 107 powerful instructions. instruction cycle time : 1.7s for 4.6m hz (high speed clock). 244s for 32768 hz (low speed clock). rom capacity : 16k x 8 bits. ram capacity : 500 x 4 bits. input port : 1 port (p0.0-p0.3), idle/stop releasing function is available by mask option. (each input pin has a pull-up and pull-down resistor available by mask option). bidrection port : 2 ports (p4, p8). idle/stop release function for p8(0..3) is available by mask option. built-in watch-dog-timer counter : it is available by mask option. 12-bit timer/counter : two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement mode. built-in time base counter : 22 stages. subroutine nesting : up to 13 levels. interrupt : external interrupt . . . . . . 2 input interrupt sources. internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt. 1 speech interrupt. lcd driver : 40x16 dots, 1/16 duty, 1/5 bias with voltage multiplier. sound effect : tone generator and random generator. speech synthesizer : 160k speech data rom (use as 160k nibbles data rom). power saving function : slow, idle, stop operation modes. package type : chip form 85 pins.
2 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary symbol pin-type function v dd, v dd2 power supply (+) v ss power supply (-) reset reset-a system reset input signal, low active mask option : none pull-up clk osc-g capacitor connecting pin for internal high frequency oscillator. lxin osc-b/osc-h crystal/resistor connecting pin for low speed clock source. lxout osc-b crystal connecting pin for low speed clock source. p0(0..3)/wakeup0..3 input-b 4-bit input port with idle/stop releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p4(0..3) i/o-o 4-bit bidirection i/o port with high current source. mask option : open-drain push-pull, high current pmos push-pull, low current pmos p8.0(int1)/wakeupa i/o-l 2-bit bidirection i/o port with external interrupt sources input and idle p8.2(int0)/wakeupc /stop releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain p8.1(trgb)/wakeupb i/o-l 2-bit bidirection i/o port with time/counter a,b external input and idle p8.3(trga)/wakeupd /stop releasing function function block diagram pin descriptions interrupt control time base timer/counter (ta,tb) system control instruction decoder instruction register rom pc data bus reset control clock generator timing generator clock mode control data pointer acc alu flag zc s stack pointer stack ram hr lr i/o control p0.0/wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 p4.0 p4.1 p4.2 p4.3 p8.0(int1)/wakeupa p8.1(trgb)/wakeupb p8.2(int0)/wakeupc p8.3(trga)/wakeupd reset clk lxout speech synthesizer lcd driver v1~v5 va,vb com0~com15 bz1 bz2 seg0~seg39 lxin
3 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary symbol pin-type function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain bz1, bz2 speech output pins v1, v2, v3, v4, v5, lcd bias pins va, vb com0~com15 lcd common output pins seg0~seg39 lcd segment output pins test tie vss as package type, no connecting as cob type. . . . scall, subroutine call entry address data table for [ldax],[ldaxi] instruction subroutine call entry address designated by [lcall a] instruction bank 1 bank 2 bank 3 reset start address int0 ; interrupt service routine entry address trga trgb tbi int1 0000h 0002h 0004h 0006h 0008h 000ah 000ch 000eh 0086h 07ffh 0800h 0fffh 1000h 1fffh spi function descriptions program rom ( 16k x 8 bits ) 16 k x 8 bits program rom contains user's program and some fixed data. the basic structure of the program rom may be categorized into 5 partitions. 1. address 0000h: reset start address. 2. address 0002h - 000ch : 6 kinds of interrupt service routine entry addresses. 3. address 000eh-0086h : scall subroutine entry address, only available at 000eh, 0016h, 001eh, 0026h, 002eh, 0036h, 003eh, 0046h, 004eh, 0056h, 005eh, 0066h, 006eh, 0076h, 007eh,0086h. 4. address 0000h - 07ffh : lcall subroutine entry address. 5. address 0000h - 1fffh : except used as above function, the other region can be used as user's program and data region. address bank 0 :
4 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary user's program and fixed data are stored in the program rom. user's program is executed using the pc value to fetch an instruction code. the 16kx8 bits program rom can be divided into 4 banks. there are 4kx8 bits per bank. the program rom bank is selected by p3(1..0). the program counter is a 13-bit binary counter. the pc and p3 are initialized to "0" during reset. when p3(1..0)=00b, the bank0 and bank1 of program rom will be selected. p3(1..0)=01b, the bank0 and bank2 will be selected. address p3=xx00b p3=xx01b p3=xx10b 0000h : : bank0 bank0 bank0 0fffh 1000h : : bank1 bank2 bank3 1fffh program example : bank 0 start: : : : ldia #00h ; set program rom to bank1 outa p3 b xa1 : xa : : : ldia #01h ; set program rom to bank2 outa p3 b xb1 : xb : : : ldia #02h ; set program rom to bank3 outa p3 b xc1 : xc : : : bxd xd : : : : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 1 xa1 : : : bxa : xa2 : :
5 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary b xa2 : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 2 xb1 : : : bxb : xb2 : : b xb2 : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 3 xc1 : : : bxc : xc2 : : b xc2 fixed data can be read out by table-look-up instruction. table-look-up instruction is requires the data point (dp) to indicate the rom address in obtaining the rom code data (except bank 0) : ldax acc rom[dp] l ldaxi acc rom[dp] h ,dp+1 dp is a 12-bit data register that stores the program rom address as pointer for the rom code data. user has to initially load rom address into dp with instructions "stadpl", and "stadpm, stadph", then then to obtain the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi" program example: read out the rom code of address 1777h by table-look-up instruction. ldia #07h; stadpl ; [dp] l 07h stadpm ; [dp] m 07h stadph ; [dp] h 07h, load dp=777h : ldl #00h; ldh #03h; ldax ; acc 6h stami ; ram[30] 6h ldaxi ; acc 5h stam ; ram[31] 5h ; org 1777h data 56h; data ram ( 500-nibble ) a total 500 - nibble data ram is available from address 000 to 1ffh data ram includes the zero page region, stacks and data areas.
6 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary zero- page: from 000h to 00fh is the zero-page location. it is used as the zero-page address mode pointer for the instruction of "std #k,y; add #k,y; clr y,b; cmp k,y". program example: to write immediate data "07h" to ram [03] and to clear bit 2 of ram [0eh]. std #07h, 03h ; ram[03] 07h clr 0eh,2 ; ram[0eh] 2 0 stack: there are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and call). user can assign any level be the starting stack by providing the level number to stack pointer (sp). when an instruction (call or interrupt) is invoked, before enter the subroutine, the previous pc address is saved into the stack until returned from those subroutines, the pc value is restored by the data saved in stack. data area: except the area used by user's application, the whole ram can be used as data area for storing and loading general data. addressing mode the 500 nibble data memory consists of two banks (bank 0 and bank 1). there are 244x4 bits (address 000h~0f3h) in bank 0 and 256x4 bits (address 100h~1ffh) in bank 1. increment address 020h - 02fh 0c0h - 0cfh 0d0h - 0dfh 0e0h - 0efh level 0 level 4 level 8 level 12 level 1 level 5 level 9 level 2 level 6 level 10 level 3 level 7 level 11 increment zero-page 000h - 00fh 010h - 01fh 0f0h - 0f3h : : : 110h - 11fh 1e0h - 1efh 1f0h - 1ffh 100h - 10fh : : : bank 0 bank 1
7 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary p9.3 instruction field ram address xxxx xxxx xxxx xxxx 0 instruction field ram address yyyy 0000 yyyy program example: load the data of ram address "143h" to ram address "023h". sep p9,3 ; p9.3 1 lda 43h ; acc ram[143h] clp p9,3 ; p9.3 0 sta 23h ; ram[023h] acc (3) zero-page addressing mode: the zero-page is in the bank 0 (address 000h~00fh). the address is the lower 4 bits code of the second byte in the instruction field. program example: write immediate "0fh" to ram address "005h". std #0fh, 05h ; ram[05h] 0fh the bank is selected by p9.3. when p9.3 is cleared to "0", the bank 0 is selected. when p9.3 is set to "1", the bank 1 is selected. the data memory consists of three address mode, namely - (1) indirect addressing mode: the address in the bank is specified by the hl registers. program example: load the data of ram address "143h" to ram address "032h". sep p9,3 ; p9.3 1 ldl #3h ; lr 3 ldh #4h ; hr 4 ldam ; acc ram[134h] clp p9,3 ; p9.3 0 ldl #2h ; lr 2 ldh #3h ; hr 3 stam ; ram[023h] acc (2) direct addressing mode: the address in the bank is directly specified by 8 bits code of the second byte in the instruction field. p9.3 hr lr r am address
8 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary +2 program counter (16k rom) program counter ( pc ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program rom instruction. for branch and call instructions, pc is changed by instruction indicating. pc only can indicate the address from 0000h-1fffh. the bank number is decided by p3. (1) branch instruction: sbr a object code: 00aa aaaa condition: sf=1; pc pc 12-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc pc +1( branch condition not satisified) pc original pc value + 1 lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc pc 12.a ( branch condition satisified ) pc hold a a a a a aaaaaaa sf=0; pc pc +2( branch condition not satisified) pc original pc value + 2 slbr a object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1fffh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0fffh) condition: sf=1; pc a ( branch condition satisified) pcaaaaaaaaaaaa a sf=0 ; pc pc + 3 ( branch condition not satisified ) pc original pc value + 3 (2) subroutine instruction: scall a object code: 1110 nnnn condition : pc a ; a=8n+6 ; n=1..fh ; a=86h, n=0 pc00000 aaaaa aaa lcall a object code: 0100 0aaa aaaa aaaa condition: pc a
9 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc. the interrupt vectors are as follows : int0 (external interrupt from p8.2) pc00000000000 1 0 spi (speech end interrupt) pc000000000010 0 trga (timer a overflow interrupt) pc0000000000 1 1 0 trgb (time b overflow interrupt) pc00000000 0 1 0 0 0 tbi (time base interrupt) pc00000000 0 1 0 1 0 int1 (external interrupt from p8.0) pc00000000 0 1 1 0 0 (4) reset operation: pc00000000000 0 0 pc00aaaaaaaaaa a ret object code: 0100 1111 condition: pc stack[sp]; sp + 1 pc the return address stored in stack rt i object code: 0100 1101 condition : flag. pc stack[sp]; ei 1; sp + 1 pc the return address stored in stack
10 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 for 3-byte instruction execution: pc + 3 accumulator accumulator(acc) is a 4-bit data register for temporary data storage. for the arithematic, logic and comparative opertion.., acc plays a role which holds the source data and result. flags there are three kinds of flag, cf (carry flag), zf (zero flag) and sf (status flag), these three 1-bit flags are included by the arithematic, logic and comparative .... operation. all flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after rti instruction is executed. (1) carry flag ( cf ) the carry flag is affected by the following operations: a. addition : cf as a carry out indicator, under addition operation, when a carry-out occures, the cf is "1", likewise, if the operation has no carry-out, cf is "0". b. subtraction : cf as a borrow-in indicator, under subtraction operation, when a borrow occures, the cf is "0", likewise, if there is no borrow-in, the cf is "1". c. comparision: cf as a borrow-in indicator for comparision operation as in the subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : under tfcfc instruction, the cf content is sent into sf then clear itself as "0". under ttsfc instruction, the cf content is sent into sf then set itself as "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generates a "0" result, the zf is "1", likewise, the zf is "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status. a. sf is initiated to "1" for reset condition. b. branch instruction is decided by sf, when sf=1, branch condition is satisified, likewise, when sf = 0, branch condition is unsatisified.
11 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary program example: check following arithematic operation for cf, zf, sf cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0 alu the arithematic operation of 4 - bit data is performed in alu unit . there are 2 flags that can be affected by the result of alu operation, zf and sf. the operation of alu is affected by cf only. alu structure alu supported user arithematic operation functions, including addition, subtraction and rotaion. alu function (1) addition: alu supports addition function with instructions addam, adcam, addm #k, add #k,y .... . the addition operation affects cf and zf. under addition operation, if the result is "0", zf will be "1", otherwise, zf will be "0", when the addition operation has a carry-out. cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: alu supports subtraction function with instructions subm #k, suba #k, sbcam, decm... . the subtraction operation affects cf and zf. under subtraction operation, if the result is negative, cf will be "0", and a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf is "1", likewise, zf is "1". zf cf sf alu data bus
12 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 (3) rotation: two types of rotation operation are available, one is rotation left, the other is rotation right. rlca instruction rotates acc value counter-clockwise, shift the cf value into the lsb bit of acc and hold the shift out data in cf. rrca instruction operation rotates acc value clockwise, shift the cf value into the msb bit of acc and hold the shift out data in cf. program example: to rotate acc clockwise (right) and shift a "1" into the msb bit of acc. ttcfs; cf 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register are two 4-bit registers, they are used as a pair of pointer for the ram memoryaddress. they are used as also 2 independent temporary 4-bit data registers. for certain instructions, l register can be a pointer to indicate the pin number ( port4 only ). hl register structure hl register function (1) hl register is used as a temporary register for instructions : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah. program example: load immediate data "5h" into l register, "0dh" into h register. ldl #05h; ldh #0dh; (2) hl register is used as a pointer for the address of ram memory for instructions : ldam, stam, stami .., program example: store immediate data "#0ah" into ram of address 35h.
13 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary clock and timing generator the clock generator is supported by a dual clock system. the high-frequency oscillator is internal oscillator, the working frequency is 4.6 mhz. the low-frequency oscillator may be sourced from crystal or rc oscillator as defined by mask option, the working frequency is 32 khz. clock generator structure there are two clock generator for system clock control unit, p14 is the status register that hold the cpu status. p16, p19 and p22 are the command register for system clock mode control. ldl #5h; ldh #3h; stdmi #0ah; ram[35] ah (3) l register is used as a pointer to indicate the bit of i/o port for instructions : selp, clpl, tfpl, (when lr = 0 indicate p4.0) program example: to set bit 0 of port4 to "1" ldl #00h; sepl ; p4.0 1 stack pointer (sp) stack pointer is a 4-bit register that stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition. when a new subroutine is received, the sp is decreased by one automatically, likewise, if returning from a subroutine, the sp is increased by one. the data transfer between acc and sp is done with instructions "ldasp" and "stasp". data pointer (dp) data pointer is a 12-bit register that stores the rom address can indicating the rom code data specified by user (refer to data rom). high-frequency generator system clock mode control fc fs system control crystal connection lxin open lxout p14 p16 p22 p19 low-frequency generator lxin clk lxout lxin lxout vdd r rc oscillator connection r=1.2m ?
14 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary system clock mode control the system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73A83 has four operation modes (dual, slow,idle and stop operation modes). operation mode oscillator system clock available function one instruction cycle normal high, low frequency high frequency clock lcd, speech, sound gen. 8 / fc slow low frequency low frequency clock lcd 8 / fs idle low frequency cpu stops lcd - stop none cpu stops all disable - dual operation mode the 4-bit c is in the dual operation mode when the cpu is reseted. this mode is dual clock system (high-frequency and low-frequency clocks oscillating). it can be changed to slow or stop operation mode with the command register (p22 or p16). lcd display, speech synthesizer and sound generator are available for the dual operation mode. slow operation mode the slow operation mode is single clock system (low-frequency clock oscillating). it can be changed to the dual operation mode with the command register (p22), stop operation mode with p16 and idel operation mode with p19. lcd display is available for the slow operation mode. speech synthesizer and sound generator are disabled in this mode. stop operation mode normal operation mode idle (cpu stops) slow operation mode reset operation high osc : stopped low osc : stopped high osc : stopped low osc : oscillating high osc : oscillating low osc : oscillating high osc : stopped low osc : oscillating command (p16) command (p16) command (p22) command (p22) command (p19) reset reset reset reset reset release i/o wakeup i/o or internal timer wakeup
15 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary p22 3210 initial value : 0000 * som som select operation mode 0 0 0 dual operation mode 1 * * slow operation mode p14 32 10 initial value : *000 * wks lfs cpus lfs low-frequency status cpus cpu status 0 lxin source is not stable 0 dual operation mode 1 lxin source is stable 1 slow operation mode wks wakeup status 0 wakeup not by internal timer 1 wakeup by internal timer port14 is the status register for cpu. p14.0 (cpu status) and p14.1 (low-frequency status) are read-only bits. p14.2 (wakeup status) will be set as "1" when cpu is waked by internal timer. p14.2 will be cleared as "0" when user out data to p14. idle operation mode the idle operation mode suspends all cpu functions except the low-frequency clock oscillation and the lcd driver. it keeps the internal status with low power consumption without stopping the slow clock oscillator and lcd display. lcd display is available for the idle operation mode. sound generator is disabled in this mode. the idle operation mode will be wakeup and return to the slow operation mode by the internal timing generator or i/o pins (p0(0..3)/wakeup 0..3 and p8(0..3)/wakeupa..d). p19 32 10 initial value : 0000 * idme sidr idme enable idle mode sidr select idle releasing condition 1 enable idle mode 0 0 p0(0..3), p8(0..3) pin input 0 no function 0 1 p0(0..3), p8(0..3) pin input and 1 sec signal 1 0 p0(0..3), p8(0..3) pin input and 0.5 sec signal 1 1 p0(0..3), p8(0..3) pin input and 15.625 ms signal stop operation mode the stop operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. this mode will be released by reset or i/o pins (p0(0..3)/ wakeup 0..3 and p8(0..3)/wakeup a..d). lcd display and sound generator are disabled in the stop operation mode.
16 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary p16 3210 initial value : 0000 * spme swwt spme enable stop mode swwt set wake-up warm-up time 1 enable stop mode 0 0 2 14 /lxin 0 no function 0 1 2 10 /lxin 10 2 12 /lxin 1 1 no function time base interrupt (tbi ) the time base can be used to generate a single fixed frequency interrupt. eight types of frequencies can be selected with the "p25" setting. p25 3 2 1 0 i nitial value : 0000 p25 dual operation mode slow operation mode 0 0 x x interrupt disable interrupt disable 0 1 0 0 interrupt frequency lxin / 2 3 hz reserved 0 1 0 1 interrupt frequency lxin / 2 4 hz reserved 0 1 1 0 interrupt frequency lxin / 2 5 hz reserved 0 1 1 1 interrupt frequency lxin / 2 14 hz interrupt frequency lxin / 2 14 hz 1 1 0 0 interrupt frequency lxin / 2 1 hz reserved 1 1 0 1 interrupt frequency lxin / 2 6 hz interrupt frequency lxin / 2 6 hz 1 1 1 0 interrupt frequency lxin / 2 8 hz interrupt frequency lxin / 2 8 hz 1 1 1 1 interrupt frequency lxin / 2 10 hz interrupt frequency lxin / 2 10 hz 1 0 x x reserved reserved timer / counter ( timera, timerb) timer/counters support three special functions: 1. even counter 2. timer. 3. pulse-width measurement. these three functions can be executed by 2 timer/counter independently. with timera, the counter data is saved in timer register tah, tam, tal. user can set counter initial value and read the counter value by instruction "ldatah(m,l)" and "statah(m,l)". with timer b register is tbh, tbm, tbl and the w/r instruction are "ldatbh (m,l)" and "statbh (m,l)". the basic structure of timer/counter is composed by two identical counter module, these two modules can be set initial timer or counter value to the timer registers, p28 and p29 are the command registers for timera and timer b, user can choose different operation modes and internal clock rates by setting these two registers. when timer/counter overflows, it will generate a trga(b) interrupt request to interrupt control unit.
17 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary port 28 3 2 1 0 tmsa ipsa initial state: 0000 timer/counter mode selection tmsa (b) function description 0 0 stop 0 1 event counter mode 1 0 timer mode 1 1 pulse width measurement mode port 29 3 2 1 0 tmsb ipsb initial state: 0000 interrupt control trga request p8.3/ trga event counter control timer control internal clock p28 12 bit counter tmsa ipsa data bus p8.1/ trgb event counter control timer control internal clock p29 12 bit counter tmsb ipsb trgb request pulse-width measurement control pulse-width measurement control timer/counter control p8.1/trgb, p8.3/trga are the external timer inputs for timerb and timera, they are used in event counter and pulse-width measurement mode. timer/counter command port: p28 is the command port for timer/countera and p29 is for the timer/ counterb. ipsa(b) dual mode 0 0 lxin/2 hz 0 1 lxin/2 hz 1 0 lxin/2 hz 1 1 lxin/2 hz internal pulse-rate selection 3 7 11 15 7 11 15 slow mode reserved lxin/2 hz lxin/2 hz lxin/2 hz
18 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary program example: to generate trga interrupt request after 60 ms with system clock lxln=32khz ldia #0100b; exae; enable mask 2 eicil 110111b; interrupt latch 0, enable ei ldia #0ah; statal; ldia #00h; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: lxin/2 3 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: lxin/2 3 ; lxin = 32khz the time of timer counter count one = 2 3 /lxin = 8/32768=0.244ms the number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0f6h the preset value of timer/counter register = 1000h - 0f6h = f0ah pulse width measurement mode internal pulse timerb (timera )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 p8.1/trgb (p8.3/trga) timerb (timera) value n n+1 n+2 n+3 n+4 n+5 n+6 timer/counter function timer/countera,b are programmable for timer, event counter and pulse width measurement mode. each timer/counter can execute any of these functions independently. event counter mode under event counter mode, the timer/counter is increased by one at any rising edge of p8.1/trgb for timerb (p8.3/trga for timer a). when timerb (timera) counts overflow, it will provide an interrupt request trgb (trga) to interrupt control unit. program example: enable timera with p28 ldia #0100b; outa p28; enable timera with event counter mode timer mode under timer mode ,the timer/counter is increased by one at any rising edge of internal pulse. user can choose up to 4 types of internal pulse rate by setting ipsb for timerb (ipsa for timera). when timer/counter counts overflow, an interrupt request will be sent to interrupt control unit.
19 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary program example: enable timera by pulse width measurement mode. ldia #1100b; outa p28; enable timera with pulse width measurement mode. interrupt function six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources. multiple interrupts are admitted according to their priority. type interrupt source priority interrupt interrupt program rom latch enable condition entry address external external interrupt(int0) 1 il5 ei=1 002h internal speech end interrupt (spi) 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt(int1) 6 il0 ei=1,mask0=1 00ch internal pulse timerb(timera) value n n+1 n+2 n+3 n+4 n+5 p 8.1/trgb(p8.3/trga) interrupt controller: il0-il5 : interrupt latch. hold all interrupt requests from all interrupt sources. il's can not be set by program, but can be reset by program or system reset, so il can only decide which interrupt source can be accepted. mask0-mask3 : except int0, mask register may permit or inhibit all interrupt sources. interrupt structure reset by system reset and program instruction mask0 mask1 mask1 mask2 mask3 il0 int1 r0 il1 tbi r1 il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb spi under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during external timer/counter input (p8.1/trgb, p8.3/trga ) in high level, interrupt request is generated as soon as timer/counter count overflow.
20 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary lcd driver it can directly drive the liquid crystal display ( lcd ) and has 40 segments, 16 commons output pins. there are total 40x16 dots can be display. the v1~v5 are the lcd bias voltage input pins. (1) lcd driver control command register: port27 3210 initial value: 0000 ldc * * lcd display control ldc function description 0 0 lcd display disable 0 1 blanking 1 0 no function 1 1 lcd display enable * : don't care. p27 is the ldc driver control command register. the initial value is 0000. when ldc ( bit2 and bit3 of p27 ) is set to "00", the lcd display is disabled. when ldc is set to "01", the lcd is blanking, the com pins are inactive and the seg pins output the display data continuously. when ldc is set to "11", the lcd display is enabled. (2) lcd display data area: the lcd display data is stored in the display data area of the data memory (ram). the lcd display data area is as illustrated below : ei : enable interrupt flip-flop may promit or inhibit all interrupt sources, when inter- rupt occurs, ei is auto cleared to "0", after rti instruction is executed, ei is auto set to "1" again. priority checker : check interrupt priority when multiple interrupts occur. interrupt operation the procedure of interrupt operation : 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts occur. 5. clear the il with which interrupt source has already been accepted. 6. excute interrupt subroutine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack. set ei to accept other interrupt requests. program example: to enable interrupt of "int0, trga" ldia #0100b; exae; set mask register "1100b" eicil 010111b ; enable interrupt f.f. and clear il3 and il5
21 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary lcd display data area : bank1 p9.3=1 p26 is the start address register of lcd common pin. port26 3210 initial value: 0000 csa program example: ldia #0000b outa p26 ldia #1100b ; lcd display enable outa p27 ldia #1010b ; store 1010b to ram[101h] sep p9,3 sta 01h 100-10fh 110-11fh 120-12fh 130-13fh 140-14fh 150-15fh 160-16fh 170-17fh 180-18fh 190-19fh 1a0-1afh 1b0-1bfh 1c0-1cfh 1d0-1dfh 1e0-1efh 1f0-1ffh com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 012345 6789abcdef seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 csa 100- 109h 110- 119h 120- 129h 130- 139h 140- 149h 150- 159h 160- 169h 170- 179h 180- 189h 190- 199h 1a0- 1a9h 1b0- 1b9h 1c0- 1c9h 1d0- 1d9h 1e0- 1ef9h 1f0- 1f9h common start address register ram 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com7 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com8 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com9 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com10 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com11 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com12 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com13 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com14 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 com15 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 the display data from the display data area are automatically read out and send to the lcd driver directly by the hardware. therefore, the display patterns can be changed only by overwritting the contents of the display data area through software. the dispaly memory area that is not used to store the lcd display data could be used as the ordinary data memory.
22 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary (3) lcd waveform : (1/5 bias) (4) lcd drive voltage : the lcd bias voltage is supplied by voltage multiplier. the application circuit is illustated as below : v5 v4 v3 v2 v1 va vb 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f speech synthesizer block diagram of speech and sound effect : on : off com0 com0 com1 com15 seg0 seg0-com0 v5 v4 v3 v2 v1 vss com0 v5 v4 v3 v2 v1 vss com1 seg0 on seg0-com0 on seg0-com1 off seg0-com1 off frame freq.=64hz frame freq.=64hz * type a : * type b : s e g 0 p23,24 write p6 write p5 write p7 read sound effect generator set sound freq. p30 write set sound mode p17 write set sound effect amplitude pwm speech decoder speech rom bz1 bz2 set speech address (write 4 times) p7 write set data address (write 5 times) read data set sample rate p5.3 read speech active spi interrupt
23 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary EM73A83 speech synthesizer operates as following : 1. send the speech start address to the address latch by writing p6 four times. 2. choose the sampling rate, enable the speech synthesizer by writing p5. 3. the rom address counters send the rom address a6 .. a17 to the speech rom. 4. act is the speech acknowledge signal. when the speech synthesizer has voice output. act is high . when act is changed from high to low, the speech synthesizer can generate the speech ending interrupt spi. the act signal can be read from p5.3. speech synthesizer control speech sample rate control register (p5 write) : 3210 initial value : *111 sr sr sample rate selection sample rate 000 pwm on clk/64/1/3 24k port 5 -- initialization is "*111". 001 clk/64/1/4 18k port 6 -- initialization is pointed to the low- 010 clk/64/2/3 12k nibble of start address latch. 011 clk/64/2/4 9k 100 clk/64/3/3 8k clk=4.6 mhz 101 clk/64/3/4 6k 111 pwm off speech active flag (p5 read) : 3210 initial value : 0*** act * * * act is the speech acknowledge signal. when the speech synthesizer has voice output, act is high. when act is high low, the speech synthesizer can generate the speech ending interrupt spi. speech start address register (p6 write) : 3210 initial value : 1111 port 6 p6l1 p6l2 p6l3 p6l4 a9 a8 a7 a6 a13 a12 a11 a10 a17 a16 a15 a14 - - - - send the speech start address to the speech synthesizer by writing p6 four times. there is a pointer counter to point the address latch (p6l1, p6l2, p6l3, p6l4). it will increase one when write p6. so, the first time writing p6 to p6l1, the second time is p6l2, the third time is p6l3, the fourth time is p6l4 and the fifth time is p6l1 latch again, ... etc. the pointer counter point to p6l1 when cpu is reset or p5 is writen. in the normal operation mode, the speech synthesizer is available. in the other operation modes, it is disable.
24 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary program example: sp_adr1 equ 1234h ; the start address of the speech section : ldia #sp_adr1 outa p6 ldia #sp_adr1/10h outa p6 ldia #sp_adr1/100h outa p6 ldia #sp_adr1/1000h outa p6 ; set sample rate & start speech ldia #0010b outa p5 ; wait speech end wait ttp p5,3 ; get speech active flag b wait using speech rom as data rom the speech rom can be used for speech synthesizer and for data rom simutaneously. first, write initial address to p7 (five times), and after four cycles, you can read p7 to get data, and address counter increases one automatically.the following read operations must be at an internval of instruction cycles which are more than 3. the read operation should be all done before you leave normal mode and change to slow mode. get speech rom data (p7 read) : 3210 port 7 set speech rom address (p7 write) : 3210 port 7 p7l1 p7l2 p7l3 p7l4 p7l5 a3 a2 a1 a0 a7 a6 a5 a4 a11 a10 a9 a8 a15 a14 a13 a12 - - a17 a16 program example: d_adr1 equ 12345h ; the start address of the speech rom : ldia #d_adr1 outa p7 ldia #d_adr1/10h outa p7 ldia #d_adr1/100h outa p7 ldia #d_adr1/1000h outa p7 ldia #d_adr1/10000h outa p7
25 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary melody (sound effect) control one channel melody/sound effect output, controlled by port 23, 24, 17, and 30. there is a built-in sound effect. it includes the tone generator and random generator. the tone generator is a binary down counter and the random generator is a 9-bit liner feedback shift register. 2 2 clk/8 f1 f2x2 p23,p24 pwm ckt. p30 output control tone generator random generator 4 kinds of divider f2 sound effect command register (p30) there are 4 kinds of basic frequency for sound generator which can be selected by p30. the output of sound effect is tone and random combination. port30 3 2 1 0 bfreq smode initial value : 0000 bfreq basic frequency (f1) select smode sound generator mode 0 0 clk/16 0 0 disable 0 1 clk/32 0 1 tone output 1 0 clk/64 1 0 random output 1 1 reserved 1 1 tone+random output (clk=4.6mkz) sta temp nop ina p7 ; read d_adr1+1 tone frequency register (p23, p24) the 8-bit tone frequency register is p24 and p23. the tone frequency will be changed when user output the different data to p23. thus, the data must be output to p24 before p23 when users want to change the 8- bit tone frequency (tf). port24 port23 3 2 1 0 3 2 1 0 initial value : 1111 1111 higher nibble register lower nibble register ** f1=clk/2 x , f2=f1/(tf+1)/2, tf=1~255, tf-0 ** example : clk=4.6 mhz, bfreq=10, tf=00110001b. ? f1=71680 hz, f2=71680hz/50/2=716.8 hz 3 cycles 4 cycles nop nop nop nop ; read data ina p7 ; read d_adr1
26 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary the basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit . the wdt counter counts for a certain time to check the cpu status, if there is no malfunction happened, the counter will be cleared and continue counting . otherwise, if there is a malfunction happened, the wdt control will send a wdt signal ( low active ) to reset cpu. the wdt checking period is assign by p21 ( wdt command port ). 0 wdt control wdt command port 12 3 counter clear request reset pin lxin/2 13 wdt counter p21 mask option tp ts tp= clk/64 (clk=4.6mhz) 1 program example: ldia #1001b ; basic frequency : clk/32, tone output outa p30 ldia #0111b ; volume control outa p17 ldia #0011b ; 1430 hz tone output outa p24 ldia #0001b outa p23 watch-dog-timer (wdt) watch-dog-timer can help user to detect the malfunction (runaway) of cpu and give system a timeup signal every certain time . user can use the time up signal to give system a reset signal when system is fail. this function is available by mask option. if the mask option of wdt is enabled, it will stop counting when cpu is reseted or in the stop operation mode. 123456789 + random generator f(x)=x 9 +x 4 +1 volume control register (p17) the are 16 levels of volume for sound generator. p17 is the volume control register. port17 initial value : 1111 3 2 1 0 vcr vcr ts/tp 1 1 1 1 15/16 1 1 1 0 14/16 :: 0 0 0 1 1/16 0 0 0 0 0/16
27 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary p21 is the control port of watch-dog-timer, and the wdt time up signal is connected to reset. port 21 3210 initial value :0000 cwc * * wdt cwc clear watchdog timer counter 0 clear counter then return to 1 1 nothing wdt set watch-dog-timer detect time 0 3 x 2 13 /lxin = 3 x 2 13 /32k hz = 0.75 sec 1 7 x 2 13 /lxin = 7 x 2 13 /32k hz = 1.75 sec program example to enable wdt with 7 x 2 13 /lxin detection time. ldia #0001b outa p21; set wdt detection time and clear wdt counter : : resetting function when cpu in normal working condition and reset pin is held in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : hardware condition in reset state initial value program counter 0000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p3, 9, 14, 16, 19, 21, 22, 25, 26, 27, 28, 29, 30 00h p5 07h p0, 4, 6, 7, 8, 17, 23, 24 0fh clk, lxin start oscillation the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset
28 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary EM73A83 i/o port description : port input function output function note 0 e input port , wakeup function 1-- -- 2-- -- 3 -- i p3(1..0) : rom bank selection 4 e input port e output port 5 i p5.3 : speech active signal (act) i speech sample rate register 6 -- i speech start address register 7 i data rom data i data start address register 8 e input port, wakeup function, e output port external interrupt input 9 -- i p9.3 : ram bank selection 10 -- -- 11 -- -- 12 -- -- 13 -- -- 14 i cpu status register -- 15 -- -- 16 i stop mode control register 17 i sound effect volume control register 18 -- 19 i idle mode control register 20 -- 21 i wdt control register 22 i dual/slow mode control register 23 i sound effect frequency register low nibble 24 i sound effect frequency register high nibble 25 i timebase control register 26 i lcd common start address register 27 i lcd control register 28 i timer/counter a control register 29 i timer/counter b control register 30 i sound effect command register 31 --
29 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary application circuit p0.0 p0.1 p0.2 bz1 bz2 reset vss va vb v5 v4 v3 v2 v1 lxout lxin clk 20p 32.768khz all 0.1 f 0.1 f 0.1 f seg0~ seg39 com0~ com15 lcd pannel v dd2 v dd EM73A83 100 ? reset 0.022 f 0.1 f 0.1 f v bat v bat 3v 100
30 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary absolute maximum ratings items sym. ratings conditions supply voltage v dd -0.5v to 6v input voltage v in -0.5v to v dd +0.5v output voltage v o -0.5v to v dd +0.5v power dissipation p d 300mw t opr =50 o c operating temperature t opr 0 o c to 50 o c storage temperature t stg -55 o c to 125 o c recommanded operating conditions items sym. ratings condition supply voltage v dd 2.2v to 4.8v input voltage v ih 0.90xv dd to v dd v il 0v to 0.10xv dd operating frequency f c 4.6mhz clk fs 32khz lxin,lxout supply current i dd - 0.5 1.2 ma v dd =3.3v,no load,normal mode,fs=32khz fc=4.6mhz -2538av dd =3.3v,no load,slow mode,fs=32khz lcd on -712av dd =3.3v,idle mode,lcd off - 0.1 1 a v dd =3.3v, stop mode hysteresis voltage v hys+ 0.50v dd - 0.75v dd v reset, p0, p8 v hys- 0.20v dd - 0.40v dd v input current i ih - - 1 a p0, reset, v dd =3.3v,v ih =3.3/0v - - 1 a open-drain, v dd =3.3v,v ih =3.3/0v i il - -250 -500 a push-pull, v dd =3.3v ,v il =0.4v,except p4 output voltage v oh 2.4 - - v push-pull, p4(high current pmos), sound, v dd =2.7v, i oh =-0.9ma 2.0 2.4 - v push-pull, p4(low current pmos), p8, v dd =2.7v, i oh =-40a v ol - 0.15 0.3 v v dd =2.7v,i ol =0.9ma, p4, p8 leakage current i lo - - 1 a open-drain, v dd =3.3v, v o =3.3v input resistor r in 100 200 300 k ? p0 150 300 450 k ? reset output current i oh 30 - - ma v dd =3v , v bz =1.5v of bz1, bz2 i ol 30 - - ma lcd bias voltage v 1 - 0.9 - v vdd=3v, lcd on load v 2 - 1.8 - v v 3 - 2.7 - v v 4 - 3.6 - v v 5 - 4.5 - v dc electrical characteristics (v dd =30.3v, v ss =0v, t opr =25 o c) parameters sym. min. typ. max. unit conditions
31 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary reset mask option lxin lxin lxout crystal osc. rc osc. p0/wakeup type input-a clk wakeup function mask option internal osc. : mask option vdd reset pin type type reset-a oscillation pin type type osc-b type osc-g input pin type type input-a type input-b type osc-h
32 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary i/o pin type type i/o type i/o-l path a : for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b : for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high. type i/o-n type i/o-o input data output data path b path a type i/o-n output data latch special function output : mask option : mask option mask option type i/o output data latch input data output data path b path a sel special function control input wakeup function mask option
33 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 com2 com1 com0 vss reset clk test lxin lxout vdd p4.0 p4.1 p4.2 p4.3 p0.0 p0.1 p0.2 p0.3 p8.0 p8.1 p8.2 p8.3 com8 com9 com10 com11 com12 com13 com14 com15 seg20 seg21 seg22 com23 com24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 vb va v5 v4 v3 v2 v1 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 vdd2 bz1 bz2 com3 EM73A83 (0,0) pad diagram pad no. symbol x y 1 seg9 -1400.8 1312.0 2 seg8 -1400.8 1191.4 3 seg7 -1400.8 1070.9 4 seg6 -1400.8 950.4 5 seg5 -1400.8 829.8 6 seg4 -1400.8 709.3 7 seg3 -1400.8 588.7 8 seg2 -1400.8 468.2 9 seg1 -1400.8 347.7 10 seg0 -1400.8 227.1 11 com7 -1400.8 106.6 12 com6 -1400.8 -14.0 13 com5 -1400.8 -134.5 14 com4 -1400.8 -255.0 15 com3 -1400.8 -375.6 16 com2 -1400.8 -496.1
34 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary pad no. symbol x y 17 com1 -1400.8 -616.7 18 com0 -1400.8 -737.2 19 vdd2 -1360.4 -859.4 20 bz1 -1354.9 -1052.0 21 bz2 -1354.9 -1266.7 22 vss -1111.5 -1290.1 23 reset -948.7 -1290.1 24 clk -828.1 -1290.1 25 test -707.6 -1290.1 26 lxin -580.4 -1290.1 27 lxout -459.9 -1290.1 28 vdd -298.6 -1275.5 29 p4.0 -170.6 -1290.1 30 p4.1 -48.5 -1290.1 31 p4.2 73.6 -1290.1 32 p4.3 195.8 -1290.1 33 p0.0 317.9 -1290.1 34 p0.1 440.1 -1290.1 35 p0.2 562.2 -1290.1 36 p0.3 684.3 -1290.1 37 p8.0 806.5 -1290.1 38 p8.1 928.6 -1290.1 39 p8.2 1050.7 -1290.1 40 p8.3 1172.9 -1290.1 41 com8 1293.4 -1295.0 42 com9 1414.0 -1295.0 43 com10 1405.0 -1158.0 44 com11 1405.0 -1037.5 45 com12 1405.0 -917.0 46 com13 1405.0 -796.4 47 com14 1405.0 -675.9 48 com15 1405.0 -555.3 49 seg20 1405.0 -434.8 50 seg21 1405.0 -314.3 51 seg22 1405.0 -193.7 52 seg23 1405.0 -73.2 53 seg24 1405.0 47.4 54 seg25 1405.0 167.9 55 seg26 1405.0 288.4 56 seg27 1405.0 409.0 57 seg28 1405.0 529.5 58 seg29 1405.0 650.1 59 seg30 1405.0 770.6
35 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary pad no. symbol x y 60 seg31 1405.0 891.1 61 seg32 1405.0 1011.7 62 seg33 1405.0 1132.2 63 seg34 1405.0 1252.8 64 seg35 1283.2 1289.5 65 seg36 1162.7 1289.5 66 seg37 1042.2 1289.5 67 seg38 921.6 1289.5 68 seg39 801.1 1289.5 69 vb 680.5 1289.5 70 va 560.0 1289.5 71 v5 439.5 1289.5 72 v4 318.9 1289.5 73 v3 198.4 1289.5 74 v2 77.8 1289.5 75 v1 -42.7 1289.5 76 seg19 -163.2 1289.5 77 seg18 -283.8 1289.5 78 seg17 -404.3 1289.5 79 seg16 -524.9 1289.5 80 seg15 -645.4 1289.5 81 seg14 -765.9 1289.5 82 seg13 -886.5 1289.5 83 seg12 -1007.0 1289.5 84 seg11 -1127.6 1289.5 85 seg10 -1248.1 1289.5 unit : m chip size : 3150 x 2930 m note : for pcb layout,ic substrate must be floated or connected to v ss .
36 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary instruction table (1) data transfer mnemonic object code ( binary ) operation description byte cycle flag cz s lda x 0110 1010 xxxx xxxx acc ram[x] 2 2 - z 1 ldam 0101 1010 acc ram[hl] 1 1 - z 1 ldax 0110 0101 acc rom[dp] l 12-z1 ldaxi 0110 0111 acc rom[dp] h ,dp+1 1 2 - z 1 ldh #k 1001 kkkk hr k11--1 ldhl x 0100 1110 xxxx xx00 lr ram[x],hr ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc k11-z1 ldl #k 1000 kkkk lr k11--1 sta x 0110 1001 xxxx xxxx ram[x] acc 2 2 - - 1 stam 0101 1001 ram[hl] acc 1 1 - - 1 stamd 0111 1101 ram[hl] acc, lr-1 1 1 - z c stami 0111 1111 ram[hl] acc, lr+1 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] k22--1 stdmi #k 1010 kkkk ram[hl] k, lr+1 1 1 - z c' tha 0111 0110 acc hr 1 1 - z 1 tla 0111 0100 acc lr 1 1 - z 1 (2) rotate mnemonic object code ( binary ) operation description byte cycle flag czs rlca 0101 0000 cf acc 11czc' rrca 0101 0001 cf acc 11czc' ( 3) arithmetic operation mnemonic object code ( binary ) operation description byte cycle flag c zs adcam 0111 0000 acc acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc acc+k 2 2 - z c' addam 0111 0001 acc acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ram[hl] +k 2 2 - z c' deca 0101 1100 acc acc-1 1 1 - z c decl 0111 1100 lr lr-1 1 1 - z c decm 0101 1101 ram[hl] ram[hl] -1 1 1 - z c inca 0101 1110 acc acc + 1 1 1 - z c'
37 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary incl 0111 1110 lr lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc k-acc 2 2 - z c sbcam 0111 0010 acc ram[hll - acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] k - ram[hl] 2 2 - z c ( 4) logical operation mnemonic object code ( binary ) operation description byte cycle flag czs anda #k 0110 1110 0110 kkkk acc acc&k 2 2 - z z' andam 0111 1011 acc acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc acc k 2 2 - z z' oram 0111 1000 acc acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ram[hl] k 2 2 - z z' xoram 0111 1001 acc acc^ram[hl] 1 1 - z z' (5) exchange mnemonic object code ( binary ) operation description byte cycle flag czs exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch mnemonic object code ( binary ) operation description byte cycle flag czs sbr a 00aa aaaa if sf=1 then pc pc 12-6 .a 5-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc a else null 2 2 - - 1 slbr a 0101 0101 1100 aaaa if sf=1 then pc a else null 3 3 - - 1 aaaa aaaa (a:1000~1fffh) 0101 0111 1100 aaaa aaaa aaaa (a:0000~0fffh) (7) compare mnemonic object code ( binary ) operation description byte cycle flag czs cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' - - - - - -
38 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary (8) bit manipulation mnemonic object code ( binary ) operation description byte cycle flag czs clm b 1111 00bb ram[hl] b 011--1 clp p,b 0110 1101 11bb pppp port[p] b 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b 022--1 sem b 1111 01bb ram[hl] b 111--1 sep p,b 0110 1101 01bb pppp port[p] b 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b 122--1 tf y,b 0110 1100 00bb yyyy sf ram[y] b '22--* tfa b 1111 10bb sf acc b '11--* tfm b 1111 11bb sf ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf port[p] b '22--* tfpl 0110 0001 sf port[lr 3-2 +4] lr 1-0 '1 2--* tt y,b 0110 1100 10bb yyyy sf ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf port[p] b 22--* (9) subroutine mnemonic object code ( binary ) operation description byte cycle flag czs lcall a 0100 0aaa aaaa aaaa stack[sp] pc, 2 2 - - - sp sp -1, pc a scall a 1110 nnnn stack[sp] pc, 1 2 - - - sp sp - 1, pc a, a = 8n + 6 (n =115 ),0086h (n = 0) ret 0100 1111 sp sp + 1, pc stack[sp] 1 2 - - - (10) input/output mnemonic object code ( binary ) operation description byte cycle flag czs ina p 0110 1111 0100 pppp acc port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] k22--1 outa p 0110 1111 000p pppp port[p] acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ram[hl] 2 2 - - 1 mnemonic object code ( binary ) operation description byte cycle flag czs cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c
39 * this specification are subject to be changed without notice. EM73A83 4-bit micro-controller for lcd product 10.31.2000 preliminary mnemonic object code ( binary ) operation description byte cycle flag czs tfcfc 0101 0011 sf cf', cf 0110-* ttcfs 0101 0010 sf cf, cf 1111-* tzs 0101 1011 sf zf 1 1 - - * (12) interrupt control mnemonic object code ( binary ) operation description byte cycle flag czs cil r 0110 0011 11rr rrrr il il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif 0,il il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif 1,il il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp sp+1,flag.pc 1 2 * * * stack[sp],eif 1 (13) cpu control mnemonic object code ( binary ) operation description byte cycle flag czs nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) operation description byte cycle flag czs ldadpl 0110 1010 1111 1100 acc [dp] l 22-z1 ldadpm 0110 1010 1111 1101 acc [dp] m 22-z1 ldadph 0110 1010 1111 1110 acc [dp] h 22-z1 ldasp 0110 1010 1111 1111 acc sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc [ta] l 22-z1 ldatam 0110 1010 1111 0101 acc [ta] m 22-z1 ldatah 0110 1010 1111 0110 acc [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc [tb] l 22-z1 ldatbm 0110 1010 1111 1001 acc [tb] m 22-z1 ldatbh 0110 1010 1111 1010 acc [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h acc 2 2 - - 1 (11) flag manipulation
40 * this specification are subject to be changed without notice. 10.31.2000 EM73A83 4-bit micro-controller for lcd product preliminary **** symbol description symbol description symbol description hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ? timer/counter a ? timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a [ta] m ([tb] m ) middle 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register [ta] h ([tb] h ) high 4-bit of timer/counter a lr 1 -0 contents of bit assigned by bit (timer/counter b) register 1 to 0 of lr lr 3-2 bit 3 to 2 of lr a 5-0 bit 5 to 0 of destination address for branch instruction pc 12-6 bit 12 to 6 of program counter transfer ? exchange + addition - substraction & logic and logic or ^ logic xor inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch - -

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