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| programmable radio on chip low powe r cyrf69213 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07552 rev. *b revised february 20, 2007 proc? lp features ? single device, two functions ? 8-bit, flash based usb peripheral mcu function and 2.4 ghz radio transceiver function in a single device ? flash-based microcontroller function ? m8c based 8-bit cpu, opti mized for human interface devices (hid) applications ? 256 bytes of sram ? 8 kbytes of flash memory with eeprom emulation ? in-system reprogrammable through d+/d? pins. ? 16-bit free running timer ? low power wake up timer ? 12-bit programmable interv al timer with interrupts ? watchdog timer ? industry-leading 2.4 ghz radio transceiver function ? operates in the unlicensed worldwide industrial, scientific and medical (ism) band (2.4 ghz?2.483 ghz) ? dsss data rates of up to 250 kbps ? gfsk data rate of 1 mbps ? ?97 dbm receive sensitivity ? programmable output power of up to +4 dbm ? auto transaction sequencer (ats) ? framing crc and auto ack ? received signal strength indication (rssi) ? automatic gain control (agc) ? component reduction ? integrated 3.3v regulator ? integrated pull up on d? ? gpios that require no external components ? operates off a single crystal ? flexible i/o ? high current drive on gpio pins. configurable 8-ma or 50-ma/pin current sink on designated pins ? each gpio pin supports high-impedance inputs, config- urable pull up, open-drain output, cmos/ttl inputs and cmos output ? maskable intrrupts on all i/o pins ? usb specification compliance ? conforms to usb specification version 2.0 ? conforms to usb hid specification version 1.1 ? supports one low speed usb device address ? supports one control endpoint and two data end points ? integrated usb transceiver ? operating voltage from 4.0v to 5.5v dc ? operating temperature from 0 to 70 c ? lead-free 40-lead qfn package ? advanced development tools based on cypress?s psoc ? to o l s microcontroller function radio function rfn rfp rfbias xtal 12mhz v reg v bat3 1-2 uf resv v ss 470nf p0_2:4,7 p1_6:7 p2_0:1 470nf gnd . . . . . . . irq/gpio miso/gpio xout/gpio pactl/gpio gnd vbus v dd_micro d+/d- 4.7uf p1.2 / v reg p1.5/mosi p1.4/sck p1.3/nss rst mosi sck nss v bat1 v bat2 v cc1 v cc2 v cc3 v io gnd . . . . . 2 2 2 4 proc? lp cyrf69213 block diagram [+] feedback [+] feedback
cyrf69213 document #: 001-07552 rev. *b page 2 of 85 applications the cyrf69213 proc lp low speed is targeted for the following applications: ? usb bridge for human in terface devices (hid) ?wireless mice ? wireless keyboards ? remote controls ? gaming applications ? usb bridge for general purpose applications ? consumer electronics ? industrial applications ? white goods ? home automation ? personal health functional description proc lp devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. communication between the mi crocontroller and the radio is via the spi interface between both functions. functional overview the cyrf69213 is a complete radio system-on-chip device, providing a complete rf system solution with a single device and a few discrete components. the cyrf69213 is designed to implement low-cost wirel ess systems operating in the worldwide 2.4-ghz industrial, scientific, and medical (ism) frequency band (2.400 ghz?2.4835 ghz). 2.4 ghz radio function the radio meets the following world-wide regulatory require- ments: ? europe ? etsi en 301 489-1 v1.4.1 ? etsi en 300 328-1 v1.3.1 ? north america ? fcc cfr 47 part 15 ? japan ? arib std-t66 data transmission modes the radio supports four different data transmission modes: ? in gfsk mode, data is transmi tted at 1 mbps without any dsss ? in 8dr mode, 1 byte is encoded in each pn code symbol transmitted ? in ddr mode, 2 bits are encoded in each pn code symbol transmitted ? in sdr mode, a single bit is encoded in each pn code symbol transmitted both 64-chip and 32-chip data pn codes are supported. the four data transmission modes apply to the data after the start of packet (sop). in particul ar, the packet length, data and crc are all sent in the same mode. usb microcontroller function the microcontroller function is based on the powerful cyrf69213 microcontroller. it is an 8-bit flash programmable microcontroller with integrated low speed usb interface. the microcontroller has up to 14 gpio pins to support usb, ps/2 and other applications. each gpio port supports high-impedance inputs, configurable pull up, open drain output, cmos/ttl inputs and cmos output. up to two pins support programmable drive strength of up to 50 ma. additionally each i/o pin can be used to generate a gpio interrupt to the microcontroller. each gpio port has its own gpio interrupt vector with th e exception of gpio port 0. the microcontroller features an internal oscillator. with the presence of usb traffic, the in ternal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). the proc lp has up to 8 kbytes of flash for user?s firmware code and up to 256 bytes of ram for stack space and user variables. the proc lp includes a watchdog timer, a vectored interrupt controller, a 12-bit programmab le interval timer with config- urable 1-ms interrupt and a 16-bit free running timer with capture registers. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 3 of 85 pinout pin name function 1 p0.4 individually configured gpio 2 xtal_in 12 mhz crystal. external clock in 3, 7, 16 v cc connected to pin 24 via 0.047- f capacitor. 4 p0.3 individually configured gpio 5 p0.1 individually configured gpio 6, 9, 39 v bat connected to pin 24 via 0.047- fshunt capacitor 8 p2.1 gpio. port 2 bit 1 10 rf bias rf pin voltage reference 11 rf p differential rf input to/from antenna 12 gnd ground 13 rf n differential rf to/from antenna 14, 17, 18, 20, 36 nc 15 p2.0 gpio. port 2 bit 0 19 resv reserved. must connect to gnd 21 d+ low-speed usb io 22 d? low-speed usb io 23 v dd_micro 4.0?5.5 for 12 mhz cpu/ 4.75?5.5 for 24 mhz cpu 24 p1.2 / v reg must be configured as 3.3v output. it must have a 1?2 f output capacitor 25 p1.3 / nss slave select spi pin 26 p1.4 / sck serial clock pin from mcu function to radio function 27 irq interrupt output, configure high/low or gpio 28 p1.5 / mosi master out slave in. 29 miso master in slave out, from radi o function.can be configured as gpio 30 xout bufferd clk, pactl_n or gpio 31 pactl control for external pa or gpio 32 p1.6 gpio. port 1 bit 6 33 v io i/o interface voltage. conne cted to pin 24 via 0.047 f 34 reset radio reset. connected to v dd via 0.47 f capacitor or to microcontroller gpio pin. must have a reset = high event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown. 35 p1.7 gpio. port 1 bit 7 36 v dd_1.8 regulated logic bypass. connected via 0.47 f to gnd 37 l/d connected to gnd 38 p0.7 gpio. port 0 bit 7 40 v reg connected to pin 24 41 e-pad connected to gnd [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 4 of 85 pinout diagram figure 1. pinout proc lp functional overview the soc is designed to implement wireless device links operating in the worldwide 2.4-ghz ism frequency band. it is intended for systems compliant with world-wide regulations covered by etsi en 301 489-1 v1.41, etsi en 300 328-1 v1.3.1 (europe), fcc cfr 47 part 15 (usa and industry canada) and telec arib_t66_march, 2003 (japan). the soc contains a 2.4-ghz 1-mbps gfsk radio transceiver, packet data buffering, packet framer, dsss baseband controller, received signal strength indication (rssi), and spi interface for data transfer and device configuration. the radio supports 98 discrete 1-mhz channels (regulations may limit the use of some of t hese channels in certain jurisdic- tions). in dsss modes the baseband performs dsss spreading/despreading, while in gfsk mode (1 mb/s - gfsk) the baseband performs start of frame (sof), end of frame (eof) detection and crc16 generation and checking. the baseband may also be configured to automatically transmit acknowledge (ack) handshake packets whenever a valid packet is received. when in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except sd r, enabling the implementation of mixed-rate systems in which different devices use different data rates. this also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low-moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. the mcu function is an 8-bit flash-programmable microcon- troller with integrated low- speed usb interface. the instruction set has been optimiz ed specifically for usb opera- tions, although it can be used for a variety of other embedded applications. the mcu function has up to eight kbytes of flash for user?s code and up to 256 bytes of ram for stack space and user variables. in addition, the mcu function includes a watchdog timer, a vectored interrupt controller, a 16-bit free-running timer, and 12-bit programmable interrupt timer. the mcu function supports in- system programming by using the d+ and d? pins as the serial programming mode interface. the programming protocol is not usb. backward compatibility the cyrf69213 ic is fully interoperable with the main modes of other cypress radios cywusb6934 and cyrf6936. the 62.5-kbps mode is supported by selecting 32-chip data_code_adr codes, ddr mode, and disabling the sop, length, and crc16 fields. similarly, the 15.675-khz mode is supported by selecting 64-chip data_code_adr codes and sdr mode. in this way, a suitably configured cyrf69213 ic device may transmit data to and/or receiv e data from a first generation device. 40-lead qfn 7 7 mm lf48a rf bias v bat xtal p2.1 v cc v bat p0.4 v cc p0.1 p0.3 v reg p0.7 p1.6 v bat l/d p1.7 pactl / gpio v io v dd_1.8 rst rf n nc p2.0 v cc nc nc resv nc gnd rf p v dd_micro p1.3 / ss p1.4 / sck irq / gpio p1.5 / mosi miso / gpio xout / gpio p1.2 / v reg d- d+ * e-pad bottom side 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 40 39 38 37 36 35 34 33 32 31 1 cyrf69213 wirelessusb lp corner tabs [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 5 of 85 functional block overview all the blocks that make up the proc lp are pr esented here. 2.4-ghz radio the radio transceiver is a dual conversion low if architecture optimized for power and range/robustness. the radio employs channel-matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides up to +4 dbm transmit power, with an output power control range of 34 db in 7 step s. the supply current of the device is reduced as the rf output power is reduced. frequency synthesizer before transmission or rece ption may commence, it is necessary for the frequency synt hesizer to settle. the settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. the ?fast channels? (<100- s settling time) are every third frequency, starting at 2400 mhz up to and including 2472 mhz (for example, 0,3,6,9??.69 & 72). baseband and framer the baseband and framer bloc ks provide the dsss encoding and decoding, sop generation and reception and crc16 generation and checking, as well as eop detection and length field. data rates and data transmission modes the soc supports four different data transmission modes: ? in gfsk mode, data is tran smitted at 1 mbps, without any dsss. ? in 8dr mode, 8 bits are encoded in each data_code_adr derived code symbol transmitted. ? in ddr mode, 2-bits are encoded in each data_code_adr derived code symbol transmitted. (as in the cywusb6934 ddr mode). ? in sdr mode, 1 bit is encoded in each data_code_adr derived code symbol transmitted. (as in the cywusb6934 standard modes.) both 64-chip and 32-chip data_code_adr codes are supported. the four data transmission modes apply to the data after the sop. in particular t he length, data, and crc16 are all sent in the same mode. in general, lower data rates reduces packet error rate in any given environment. by combining the data_code_adr code lengths and data transmission modes described above, the cyrf69213 ic supports the following data rates: ? 1000-kbps (gfsk) ? 250-kbps (32-chip 8dr) ? 125-kbps (64-chip 8dr) ? 62.5-kbps (32-chip ddr) ? 31.25-kbps (64-chip ddr) ? 15.625-kbps (64-chip sdr) lower data rates typically provide longer range and/or a more robust link. link layer modes the cyrf69213 ic device supports the following data packet framing features: sop ? packets begin with a 2-symbol start of packet (sop) marker. this is required in gfsk and 8dr modes, but is optional in ddr mode and is not supported in sdr mode; if framing is disabled then an sop event is inferred whenever two successive correlati ons are detected. the sop_code_adr code used for t he sop is different from that used for the ?body? of the packet, and if desired may be a different length. sop must be configured to be the same length on both sides of the link. eop ? there are two options for detecting the end of a packet. if sop is enabled, then a packet length field may be enabled. gfsk and 8dr must enable the leng th field. this is the first 8 bits after the sop symbol, and is transmitted at the payload data rate. if the length field is enabled, an end of packet (eop) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the crc16 (if enabled?see below). the alternative to using the length field is to infer an eop condition from a configurable number of successive non-correlations; this option is not available in gfsk mode and is only recommended when using sdr mode. crc16 ? the device may be configured to append a 16-bit crc16 to each packet. the crc16 uses the usb crc polynomial with the added prog rammability of the seed. if enabled, the receiver will verify the calculated crc16 for the payload data against the received value in the crc16 field. the starting value for the crc16 calculation is configurable, and the crc16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data crc16 will be checked against both the configured and zero crc16 seeds. crc16 detects the following errors: ? any one bit in error ? any two bits in error (no matt er how far apart, which column, and so on) ? any odd number of bits in error (no matter where they are) ? an error burst as wide as the checksum itself figure 2 shows an example packet with sop, crc16 and lengths fields enabled. table 1. internal pa output power step table pa setting typical output power (dbm) 7+4 60 5?5 4 ?10 3 ?15 2 ?20 1 ?25 0 ?30 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 6 of 85 figure 2. example default packet format packet buffers packet data and configuration registers are accessed through the spi interface. all confi guration registers are directly addressed through the address field in the spi packet. config- uration registers are provided to allow configuration of dsss pn codes, data rate, operating mode, interrupt masks, interrupt status, and others. packet buffers all data transmission and reception uses the 16-byte packet buffers?one for transmission and one for reception. the transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst spi transaction, and then transmitted with no further mcu intervention. similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. the cyrf69213 ic supports packet length of up to 40 bytes; interrupts are provided to allow an mcu to use the transmit and receive buffers as fifos. when transmitting a packet longer than 16 bytes, the mcu can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. similarly, when receiving packets longer than 16 bytes, the mcu function must fetch received data from the fifo periodically during packet reception to prevent it from overflowing. auto transaction sequencer (ats) the cyrf69213 ic provides automated support for trans- mission and reception of acknowledged data packets. when transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automati- cally switches to receive mode and waits for a handshake packet?and then automatically reverts to sleep mode or idle mode when either an ack packet is received, or a timeout period expires. similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automatically transitions to tr ansmit mode, transmits an ack packet, and then switches back to receive mode to await the next packet. the contents of the packet buffers are not affected by the transmission or reception of ack packets. in each case, the entire packet transaction takes place without any need for mcu firmware action; to transmit data the mcu simply needs to load the data packet to be transmitted, set the length, and set the tx go bit. similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt request indicating reception of a packet. interrupts the radio function provides an interrupt (irq) output, which is configurable to indicate the occurrence of various different events. the irq pin may be programmed to be either active high or active low, and be either a cmos or open drain output. the irq pin can be multiplexed on the spi if routed to an external pin. the radio function features thr ee sets of interrupts: transmit, receive, and system interrupts. these interrupts all share a single pin (irq), but can be independently enabled/disabled. in transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. however, the contents of the enable registers are preserved when switching between transmit and receive modes. if more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, th e status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status r egister. it is therefore possible to use the devices without making use of the irq pin by polling the status register(s) to wait fo r an event, rather than using the irq pin. the microcontroller function supports 23 maskable interrupts in the vectored interrupt controll er. interrupt sources include a usb bus reset, lvr/por, a programmable interval timer, a 1.024-ms output from the fr ee running timer, three usb endpoints, two capture timers, five gpio ports, three gpio pins, two spi, a 16-bit free running timer wrap, an internal wake-up timer, and a bus active interrupt. the wake-up timer causes periodic interrupts when enabled. the usb endpoints interrupt after a usb transaction complete is on the bus. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge ev ent. a total of eight gpio interrupts support both ttl or cmos thresholds. for additional flexibility, on the edge sensitive gpio pins, the interrupt polarity is programmable to be either rising or falling. clocks the radio function has a 12-mhz crystal (30-ppm or better) directly connected between xtal and gnd without the need for external capacitors. a digital clock out function is provided, with selectable output frequenci es of 0.75, 1.5, 3, 6, or 12 mhz. this output may be used to clock an external micro- controller (mcu) or asic. this output is enabled by default, but may be disabled. below are the requirements for the crystal to be directly connected to xtal pin and gnd: p sop 1 sop 2 length crc 16 payload data preamble n x 16us 1st framing symbol* 2nd framing symbol* packet length 1 byte period *note:32 or 64us [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 7 of 85 ? nominal frequency: 12 mhz ? operating mode: fundamental mode ? resonance mode: parallel resonant ? frequency initial stability: 30 ppm ? series resistance: < 60 ohms ? load capacitance: 10 pf ? drive level: 10 w?100 w the mcu function features an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). the clock generator provides the 12-mhz and 24-mhz clocks that remain internal to the microcontroller. gpio interface the mcu function features up to 20 general-purpose i/o (gpio) pins to support usb, ps/2, and other applications. the i/o pins are grouped into five ports (port 0 to 4). the pins on port 0 and port 1 may each be configured individually while the pins on ports 2, 3, and 4 may only be configured as a group. each gpio port supports high-impedance inputs, configurable pull up, open drain output, cmos/ttl inputs, and cmos output with up to five pins that support program- mable drive strength of up to 50-ma sink current. gpio port 1 features four pins that interfac e at a voltage level of 3.3 volts. additionally, each i/o pin can be used to generate a gpio interrupt to the microcontroller. each gpio port has its own gpio interrupt vector with the exception of gpio port 0. gpio port 0 has three dedicated pins that have independent interrupt vectors (p0.2?p0.4). power-on reset/low-voltage detect the power-on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at flash address 0x0000. when power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. there is a low-voltage detect circuit that detects when v cc drops below a programmable trip voltage. it may be configurable to generate an lvd interrupt to inform the processor about the low-voltage event. por and lvd share the same interrupt. there is not a separate interrupt for each. the watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. power management the device draws its power supply from the usb v bus line. the v bus supplies power to the m cu function, which has an internal 3.3 v regulator. this 3.3 v is supplied to the radio function via p1.2/v reg after proper filtering as shown in figure 3. figure 3. power management from internal regulator timers the free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1- s resolution and the 1.024-ms outputs. the timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. usb interface the mcu function includes an integrated usb serial interface engine (sie) that allows the chip to easily interface to a usb host. the hardware supports one usb device address with three endpoints. low noise amplifier (lna) and received signal strength indication (rssi) the gain of the receiver may be controlled directly by clearing the agc en bit and writing to the low noise amplifier (lna) bit of the rx_cfg_adr register. when the lna bit is cleared, the receiver gain is reduced by approximately 20 db, allowing accurate reception of very strong re ceived signals (for example when operating a receiver very close to the trans- mitter). an additional 20 db of receiver attenuation can be added by setting the attenuation (att) bit; this allows data reception to be limited to devices at very short ranges. disabling agc and enabling lna is recommended unless receiving from a device using external pa. the rssi register returns the relative signal strength of the on-channel signal power. when receiving, the device may be configured to automati- cally measure and store the re lative strength of the signal being received as a 5-bit value. when enabled, an rssi reading is taken and may be read through the spi interface. proc lp v reg v bat3 v bat1 v bat2 v cc1 v cc2 v cc3 l/d v io 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f 0.047f v dd_micro v bus 0.1f p1.2 / v reg [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 8 of 85 an rssi reading is taken automat ically when the start of a packet is detected. in addition , a new rssi reading is taken every time the previous reading is read from the rssi register, allowing the background rf energy level on any given channel to be easily measured when rssi is read when no signal is being received. a new reading can occur as fast as once every 12 s. spi interface the spi interface between the mcu function and the radio function is a 3-wire spi interface. the three pins are mosi (master out slave in), sck (s erial clock), ss (slave select). there is an alternate 4-wire mi so interface that requires the connection of two external pins. the spi interface is controlled by configuring the spi config ure register (sicr address: 0x3d). 3-wire spi interface the radio function receives a clock from the mcu function on the sck pin. the mosi pin is multiplexed with the miso pin. bidirectional data transfer takes place between the mcu function and the radio function through this multiplexed mosi pin. when using this mode the user firmware should ensure that the mosi pin on the mcu function is in a high impedance state, except when the mcu is actively transmitting data. firmware must also control t he direction of data flow and switch directions between mcu function and radio function by setting the swap bit [bit 7] of the spi configure register. the ss pin is asserted prior to initiating a data transfer between the mcu function and the radio function. the irq function may be optionally multiplexed with the mosi pin; when this option is enabled the irq function is not available while the ss pin is low. when using this configuration, user firmware should ensure that the mosi functi on on mcu function is in a high-impedance state whenever ss is high. figure 4. 3-wire spi mode 4-wire spi interface the 4-wire spi communications interface consists of mosi, miso, sck, and ss. the device receives sck from the mcu function on the sck pin. data from the mcu function is shifted in on the mosi pin. data to the mcu function is sh ifted out on the miso pin. the active low ss pin must be asserted for the two functions to communicate. the irq function may be optionally multiplexed with the mosi pin; when this option is enabled the irq function is not available while the ss pin is low. when using this configuration, user firmware should ensure that the mosi function on mcu function is in a high-impedance state whenever ss is high. figure 5. 4-wire spi mode spi communication and transactions the spi transactions can be single byte or multi-byte. the mcu function initiates a data transfer through a command/address byte. the following bytes are data bytes. the spi transaction format is shown in figure 6 . the dir bit specifies the direction of data transfer. 0 = master reads from slave. 1 = master writes to slave. the inc bit helps to read or write consecutive bytes from contiguous memory locations in a single burst mode operation. if slave select is asserted and inc = 1, then the master mcu function reads a byte from the radio, the address is incre- mented by a byte location, and then the byte at that location is read, and so on. if slave select is asserted and inc = 0, then the mcu function reads/writes the bytes in the same register in burst mode, but if it is a register file then it r eads/writes the bytes in that register file. the spi interface between the radio function and the mcu is not dependent on the internal 12-mhz oscillator of the radio. therefore, radio function registers can be read from or written into while the radio is in sleep mode. spi io voltage references the spi interfaces between mcu function and the radio and the irq and rst have a separate voltage reference v io , enabling the radio function to directly interface with the mcu mcu function p1.5/mosi p1.4/sck p1.3/nss mosi sck nss radio function mosi sck nss mosi/miso multiplexed on one mosi pin mcu function p1.5/mosi p1.4/sck p1.3/nss p1.6/miso mosi sck nss radio function miso mosi sck nss this connection is external to the proc lp chip [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 9 of 85 function, which operates at higher supply voltage. the internal spio pins between the mcu function and radio function should be connected with a regulated voltage of 3.3v (by setting [bit4] of registers p13cr, p14cr, p15cr, and p16cr of the mcu function) and the internal 3.3v regulator of the mcu function should be turned on. spi connects to external devices the three spi wires, mosi, sc k, and ss are also drawn out of the package as external pins to allow the user to interface their own external devices (such as optical sensors and others) through spi. the radio function also has its own spi wires miso and irq, which can be used to send data back to the mcu function or send an interrupt request to the mcu function. they can also be configured as gpio pins. cpu architecture this family of microcontrollers is based on a high-perfor- mance, 8-bit, harvard-architecture microprocessor. five registers control the primary op eration of the cpu core. these registers are affected by various instructions, but are not directly accessible through the register space by the user. the 16-bit program counter register (cpu_pc) allows for direct addressing of the full eight kbytes of program memory space. the accumulator register (cpu_a) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. the index register (cpu_x) holds an offset value that is used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu_sp) holds the address of the current top-of-stack in the data memory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it can also be affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] is used to globally enable or disable interrupts. the user cannot manipulate the supervisory state status bit [3]. the flags are affe cted by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed (for example, and, or, xor). see table 19 . cpu registers flags register the flags register can only be set or reset with logical instruction. figure 6. spi transaction format byte 1 byte 1+n bit# 7 6 [5:0] [7:0] bit name dir inc address data table 2. cpu registers and register names register register name flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x table 3. cpu flags register (cpu_f) [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xio super carry zero global ie read/write ? ? ? r/w r rw rw rw default 00000010 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 10 of 85 accumulator register index register stack pointer register bits 7:5 reserved bit 4 xio set by the user to select between the register banks 0 = bank 0 1 = bank 1 bit 3 super indicates whether the cpu is executing us er code or supervisor code. (this code c annot be accessed directly by the user.) 0 = user code 1 = supervisor code bit 2 carry set by cpu to indicate whether there has been a ca rry in the previous logical/arithmetic operation 0 = no carry 1 = carry bit 1 zero set by cpu to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = not equal to zero 1 = equal to zero bit 0 global ie determines whether all interrupts are enabled or disabled 0 = disabled 1 = enabled note cpu_f register is only readable with explicit register address 0xf7. the or f, expr and and f, expr instructions must be used to set and clear the cpu_f bits table 3. cpu flags register (cpu_f) [r/w] table 4. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ???????? default 00000000 bits 7:0 cpu accumulator [7:0] 8-bit data value holds the result of any logical/arithm etic instruction that uses a source addressing mode table 5. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ???????? default 00000000 bits 7:0 x [7:0] 8-bit data value holds an index for any inst ruction that uses an indexed addressing mode table 6. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ???????? default 00000000 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 11 of 85 cpu program counter high register cpu program counter low register addressing modes examples of the different addressing modes are discussed in this section and example code is given. source immediate the result of an instruction using this addressing mode is placed in the a register, the f register, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithmetic instructions require two sources. instructions using this addressing mode are two bytes in length. examples source direct the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the inst ruction opcode. operand 1 is an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arithmetic instruct ions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples source indexed the result of an instruction using this addressing mode is placed in either the a register or the x register, which is bits 7:0 stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack table 6. cpu stack pointer register (cpu_sp) table 7. cpu program counter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ???????? default 00000000 bits 7:0 program counter [15:8] 8-bit data value holds the higher byte of the program counter table 8. cpu program counter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ???????? default 00000000 bits 7:0 program counter [7:0] 8-bit data value holds the lower byte of the program counter table 9. source immediate opcode operand 1 instruction immediate value add a, 7 ;in this case, the immediate value ;of 7 is added with the accumulator, ;and the result is placed in the ;accumulator. mov x, 8 ;in this case, the immediate value ;of 8 is moved to the x register. and f, 9 ;in this case, the immediate value ;of 9 is logically anded with the f ;register and the result is placed ;in the f register. table 10.source direct opcode operand 1 instruction source address add a, [7] ;in this case, the value in ;the ram memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the accumulator. mov x, reg[8] ;in this case, the value in ;the register space at address ;8 is moved to the x register. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 12 of 85 specified as part of the instru ction opcode. operand 1 is added to the x register forming an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arit hmetic instructions require two sources; the second source is the a register or x register specified in the opcode. inst ructions using this addressing mode are two bytes in length. examples destination direct the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specif ied as part of the instruction opcode. arithmetic instructi ons require two sources; the second source is the location s pecified by operand 1. instruc- tions using this addressing mode are two bytes in length. examples destination indexed the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register forming the address that points to the location of the result. the source for the instruction is the a register . arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example destination direct source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1. instructions using this addressing mode are three bytes in length. examples destination indexed source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are three bytes in length. table 11.source indexed opcode operand 1 instruction source index add a, [x+7] ;in this case, the value in ;the memory location at ;address x + 7 is added with ;the accumulator, and the ;result is placed in the ;accumulator. mov x, reg[x+8] ;in this case, the value in ;the register space at ;address x + 8 is moved to ;the x register. table 12.destination direct opcode operand 1 instruction destination address add [7], a ;in this case, the value in ;the memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the memory ;location at address 7. the ;accumulator is unchanged. mov reg[8], a ;in this case, the accumula- ;tor is moved to the regis- ;ter space location at ;address 8. the accumulator ;is unchanged. table 13.destination indexed opcode operand 1 instruction destination index add [x+7], a ;in this case, the value in the ;memory location at address x+7 ;is added with the accumulator, ;and the result is placed in ;the memory location at address ;x+7. the accumulator is ;unchanged. table 14.destination direct immediate opcode operand 1 operand 2 instruction destination address immediate value add [7], 5 ;in this case, value in the mem- ;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. mov reg[8], 6 ;in this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8. table 15.destination indexed immediate opcode operand 1 operand 2 instruction destination index immediate value [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 13 of 85 examples destination direct source direct the result of an instruction using this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an address that points to a location in the ram memory that is the s ource for the instruction. this addressing mode is only valid on the mov instruction. the instruction using this addressing mode is three bytes in length. example source indirect post increment the result of an instruction using this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) fo r the source of the instruction. the indirect address is increment ed as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction usin g this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example destination indirect post increment the result of an instruction using this addressing mode is placed within the memory sp ace. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. the indirect address is incremented as part of the instruction execution. the sour ce for the instruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction us ing this addressing mode is two bytes in length. example add [x+7], 5 ;in this case, the value in ;the memory location at ;address x+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address x+7. mov reg[x+8], 6 ;in this case, the immedi- ;ate value of 6 is moved ;into the location in the ;register space at ;address x+8. table 16.destination direct source direct opcode operand 1 operand 2 instruction destination address source address mov [7], [8] ;in this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7. table 17.source indirect post increment opcode operand 1 instruction source address address mvi a, [8] ;in this case, the value in the ;memory location at address 8 is ;an indirect address. the memory ;location pointed to by the indi- ;rect address is moved into the ;accumulator. the indirect ;address is then incremented. table 18.destination indirect post increment opcode operand 1 instruction destination address address mvi [8], a ;in this case, the value in ;the memory location at ;address 8 is an indirect ;address. the accumulator is ;moved into the memory loca- ;tion pointed to by the indi- ;rect address. the indirect ;address is then incremented. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 14 of 85 instruction set summary the instruction set is summarized in ta b l e 1 9 numerically and serves as a quick reference. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (available on the www.cypress.com web site). table 19.instruction set summary sorted numerically by opcode order [1, 2] opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a cyrf69213 document #: 001-07552 rev. *b page 16 of 85 data memory organization the mcu function has 256 bytes of data ram figure 8. data memory organization flash this section describes the flash block of the cyrf69213. much of the user-visible flash functionality, including programming and security, are implemented in the m8c supervisory read only memory (srom). cyrf69213 flash has an endurance of 1000 cycles and 10-year data retention. flash programming and security all flash programming is performed by code in the srom. the registers that control the flas h programming are only visible to the m8c cpu when it is executing out of srom. this makes it impossible to read, write, or erase the flash by bypassing the security mechanisms implemented in the srom. customer firmware can only program the flash via srom calls. the data or code images can be sourced by way of any interface with the appropriate support firmware. this type of programming requires a ?boot-loader??a piece of firmware resident on the flash. for safety reasons this boot-loader should not be overwritten during firmware rewrites. the flash provides four auxiliary rows that are used to hold flash block protection flags, boot time calibration values, configuration tables, and any device values. the routines for accessing these auxiliary rows are documented in the srom section. the auxiliary rows are not affected by the device erase function. in-system programming most designs that include an cyrf69213 part will have a usb connector attached to the usb d+/d? pins on the device. these designs require the ability to program or reprogram a part through these two pins alone. cyrf69213 device enables this type of in-system programming by using the d+ and d? pins as the serial programming mode interface. this allows an external controller to cause the cyrf69213 part to enter serial programming mode and then to use the test queue to issue flash access functions in the srom. the programming protocol is not usb. srom the srom holds code that is used to boot the part, calibrate circuitry, and perform flash operations. ( ta b l e 2 0 lists the srom functions.) the functions of the srom may be accessed in normal user code or operating from flash. the srom exists in a separate me mory space from user code. the srom functions are accessed by executing the super- visory system call instruction (ssc), which has an opcode of 00h. prior to executing the ssc, the m8c?s accumulator needs to be loaded with the desired srom function code from ta b l e 2 0 . undefined functions will cause a halt if called from user code. the srom functions are executing code with calls; therefore, the functions require stack space. with the exception of reset, all of the srom functions have a parameter block in sram that must be configured before executing the ssc. table 21 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this section. two important variables that are used for all functions are key1 and key2. these variables are used to help discrim- inate between valid sscs and inadvertent sscs. key1 must always have a value of 3ah, wh ile key2 must have the same value as the stack pointer when the srom function begins execution. this would be the stack pointer value when the ssc opcode is executed, plus three. if either of the keys do after reset address 8-bit psp 0x00 stack begins here and grows upward. top of ram memory 0xff table 20.srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 17 of 85 not match the expected values, the m8c will halt (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the c ode starts with a halt, to force the program to jump directly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a the srom also features return codes and lockouts. return codes return codes aid in the determination of success or failure of a particular function. the return code is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1?s position in the parameter bl ock is used to return other data. read, write, and eras e operations may fail if the target block is read or write protected. bl ock protection levels are set during device programming. the eraseall function overwrites data in addition to leaving the entire user flash in the erase state. the eraseall function loops through the number of flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. after all the user space in all the flash macros are erased, a second loop erases and then programs each protection block with zeros. srom function descriptions all srom functions are described in the following sections. swbootreset function the srom function, swbootrese t, is the function that is responsible for transitioning the device from a reset state to running user code. the swbootreset function is executed whenever the srom is entered with an m8c accumulator value of 00h; the sram parameter block is not used as an input to the function. this will happen, by design, after a hardware reset, because the m8c's accumulator is reset to 00h or when user code execut es the ssc instruction with an accumulator value of 00h. the swbootreset function will not execute when the ssc instruction is executed with a bad key value and a nonzero functi on code. a cyrf69213 device will execute the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit che cksum, before releasing the m8c to run user code. readblock function the readblock function is used to read 64 contiguous bytes from flash?a block. the first thing this function does is to check the protection bits and determine if the desired blockid is readable. if read protection is turned on, the readbl ock function will exit, setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a read failure. if read protection is not enabled, the function will read 64 bytes from the flash using a romx instruction and store the results in sram using an mvi instruction. the first of the 64 bytes will be stored in sram at the address indicated by the value of the pointer parameter. when the readblo ck completes successfully, the accumulator, key1, and key2 will all have a value of 00h. writeblock function the writeblock function is used to store data in the flash. data is moved 64 bytes at a time from sram to flash using this function. the first thing the writeblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the write- block function will exit, setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the configuration of the writeblo ck function is straightforward. the blockid of the flash block, where the data is stored, must be determined and stored at sram address fah. the sram address of the first of the 64 bytes to be stored in flash must be indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock table 21.srom function parameters variable name sram address key1/counter/return code 0,f8h key2/tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 22.srom return codes return code description 00h success 01h function not allowed due to level of protection on block 02h software reset without hardware reset 03h fatal error, srom halted table 23.readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data should be stored [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 18 of 85 and delay values must be set correctly. the clock value determines the length of the wr ite pulse that will be used to store the data in the flash. the clock and delay values are dependent on the cpu speed. refer to ?clocking? section for additional information. eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. the first thing the eraseblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the eraseblock function will exit, setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in prog ramming. erasing a block will not cause data in a block to be one hundred percent unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a writeblock of all zeros. to set up the parameter blo ck for the eraseblock function, correct key values must be stored in key1 and key2. the block number to be erased must be stored in the blockid variable and the clock and delay values must be set based on the current cpu speed. protectblock function the cyrf69213 device offers flash protection on a block-by-block basis. table 26 lists the protection modes available. in the table, er and ew are used to indicate the ability to perform external reads and writes. for internal writes, iw is used. internal reading is always permitted by way of the romx instruction. the ability to read by way of the srom readblock function is indicated by sr. the protection level is stored in two bits according to ta b l e 2 6 . these bits are bit packed into the 64 bytes of th e protection block. therefore, each protection block byte stor es the protection level for four flash blocks. the bits are packe d into a byte, with the lowest numbered block?s protection level stored in the lowest numbered bits. the first address of the protection block contains the protection level for blocks 0 th rough 3; the second address is for blocks 4 through 7. the 64th byte will store the protection level for blocks 252 through 255. the level of protection is only decreased by an eraseall, which places zeros in all locations of the protection block. to set the level of protection, the protectblock function is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stored in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and th ere is only one protection block per flash macro, the protectblock function expects very few variables in the parameter block to be set prior to calling the function. the parameter block values that must be set, besides the keys, are the clock and delay values. eraseall function the eraseall function performs a series of steps that destroy the user data in the flash macr os and resets the protection block in each flash macro to all zeros (the unprotected state). the eraseall function does not affect the three hidden blocks above the protection block in each flash macro. the first of table 24.writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed blockid 0,fah 8-kb flash block number (00h?7fh) 4-kb flash block number (00h?3fh) 3-kb flash block number (00h?2fh) pointer 0,fbh first of 64 addresses in sram, where the data to be stored in flash is located prior to calling writeblock clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 25.eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 26.protection modes mode settings description marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 76543210 block n+3 block n+2 block n+1 block n table 27.protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 19 of 85 these four hidden blocks is used to store the protection table for its eight kbytes of user data. the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to destroy all traces of the previo us contents. the bulk program is followed by a second erase that leaves the flash macro in a state ready for writing. the erase, program, erase sequence is then performed on the next lowest flash macro in the address space if it exists. following the erase of the user space, the protection block for the flash macro with the highest address range is erased. following the erase of the protection block, zeros are written into every bit of the protection table. the next lowest flash macro in the address space then has its protection block erased and filled with zeros. the end result of the eraseall function is that all user data in the flash is destroyed and t he flash is left in an unpro- grammed state, ready to accept one of the various write commands. the protection bits for all user data are also reset to the zero state. the parameter block values that must be set, besides the keys, are the clock and delay values. tableread function the tableread function gives the user access to part-specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the cyrf69213 is simply a 64-byte row broken up into eight tables of eight bytes. the tables are numbered zero through seven. all user and hidden blocks in the cyrf69213 parts consist of 64 bytes. an internal table holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision id is returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semiconductor product engineering. the revision id is hard coded into the srom. the revision id is discussed in more detail later in this section. an internal table holds alternate trim values for the device and returns a one-byte internal revision counter. the internal revision counter starts out with a value of zero and is incre- mented each time one of the other revision numbers is not incremented. it is reset to zero each time one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a register. the cpu_x register will always be set to ffh when trim values are read. the blockid value, in the parameter block, is used to indicate which table should be returned to the user. only the three least significant bits of the blockid parameter are used by the tableread function for the cyrf69213. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revi sion id. the revision id is a 16-bit value hard coded into the srom that uniquely identifies the die?s design. checksum function the checksum function calculates a 16-bit checksum over a user specifiable number of blo cks, within a single flash macro (bank) starting from block zero. the blocki d parameter is used to pass in the number of blocks to calculate the checksum over. a blockid val ue of 1 will calculate the checksum of only block 0, wh ile a blockid value of 0 will calculate the checksum of all 256 user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds the lower eight bi ts of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed. romx add [key1], a adc [key2], 0 clocking the cyrf69213 internal oscillator outputs two frequencies, the internal 24-mhz oscillator and the 32-khz low-power oscillator. the internal 24-mhz oscillator is designed such that it may be trimmed to an output frequency of 24 mhz over temperature and voltage variation. with the presence of usb traffic, the internal 24-mhz oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). without usb traffic, the internal 24-mhz oscillator accuracy is 24 mhz 5% (between table 28.eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider us ed to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 29.table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah table number to read table 30.checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah number of flash blocks to calculate checksum on [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 20 of 85 0?70c). no external components are required to achieve this level of accuracy. the internal low-speed oscillator of nominally 32 khz provides a slow clock source for the cyrf69213 in suspend mode, particularly to generate a periodic wake-up interrupt and also to provide a clock to sequential logic during power-up and power-down events when the main clock is stopped. in addition, this oscillator can also be used as a clocking source for the interval timer clock (itmrclk) and capture timer clock (tcapclk). the 32-khz low-power oscillator can operate in low-power mode or can provide a more accurate clock in normal mode. the internal 32-khz low-power oscil- lator accuracy ranges (between 0 ? 70 c) as follows: 5v normal mode: ?8% to + 16% 5v lp mode: +12% to + 48% when using the 32-khz oscillator the pitmrl/h should be read until two consecutive readings match before sending/receiving data. the following firmware example assumes the developer is interested in the lower byte of the pit. read_pit_counter: mov a, reg[pitmrl] mov [57h], a mov a, reg[pitmrl] mov [58h], a mov [59h], a mov a, reg{pitmrl] mov [60h], a ;;;start comparison mov a, [60h] mov x, [59h] sub a, [59h] jz done mov a, [59h] mov x, [58h] sub a, [58h] jz done mov x, [57h] ;;;correct data is in memory location 57h done: mov [57h], x ret [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 21 of 85 clock architecture description the cyrf69213 clock selection circuitry allows the selection of independent clocks for the cpu, usb, interval timers, and capture timers. the cpu clock, cpuclk, can be sourced from the external crystal oscillator or the in ternal 24-mhz oscillator. the selected clock source can optionally be divided by 2 n where n is 0?5,7 (see ta b l e 3 4 ). usbclk, which must be 12 mhz for the usb sie to function properly, can be sourced by the internal 24-mhz oscillator or the external crystal oscillator. an optional divide-by-two allows the use of the 24-mhz source. the interval timer clock (itmrclk), can be sourced from the external crystal oscillator, the internal 24-mhz oscillator, the internal 32-khz low-power oscillator, or from the timer capture clock (tcapclk). a prog rammable prescaler of 1, 2, 3, 4 then divides the selected source. the timer capture clock (tcapclk) can be sourced from the external crystal oscillator, internal 24-mhz oscillator, or the internal 32-khz low-power oscillator. when it is not being used by the external crystal oscillator, the clkout pin can be driven from one of many sources. this is used for test and can also be used in some applications. the sources that can drive the clkout are: ? clkin after the optional eftb filter ? internal 24-mhz oscillator ? internal 32-khz low-power oscillator ? cpuclk after the programmable divider figure 9. clock block diagram cpu_clk ext 24 mhz mux clk_usb sel scale clk_24mhz clk_ext cpuclk sel mux scale (divide by 2 n , n = 0-5,7) clk_32 khz lp osc 32 khz sel scale out 0x 12 mhz 0x 12 mhz 1 1 ext/2 11 ext [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 22 of 85 table 31.iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the iosc calibrate register is used to calibrate the internal oscillator. the reset value is undefined, but during boot the sro m writes a calibration value that is determined during manufacturing test. this value should not require change during normal use. this is the meaning of ?d? in the default field bits 7:5 foffset [2:0] this value is used to trim the frequency of the internal oscillator. these bits are not used in factory calibration and will be zero. setting each of these bits causes the appr opriate fine offset in oscillator frequency foffset bit 0 = 7.5 khz foffset bit 1 = 15 khz foffset bit 2 = 30 khz bits 4:0 gain [4:0] the effective frequency change of the offset input is controlled through the gain inpu t. a lower value of the gain setting incr eases the gain of the offset input. this value sets the size of each offset step for the internal oscillator. nominal gain change (kh z/off- setstep) at each bit, typical conditions (24-mhz operation): gain bit 0 = ?1.5 khz gain bit 1 = ?3.0 khz gain bit 2 = ?6 khz gain bit 3 = ?12 khz gain bit 4 = ?24 khz table 32.lposc trim (l posctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32-khz low power reserved 32-khz bias trim [1:0] 32-khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default 0 d d d dd d d this register is used to calibrate the 32-khz low-speed oscillator. the reset value is undefined, but during boot the srom writ es a calibration value that is determined during manufacturing test. this value should not require change during normal use. this is the meaning of ?d? in the default field. if the 32-khz low-power bit needs to be written, care should be taken not to disturb the 32-khz bias trim and th e 32-khz freq trim fields from their factory calibrated values bit 7 32-khz low power 0 = the 32-khz low-speed oscillator operates in normal mode 1 = the 32-khz low-speed oscillator operates in a low-power mo de. the oscillator continues to function normally but with reduced accuracy bit 6 reserved bits 5:4 32-khz bias trim [1:0] these bits control the bias current of the low-power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = reserved important note do not program the 32-khz bias trim [1:0] field with the reserv ed 10b value, as the oscillator does not oscillate at all corner conditions with this setting bits 3:0 32-khz freq trim [3:0] these bits are used to trim the frequency of the low-power oscillator [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 23 of 85 table 33.cpu/usb clock config cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved usb clk/2 disable usb clk select reserved cpuclk se- lect read/write ? r/w r/w ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit 6 usb clk/2 disable this bit only affects the usbclk when the s ource is the external crysta l oscillator. when the usbclk source is the internal 24-mhz oscillator, the divi de by two is always enabled 0 = usbclk source is divided by two. this is the correct setti ng to use when the internal 24-mhz oscillator is used, or when th e external source is used with a 24-mhz clock 1 = usbclk is undivided. use this setti ng only with a 12-mhz external clock bit 5 usb clk select this bit controls the clock source for the usb sie 0 = internal 24-mhz o scillator. with the presence of usb tr affic, the internal 24- mhz oscillator can be tr immed to meet the usb requirement of 1.5% tolerance (see table 35 ) 1 = external clock?inter nal oscillator is not trimmed to usb traffic. proper usb sie operation requires a 12-mhz or 24-mhz clock accurate to <1.5% bits 4:1 reserved bit 0 cpu clk select 0 = internal 24-mhz oscillator 1 = external clock?external clock at clkin (p0.0) pin note the cpu speed selection is confi gured using the osc_cr0 register ( ta b l e 3 4 ) [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 24 of 85 table 34.osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bits 7:6 reserved bit 5 no buzz during sleep (the sleep bit is set in the cpu_scr register? ta b l e 3 8 ), the lvd and por detection circuit is turned on period- ically to detect any por and lvd events on the v cc pin (the sleep duty cycle bits in t he eco_tr are used to control the duty cycle? ta b l e 4 2 ). to facilitate the detection of por and lvd events, th e no buzz bit is used to force the lvd and por detec- tion circuit to be continuously enabl ed during sleep. this results in a faster response to an lvd or por event during sleep at the expense of a slightly higher than average sleep current 0 = the lvd and por detection circuit is turned on periodically as c onfigured in the sleep duty cycle 1 = the sleep duty cycle value is overridden. the lvd and por detecti on circuit is always enabled note the periodic sleep duty cycle enabling is independent with the sleep interval shown in the sleep [1:0] bits below bits 4:3 sleep timer [1:0] note sleep intervals are approximate bits 2:0 cpu speed [2:0] the cyrf69213 may operate over a range of cpu clock speeds. the reset value for the cpu speed bits is zero; therefore, the default cpu speed is one-eighth of the internal 24 mhz, or 3 mhz regardless of the cpu speed bit?s setting, if the actual cpu sp eed is greater than 12 mhz, the 24-mhz operating requirements apply. an example of this scenario is a dev ice that is configured to use an external clock, which is s upplying a frequency of 2 0 mhz. if the cpu speed register?s value is 0b011, the cpu clock w ill be 20 mhz. therefore the supply voltage requirements for the device are the same as if the part was operating at 24 mh z. the operating voltage requirements are not relaxed until the cpu speed is at 12 mhz or less important note correct usb operations require the cpu cl ock speed be at least 1.5 mhz or not less than usb clock/8. if the two clocks have the same source then the cpu clock divider should not be set to divide by more than 8. if the two clocks have different sources , care must be taken to ensure that the maximum ratio of usb clock/cpu clock ca n never exceed 8 across the full specification range of both cl ock sources sleep timer [1:0] sleep timer clock frequency (nominal) sleep period (nominal) watchdog period (nominal) 00 512 hz 1.95 ms 6 ms 01 64 hz 15.6 ms 47 ms 10 8 hz 125 ms 375 ms 11 1 hz 1 sec 3 sec cpu speed [2:0] cpu when internal oscillator is selected external clock 000 3 mhz (default) clock in/8 001 6 mhz clock in/4 010 12 mhz clock in/2 011 24 mhz clock in/1 100 1.5 mhz clock in/16 101 750 khz clock in/32 110 187 khz clock in/128 111 reserved reserved [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 25 of 85 table 35.usb osclock clock config uration (osclckcr) [0x39] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved fine tune only usb osclock disable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register is used to trim the inter nal 24-mhz oscillator using received low-speed usb packets as a timing reference. the us b osclock circuit is active when the internal 24 -mhz oscillator prov ides the usb clock bits 7:2 reserved bit 1 fine tune only 0 = enable 1 = disable the oscillator lock from performing the course-tune portion of its retuning. the oscillator lock must be allowed to per- form a course tuning in order to tune the oscillator for correc t usb sie operation. after the oscillator is properly tuned this bit can be set to reduce variance in the internal oscillator frequency that would be caused by course tuning bit 0 usb osclock disable 0 = enable. with the presence of usb traffic, the inte rnal 24-mhz oscillator prec isely tunes to 24 mhz 1.5% 1 = disable. the internal 24-mhz oscillator is not trimmed based on usb packets. this setting is useful when the internal oscil - lator is not sourcing the usbsie clock table 36.timer clock conf ig (tmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapcl divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default - - - - 1 1 0 0 bits 7:6 tcapclk divider tcapclk divider controls the tcapclk divisor 00 = divide by 2 01 = divide by 4 10 = divide by 6 11 = divide by 8 bits 5:4 tcapclk select the tcapclk select field controls the source of the tcapclk 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator?external crystal oscillator on clkin and clkout if the external crystal oscillator is enabled , clkin input if the external crystal os cillator is disabled (the xosc enable bi t of the clkiocr register is cleared? ta b l e 3 7 ) 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk disabled note the 1024- s interval timer is based on the assumption that tcapclk is running at 4 mhz. changes in tcapclk frequency will cause a corresponding change in the 1024- s interval timer frequency bits 3:2 itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bits 1:0 itmrclk select 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator ? exter nal crystal oscillator on clkin and clkout if the external cryst al oscillator is enabl ed, clkin input if the external cr ystal oscillator is disabled 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 26 of 85 interval timer clock (itmrclk) the interval timer clock (itmrclk) can be sourced from the external crystal oscillator, the internal 24-mhz oscillator, the internal 32-khz low-power oscillator, or the timer capture clock. a programmable prescaler of 1, 2, 3, or 4 then divides the selected source. the 12-bit programmable interval timer is a simple down counter with a programmable reload value. it provides a 1- s resolution by default. when the down counter reaches zero, the next clock is spent reloading. the reload value can be read and written while the counter is running, but care should be taken to ensure that the counter does not unintentionally reload while the 12-bit reload value is only partially stored?for exam ple, between the two writes of the 12-bit value. the programmable interval timer generates an interrupt to the cpu on each reload. the parameters to be set will appear on the device editor view of psoc designer once you place the cyrf69213 timer user module. the parameters are pitimer_source and pitimer_divider. the pitimer_s ource is the clock to the timer and the pitmer_divider is the value the clock is divided by. the interval register (pitmr) holds the value that is loaded into the pit counter on terminal count. the pit counter is a down counter. the programmable interval timer resolution is configurable. for example: tcapclk divide by x of cpu clock (for example tcapclk divide by 2 of a 24-mhz cpu clock will give a frequency of 12 mhz) itmrclk divide by x of tcapclk (for example, itmrclk divide by 3 of tcapclk is 4 mhz so resolution is 0.25 s) timer capture clock (tcapclk) the timer capture clock can be sourced from the external crystal oscillator, internal 24-mhz oscillator or the internal 332-khz low-power oscillator. a programmable prescaler of 2, 4, 6, or 8 then divide s the selected source. figure 10. programmable inte rval timer block diagram system clock clock timer configuration status and control 12-bit reload value 12-bit down counter 12-bit reload counter interrupt c ontroller [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 27 of 85 figure 11. timer capture block diagram cpu clock during sleep mode when the cpu enters sleep mode the cpuclk select (bit [0], ta b l e 3 3 ) is forced to the internal oscillator, and the oscillator is stopped. when the cpu comes out of sleep mode it is running on the internal oscillator. the internal oscillator recovery time is three clock cycles of the internal 32-khz low-power oscillator. if the system requires the cpu to run off the external clock after awakening from sleep mode, firmware will need to switch the clock source for the cpu. reset the microcontroller supports two types of resets: power-on reset (por) and watchdog reset (wdr). when reset is initiated, all registers are restored to their default states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and control register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware can interrogate these bits to determine the cause of a reset. the microcontroller resumes execution from flash address 0x0000 after a reset. the internal clocking mode is active after a reset, until changed by user firmware. note the cpu clock defaults to 3 mhz (internal 24-mhz oscil- lator divide-by-8 mode) at por to guarantee operation at the low v cc that might be present during the supply ramp. 16-bit counter configuration status and control prescale mux capture registers interrupt controller 1ms tim er overflow interrupt captimer clock system clock capture0 int capture1 in t table 37.clock i/o config (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved clkout select read/write ? ? ?- - - r/w r/w default 0 0 0000 0 0 bits 7:2 reserved bits 1:0 clkout select 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator ? exter nal crystal oscillator on clkin and clkout if the external cryst al oscillator is enabl ed, clkin input if the external oscillator is disabled 1 0 = internal 32-khz low-power oscillator 1 1 = cpuclk [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 28 of 85 power-on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6v for the upward supply transition, with typically 50 mv of hysteresis during the power-on transient. bit 4 of the system status and control register (cpu_scr) is set to record this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the v cc supply to stabilize before executing the first instruction at address 0x00 in the flash. if the v cc voltage drops below the por downward supply trip point, por is reasserted. the v cc supply needs to ramp linearly from 0 to 4v in 0 to 200 ms. important the pors status bit is set at por and can only be cleared by the user. it cannot be set by firmware. watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. once the pors bit is cleared, the wdt cannot be disabled. the only exception to this is if a por event takes place, which will disable the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer is clocked by the internal 32-khz low-power osc illator system clock. the user can program the sleep time period using the sleep timer bits of the osc_cr0 register ( ta b l e 3 4 ). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector will be generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflows. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user can either clear the wdt, or the wdt and the sleep timer. whenever the user writ es to the reset wdt register (res_wdt), the wdt will be cleared. if the data that is written is the hex value 0x38, the sleep timer will also be cleared at the same time. table 38.system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved stop read/write r ? r/c [3] r/c [3] r/w ? ? r/w default 0 0 0 1 00 0 0 the bits of the cpu_scr register are used to convey status and control of events for various functions of an cyrf69213 device bit 7 gies the global interrupt enable status bit is a read only status bi t and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_f regi ster. however, the cpu_f register is now readable. when this b it is set, it indicates that the gie bit in the cpu_f register is al so set which, in turn, indicates that the microprocessor will service interrupts 0 = global interrupts disabled 1 = global interrupt enabled bit 6 reserved bit 5 wdrs the wdrs bit is set by the cpu to indicate that a wdr event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no wdr 1 = a wdr event has occurred bit 4 pors the pors bit is set by the cpu to indicate that a por event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no por 1 = a por event has occurred. (note that wdr ev ents will not occur until this bit is cleared) bit 3 sleep set by the user to enable cpu sleep state. cpu will remain in sleep mode until any in terrupt is pending. the sleep bit is cover ed in more detail in the sleep mode section 0 = normal operation 1 = sleep bit 2:1 reserved bit 0 stop this bit is set by the user to halt the cp u. the cpu will remain halted until a reset (wdr, por, or external reset) has taken place. if an application wants to stop code execution until a rese t, the preferred method would be to use the halt instruction rather than writing to this bit 0 = normal cpu operation 1 = cpu is halted (not recommended) note 3. c = clear. this bit can only be cleared by the user and cannot be set by firmware [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 29 of 85 sleep mode the cpu can only be put to sleep by the firmware. this is accomplished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu will remain asleep until an interrupt comes pending, or there is a reset event (either a power-on reset, or a watchdog timer reset). the low-voltage detection circuit (lvd) drops into fully functional power-reduced states , and the laten cy for the lvd is increased. the actual latency can be traded against power consumption by changing the sl eep duty cycle field of the eco_tr register. the internal 32-khz low-speed oscillator remains running. prior to entering suspend mode, firmware can optionally configure the 32-khz low-speed oscillator to operate in a low-power mode to help reduce the overall power consumption (using bit 7, table 32 ). this will help save approximately 5 a; however, the trade off is that the 32-khz low-speed oscillator will be less accurate. all interrupts remain active. only the occurrence of an interrupt will wake the part from sleep. the stop bit in the system status and control register (cpu_scr) must be cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not have any effect. any unmasked interrupt will wake the system up. as a result, any interrupts not intended for waking must be disabled through the interrupt mask registers. when the cpu enters sleep mo de the cpuclk select (bit 1, ta b l e 3 3 ) is forced to the internal oscillator. the internal oscil- lator recovery time is three cl ock cycles of the internal 32-khz low-power oscillator. the internal 24-mhz oscillator restarts immediately on exiting sleep mode. if an external clock is used, firmware will need to switch the clock source for the cpu. on exiting sleep mode, once the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system co mponents while maintaining very low average power consumption. the sleep interrupt may also be used to provide periodic interrupts during non-sleep modes. sleep sequence the sleep bit is an input into the sleep logic circuit. this circuit is designed to sequence the device into and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 12 and is defined as follows. 1. firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immediately asserted. this is a request by the system to halt cpu op- eration at an instruction boundary. the cpu samples brq on the positive edge of cpuclk. 2. due to the specific timing of the register write, the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clo ck. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system-wide power down (pd) signal. in figure 12 the cpu is halted an d the system-wide power down signal is asserted. 3. the system-wide pd (power down) signal controls several major circuit blocks: the flash memory module, the internal 24-mhz oscillator, the eftb filter and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on chip are the low power oscillator, the bandgap refresh circuit, and the supply voltage monitor (por/lvd) circuit. note to achieve the lowest possible power consumption during suspend/sleep, the following conditions must be observed in addition to considerations for the sleep timer. ? all gpios must be set to outputs and driven low ? the usb pins p1.0 and p1.1 should be configured as inputs with their pull ups enabled. table 39.reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w ww w w default 0 0 0 0 00 0 0 any write to this register will clear watchdog timer, a write of 0x38 will also clear the sleep timer bits 7:0 reset watchdog timer [7:0] [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 30 of 85 figure 12. sleep timing wakeup sequence once asleep, the only event th at can wake the system up is an interrupt. the global interrupt enable of the cpu flag register does not need to be set. any unmasked interrupt will wake the system up. it is optiona l for the cpu to actually take the interrupt after the wakeup sequence. the wakeup sequence is synchronized to the 32-khz clock for purposes of sequencing a startup delay, to allow the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the delay is to allow the oscillator, bandgap, and lvd/por circuits time to settle before actually being used in the system. as shown in figure 13 , the wakeup sequence is as follows: 1. the wakeup interrupt occurs and is synchronized by the negative edge of the 32-khz clock. 2. at the following positive ed ge of the 32-khz clock, the system-wide pd signal is negated. the flash memory module, internal oscillator, eftb, and bandgap circuit are all powered up to a normal operating state. 3. at the following positive edge of the 32-khz clock, the current values for the precision por and lvd have settled and are sampled. 4. at the following negative edge of the 32-khz clock (after about 15 s nominal), the brq signal is negated by the sleep logic circuit. on the following cpuclk, bra is negated by the cpu and instruction execution resumes. note that in figure 13 fixed function blocks, such as flash, internal oscillator, eftb, and bandgap, have about 15 s start up. the wakeup times (interrupt to cpu operational) will range from 75 s to 105 s. firmware write to scr sleep bit causes an immediate brq iow sleep brq pd bra cpuclk cpu captures brq on next cpuclk edge cpu responds with a bra on the falling edge of cpuclk, pd is asserted. the 24/48 mhz system clock is halted; the flash and bandgap are powered down [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 31 of 85 figure 13. wakeup timing int sleep pd lvd ppor bandgap clk32k sample sample lvd/por cpuclk/ 24mhz bra brq enable cpu (not to scale) sleep timer or gpio interrupt occurs interrupt is double sampled by 32k clock and pd is negated to system cpu is restarted after 90 ms (nominal) [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 32 of 85 low-voltage detect control por compare state table 40.low-voltage control re gister (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[2:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the power-on reset/low-voltage detection block bits 7:6 reserved bits 5:4 porlev[1:0] this field controls the level belo w which the precision power-on-reset (ppor) detector generates a reset 0 0 = 2.7v range (trip near 2.6v) 0 1 = 3v range (trip near 2.9v) 1 0 = 5v range, > 4.75v (trip near 4.65v) 1 1 = ppor will not generate a reset, but values read from the voltage monitor comparators register ( ta b l e 4 1 ) give the inter- nal ppor comparator state with trip point set to the 3v range setting bit 3 reserved bits 2:0 vm[2:0] this field controls the level below which the low-voltage-det ect trips?possibly generating an interrupt and the level at which the flash is enabled for operation. vm[2:0] lvd trip point (v) min. typical max. 000 2.681 2.70 2.735 001 2.892 2.92 2.950 010 2.991 3.02 3.053 011 3.102 3.13 3.164 100 4.439 4.48 4.528 101 4.597 4.64 4.689 110 4.680 4.73 4.774 111 4.766 4.82 4.862 table 41.voltage monitor comparator s register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ?? r r default 0 0 0 0 00 0 0 this read-only register allows reading the current state of the low-voltage-detection and precis ion-power-on-reset comparators bits 7:2 reserved bit 1 lvd this bit is set to indicate that the low-voltage-detect compar ator has tripped, indicating that the supply voltage has gone bel ow the trip point set by vm[2:0] (see ta b l e 4 0 ) 0 = no low-voltage-detect event 1 = a low-voltage-detect has tripped bit 0 ppor this bit is set to indicate that the pr ecision-power-on-reset comparat or has tripped, indicating that the supply voltage is bel ow the trip point set by porlev[1:0] 0 = no precision-power-on-reset event 1 = a precision-power-on-reset event has tripped [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 33 of 85 eco trim register general-purpose i/o ports the general-purpose i/o ports are discussed in the following sections. port data registers table 42.eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in numbers of 32-khz clock per iods) of ?on? time versus ?o ff? time for lvd and por detection circuit bits 7:6 sleep duty cycle [1:0] 0 0 = 128 periods of the internal 32-khz low-speed oscillator 0 1 = 512 periods of the internal 32-khz low-speed oscillator 1 0 = 32 periods of the internal 32-khz low-speed oscillator 1 1 = 8 periods of the inter nal 32-khz low-speed oscillator table 43.p0 data register (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 reserved reserved p0.4/int2 p0.3/int1 p0.2/int0 reserved reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 00000000 this register contains the data for port 0. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 0 pins bit 7 p0.7 data bits 6:5 reserved the use of the pins as the p0.6?p0.5 gpios an d the alternative functi ons exist in the cyrf69213 bits 4:2 p0.4?p0.2 data/int2 ? int0 in addition to their use as the p0.4?p0.2 gp ios, these pins can also be used for the al ternative functions as the interrupt pin s (int0?int2). to configure the p0.4?p0.2 pins, refer to the p0.2/int0?p0.4/int2 configuration register ( table 46 ) the use of the pins as the p0.4?p0.2 gpios an d the alternative functi ons exist in the cyrf69213 bit 1 reserved bit 0 reserved table 44.p1 data register (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 34 of 85 gpio port configuration all the gpio configuration registers have common configu- ration controls. the following are the bit definitions of the gpio configuration registers. int enable when set, the int enable bit allows the gpio to generate inter- rupts. interrupt generate can occur regardless of whether the pin is configured for input or output. all interrupts are edge sensitive, however for any interr upt that is shared by multiple sources (that is, ports 2, 3, and 4) all inputs must be deasserted before a new interrupt can occur. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin and then to generate the interrupt by driving the appropriate pin state. this is useful in test and may have value in applications as well. int act low when set, the corresponding interrupt is active on the falling edge. when clear, the corresponding interrupt is active on the rising edge. ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. high sink when set, the output can sink up to 50 ma. when clear, the output can sink up to 8 ma. on the cyrf69213, only the p1.7?p1.3 have 50-ma sink drive capability. other pins have 8-ma sink drive capability. open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, the pin is in high-impedance state. if the corresponding bit in the port data register is clear, the pin is driven low. when clear, the output is driven low or high. pull-up enable when set the pin has a 7k pull up to v cc (or vreg for ports with v3.3 enabled). when clear, the pull up is disabled. output enable when set, the output driv er of the pin is enabled. when clear, the output driver of the pin is disabled. for pins with shared functions there are some special cases. vreg output/spi use the p1.2 (vreg), p1.3 (ssel) , p1.4 (sclk), p1.5 (smosi) and p1.6 (smiso) pins can be used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding vreg output or spi use bit. the spi function controls the output enable for its dedicated function pins when their gpio enable bit is clear. this register contains the data for port 1. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 1 pins bit 7 p1.7 data bits 6:3 p1.6?p1.3 data/spi pins (smiso, smosi, sclk, ssel) in addition to their use as the p1.6?p1.3 gp ios, these pins can also be used for the al ternative function as the spi interface pins. to configure the p1.6?p1.3 pins, refer to the p1.3?p1.6 configuration register ( ta b l e 5 1 ) the use of the pins as the p1.6?p1.3 gpios and the alternative functions exist in all the cyrf69213 parts bit 2 p1.2/vreg a 1- f min, 2- f max capacitor is required on vreg output. bits 1:0 p1.1?p1.0/d? and d+ when usb mode is disabled (bit 7 in ta b l e 7 6 is clear), the p1.1 and p1.0 bits are used to control the state of the p1.0 and p1.1 pins. when the usb mode is enabled, the p1.1 and p1.0 pi ns are used as the d? and d+ pins, respectively. if the usb force state bit (bit 0 in table 74 ) is set, the state of the d? and d+ pins can be controlled by writing to the d? and d+ bits table 44.p1 data register (p1data) [0x01] [r/w] table 45.p2 data register (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p2.1?p2.0 read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 2. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins bits 7:2 reserved data [7:2] bits 1:0 p2 data [1:0] [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 35 of 85 3.3v drive the p1.3 (ssel), p1.4 (scl k), p1.5 (smosi) and p1.6 (smiso) pins have an alternat e voltage source from the voltage regulator. if the 3.3v drive bit is set a high level is driven from the voltage regulator instead of from v cc . setting the 3.3v drive bit does not enable the voltage regulator. that must be done explicitly by setting the vreg enable bit in the vregcr register ( table 75 ). figure 14. block diagram of a gpio v cc vreg v cc vreg gpi o pi n r up dat a ou t v cc gnd vreg gnd 3.3v drive pull-up enable output enable open drain port data high sink data in ttl threshol d table 46.p0.2/int0?p0.4/int2 configur ation (p02cr?p04cr) [0x07?0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull-up enable output enable read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p0.2?p0.4, respec tively. these pins are shared between the p0.2?p0.4 gpios and th e int0?int2. these registers exist in all cyrf69213 parts. the int0?int2 inte rrupts are different than all the other gpio interrupts. these pins are connected directly to the interrupt controller to provide three edge-se nsitive interrupts with independent interrupt vectors. these inter rupts occur on a rising edge when int act low is clear and on a falling edge when int act low is set. these pins are enabled as interrupt sources in th e interrupt controller registers ( table 72 and ta b l e 7 0 ) to use these pins as interrupt inputs conf igure them as inputs by clearing the co rresponding output enable. if the int0?int2 pi ns are configured as outputs with interrupts enabled, firmware can generate an in terrupt by writing the appropriate value to the p0.2, p0.3 and p 0.4 data bits in the p0 data register regardless of whether the pins are used as interrupt or gpio pi ns the int enable, int act low, ttl threshold, open drain, and p ull-up enable bits control the behavior of the pin the p0.2/int0?p0.4/int2 pins are individual ly configured with the p02cr (0x07), p03c r (0x08), and p04cr (0x09), respectively. note changing the state of the int act low bit can cause an unintent ional interrupt to be generated. when configuring these interru pt sources, it is best to follow the following procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 36 of 85 table 47.p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of pin p0.7. table 48.p1.0/d+ configuration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved reserved output enable read/write r/w r/w r/w ? ?? ? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.0 (d+) pin w hen the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 76 for information on enabling usb. when usb is enabled, none of the controls in this register have any effect on the p1.0 pin note the p1.0 is an open drain only output. it can actively dr ive a signal low, but cannot actively drive a signal high bit 1 ps/2 pull-up enable 0 = disable the 5k-ohm pull-up resistors 1 = enable 5k-ohm pull-up resistors for both p1.0 and p1.1. enable the use of the p1.0 (d+) and p1.1 (d?) pins as a ps2 style interface table 49.p1.1/d? configuration (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved open drain reserved output enable read/write ? r/w r/w ? ?r/w? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.1 (d?) pin when the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 76 for information on enabling usb. when usb is enabled, none of the controls in this register have any effect on the p1.1 pin. when usb is disabled, the 5-kohm pull-up resistor on this pin can be enabled by the ps/2 pull-up enable bit of the p1 0cr register ( table 48 ) note there is no 2-ma sourcing capability on th is pin. the pin can only sink 5 ma at v ol3 table 50.p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl threshol d reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.2 bit 7 clk output 0 = the internally selected clock is not sent out onto p1.2 pin 1 = when clk output is set, the internally selected clock is sent out onto p1.2 pin [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 37 of 85 table 51.p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.3 pin. this register exists in all cyrf69213 parts the p1.3 gpio?s threshold is always set to ttl when the spi hardware is enabled, the output enable and output state of the pin is controlled by the spi circuitry. when the sp i hardware is disabled, the pin is controlled by the output enabl e bit and the corresponding bit in the p1 data register regardless of whether the pin is used as an spi or gpio pin the int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin the 50-ma sink drive capability is only available in the cy7c638xx. table 52.p1.4?p1.6 configuration (p14cr?p16cr) [0x11?0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p1.4?p1.6, respectively the p1.4?p1.6 gpio?s threshold is always set to ttl when the spi hardware is enabled, pins that are configured as spi use have their output enable and output state controlled by t he spi circuitry. when the spi hardware is disabled or a pin has its spi use bit cl ear, the pin is controlled by the output enable bit and the co rresponding bit in the p1 data register regardless of whether any pin is used as an spi or gpio pin t he int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin bit 7 spi use 0 = disable the spi alternate func tion. the pin is used as a gpio 1 = enable the spi function. the spi circuitry controls the output of the pin important note for comm modes 01 or 10 (spi master or spi slave, see ta b l e 5 6 ) when configured for spi (spi use = 1 and comm modes [1:0] = spi mast er or spi slave mode), the input/output direction of pins p 1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1 .4's input/output direction is no t automatically set; it must be explicitly set by firmware. for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input table 53. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register controls the operation of pin p1.7. this register only exists in cy7c638xx the 50-ma sink drive capability is only available in the cy7c638xx. the p1.7 gpio?s threshold is always set to ttl table 54.p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register only exists in cy7c638xx. this register controls the operation of pins p2.0?p2.1. in the cy7c638xx, only 8-ma sin k drive capability is available on this pi n regardless of the setting of the high sink bit [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 38 of 85 serial peripheral interface (spi) the spi master/slave interface core logic runs on the spi cl ock domain, making its functiona lity independent of system clock speed. spi is a four pin serial interface comprised of a clock, an enable and two data pins. figure 15. spi block diagram spi state machine ss_n data (8 bit) load empty data (8 bit) load full sclk output enable slave select output enable master in, slave out oe master out, slave in, oe shift buffer input shift buffer output shift buffer sck clock generation sck clock select sck clock phase/polarity select register block sck speed sel master/slave sel sck polarity sck phase little endian sel miso/mosi crossbar gpio block ss_n le_sel sck le_sel sck_oe ss_n_oe miso_oe mosi_oe sck sck_oe ss_n_oe sck ss_n master/slave set miso mosi miso_oe mosi_oe [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 39 of 85 spi data register when an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty, firmware has 7 spi clocks to manage the buffers?to empty the receiv er buffer, or to refill the transmit holding register. failu re to meet this timing requirement will result in incorrect data transfer. spi configure register table 55.spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the contents of the receive buffer. when written, it loads the transmit holding register bits 7:0 spi data [7:0] table 56.spi configure register (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 swap 0 = swap function disabled 1 = the spi block swaps its use of smosi and smiso. among other things, this can be useful in implementing single wire spi-like communications bit 6 lsb first 0 = the spi transmits and receives t he msb (most significant bit) first 1 = the spi transmits and receives the lsb (least significant bit) first. bits 5:4 comm mode [1:0] 0 0: all spi communication disabled 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3 cpol this bit controls the spi clock (sclk) idle polarity 0 = sclk idles low 1 = sclk idles high bit 2 cpha the clock phase bit contro ls the phase of the clock on which data is sampled. ta b l e 5 7 shows the timing for the various com- binations of lsb first, cpol, and cpha bits 1:0 sclk select this field selects the speed of the master sclk. when in master mode, sclk is generated by dividing the base cpuclk important note for comm modes 01b or 10b (spi master or spi slave): when configured for spi, (spi use = 1? ta b l e 5 2 ), the input/output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input/output direction is not automatically set; it must be explicitly set by fi rmware. for spi master mode , pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 40 of 85 table 57.spi mode timing vs. lsb first, cpol and cpha lsb first cpha cpol diagram 000 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 41 of 85 timer registers all timer functions of the cyrf 69213 are provided by a single timer block. the timer block is asynchronous from the cpu clock. registers free-running counter the 16-bit free-running counter is clocked by a 4/6-mhz source. it can be read in software for use as a general-purpose time base. when the low order byte is read, the high order byte is registered. reading the high order byte reads this register allowing the cpu to read the 16-b it value atomically (loads all bits at one time). the free-runni ng timer generates an interrupt at a 1024- s rate. it can also generate an interrupt when the free-running counter overflow occurs?every 16.384 ms. this allows extending the length of the timer in software. figure 16. 16-bit free-running counter block diagram table 58.spi sclk frequency sclk select cpuclk divisor sclk frequency when cpuclk = 12 mhz 24 mhz 00 6 2 mhz 4 mhz 01 12 1 mhz 2 mhz 10 48 250 khz 500 khz 11 96 125 khz 250 khz timer capture clock 16-bit free running counter overflow interrupt 1024- s timer interrupt table 59.free-running timer low-ord er byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 free-running timer [7:0] this register holds the low-order byte of the 16-bit free-runni ng timer. reading this register c auses the high-order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. for reads, the actual read occurs in the cycle when the low order is read. for writes, the actual time the write occurs is the cycle when the high order is written when reading the free-running timer, the low-order byte should be read first and the high-order second. when writing, the low-o rder byte should be written first then the high-order byte table 60.free-running timer high-order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 free-running timer [15:8] when reading the free-running timer, the low-order byte should be read first and the high-order second. when writing, the low-o rder byte should be written first then the high-order byte [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 42 of 85 table 61.programmable interval timer low (pitmrl) [0x26] [r] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bits 7:0 ?prog interval timer [7:0] this register holds the low-order byte of the 12-bit programmabl e interval timer. reading this r egister causes the high-order b yte to be moved into a holding register allowing an auto matic read of all 12 bits simultaneously table 62.programmable interval timer high (pitmrh) [0x27] [r] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write ? ? ? ? rr r r default 0 0 0 0 00 0 0 bits 7:4 reserved bits 3:0 prog internal timer [11:8] this register holds the high-order nibble of the 12-bit programmable interval timer. reading this register returns the high-ord er nibble of the 12-bit timer at the instant that the low-order byte was last read table 63.programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:0 prog interval [7:0] this register holds the lower 8 bits of the timer. while writi ng into the 12-bit reload register, write lower byte first then t he higher nibble table 64.programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bits 7:4 reserved bits 3:0 prog interval [11:8] this register holds the higher 4 bits of the timer. while writ ing into the 12-bit reload register, write lower byte first then the higher nibble [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 43 of 85 figure 17. 16-bit free-running counter loading timing diagram figure 18. memory mapped registers read/write timing diagram clk_sys write valid addr write data frt reload ready clk timer 12b prog timer 12b reload interrupt capture timer clk 16b free running counter load 16b free running counter 00a0 00a1 00a2 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00ab 00ac 00ad 00ae 00af 00b0 00b1 00b2 acbe acbf acc0 16-bit free running counter loading timing 12-bit programmable timer load timing memory mapped registers read/write timing diagram clk_sys rd_wrn valid addr rdata wdata [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 44 of 85 interrupt controller the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functional block in the cyrf69213 devices. the registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. the registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. the following table lists all interrupts and the priorities that are available in the cyrf69213. architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 19 clocking in a ?1?. the interrupt will remain posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which will be taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. it simply prevents a posted interrupt from becoming pending. nested interrupts can be accomplished by re-enabling inter- rupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the cyrf69213 interrupt controller is shown in figure 19 . figure 19. interrupt co ntroller block diagram table 65.interrupt number s, priorities, vectors interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7001chint1 8 0020h ep0 9 0024h ep1 10 0028h ep2 11 002ch usb reset 12 0030h usb active 13 0034h 1-ms interval timer 14 0038h programmable interval timer 15 003ch reserved 16 0040h reserved 17 0044h 16-bit free running timer wrap 18 0048h int2 19 004ch reserved 20 0050h gpio port 2 21 0054h reserved 22 0058h reserved 23 005ch reserved 24 0060h reserved 25 0064h sleep timer table 65.interrupt number s, priorities, vectors (continued) interrupt priority interrupt address name interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit settin g d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ... [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 45 of 85 interrupt processing the sequence of events that occur during interrupt processing is as follows: 1. an interrupt becomes active, either because: a. the interrupt condition occurs (for example, a timer expires). b. a previously posted interrupt is enabled through an update of an interrupt mask register. c. an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. 2. the current executing instruction finishes. 3. the internal interrupt is di spatched, taking 13 cycles. during this time, the following actions occur: a. the msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the program stack by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. b. the pch, pcl, and flag r egister (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. c. the cpu_f register is then cleared. since this clears the gie bit to 0, additional interrupts are temporarily disabled d. the pch (pc[15:8]) is cleared to zero. e. the interrupt vector is read from the interrupt controller and its value placed into pcl (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the por/lvd interrupt). 4. program execution vectors to the interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service ro utine (isr) for this interrupt. 5. the isr executes. note that interrupts are disabled since gie = 0. in the isr, interrupts can be re-enabled if desired by setting gie = 1 (care must be taken to avoid stack overflow). 6. the isr ends with a reti inst ruction which restores the program counter and flag registers (cpu_pc and cpu_f). the restored flag register re-enables interrupts, since gie = 1 again. 7. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction. interrupt latency the time between the assertion of an enabled interrupt and the start of its isr can be calculated from the following equation. latency = time for current inst ruction to finish + time for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5-cycle jmp instruction is executing when an interrupt becomes active, the total number of cpu clock cycles before the isr begins would be as follows: (1 to 5 cycles for jmp to fini sh) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the example above, at 24 mhz, 25 clock cycles take 1.042 s. interrupt registers the interrupt registers are discu ssed it the following sections. interrupt clear register the interrupt clear registers (int_clrx) are used to enable the individual interrupt sources? ability to clear posted inter- rupts. when an int_clrx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. therefore, reading these registers gives the user the ability to determine all posted interrupts. table 66. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 46 of 85 interrupt mask registers the interrupt mask registers (int_mskx) are used to enable the individual interrupt sources? ability to create pending inter- rupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_msk3), which may be referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit may generate an interrupt that will become a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when is cleared, writing 1's to an int_clrx register has no effect. however, writing 0's to an int_clrx register, when enswint is cleared, will cause the corresponding inte rrupt to clear. if th e enswint bit is set, any 0?s written to the int_clrx registers are ignored. however, 1?s written to an int_clrx register, while enswint is set, will cause an interrupt to post for the corresponding interrupt. software interrupts can aid in debugging interrupt service routines by eliminat ing the need to create system level inter- actions that are sometime s necessary to create a hardware-only interrupt. table 67. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt bit 7 reserved table 68.interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved reserved gpio port 2 reserved int2 16-bit counter wrap reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt bits 7,6,5,3,0 reserved table 69.interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r/w ? ? ? ? ? ? ? default 0 0 0 0 00 0 0 bit 7 enable software interrupt (enswint) 0 = disable. writing 0?s to an int_clrx register, when ensw int is cleared, will cause t he corresponding interrupt to clear 1 = enable. writing 1?s to an int_clrx register, when ensw int is set, will cause the corresponding interrupt to post bits 6:0 reserved [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 47 of 85 table 70.interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved reserved gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable reserved read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 reserved bit 6 reserved bit 5 reserved bit 4 gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3 reserved bit 2 int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0 reserved table 71.interrupt mask 1 (int_msk1) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 reserved bit 6 prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5 1-ms timer interrupt enable 0 = mask 1-ms interrupt 1 = unmask 1-ms interrupt bit 4 usb active interrupt enable 0 = mask usb active interrupt 1 = unmask usb active interrupt bit 3 usb reset interrupt enable 0 = mask usb reset interrupt 1 = unmask usb reset interrupt bit 2 usb ep2 interrupt enable 0 = mask ep2 interrupt 1 = unmask ep2 interrupt bit 1 usb ep1 interrupt enable 0 = mask ep1 interrupt 1 = unmask ep1 interrupt bit 0 usb ep0 interrupt enable 0 = mask ep0 interrupt 1 = unmask ep0 interrupt [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 48 of 85 interrupt vector clear register table 72. interrupt mask 0 (int_msk0) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 6 sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 5 int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 4 gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 3 spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 2 spi transmit interrupt enable 0 = mask spi transmit interrupt 1 = unmask spi transmit interrupt bit 1 int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 0 por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt table 73.interrupt vector clear register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the interrupt vector clear register (int_vc) holds the interr upt vector for the highest priority pending interrupt when read, a nd when written will clear all pending interrupts bits 7:0 pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest prio rity pending interrupt. writing to this register will clear all pending interrupts [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 49 of 85 usb transceiver usb transceiver configuration vreg control table 74.usb transceiver configure register (usbxcr) [0x74] [r/w] bit # 7 6 5 4 3 2 1 0 field usb pull-up enable reserved usb force state read/write r/w ? ? ? ? ? ? r/w default 0 0 0 0 00 0 0 bit 7 usb pull-up enable 0 = disable the pull-up resistor on d? 1 = enable the pull-up resistor on d?. this pull-up is to v cc if vreg is not enabled or to the internally generated 3.3v when vreg is enabled bits 6:1 reserved bit 0 usb force state this bit allows the state of the usb i/o pins dp and d+ to be forced to a state while usb is enabled 0 = disable usb force state 1 = enable usb force state. allows the d? and d+ pins to be controlled by p1.1 and p1.0 respectively when the usbio is in usb mode. refer to table 44 for more information note the usb transceiver has a dedicated 3.3v r egulator for usb signalling purposes and to pr ovide for the 1.5k d? pull up. unlike t he other 3.3v regulator, this regulator cannot be c ontrolled/accessed by firmware. when the dev ice is suspended, this regulator is disab led along with the bandgap (which provides the reference voltage to the regulator) and the d? line is pulled up to 5v through an alternate 6.5 k resistor. during wakeup following a suspend, the band gap and the regulator are swit ched on in any order. under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator and t he band gap turn on in that particular order, there is possib ility of a glitch/low pulse occurring on the d? line. the host ca n misinterpret this as a deattach condi tion. this condition, although rare, can be a voided by keeping the bandgap circuitry enabled during sleep. this is achieved by setting the ?no buzz? bi t, bit[5] in the osc_cr0 register. this is an issue only if the device is put to sleep during a bus reset condition table 75.vreg control register (vregcr) [0x73] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved keep alive vreg enable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 00 0 0 bits 7:2 reserved bit 1 keep alive keep alive when set allows the voltage regulator to source up to 20 a of current when voltage regulator is disabled, p12cr[0],p12cr[7] should be cleared. 0 = disabled 1 = enabled bit 0 vreg enable this bit turns on the 3.3v voltage regulator. the voltage regulator only functions with in specifications when v cc is above 4.35v. this block should not be enabled when v cc is below 4.35v?although no damage or irr egularities will occur if it is enabled below 4.35v 0 = disable the 3.3v voltage regulator output on the vreg/p1.2 pin 1 = enable the 3.3v voltage regulator output on the vr eg/p1.2 pin. gpio functionality of p1.2 is disabled note use of the alternate drive on pins p1.3?p1.6 requires that t he vreg enable bit be set to enable the regulator and provide the alternate voltage [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 50 of 85 usb serial interface engine (sie) the sie allows the microcontroller to communicate with the usb host at low-speed data rates (1.5 mbps). the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: ? translating the encoded received data and formatting the data to be transmitted on the bus ? crc checking and generation. flagging the microcontroller if errors exist during transmission ? address checking. ignoring the transactions not addressed to the device ? sending appropriate ack/nak/stall handshakes ? identifying token type (setup, in, or out). setting the appropriate token bit once a valid token is received ? placing valid received data in the appropriate endpoint fifos ? sending and updating the data toggle bit (data1/0) ? bit stuffing/unstuffing. firmware is required to handle t he rest of the usb interface with the following tasks: ? coordinate enumeration by decoding usb device requests ? fill and empty the fifos ? suspend/resume coordination ? verify and select data toggle values usb device table 76.usb device address (usbcr) [0x40] [r/w] bit # 7 6 5 4 3 2 1 0 field usb enable device address[6:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the content of this register is cleared when a usb bus reset condition occurs bit 7 usb enable this bit must be enabled by firmware before the serial interf ace engine (sie) will respond to usb traffic at the address specif ied in device address [6:0]. when this bit is cleared, the usb transceiver enters power- down state. user?s firmware should clear this bit prior to entering sleep mode to save power 0 = disable usb device address and put the usb transceiver into power-down state 1 = enable usb device address and put the usb transceiver into normal operating mode bits 6:0 device address [6:0] these bits must be set by firmware during the usb enumeration process (for example, setaddress) to the non-zero address assigned by the usb host table 77.endpoint 0, 1, and 2 count (ep0cnt?ep2cnt) [0x41, 0x43, 0x45] [r/w] bit # 7 6 5 4 3 2 1 0 field data toggle data valid reserved byte count[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 data toggle this bit selects the data packet's toggle state. for in transac tions, firmware must set this bit to the select the transmitted data toggle. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. 0 = data0 1 = data1 bit 6 data valid this bit is used for out and setup tokens on ly. this bit is cleared to ?0? if crc, bi tstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings 0 = data is invalid. if enabled, the endpoint interr upt will occur even if in valid data is received 1 = data is valid bits 5:4 reserved bits 3:0 byte count bit [3:0] byte count bits indicate the number of data bytes in a transactio n: for in transactions, firmware loads the count with the numb er of bytes to be transmitted to the host from the endpoint fifo. vali d values are 0 to 8 inclusive. for out or setup transactions, t he count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2?10 inclusive. for endpoint 0 count register, whenever the count updates from a setup or out transaction, the count register locks and cannot be written by the cpu. reading the register unlocks it. this pr events firmware from overwriting a status update on it [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 51 of 85 endpoint 0 mode because both firmware and the sie are allowed to write to the endpoint 0 mode and count registers the sie provides an interlocking mechanism to prevent accidental overwriting of data. when the sie writes to these registers they are locked and the processor cannot write to them until after it has read them. writing to this register clears the upper four bits regardless of the value written. table 78.endpoint 0 mode (ep0mode) [0x44] [r/w] bit # 7 6 5 4 3 2 1 0 field setup received in received out received ack?d trans mode[3:0] read/write r/c[3] r/c[3] r/c[3] r/c[3] r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 setup received this bit is set by hardware when a valid setup packet is receiv ed. it is forced high from the start of the data packet phase of the setup transactions until the end of the data phase of a control write transfer and cannot be cleared during this interval. while this bit is set to ?1?, the cpu cannot write to the ep0 fifo. this prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data this bit is cleared by any non- locked writes to the register 0 = no setup received 1 = setup received bit 6 in received this bit, when set, indicates a valid in packet has been receiv ed. this bit is updated to ?1? after the host acknowledges an in data packet.when clear, it indicates that either no in has been re ceived or that the host didn?t acknowledge the in data by sen d- ing an ack handshake this bit is cleared by any non- locked writes to the register. 0 = no in received 1 = in received bit 5 out received this bit, when set, indicates a valid out packet has been received and acked. this bit is updated to ?1? after the last receive d packet in an out transaction. when clear, it indicates no out received this bit is cleared by any non- locked writes to the register 0 = no out received 1 = out received bit 4 ack?d transaction the ack?d transaction bit is set whenever the sie engages in a trans action to the register?s endpoint that completes with a ack packet this bit is cleared by any non- locked writes to the register 1 = the transaction completes with an ack 0 = the transaction does not complete with an ack bits 3:0 mode [3:0] the endpoint modes determine how the sie responds to usb traffi c that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoint [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 52 of 85 endpoint data buffers the three data buffers are used to hold data for both in and out transactions. each data buffer is 8 bytes long. the reset values of the endpoint data registers are unknown. unlike past encore parts the usb data buffers are onl y accessible in the i/o space of the processor. table 79.endpoint 1 and 2 mode (ep1mode ? ep2mode) [0x45, 0x46] [r/w] bit # 7 6 5 4 3 2 1 0 field stall reserved nak int enable ack?d transaction mode[3:0] read/write r/w r/w r/w r/c (note 3) r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7 stall when this bit is set the sie will stall an out packet if the mode bits are set to ack-out, and the sie will stall an in packet if the mode bits are set to ack-in. this bit must be clear for all other modes bit 6 reserved bit 5 nak int enable this bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a nak. unlike encore, cyrf69213 family members do not generate an endpoint inte rrupt under these conditions unless this bit is set 0 = disable interrupt on nak?d transactions 1 = enable interrupt on nak?d transaction bit 4 ack?d transaction the ack?d transaction bit is set whenever the sie engages in a tr ansaction to the register?s endpoint that completes with an ack packet this bit is cleared by any writes to the register 0 = the transaction does not complete with an ack 1 = the transaction completes with an ack bits 3:0 mode [3:0] the endpoint modes determine how the sie responds to usb traffi c that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoint. note when the sie writes to the ep1mode or the ep2mode register it blocks firmware writes to the ep2 mode or the ep1mode registers, respectively (if both writes occur in the same clock cycle). this is because the design em ploys only one common ?update? signal for both ep1mode and ep2mode registers. thus, when sie writes to the ep1 mode register, the update signal is set and this prevents firmwa re writes to ep2mode register. sie writes to the endpoint mode registers have higher priority than firmware writes. this mode register wr ite block situation can put the endpoints in incorrect modes. firmware must read the ep1/2mode registers immediately following a firmware write and rewrite if the value read is incorrect table 80.endpoint 0 data (ep0data) [0x50-0x57] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 0 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57 table 81.endpoint 1 data (ep1data) [0x58-0x5f] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 1 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5f [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 53 of 85 usb mode tables mode column the 'mode' column contains t he mnemonic names given to the modes of the endpoint. the mode of the endpoint is deter- mined by the four-bit binaries in the 'encoding' column as discussed in the following section. the status in and status out represent the status in or out stage of the control transfer. encoding column the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( ta b l e 7 8 and ta b l e 7 9 ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0] of the endpoint 0 mode register are set to '0001', which is nak in/out mode, the sie will send an ack handshake in response to setup tokens and nak any in or out tokens. setup, in, and out columns depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the sie's responses when the endpoint receives setup, in, and out tokens, respectively. a 'check' in the out column means that upon receiving an out token the sie checks to s ee whether the out is of zero length and has a data toggle (data1/0) of 1. if these condi- tions are true, the sie responds with an ack. if any of the above conditions is not met, the sie will respond with either a stall or ignore. a 'tx count' entry in the in column means that the sie will transmit the number of bytes specified in the byte count bit [3:0] of the endpoint count register ( ta b l e 7 7 ) in response to any in token. table 82.endpoint 2 data (ep2data) [0x60-0x67] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 2 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67 mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. used by data and control endpoints nak in/out 0001 accept nak nak nak in and out token. control endpoint only status out only 0010 accept stall check stall in and ack zero byte out. control endpoint only stall in/out 0011 accept stall stall stall in and out token. control endpoint only status in only 0110 accept tx0 byte stall stall out and send zero byte data for in token. control end- point only ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. control endpoint only ack in ? status out 1111 accept tx count check respond to in data or status out. control endpoint only nak out 1000 ignore ignore nak send nak handshake to out token. data endpoint only ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on issuance of ack handshake to an out. data endpoint only ack out (stall = 1) 1001 ignore ignore stall stall the out transfer nak in 1100 ignore nak ignore send nak handshake for in token. data endpoint only ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after receiving ack handshake to an in data. data endpoint only ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. data endpoint only reserved 0101 ignore ignore ignore these modes are not supported by sie. firmware should not use this mode in control and data endpoints reserved 0111 ignore ignore ignore reserved 1010 ignore ignore ignore reserved 0100 ignore ignore ignore reserved 1110 ignore ignore ignore [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 54 of 85 details of mode for differing traffic conditions control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo disabled 0000 x x x x ignore all stall_in_out 0011 setup >10 x x junk ignore 0011 setup <=10 invalid x junk ignore 0011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0011 in x x x stall stall in 0011 out >10 x x ignore 0011 out <=10 invalid x ignore 0011 out <=10 valid x stall stall out nak_in_out 0001 setup >10 x x junk ignore 0001 setup <=10 invalid x junk ignore 0001 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0001 in x x x nak nak in 0001 out >10 x x ignore 0001 out <=10 invalid x ignore 0001 out <=10 valid x nak nak out ack_in_status_out 1111 setup >10 x x junk ignore 1111 setup <=10 invalid x junk ignore 1111 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1111 in x x x tx host not ack'd 1111 in x x x tx 1 1 0001 yes host ack'd 1111 out >10 x x ignore 1111 out <=10 invalid x ignore 1111 out <=10, <>2 valid x stall 0011 yes bad status 1111 out 2 valid 0 stall 0011 yes bad status 1111 out 2 valid 1 ack 1 1 0010 1 1 2 yes good status status_out 0010 setup >10 x x junk ignore 0010 setup <=10 invalid x junk ignore 0010 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0010 in x x x stall 0011 yes stall in 0010 out >10 x x ignore 0010 out <=10 invalid x ignore 0010 out <=10, <>2 valid x stall 0011 yes bad status 0010 out 2 valid 0 stall 0011 yes bad status 0010 out 2 valid 1 ack 1 1 1 1 2 yes good status ack_out_status_in 1011 setup >10 x x junk ignore 1011 setup <=10 invalid x junk ignore 1011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1011 in x x x tx 0 host not ack'd [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 55 of 85 1011 in x x x tx 0 1 1 0011 yes host ack'd 1011 out >10 x x junk ignore 1011 out <=10 invalid x junk ignore 1011 out <=10 valid x ack 1 1 0001 update 1 update data yes good out status_in 0110 setup >10 x x junk ignore 0110 setup <=10 invalid x junk ignore 0110 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0110 in x x x tx 0 host not ack'd 0110 in x x x tx 0 1 1 0011 yes host ack'd 0110 out >10 x x ignore 0110 out <=10 invalid x ignore 0110 out <=10 valid x stall 0011 yes stall out data out endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack out (stall bit = 0) 1001 in x x x ignore 1001 out >max x x junk ignore 1001 out <=max invalid invalid junk ignore 1001 out <=max valid valid ack 1 1000 update 1 update data yes ack out ack out (stall bit = 1) 1001 in x x x ignore 1001 out >max x x ignore 1001 out <=max invalid invalid ignore 1001 out <=max valid valid stall stall out nak out 1000 in x x x ignore 1000 out >max x x ignore 1000 out <=max invalid invalid ignore 1000 out <=max valid valid nak if enabled nak out data in endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack in (stall bit = 0) 1101 out x x x ignore 1101 in x x x host not ack'd 1101 in x x x tx 1 1100 yes host ack'd ack in (stall bit = 1) 1101 out x x x ignore 1101 in x x x stall stall in nak in 1100 out x x x ignore 1100 in x x x nak if enabled nak in details of mode for differing traffic conditions (continued) [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 56 of 85 register summary addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 reserved reserved p0.4/int2 p0.3/int1 p0.2/int0 reserved reserved b--bbb-- 00000000 01 p1data p1.7 p1.6/smi so p1.5/smo si p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ bbbbbbbb 00000000 02 p2data res p2.1?p2.0 bbbbbbbb 00000000 07?09 p02cr? p04cr reserved reserved int act low ttl thresh reserved open drain pull-up enable output enable --bbbbbb 00000000 0c p07cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 0d p10cr reserved int enable int act low reserved reserved output enable -bb----b 00000000 0e p11cr reserved int enable int act low reserved open drain reserved output enable -bb--b-b 00000000 0f p12cr clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 10 p13cr reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable -bbbbbbb 00000000 11?13 p14cr? p16cr spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable bbbbbbbb 00000000 14 p17cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 15 p2cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 20 frtmrl free-running timer [7:0] bbbbbbbb 00000000 21 frtmrh free-running timer [15:8] bbbbbbbb 00000000 26 pitmrl prog interval timer [7:0] bbbbbbbb 00000000 27 pitmrh reserved prog interval timer [11:8] ----bbbb 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh reserved prog interval [11:8] ----bbbb 00000000 30 cpuclkcr reserved usb clk/2 disable usb clk select reserved cpu clk select -bb----b 00010000 31 itmrclkcr tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 10001111 32 clkiocr reserved reserved clkout select ---bbbbb 00000000 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 35 xosctr reserved reserved reserved mode ---bbb-b 000ddd0d 36 lposctr 32-khz low power reserved 32-khz bias trim [1:0] 32-khz freq trim [3:0] b-bbbbbb dddddddd 39 osclckcr reserved fine tune only usb osclock disable ------bb 00000000 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 40 usbcr usb enable device address[6:0] bbbbbbbb 00000000 41 ep0cnt data toggle data valid reserved byte count[3:0] bbbbbbbb 00000000 42 ep1cnt data toggle data valid reserved byte count[3:0] bbbbbbbb 00000000 43 ep2cnt data toggle data valid reserved byte count[3:0] bbbbbbbb 00000000 44 ep0mode setup rcv?d in rcv?d out rcv?d ack?d trans mode[3:0] ccccbbbb 00000000 45 ep1mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 46 ep2mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 50?57 ep0data endpoint 0 data buffer [7:0] bbbbbbbb ???????? 58?5f ep1data endpoint 1 data buffer [7:0] bbbbbbbb ???????? 60?67 ep2data endpoint 2 data buffer [7:0] bbbbbbbb ???????? [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 57 of 85 legend in the r/w column, b = both read and write r = read only w = write only c = read/clear ? = unknown d = calibration value. should not change during normal use 73 vregcr reserved keep alive vreg enable ------bb 00000000 74 usbxcr usb pull-up enable reserved usb force state b------b 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd bbbbbbbb 00000000 db int_clr1 reserved prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 -bbbbbbb 00000000 dc int_clr2 reserved reserved reserved gpio port 2 reserved int2 16-bit counter wrap reserved -bbbbbb- 00000000 de int_msk3 enswint reserved b------- 00000000 df int_msk2 reserved reserved reserved gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable reserved ---bbbb- 00000000 e1 int_msk1 reserved prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable bbbbbbbb 00000000 e0 int_msk0 gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwwww 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 - cpu_f reserved xoi super carry zero global ie ---brwww 00000010 ff cpu_scr gies reserved wdrs pors sleep reserved reserved stop r-ccb--b 00010000 1e0 osc_cr0 reserved no buzz sleep timer [1:0] cpu speed [2:0] --bbbbbb 00000000 1e3 lvdcr reserved porlev[1:0] reserved vm[2:0] --bb-bbbb 00000000 1eb eco_tr sleep duty cycle [1:0] reserved bb------ 00000000 1e4 vltcmp reserved lvd ppor ------rr 00000000 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 58 of 85 radio function register descriptions all registers are read and writeable, except where noted. regist ers may be written to or read from either individually or in sequential groups. a single-byte read or wr ite reads or writes from the addressed re gister. incrementing burst read and write i s a sequence that begins with an address, and then reads or writes to/from each regist er in address order for as long as clocking continues. it is possible to repeatedly read (poll) a single register using a non-incrementing burst read. these registers are managed and configured over spi by t he user firmware running in the microcontroller function. table 83.register map summary address mnemonic b7 b6 b5 b4 b3 b2 b1 b0 default [4] access [4] 0x00 channel_adr not used channel -1001000 -bbbbbbb 0x01 tx_length_adr tx length 00000000 bbbbbbbb 0x02 tx_ctrl_adr tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen 00000011 bbbbbbbb 0x03 tx_cfg_adr not used not used data code length data mode pa setting --000101 --bbbbbb 0x04 tx_irq_status_adr os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq 10111000 rrrrrrrr 0x05 rx_ctrl_adr rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen 00000111 bbbbbbbb 0x06 rx_cfg_adr agc en lna att hilo fast turn en not used rxow en vld en 10010-10 bbbbb-bb 0x07 rx_irq_status_adr rxow irq sofdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq 00000000 brrrrrrr 0x08 rx_status_adr rx ack pkt err eop err crc0 bad crc rx code rx data mode 00001--- rrrrrrrr 0x09 rx_count_adr rx count 00000000 rrrrrrrr 0x0a rx_length_adr rx length 00000000 rrrrrrrr 0x0b pwr_ctrl_adr pmu en lvirq en pmu mode force not used lvi th pmu outv 10100000 bbb-bbbb 0x0c xtal_ctrl_adr xout fn xs irq en not used not used freq 000--100 bbb--bbb 0x0d io_cfg_adr irq od irq pol miso od xout od pactl od pactl gpio spi 3pin irq gpio 00000000 bbbbbbbb 0x0e gpio_ctrl_adr xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip 0000---- bbbbrrrr 0x0f xact_cfg_adr ack en not used frc end end state ack to 1-000000 b-bbbbbb 0x10 framing_cfg_adr sop en sop len len en sop th 10100101 bbbbbbbb 0x11 data32_thold_adr not used not used not used not used th32 ----0100 ----bbbb 0x12 data64_thold_adr not used not used not used th64 ---01010 ---bbbbb 0x13 rssi_adr sop not used lna rssi 0-100000 r-rrrrrr 0x14 eop_ctrl_adr hen hint eop 10100100 bbbbbbbb 0x15 crc_seed_lsb_adr crc seed lsb 00000000 bbbbbbbb 0x16 crc_seed_msb_adr crc seed msb 00000000 bbbbbbbb 0x17 tx_crc_lsb_adr crc lsb -------- rrrrrrrr 0x18 tx_crc_msb_adr crc msb -------- rrrrrrrr 0x19 rx_crc_lsb_adr crc lsb 11111111 rrrrrrrr 0x1a rx_crc_msb_adr crc msb 11111111 rrrrrrrr 0x1b tx_offset_lsb_adr strim lsb 00000000 bbbbbbbb 0x1c tx_offset_msb_adr not used not used not used not used strim msb ----0000 ----bbbb 0x1d mode_override_adr rsvd rsvd frc sen frc awake not used not used rst 00000--0 wwwww--w 0x1e rx_override_adr ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used 0000000- bbbbbbb- 0x1f tx_override_adr ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv 00000000 bbbbbbbb 0x27 clk_override_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x28 clk_en_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x29 rx_abort_adr rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd 00000000 wwwwwwww 0x32 auto_cal_time_adr auto_cal_time_max 00000011 wwwwwwww 0x35 auto_cal_offset_adr auto_cal_offset_minus_4 00000000 wwwwwwww 0x39 analog_ctrl_adr rsvd rsvd rsvd rsvd rsvd rsvd rsvd all slow 00000000 wwwwwwww register files 0x20 tx_buffer_adr tx buffer file -------- wwwwwwww 0x21 rx_buffer_adr rx buffer file -------- rrrrrrrr 0x22 sop_code_adr sop code file note 5 bbbbbbbb 0x23 data_code_adr data code file note 6 bbbbbbbb 0x24 preamble_adr preamble file note 7 bbbbbbbb 0x25 mfg_id_adr mfg id file na rrrrrrrr notes 4. b = read/write, r = read only, w = write only, - = not used, default value is undefined. 5. sop_code_adr default = 0x17ff9e213690c782. 6. data_code_adr default = 0x02f9939702fa5ce3012bf1db0132be6f. 7. preamble_adr default = 0x333302. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 59 of 85 mnemonic channel_adr address 0x00 bit 7 6 5 4 3 2 1 0 default - 1 0 0 1 0 0 0 read/write - r/w r/w r/w r/w r/w r/w r/w function not used channel bits 6:0 this field selects the channel. 0x00 sets 2400 mhz; 0x62 sets 2498 mhz. values above 0x62 are not valid. the default ch annel is a fast channel above the frequency typically used in non-overlappi ng wifi systems. any write to this register will impact th e time it takes the synthesizer to settle. fast (100- s) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96 medium (180- s) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94 slow (270- s) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97 usable channels subjec t to regulation. d o not access or modify this register during transmit or receive. mnemonic tx_length_adr address 0x01 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function tx length bits 7:0 this register sets the length of the packet to be trans mitted. a length of zero is valid, and will transmit a packet wi th sop, length and crc16 fields (if enabled), but no data field. packet lengths of more than 16 bytes will require that some data bytes be wri t- ten after transmission of the packet has begun. typically, length is updated prior to setting tx go. the maximum packet length for all packets is 40 bytes except for framed 64-ch ip ddr where the maximum packet length is 16 bytes. maximum packet length is limited by the delta between the transmitter and receiver cr ystals of 60-ppm or better. mnemonic tx_ctrl_adr address 0x02 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen bit 7 start transmission. setting this bit triggers the transmissi on of a packet. writing a 0 to this flag has no effect. this b it is cleared automatically at the end of packet transmission. the transmit buf fer may be loaded either before or after setting this bit. if data is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth), the length of the sop code, the length of preamble, and the packet data rate. for example, if starting from idle mode on a fast channel in 8dr mode with 32-chip so p codes the time available is 100 s (synth start) + 32 s (preamble) + 64 s (sop length) + 32 s (length byte) = 228 s. if there are no bytes in the tx buffer at the end of transmission of the length field, a txberr irq will occur. bit 6 clear tx buffer. writing a 1 to this register clears the transmit buffer. writing a 0 to this bit has no effect. the previ ous packet may be retransmitted by setting tx go and not setting this bit. a new transmit packet may be loaded and transmitted without setting this bit if tx go is set after the new packet is loaded to the buffer. if the tx_buffer_adr is to be loaded after the t x go bit has been set, then this bit should be set before loading a new transmit packet to the buffer and before tx go is set. bit 5 buffer not full interrupt enable. see tx_irq_status_adr for description. bit 4 buffer half empty interrupt enable . see tx_irq_status_adr for description. bit 3 buffer empty interrupt enable. see tx_irq_status_adr for description. bit 2 buffer error interrupt enable. s ee tx_irq_status_adr for description. bit 1 transmission complete interrupt enable. see tx_irq_s tatus_adr for description. txc irqen and txe irqen must be set together. bit 0 transmit error interrupt enable. see tx_irq_status_ adr for description. txc irqen and txe irqen must be set together. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 60 of 85 mnemonic tx_cfg_adr address 0x03 bit 7 6 5 4 3 2 1 0 default - - 0 0 0 1 0 1 read/write - - r/w r/w r/w r/w r/w r/w function not used not used data code length data mode pa setting bit 5 data code length. this bit selects the length of the data _code_adr code for the data portion of the packet. this bit is ignored when the data mode is set to gfsk. 1 = 64 chip codes, 0 = 32 chip codes. bits 4:3 data mode. this field sets the data transmission mode. 00 = 1-mbps gfsk, 01 = 8dr mode, 10 = ddr mode, 11 = sdr mode. it is recommended that firmware sets the all slow bit in register analog_ctrl_adr when using gfsk data rate mode. bits 2:0 pa setting. this field sets the transmit signal strength. 0 = ?30 dbm, 1 = ?25 dbm, 2 = ?20 dbm, 3 = ?15 dbm, 4 = ?10 db m, 5 = ?5 dbm, 6 = 0 dbm, 7 = +4 dbm. mnemonic tx_irq_status_adr address 0x04 bit 7 6 5 4 3 2 1 0 default 1 0 1 1 1 0 0 0 read/write r r r r r r r r function os irq lv irq txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq the state of all irq status bits is vali d regardless of whether or not the irq is enabled. the irq output of the device is in i ts active state whenever one or more bits in this register is set and the corr esponding irq enable bit is also se t. status bits are non-atomic (different flags may change value at different times in respon se to a single event). in particular, st andard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state. bit 7 oscillator stable irq status. this bit is set when the internal cr ystal oscillator has settled (synthesizer sequence start s). bit 6 low voltage interrupt status. this bit is set when the voltage on v bat is below the lvi threshold (see pwr_ctl_adr). this interrupt is automatically disabled whenever the pmu is disabled. when enabled, this bit reflects the voltage on v bat . bit 5 buffer not full interrupt status. this bit is set wheneve r there are 15 or fewer bytes remaining in the transmit buffer. bit 4 buffer half empty interrupt status. this bit is set whenever there are 8 or fewer bytes remaining in the transmit buffer. bit 3 buffer empty interrupt status. this bit is set at any time that the transmit buffer is empty. bit 2 buffer error interrupt status. this irq is triggered by ei ther of two events: (1) when the transmit buffer (tx_buffer_adr) is empty and the number of bytes remaining to be transmitted is great er than zero; (2) when a byte is written to the transmit buff er and the buffer is already full. this irq is cleared by setting bit tx clr in tx_ctrl_adr. bit 1 transmission complete interrupt status. this irq is tri ggered when transmission is comp lete. if transaction mode is not enabled then this interrupt is triggered immediately after transmi ssion of the last bit of the crc16. if transaction mode is enabled, this interrupt is triggered at the end of a transacti on. reading this register clears this bit. txc irq and txe irq fl ags may change value at different times in response to a single ev ent. if transaction mode is enabled and the first read of this re gis- ter returns txc irq = 1 and txe irq = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of txe. there can be a case when this bit is not triggered when ack en = 1 and there is an error in transmission. if the first read of th is register returns txc irq = 1 and txe irq = 1 then the firmware must not execut e a second read to this register for a given transaction. if an ack is received rxc irq and rxe irq may be asserted instead of txc irq and txe irq. bit 0 transmit error interrupt status. this irq is triggered when there is an error in transmission. this interrupt is only appl icable to transaction mode. it is triggered whenever no valid ack packet is received within the ack timeout period. reading this register clears this bit. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 61 of 85 mnemonic rx_ctrl_adr address 0x05 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen status bits are non-atomic (different flags may change va lue at different times in response to a single event). bit 7 start receive. setting this bit caus es the device to transition to receive mode. if necessary, the crystal oscillator and synthesizer will start automatically after this bit is set. firmware must nev er clear this bit. this bit must not be set until after it sel f clears. the recommended method to exit receive mode when an error has occurred is to force end state and then dummy read all rx_count_adr bytes from rx_buffer_adr or poll rssi_adr.sop (bit 7) until set. see xact_cfg_adr and rx_abort_adr for description. bit 6 start of packet detect interrupt enable. see rx_irq_status_adr for description. bit 5 buffer full interrupt enable. s ee rx_irq_status_adr for description. bit 4 buffer half empty interrupt enable. see rx_irq_status_adr for description. bit 3 buffer not empty interrupt enable. see rx_irq_status_adr for description. bit 2 buffer error interrupt enable. see rx_irq_status_adr for description. bit 1 packet reception complete interrupt e nable. see rx_irq_status_adr for description. bit 0 receive error interrupt enable. see rx_irq_status_adr for description. mnemonic rx_cfg_adr address 0x06 bit 7 6 5 4 3 2 1 0 default 1 0 0 1 0 - 1 0 read/write r/w r/w r/w r/w r/w - r/w r/w function agc en lna att hilo fast turn en not used rxow en vld en status bits are non-atomic (different flags may change va lue at different times in response to a single event). bit 7 automatic gain control (agc) enable. when this bit is se t, agc is enabled, and the lna is controlled by the agc circuit. when this bit is cleared the lna is contro lled manually using the lna bit. typical applic ations will clear this bit during init ializa- tion. it is recommended that this bit be di sabled and bit 6 (lna) be enabled unless the dev ice will be used in a system where i t may receive data from a device using an ex ternal pa to transmit signals at >+4 dbm. bit 6 low noise amplifier (lna) manual control. when agc en (bit 7) is cleared, this bit controls the state of the receiver lna; when agc en is set, this bit has no effect. setting this bit enables the lna; clearing th is bit disables the lna. device curren t in receive mode is slightly lower when the lna is disabled. typical ap plications will set this bit during initialization. bit 5 receive attenuator enable. setting this bit enables the re ceiver attenuator. the receiver attenuator may be used to desens itize the receiver so that only very strong signals may be received. this bit should only be set when the agc en is disabled and the lna is manually disabled. bit 4 hilo. when fast turn en is set, this bit is used to se lect whether the device will use the high frequency for the channel selected, or the low frequency. 1 = hi; 0 = lo. when fast turn en is not enabled this also c ontrols the highlow bit to the receiver and should be left at the default value of 1 for high si de receive injection. typical appl ications will clear this bit during initialization. bit 3 fast turn mode enable. when this bit is set, the hilo bit determines whether the device receives data transmitted 1mhz above the rx synthesizer frequency or 1 mhz below the receiver synthesiz er frequency. use of this mode allows for very fast turnaround, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthe- sizer resettling period between transmit and receive. note that when this bit is set, and the hilo bit is cleared, received dat a bits are automatically inverted to compensate for the inversi on of data received on the ?image? frequency. typical applications will set this bit during initialization. bit 1 overwrite enable. when this bit is set, if an sop is detec ted while the receive buffer is not empty, then the existing con tents of receive buffer are lost, and the new packet is loaded into the re ceive buffer. when this bit is set, the rxow irq is enabled. i f this bit is cleared, then the receive buffer may not be overwri tten by a new packet, and whenever the receive buffer is not emp ty sop conditions are ignored, and it is not poss ible to receive data until the previously received packet has been completely rea d from the receive buffer. bit 0 valid flag enable. when this bit is set, the receive buffer can store only 8 bytes of data. the other half of the buffer i s used to store valid flags. see rx_buffer_adr for more detail. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 62 of 85 mnemonic rx_irq_status_adr address 0x07 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r r r r r r r function rxow irq rsvd rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq the state of all irq status bits is vali d regardless of whether or not the irq is enabled. the irq output of the device is in i ts active state whenever one or more bits in this register is set and the corr esponding irq enable bit is also se t. status bits are non-atomic (different flags may change value at different times in respon se to a single event). in particular, st andard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state. bit 7 receive overwrite interrupt status. this irq is triggered when the receive buffer is overwritten by a packet being receive d before the previous packet has been read from the buffer. this bit is cleared by writing any val ue to this register. this condi tion is only possible when the rxow en bit in rx_cfg_adr is set. th is bit must be written ?1? by firmware before the new packet may be read from the receive buffer. bit 6 reserved. must not be set. bit 5 receive buffer full interrupt status. this bit is set whenever the receive buffer is full, and cleared otherwise. bit 4 receive buffer half full interrupt status. this bit is set whenever there are eight or more bytes remaining in the receive buffer. firmware must read exactly eight bytes when r eading rxb8 irq. it is possible, in rare cases, that the last byte of a packet may remain in the buffer even though the rxb1_irq flag has cleared. this can only happen on the last byte of a packet and only if the packet data is being read out of the buffer while the pack et is still being received. t he flag is trustworthy under all other conditions, and for all bytes prior to the la st. when using rxb1_irq and unloading the packet data during reception, the user should be sure to check the rx_count_adr value after the rxc/ rxe is set and unload the last remaining byte if the number of bytes unloaded is less than the reported count, even though the rxb1_irq is not set bit 3 receive buffer not empty interrupt stat us. this bit is set at any time that ther e are 1 or more bytes in the receive buffe r, and cleared when the receive buffer is empty. rxb1 irq must not be set when rxb8 irq is set and vice versa. bit 2 receive buffer error interrupt status. this irq is tri ggered in one of two ways: (1) when the receive buffer is empty and there is an attempt to read data; (2) when the receive buffer is full and more data is received. this flag is cleared when rx go is s et and a sop is received. bit 1 packet receive complete interrupt status. this irq is triggered when a packet has been received. if transaction mode is enabled, then this bit is not set until after transmission of the ack. if transaction mode is not enabled then this bit is set as soon as a valid packet is received. this bit is cleared when this register is read. rxc irq and rxe irq flags may change value at different times in response to a single event. there are cases when this bit is not triggered when ack en = 1 and there is an error in reception. therefore, firmware should examine rxc irq, rxe irq, and crc 0 to determine receive status. if the first read of this register returns rxc irq = 1 and rxe irq = 0 then fi rmware must execute a second read to this register to deter- mine if an error occurred by examining the status of rxe irq. if the first read of this register returns rxc irq = 1 and rxe ir q = 1 then the firmware must not execute a second read to this register for a given transaction. bit 0 receive error interrupt status. this irq is triggered when there is an error in reception. it is triggered whenever a pack et is received with a bad crc16, an unexpected eop is detected, a packet type (data or ack) mismatch, or a packet is dropped because the receive buffer is still not empty when the next pack et starts. the exact cause of the error may be determined by reading rx_status_adr. this bit is cleared when this register is read. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 63 of 85 mnemonic rx_status_adr address 0x08 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 1 - - - read/write r r r r r r r r function rx ack pkt err eop err crc0 bad crc rx code rx data mode it is expected that firmware does not read this register until afte r tx go self clears. status bits are non-atomic (different f lags may change value at different times in response to a single event). bit 7 rx packet type. this bit is set when the received packe t is an ack packet, and cleared when the received packet is a stand ard packet. bit 6 receive packet type error. this bit is set when the pack et type received is not what was expected and cleared when the packet type received was as expected. for example, if a data packet is expected and an ack is received, this bit will be set. bit 5 unexpected eop. this bit is set when an eop is det ected before the expected data length and crc16 fields have been received. this bit is cleared when sop pattern for the next pa cket has been received. this incl udes the case where there are invalid bits detected in the length fiel d and the length field is forced to 0. bit 4 zero-seed crc16. this bit is set whenever the crc16 of the last received packet has a zero seed. bit 3 bad crc16. this bit is set when the crc 16 of the last received packet is incorrect. bit 2 receive code length. this bit indicates the data_code_ad r code length used in the last correctly received packet. 1 = 64-chip code, 0 = 32-chip code. bits 1:0 receive data mode. these bits i ndicate the data mode of the last correctly received packet. 00 = 1-mbps gfsk, 01 = 8dr, 10 = ddr, 11 = not valid. these bits do not apply to unframed packets. mnemonic rx_count_adr address 0x09 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r r r r r r r r function rx count count bits are non-atomic (updated at different times). bits 7:0 this register contains the total number of payload bytes received during recept ion of the current packet. after packet reception is complete, this register will match the value in rx_length_adr unless there was a packet error. this register is reset to 0x00 when rx_length_adr is loaded. count should not be read when rx_go = 1 during a transaction. mnemonic rx_length_adr address 0x0a bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r r r r r r r r function rx length length bits are non-atomic (different flags may change valu e at different times in response to a single event). bits 7:0 this register contains the length field which is updat ed with the reception of a new length field (shortly after start of packet detected). if there is an error in the rece ived length field, 0x00 is loaded instead, except when using gfsk datarate, and an error is flagged. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 64 of 85 mnemonic pwr_ctrl_adr address 0x0b bit 7 6 5 4 3 2 1 0 default 1 0 1 - 0 0 0 0 read/write r/w r/w r/w - r/w r/w r/w r/w function pmu en lvirq en pmu mode force not used lvi th pmu outv bit 7 power management unit (pmu) enable. setting this bit enables the pmu if pmu mode force (bit 5) is set, otherwise it has no effect. see pmu mode force bit (bit 5) description. bit 6 low voltage interrupt enable. setting this bit enables the lv irq interrupt. when this interrupt is enabled, if the v bat voltage falls below the threshold set by lvi th, then a low voltage in terrupt will be generated. the lvi is not available when the devi ce is in sleep mode. the lvi event on irq pin is aut omatically disabled whe never the pmu is disabled. bit 5 pmu mode force. if this bit is set, the pmu operation will be based on the value of pmu enable bit (bit 7). if this bit is not set, then the pmu is diabled when in sleep mode and enabled when not in sleep mode. bits 3:2 low voltage interrupt threshold. this field sets the voltage on v bat at which the lvi is triggered. 11 = 1.8v, 10 = 2.0v, 01 = 2.2v, 00 = pmu outv voltage. bits 1:0 pmu output voltage. this field sets the minimum output voltage of the pmu. 11 = 2.4v, 10 = 2.5v, 01 = 2.6v, 00 = 2.7v. when the pmu is active, the voltage output by the pmu on v reg will never be less than this voltag e, provided that the total load on the v reg pin is less than the specifi ed maximum value and the voltage in v bat is greater than the specified minimum value. to force the chip to always enable the pmu (including in sleep mode) , set bit 5 and bit 7. to force the chip to always disable the pmu set bit 5 and clear bit 7. to allow the chip to disable pmu only du ring sleep clear bit 5. the sequence of writing the bits in this register impact the sleep current i sb . mnemonic xtal_ctrl_adr address 0x0c bit 7 6 5 4 3 2 1 0 default 0 0 0 - - 1 0 0 read/write r/w r/w r/w - - r/w r/w r/w function xout fn xsirq en not used not used freq bits 7:6 xout pin function. this field sele cts between the different functions of the xo ut pin. 00 = clock frequency set by xout freq; 01 = active low pa control; 10 = radio data serial bit st ream. if this option is selected and spi is configured for 3-wir e mode then the miso pin will output a serial clock associated with this data stream; 11 = gpio. to disable this output, set to gpio mode, and set the gpio state in io_cfg_adr. bit 5 crystal stable interrupt enable. this bit enables the os irq interrupt. when enabled, this interrupt generates an irq even t when the crystal has stabilized after the dev ice has woken from sleep mode. this event is cleared by writing zero to this bit. bits 2:0 xout frequency. this field sets the frequency output on the xout pin when xout fn is set to 00. 0 = 12 mhz, 1 = 6 mhz, 2 = 3 mhz, 3 = 1.5 mhz, 4 = 0.75 mhz; other values are not defined. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 65 of 85 mnemonic io_cfg_adr address 0x0d bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function irq od irq pol miso od xout od pactl od pactl gpio spi 3pin irq gpio to use a gpio pin as an input, the output mode must be set to open drain, and a ?1? written to the corresponding output registe r bit. bit 7 irq pin drive strength. setting this bit configures the irq pin as an open drai n output. clearing this bit configures the irq pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 6 irq polarity. setting this bit configur es the irq signal polarity to be active high. clearing this bit configures the irq signal polarity to be active low. bit 5 miso pin drive strength. setting this bit configures the miso pin as an open dr ain output. clearing this bit configures th e miso pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 4 xout pin drive strength. setting this bit configures the xout pin as an open dr ain output. clearing this bit configures th e xout pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 3 pactl pin drive strength. setting this bit configures the pactl pin as an open drain output. clearing this bit configures the pactl pin as a standard cmos output, with the output ?1? drive voltage being equal to the v io pin voltage. bit 2 pactl pin function. when this bit is set the pactl pin is available for use as a gpio. bit 1 spi mode. when this bit is cleared, the spi interface acts as a standard 4-wire spi slave in terface. when this bit is set, the spi interface operates in ?3-wire mode? combining miso and mosi on the same pin (sdat), and the miso pin is available as a gpio pin. bit 0 irq pin function. when this bit is cleared, the irq pin is asserted when an irq is active; the polarity of this irq signal is con- figurable in irq pol. when this bit is se t, the irq pin is available for use as a gp io pin, and the irq function is multiplexed onto the mosi pin. in this case the irq signal state is presented on the mosi pin whenever the ss signal is inactive (high). mnemonic gpio_ctrl_adr address 0x0e bit 7 6 5 4 3 2 1 0 default 0 0 0 0 - - - - read/write r/w r/w r/w r/w r r r r function xout op miso op pactl op irq op xout ip miso ip pactl ip irq ip to use a gpio pin as an input, the output mode must be set to open drain, and a ?1? written to the corresponding output registe r bit. bit 7 xout output. when the xout pin is configured to be a gpio, the state of this bit sets the output state of the xout pin. bit 6 miso output. when the miso pin is configured to be a gpio, the state of this bit sets the output state of the miso pin. bit 5 pactl output. when the pactl pin is configured to be a gpio, the state of this bit sets the output state of the pactl pin. bit 4 irq output. when the irq pin is configured to be a gpio , the state of this bit sets the output state of the irq pin. bit 3 xout input. when the xout pin is configured to be a gpio , the state of this bit reflects the voltage on the xout pin. bit 2 miso input. when the miso pin is conf igured to be a gpio, the state of this bit reflects the voltage on the miso pin. bit 1 pactl input. when the pactl pin is configured to be a gpio , the state of this bit reflects the voltage on the pactl pin. bit 0 irq input. when the irq pin is configured to be a gpio, the state of this bit reflects the voltage on the irq pin. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 66 of 85 mnemonic xact_cfg_adr address 0x0f bit 7 6 5 4 3 2 1 0 default 1 - 0 0 0 0 0 0 read/write r/w - r/w r/w r/w r/w r/w r/w function ack en not used frc end end state ack to bit 7 acknowledge enable. when this bit is set, an ack packet is automatically transmi tted whenever a valid packet is received; in this case the device is considered to be in transaction mode. after transmission of the ack packet, the device automatically transitions to the end state. when this bit is cleared, the devic e transitions directly to the end state immediately after the end of packet transmission. bit 5 force end state. setting this bit forces a transition to t he state set in end state. by setting the desired end state at t he same time as setting this bit the device ma y be forced to immediately transition from its current state to any other state. thi s bit is automatically cleared upon completion. bits 4:2 transaction end state. this field defines the mode to which the device trans itions after receiving or transmitting a pa cket. 000 = sleep mode; 001 = idle mode; 010 = synth mode (tx); 011 = synth mode (rx); 100 = rx mode. in normal use, this field will typically be set to 000 or 001 when the devi ce is transmitting packets and 100 when the device is receiving packets. note that when the device transitions to receive mode as an end state, the receiver must still be armed by setting rx go before the device can begin receiving data. if the system only support pack ets <=16 bytes then firmware should examine rxc irq and rxe irq to determine the status of the packet. if the system supports packets > 16 bytes ensure that end state is not sleep, force rxf = 1, perform receive operation, force rxf = 0, and if necessary set end state back to sleep. bits 1:0 ack timeout. when the device is configured for transaction mode, this field sets the ti meout period after transmission of a packet during which an ack must be correctly received in order to prevent a transmit error condition from being detected. this timeout period is expressed in terms of a number of sop_code _adr code lengths; if sop len is set, then the timeout period is this value multiplied by 64 s and if sop len is cleared then the timeout is this value multiplied by 32 s. 00 = 4x, 01 = 8x, 10 = 12x, 11 = 15x the sop_code_adr code length. ack_to must be set to greater than 30 + data code length (only for 8dr) + preamble length + sop code length (x2). mnemonic framing_cfg_adr address 0x10 bit 7 6 5 4 3 2 1 0 default 1 0 1 0 0 1 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w function sop en sop len len en sop th bit 7 sop enable. when this bit is set, each transmitted packet begins with a sop fiel d, and only packets beginning with a valid sop field will be received. if this bit is cleared, no sop field will be generated w hen a packet is transmitted, and packet rec ep- tion will begin whenever two succes sive correlations against the data_code_adr code are detected. bit 6 sop pn code length. when this bit is set the sop_ code_adr code length is 64 chips. when this bit is cleared the sop_code_adr code length is 32 chips. bit 5 packet length enable. when this bit is set the 8-bit val ue contained in tx_length_adr is tr ansmitted immediately after the sop field. in receive mode, the 8 bits i mmediately following the sop field are interpreted as the length of the packet. when th is bit is cleared no packet length field is transmitted. 8dr always sends the packet length field (forces len en = 1). gfsk requires user set len en = 1. bits 4:0 sop correlator threshold. this is the receive data co rrelator threshold used when a ttempting to detect a sop symbol. th ere is a threshold for the sop_code_adr c ode. this (single) threshold is appl ied independently to each of sop1 and sop2 fields. there are then two thresholds for each of the 64 -chip data_code_adr codes and 32-chip data_code_adr codes. when sop len is set, all 5 bits of this fiel d are used. when sop len is cleared, the most significant bit is disregarded. typic al applications configure sop th = 04h fo r sop32 and sop th = 0eh for sop64. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 67 of 85 mnemonic data32_thold_adr address 0x11 bit 7 6 5 4 3 2 1 0 default - - - - 0 1 0 0 read/write - - - - r/w r/w r/w r/w function not used not used not used not used th32 bits 3:0: 32-chip data pn code correlator threshold. this regist er sets the correlator threshold used in dsss modes when data code length (see tx_cfg_adr) is set to 32. typical applications configure th32 = 05h. mnemonic data64_thold_adr address 0x12 bit 7 6 5 4 3 2 1 0 default - - - 0 1 0 1 0 read/write - - - r/w r/w r/w r/w r/w function not used not used not used th64 bits 4:0 64 chip data pn code correlator threshold. this regist er sets the correlator threshold used in dsss modes when the data code length (see tx_cfg_adr) is set to 64. typical applications configure th64 = 0eh. mnemonic rssi_adr address 0x13 bit 7 6 5 4 3 2 1 0 default 0 - 1 0 0 0 0 0 read/write r - r r r r r r function sop not used lna rssi a received signal strength indicator (rssi) reading is taken aut omatically when an sop symbol is detected. in addition, an rssi reading is taken whenever rssi_adr is read. the contents of this register are not valid after the device is configured for receive mode un til either a sop symbol is detected, or the register is read. the conversion can occur as often as once every 12 s. to measure the background rf signal strength on a channel before a packet has been received, the mcu should perform a ?dummy? r ead of this register, the results of which shoul d be discarded. this ?dummy? read will cause an rssi measurement to be taken, and ther efore subsequent readings of the r egister will yield valid data. bit 7 sop rssi reading. when set, this bit indicates that t he reading in the rssi field was taken when a sop symbol was detected. when cleared, this bit indicate s that the reading stored in the rssi fiel d was triggered by a previous spi read of th is register. bit 5 lna state. this bit indicates the lna state when the rssi reading was taken. when cleared, this bit indicates that the lna was disabled when the rssi reading was taken; if set, this bit i ndicates that the lna was enabled when the rssi reading was taken. bits 4:0 rssi reading. this field indicates the instantaneous strength of the rf signal being received at the time that the rssi reading was taken. a larger value indicates a stronger signal. the signal strength measured is for the rf signal on the configured chan - nel, and is measured after the lna stage. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 68 of 85 mnemonic eop_ctrl_adr address 0x14 bit 7 6 5 4 3 2 1 0 default 1 0 1 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function hen hint eop if the len en bit is set, then the contents of this register hav e no effect. if the len en bit is cleared, then this register i s used to configure how an eop (end of packet) condition is detected. bit 7 eop hint enable. when set, this bit will cause an eop to be detected if no correlations have been detected for the number of symbol periods set by the hint field and the last two rece ived bytes match the calculated crc16 for all previously received bytes. use of this mode reduces the chance of non-correlations in the middle of a packet from being detected as an eop con- dition. bits 6:4 eop hint symbol count. the minimum number of symbols of consecutive non-correlations at which the last two bytes are checked against the calculated crc16 to detect an eop condition. bits 4:0 eop symbol count. an eop conditi on is deemed to exist when the number of c onsecutive non-correlations is detected. mnemonic crc_seed_lsb_adr address 0x15 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function crc seed lsb the crc16 seed allows different devices to generate or recognize di fferent crc16s for the same payload data. if a transmitter a nd receiver use a randomly selected crc16 seed, the probability of correctl y receiving data intended for a different receiver is 1/65535, e ven if the other transmitter/receiver are using the same sop_code_adr codes and channel. bits 7:0 crc16 seed least significant byte. the lsb of the starting value of the crc16 calculation. mnemonic crc_seed_msb_adr address 0x16 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function crc seed msb bits 7:0 crc16 seed most significant byte. the ms b of the starting value of the crc16 calculation. mnemonic tx_crc_lsb_adr address 0x17 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function tx crc lsb bits 7:0 calculated crc16 lsb. the lsb of the crc16 that was calc ulated for the last transmitted packet. this value is only vali d after packet transmission is complete. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 69 of 85 mnemonic tx_crc_msb_adr address 0x18 bit 7 6 5 4 3 2 1 0 default - - - - - - - - read/write r r r r r r r r function tx crc msb bits 7:0 calculated crc16 msb. the msb of the crc16 that was calc ulated for the last transmitted pa cket. this value is only vali d after packet transmission is complete. mnemonic rx_crc_lsb_adr address 0x19 bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 read/write r r r r r r r r function rx crc lsb bits 7:0 received crc16 lsb. the lsb of the crc16 field from the la st received packet. this value is valid whether or not the cr c16 field matched the calculated crc16 of the received packet. mnemonic rx_crc_msb_adr address 0x1a bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 read/write r r r r r r r r function rx crc msb bits 7:0 received crc16 msb. the msb of the crc16 field from the last received packet. this val ue is valid whether or not the crc16 field matched the calculated crc16 of the received packet. mnemonic tx_offset_lsb_adr address 0x1b bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r r r r r r r function strim lsb bits 7:0 the least significant 8 bits of th e synthesizer offset value. this is a 12- bit 2?s complement signed number, which may be used to offset the transmit frequency of the de vice by up to 1.5 mhz. a positive value increases the transmit frequency, and a neg- ative value reduces the transmit frequency. a value of +1 increases the transmi t frequency by 732.6 hz; a value of ?1 decreases the transmit frequency by 732.6 hz. a value of 0x0555 increases the tr ansmit frequency by 1 mhz; a value of 0xaab decreases the transmit frequency by 1 mhz. typically, this register is loaded with 0x55 dur ing initialization. this featu re is typically used to avoid the need to change the synthesizer frequency when switching between tx and rx. as the if = 1 mhz the rx frequency is offset 1 mhz from the synthesizer frequency; ther efore, transmitting with a 1- mhz offset allows the same synthesizer frequency to be used for both transmit and receive. synthesizer offset has no effect on receive frequency. mnemonic tx_offset_msb_adr address 0x1c bit 7 6 5 4 3 2 1 0 default - - - - 0 0 0 0 read/write - - - - r/w r/w r/w r/w function not used not used not used not used strim msb bits 3:0 the most significant 4 bits of the synthesizer trim valu e. typically, this register is loaded with 0x05 during initiali zation. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 70 of 85 mnemonic mode_override_adr address 0x1d bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 - - 0 read/write w w w w w - - w function rsvd rsvd frc sen frc awake not used not used rst bits 7 reserved. do not write a 1 to these bits. bits 5 manually initiate synthesizer. setting this bit forces the synthesizer to star t. clearing this bit has no effect. for thi s bit to operate correctly, the oscillator must be running before this bit is set. bits 4:3 force awake. force the device out of sleep mode. setti ng both bits of this field forc es the oscillator to keep running at all times regardless of the end state setting. clearing bo th of these bits dis ables this function. bits 0 reset. setting this bit forc es a full reset of the device. clearing this bit has no effect. mnemonic rx_override_adr address 0x1e bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 - read/write r/w r/w r/w r/w r/w r/w r/w - function ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used this register provides the ability to overri de some automatic features of the device. bits 7 when this bit is set, the device us es the transmit synthesizer frequency rather than the receive synthesizer frequency fo r the given channel when automatically entering receive mode. bits 6 when this bit is set and ack en is enabled, the transmission of the ack packet is delayed by 20 s. bits 5 force expected packet type. when this bit is set, and the device is in receive mode, the dev ice is configured to receive an ack packet at the data rate defined in tx_cfg_adr. bits 4 force receive data rate. when this bit is set, the receiver will ignore the data rate encoded in the sop symbol, and will receive data at the data rate defined in tx_cfg_adr. bits 3 reject packets with a zero-seed crc16. setting this bit caus es the receiver to reject packets with a zero-seed, and accep t only packets with a crc16 that matches the seed in crc_seed_lsb_adr and crc_seed_msb_adr. bits 2 the rx crc16 checker is disabled. if packets with crc16 enabled are received, the crc16 will be treated as payload data and stored in the receive buffer. bits 1 accept bad crc16. setting this bit causes the receiver to accept packets with a crc16 that do not match the seed in crc_seed_lsb_adr and crc_seed_msb_adr. an ack is to be s ent regardless of the condition of the received crc16. mnemonic tx_override_adr address 0x1f bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w function ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv this register provides the ability to overri de some automatic features of the device. bits 7 when this bit is set, the device us es the receive synthesizer frequency rather than the transmit synthesizer frequency fo r the given channel when automatically entering transmit mode. bits 6 force preamble. when this bit is set, the device will transmit a continuous repetition of the preamble pattern (see preamble_adr) after tx go is set. this mode is useful for some regulatory approval procedures. bits 5 reserved. do not write a 1 to this bit. bits 4 transmit ack packet. when th is bit is set, the device sends an ack packet when tx go is set. bits 3 ack override. use tx_cfg_adr to determine the dat a rate and the crc16 used when transmitting an ack packet. bits 2 disable transmit crc16. when set, no crc16 fi eld is present at the end of transmitted packets. bits 1 reserved. do not write a 1 to this bit. bits 0 tx data invert. when this bit is set the transmit bitstream is inverted. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 71 of 85 mnemonic clk_offset_adr address 0x27 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd this register provides the ability to overri de some automatic features of the device. bits 7:2 reserved. do not write a 1 to these bits. bits 1 force receive clock bits 0 reserved. do not write a 1 to this bit. mnemonic clk_en_adr address 0x28 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd this register provides the ability to overri de some automatic features of the device. bits 7:2 reserved. do not write a 1 to these bits. bits 1 force receive clock enable. typical applic ation will set this bi t during initialization. bits 0 reserved. do not write a 1 to this bit. mnemonic rx_abort_adr address 0x29 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd this register provides the ability to overri de some automatic features of the device. bits 7:6 reserved. do not write a 1 to these bits. bits 5 receive abort enable. bits 4:0 reserved. do not write a 1 to these bits. mnemonic auto_cal_time_adr address 0x32 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 1 1 read/write w w w w w w w w function auto_cal_time_max this register provides the ability to over-r ide some automatic features of the device. bits 7:0 auto cal time max. firmware must write 3ch to this register during initialization. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 72 of 85 mnemonic auto_cal_offset_adr address 0x35 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function auto_cal_offset_minus_4 this register provides the ability to overri de some automatic features of the device. bits 7:0 auto cal time max. firmware must wr ite 14h to this register during initialization. mnemonic analog_ctrl_adr address 0x39 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 read/write w w w w w w w w function rsvd rsvd rsvd rsvd rsvd rsvd rsvd all slow this register provides the ability to over-r ide some automatic features of the device. bits 7:1 reserved. do not write a 1 to these bits. bits 0 all slow. when set, the synth settling time for all c hannels is the same as for slow channels. it is recommended that fir mware set this bit when using gfsk data rate mode. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 73 of 85 register files files are written to or read from using non-incrementing burst read or wr ite transactions. in most cases reading a file may be destructive; the file must be completely read, otherwise the contents may be altered. mnemonic tx_buffer_adr address 0x20 length 16 bytes r/w w default 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx the transmit buffer is a fifo. writing to this file adds a byte to the packet being sent. writing more bytes to this file than the packet length in tx_length_adr will have no effect, and these bytes will be lost after successful packet transmission. it is not possible to load two 8-byte packets into this register, and then transmit them sequentially by enabling the tx go bit twice; this would have the effect of sending the first eight bytes twice. mnemonic rx_buffer_adr address 0x21 length 16 bytes r/w r default 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx the receive buffer is a fifo. received bytes ma y be read from this file register at any time that it is not empty, but when rea ding from this file register before a packet has been completely received care must be taken to ensure that error packets (for example with bad crc 16) are handled correctly. when the receive buffer is configured to be overwritten by new pa ckets (the alternative is for new packets to be discarded if t he receive buffer is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overw ritten by a newly received packet while this file register is being read. when the vld en bit in rx_cfg_adr is set, the bytes in this file register alternate?the first byte read is data, the second byt e is a valid flag for each bit in the first byte, the third byte is data, the four th byte valid flag, and so on. in sdr and ddr modes the valid f lag for a bit is set if the correlation coefficient for the bit exceeded the correlator th reshold, and is cleared if it did not. in 8dr mode, the msb o f a valid flag byte indicates whether or not the correlation coefficient of the corr esponding received symbol exceeded the threshold. the seven lsb s contain the number of erroneous chips received for the data. mnemonic sop_code_adr address 0x22 length 8 bytes r/w r/w default 0x17ff9e213690c782 when using 32-chip sop_code_adr codes, only the first four bytes of this register are used; in order to complete the file write process, these four bytes must be followed by four bytes of ?dummy? data. however, a class of codes know n as ?multiplicative codes? may be used; there are 64-chip codes with good auto-correlation and cross-correlatio n properties where the least signi ficant 32 chips themselves h ave good auto-correlation and cross-correlation proper ties when used as 32-chip codes. in this case the same eight-byte value may be loa ded into this file and used for both 32-chip and 64-chip sop symbols. when reading this file, all eight bytes must be read; if fewer t han eight bytes are read from the file, the contents of the fil e will have been rotated by the number of bytes read. this applies to writes, as well. recommended sop codes: 0x91ccf8e291cc373c 0x0fa239ad0fa1c59b 0x2ab18fd22ab064ef 0x507c26dd507ccd66 0x44f616ad44f6e15c 0x46ae31b646aecc5a 0x3cdc829e3cdc78a1 0x7418656f74198eb9 0x49c1df6249c0b1df 0x72141a7f7214e597 d o not access or modify this register during transmit or receive. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 74 of 85 absolute maximum ratings storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied ........ 0c to +70c supply voltage on any power supply pin relative to v ss ?0.3v to +3.9v dc voltage to logic inputs [8] ................... ?0.3v to v io +0.3v dc voltage applied to outputs in high-z state .. ?0.3v to v io +0.3v static discharge voltage (digital) [9] ............ ............... >2000v static discharge voltage (rf) [9] ................................. 1100v latch-up current......................................+200 ma, ?200 ma ground voltage.................................................................. 0v f osc (crystal frequency)........................... 12 mhz 30 ppm mnemonic data_code_adr address 0x23 length 16 bytes r/w r/w default 0x02f9939702fa5ce3012bf1db0132be6f this file is ignored when using the device in 1-mbps gfsk mode. in 64-sdr mode, only the first ei ght bytes are used; in order t o complete the file write process, these eight bytes must be followed by ei ght bytes of ?dummy? data. in 32-sdr mode, only four bytes are used, and in 32-ddr mode only eight bytes are used. in 64-ddr and 8dr modes, all sixteen bytes are used. cert ain sixteen-byte sequences have been calculated that provide excellent auto-correlation and cross-corr elation properties, and it is recommended that such sequences be used; the default value of this register is one such sequence. in typica l applications, all devices use the same data_code_adr codes, and devices and systems are addressed by using different sop_code_adr codes; in such cases it ma y never be necessary to change the contents of this register from the default value. when reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. this applies to writes, as well. typical applications shoul d use the default code. d o not access or modify this register during transmit or receive. mnemonic preamble_adr address 0x24 length 3 bytes r/w r/w default 0x333302 byte 1 ? the number of repetitions of the preamble sequence that are to be transmitted. the preamble may be disabled by writing 0x00 to this byte. byte 2 ? least significant eight chips of the preamble sequence byte 3? most significant eight chips of the preamble sequence if using 64-sdr to communicate with cywusb69xx devices, set number of repetitions to four for optimum performance when reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the fil e will have been rotated by the number of bytes read. this applies to writes, as well. d o not access or modify this register during transmit or receive. mnemonic mfg_id_adr address 0x25 length 6 bytes r r default na byte 1 ? 4 bits version + 2 bits vendor id + high 2 bits of year byte 2 through byte 6: manufacturing id for the device. to minimize ~190 a of current consumption (default), execute a ?dummy? single-by te spi write to this address with a zero data stage after the contents have been read. non-zero to enable reading of fuses. zero to disable reading fuses. notes 8. it is permissible to connect voltages above v io to inputs through a series resistor limiting i nput current to 1 ma. ac timing not guaranteed. 9. human body model (hbm). [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 75 of 85 notes 10. includes current drawn while starting crystal, starting synthesizer, transmitting packet (including sop and crc16), changing to receive mode, and receiving ack handshake. device is in sleep except during this transaction. dc characteristics (t = 25 c) parameter description conditions min. typ. max. unit radio function operating voltages v bat battery voltage 0?70 c 1.8 3.6 v v io v io voltage 1.8 3.6 v v cc v cc voltage 0?70 c 2.4 3.6 v mcu function operating voltages v dd_micro1 operating voltage no usb activity, cpu speed < 12 mhz 4.0 5.25 v v dd_micro2 operating voltage usb activity, cpu speed < 12 mhz. flash programming 4.35 5.25 v v lvd low-voltage detect trip voltage (8 programmable trip points) 2.68 4.87 v device current (for total current consumption in different modes, fo r example radio, active, mcu, sleep, etc., add radio function current and mcu function current) i dd (gfsk) [10] average i dd , 1 mbps, slow channel pa = 5, 2-way, 4 bytes/10 ms 10.87 ma i dd (32-8dr) [10] average i dd , 250 kbps, fast channel pa = 5, 2-way, 4 bytes/10 ms 11.2 ma i sb sleep mode i dd radio function and mcu function in sleep mode, v reg in keep alive. 40.1 a radio function current (v dd_micro = 5.0v, v reg enabled, mcu sleep) idle i cc radio off, xtal active xout disabled 2.1 ma i synth i cc during synth start 9.8 ma tx i cc i cc during transmit pa = 5 (?5 dbm) 22.4 ma tx i cc i cc during transmit pa = 6 (0 dbm) 27.7 ma tx i cc i cc during transmit pa = 7 (+4 dbm) 36.6 ma rx i cc i cc during receive lna off, att on 20.2 ma rx i cc i cc during receive lna on, att off 23.4 ma mcu function current (v dd_micro = 5.0v, v reg disabled) i dd_micro1 v dd_micro operating supply current no gpio loading, 6 mhz 10 ma i sb1 standby current internal and external oscillators, bandgap, flash, cpu clock, timer clock, usb clock all disabled 410a usb interface v on static output high 15k 5% ohm to v ss 2.8 3.6 v v off static output low r up is enabled 0.3 v v di differential input sensitivity 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2 v c in transceiver capacitance 20 pf i io hi-z state data line leakage 0v < v in < 3.3v ?10 10 a radio function gpio interface v oh1 output high voltage condition 1 at i oh = ?100.0 a v io ? 0.1 v io v v oh2 output high voltage condition 2 at i oh = ?2.0 ma v io ? 0.4 v io v [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 76 of 85 rf characteristics v ol output low voltage at i ol = 2.0 ma 0 0.4 v v ih input high voltage 0.76v io v io v v il input low voltage 0 0.24v io v i il input leakage current 0 < v in < v io ?1 0.26 +1 a c in pin input capacitance except xtal, rf n , rf p , rf bias 3.5 10 pf mcu function gpio interface r up pull-up resistance 4 12 k ? v icr input threshold voltage low, cmos mode low to high edge 40% 65% v cc v icf input threshold voltage low, cmos mode high to low edge 30% 55% v cc v hc input hysteresis voltage, cmos mode high to low edge 3% 10% v cc v ilttl input low voltage, ttl mode i/ o-pin supply = 2.9?3.6v 0.8 v v ihttl input high voltage, ttl mode i/o-pin supply = 4.0?5.5v 2.0 v v ol1 output low voltage, high drive [11] i ol1 = 50 ma 0.8 v v ol2 output low voltage, high drive [11] i ol1 = 25 ma 0.4 v v ol3 output low voltage, low drive [11] i ol2 = 8 ma 0.4 v v oh output high voltage [11] i oh = 2 ma v cc ? 0.5 v 3.3v regulator i vreg max regulator output current v cc > 4.35v 125 ma i ka keep alive current when regulator is disabled with ?keep alive? enable 20 a v reg1 v reg output voltage v cc > 4.35v, 0 < temp < 40c, 25 ma < i vreg < 125 ma 3.0 3.6 v v reg2 v reg output voltage v cc > 4.35v, 0 < temp < 40c, 1 ma < i vreg < 25 ma 3.15 3.45 v v ka keep alive voltage keep alive bit set in vregcr 2.35 3.9 v dc characteristics (t = 25 c) (continued) parameter description conditions min. typ. max. unit note 11. except for pins p1.0, p1.1 in gpio mode. table 84.radio parameters parameter description cond itions min. typ. max. unit rf frequency range subject to regulations. 2.400 2.497 ghz receiver (t = 25c, v cc = 3.0v, f osc = 12.000 mhz, ber < 10 ? 3 ) sensitivity 125 kbps 64-8dr ber 1e-3 ?97 dbm sensitivity 250 kbps 32-8dr ber 1e-3 ?93 dbm sensitivity cer 1e-3 ?80 ?87 dbm sensitivity gfsk ber 1e-3, all slow = 1 ?84 dbm lna gain 22.8 db att gain ?31.7 db maximum received signal lna on ?15 ?6 dbm rssi value for pwr in ?60 dbm lna on 21 count rssi slope 1.9 db/count [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 77 of 85 interference performance (cer 1e-3) co-channel interference rejection carrier-to-interference (c/i) c = ?60 dbm, 9 db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm 3 db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ?30 db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ?38 db out-of-band blocking 30 mhz?12.75 mhz [12] c = ?67 dbm ?30 dbm intermodulation c = ?64 dbm, ? f = 5,10 mhz ?36 dbm receive spurious emission 800 mhz 100-khz resbw ?79 dbm 1.6 ghz 100-khz resbw ?71 dbm 3.2 ghz 100-khz resbw ?65 dbm transmitter (t = 25c, v cc = 3.0v, f osc = 12.000 mhz) maximum rf transmit power pa = 7 +2 4 +6 dbm maximum rf transmit power pa = 6 ?2 0 +2 dbm maximum rf transmit power pa = 5 ?7 ?5 ?3 dbm maximum rf transmit power pa = 0 ?35 dbm rf power control range 39 db rf power range control step size seven steps, monotonic 5.6 db frequency deviation min pn code pattern 10101010 270 khz frequency deviation max pn code pattern 11110000 323 khz error vector magnitude (fsk error) >0 dbm 10 %rms occupied bandwidth ?6 dbc, 100-khz resbw 500 876 khz transmit spurious emission (pa = 7) in-band spurious second channel power (2 mhz) ?38 dbm in-band spurious third channel power (> 3 mhz) ?44 dbm non-harmonically related spurs (8.000 ghz) ?38 dbm non-harmonically related spurs (1.6 ghz) ?34 dbm non-harmonically related spurs (3.2 ghz) ?47 dbm harmonic spurs (second harmonic) ?43 dbm harmonic spurs (third harmonic) ?48 dbm fourth and greater harmonics ?59 dbm power management (crystal pn# ecera gf-1200008) crystal start to 10 ppm 0.7 1.3 ms crystal start to irq xsirq en = 1 0.6 ms synth settle slow channels 270 s synth settle medium channels 180 s synth settle fast channels 100 s link turn-around time gfsk 30 s link turn-around time 250 kbps 62 s link turn-around time 125 kbps 94 s link turn-around time <125 kbps 31 s table 84.radio parameters (continued) parameter description cond itions min. typ. max. unit [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 78 of 85 ac test loads and waveforms for digital pins figure 20. ac test loads and waveforms for digital pins note 12. exceptions f/3 & 5c/3. 13. when using an external switching regulator to power the radio, the switching frequency should be set very far from the if fr equency of 1 mhz. max. packet length < 60 ppm crystal to crystal all modes except 64-ddr 40 bytes max. packet length < 60 ppm crystal to crystal 64-ddr 16 bytes table 84.radio parameters (continued) parameter description cond itions min. typ. max. unit 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: v th thvenin equivalent rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 a c test loads dc test load ac characteristics parameter description conditions min. typical max. unit 3.3v regulator v orip output ripple voltage 45 55 % usb driver t r1 transition rise time c load = 200 pf 75 ns t r2 transition rise time c load = 600 pf 300 ns t f1 transition fall time c load = 200 pf 75 ns t f2 transition fall time c load = 600 pf 300 ns t r rise/fall time matching 80 125 % v crs output signal crossover voltage 1.3 2.0 v usb data timing t drate low-speed data rate ave. bit rate (1.5 mbps 1.5%) 1.4775 1.5225 mbps t djr1 receiver data jitter tolerance to next transition ?75 75 ns t djr2 receiver data jitter tolerance to pair transition ?45 45 ns t deop differential to eop transition skew ?40 100 ns t eopr1 eop width at receiver rejects as eop 330 ns t eopr2 eop width at receiver accept as eop 675 ns t eopt source eop width 1.25 1.5 s [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 79 of 85 figure 21. clock timing figure 22. usb data signal timing t udj1 differential driver jitter to next transition ?95 95 ns t udj2 differential driver jitter to pair transition ?95 95 ns t lst width of se0 during diff. transition 210 ns non-usb mode driver characteristics t fps2 sdata/sck transition fall time 50 300 ns spi timing t smck spi master clock rate f cpuclk /6 2 mhz t ssck spi slave clock rate 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ns t mdo master data output time [14] sck to data valid ?25 50 ns t mdo1 master data output time, first bit with cpha = 0 time before leading sck edge 100 ns t msu master input data set-up time 50 ns t mhd master input data hold time 50 ns t ssu slave input data set-up time 50 ns t shd slave input data hold time 50 ns t sdo slave data output time sck to data valid 100 ns t sdo1 slave data output time, first bit with cpha = 0 time after ss low to data valid 100 ns t sss slave select set-up time before first sck edge 150 ns t ssh slave select hold time after last sck edge 150 ns ac characteristics (continued) parameter description conditions min. typical max. unit clock t cyc t cl t ch 90% 10% 90% 10% d ? d + t r t f v crs v oh v ol notes 14. in master mode first bit is available 0.5 spiclk cycle before master clock edge available on the sclk pin. [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 80 of 85 figure 23. clock timing figure 24. usb data signal timing figure 25. receiver jitter tolerance clock t cyc t cl t ch 90% 10% 90% 10% d ? d + t r t f v crs v oh v ol differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 81 of 85 figure 26. differential to eop transition skew and eop width figure 27. differential data jitter t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 82 of 85 figure 28. spi master timing, cpha = 1 figure 29. spi slave timing, cpha = 1 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 83 of 85 figure 30. spi master timing, cpha = 0 figure 31. spi slave timing, cpha = 0 msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 84 of 85 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram figure 32. 40-pin lead-free qfn 6x6 mm wirelessusb, psoc, encore and proc are trademarks of cypr ess semiconductor corporation. all products and company names mentioned in this document may be t he trademarks of their respective holders. table 85.ordering information package ordering part number 40-pin lead-free qfn 6x6 mm cyrf69213-40 lfxc top view 0.60[0.024] 5.70[0.224] 5.90[0.232] a c 1.00[0.039] max. n bottom view seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08 [0.003] 0.50[0.020] 0.05[0.002] max. 2 side view (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 4.45[0.175] 6.10[0.240] 5.80[0.228] 4.55[0.179] 0.45[0.018] 0.20[0.008] r. dia. 0.28[0.011] 0.30[0.012] 0.60[0.024] 5.90[0.232] 5.80[0.228] 5.70[0.224] 6.10[0.240] 4.55[0.179] 4.45[0.175] 3. package weight: 0.086g 1. hatch is solderable exposed area 4. all dimensions are in mm [min/max] 2. reference jedec#: mo-220 notes : pad exposed solderable 18.5 18.5 51-85190-*a [+] feedback [+] feedback cyrf69213 document #: 001-07552 rev. *b page 85 of 85 document history page document title: cyrf69213 programmable radio on chip low power document #: 001-07552 rev. ecn no. issue date orig. of change description of change ** 436355 see ecn oyr new advance data sheet. *a 501280 see ecn oyr preliminary data sheet. *b 631538 see ecn boo final datasheet. updated dc ch aracteristics table with characterization data. minor text changes removed all residual references to external crystal oscillator and gpio4 voltage regulator line/load regulation documented gpio capacitance and timing diagram included sleep and wake up sequence documented. ep1mode/ep2mode register issue discussed updated radio function register descriptions changed l/d pin description changed rst capacitor from 0.1uf to 0.47uf [+] feedback [+] feedback |
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