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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. document no. u13477ej1v0ds00 (1st edition) date published may 2001 j cp(k) printed in japan ? 1998 8-bit single-chip microcontroller data sheet mos integrated circuit shows major revised points. the pd78f9831 is an 8-bit single-chip microcontroller (for lcd driving) of the 78k/0s series. the pd78f9831 is produced by replacing the internal rom of the pd789830 with larger flash memory. flash memory can be written or erased electrically without having to remove it from board. therefore, the pd78f9831 is best suited for prototypes in system development, low-volume production, or systems likely to be upgraded frequently. the functions of the pd78f9831 are described in the following user's manuals. refer to these manuals when designing a system based on the pd78f9831. pd789830 subseries user's manual : u13679e 78k/0s series user's manual, instruction : u11047e features ? internal flash memory: 48 kbytes ? ram sizes ? internal ram : 2 kbytes ? lcd data ram : 40 16 bits ? variable minimum instruction execution time: from high-speed (0.4 s: with the main system clock running at 5.0 mhz) to very low-speed (122 s: with the subsystem clock running at 32.768 khz) ? 38 i/o ports ? serial interface (uart00) ? lcd controller/driver ? up to 40 segment signal outputs ? up to 16 common signal outputs ? 1/5 bias mode ? four timers: ? 16-bit timer ? 8-bit timer ? watch timer ? watchdog timer ? pulse output: clock output/buzzer output ? built-in key return signal detection circuit ? power supply voltage: v dd = 2.7 to 5.5 v applications card readers
data sheet u13477ej1v0ds 2 pd78f9831 ordering information part number package pd78f9831gc-8eu 100-pin plastic lqfp (fine pitch) (14 14 mm)
data sheet u13477ej1v0ds 3 pd78f9831 78k/0s series development the 78k/0s series products are shown below. the subseries names are indicated in frames. 52-pin 52-pin pd789327 pd789467 products under development products in mass production pd789014 small-scale package, general-purpose applications 78k/0s series 28-pin lcd drive inverter control 44-pin pd789842 assp 80-pin 80-pin pd789446 pd789456 pd789436 pd789417a pd789407a pd789426 pd789306 pd789316 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789177y pd789167y y subseries products support smb. dot lcd drive 20-pin pd789860 pd789840 44-pin 44-pin pd789800 20-pin pd789861 88-pin pd789830 pd789835 144-pin 42/44-pin 44-pin pd789074 30-pin vfd drive 52-pin pd789871 80-pin pd789803 64-pin 80-pin 30-pin pd789477 pd789088 pd789046 pd789026 pd789488 ? pd789014 with enhanced timer and increased rom, ram capacity on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock pd789026 with enhanced timer pd789074 with enhanced timer and increased rom, ram capacity pd789167 with enhanced 10-bit a/d converter pd789104a with enhanced timer pd789124a with enhanced 10-bit a/d converter rc oscillation version of the pd789104a pd789104a with enhanced 10-bit a/d converter pd789026 with added 8-bit a/d converter and multiplier pd789104a with added eeprom tm pd789146 with enhanced 10-bit a/d converter on-chip inverter controller and uart total display outputs: 25 pd789426 with enhanced 10-bit a/d converter pd789446 with enhanced 10-bit a/d converter sio, 8-bit a/d converter, and resistance division type lcd (28 4) sio, 8-bit a/d converter, and on-chip voltage booster type lcd (15 4) pd789407a with enhanced 10-bit a/d converter sio, 8-bit a/d converter, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 8-bit a/d converter and on-chip voltage booster type lcd sio and on-chip resistance division type lcd sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) sio, 8-bit a/d converter, and resistance division type lcd (28 4) segments: 40, commons: 16 segment/common outputs: 96 for keyless entry, on-chip poc and key return circuit for keypad, on-chip poc for pc keyboard, on-chip usb function rc oscillation version of the pd789860 for pc keyboard, on-chip usb hub function remark the vacuum fluorescent display (vfd) is a typical name. in some documents, however, it is described as the fluorescent indicator panel (fip ? ). the vfd and fip have identical functions.
data sheet u13477ej1v0ds 4 pd78f9831 the major functional differences among the subseries are listed below. timer v dd function subseries name rom capacity (bytes) 8-bit 16- bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remark pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 small scale, general- purpose applica- tions pd789014 2 k to 4 k 2 ch ? ? 1 ch ?? 1 ch (uart: 1 ch) 22 1.8 v ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small- scale, general- purpose applica- tions + a/d function pd789104a 2 k to 8 k 1 ch 1 ch ? 1ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ?? 1 ch 33 2.7 v ? pd789488 32 k ? 8 ch pd789477 24 k 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 k to 16 k 1 ch ? 2 ch (uart: 1 ch) 23 pd789427 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 28 1.8 v dot lcd drive pd789830 24 k 1 ch 1 ch 1 ch 1 ch ? ? 1 ch (uart: 1 ch) 30 2.7 v ? pd789803 8 k to 16 k 41 3.6 v pd789800 ? 2 ch (usb: 1 ch) 31 4.0 v pd789840 8 k 4 ch 1 ch 29 2.8 v ? pd789861 rc oscillation version, on- chip eeprom assp pd789860 4 k 2 ch ?? 1 ch ? ? ? 14 1.8 v on-chip eeprom note 10-bit timer: 1 channel
data sheet u13477ej1v0ds 5 pd78f9831 functions item function internal memory flash memory 48 kbytes ram 2 kbytes lcd data ram 40 16 bits minimum instruction execution time ? 0.4/1.6 s (operation with main system clock r unning at 5.0 mhz) ? 122 s (operation with sub system clock r unning at 32.768 khz) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) i/o ports total of 38 port pins ? 37 cmos input/output pins ? n-ch open-drain input/output pin serial interface ? uart mode lcd controller/driver ? up to 40 segment signal outputs ? up to 16 common signal outputs ? 1/5 bias mode timers ? 16-bit timer ? 8-bit timer ? watch timer ? watchdog timer pulse output clock output/buzzer output maskable 10 internal and 6 external interrupts vectored interrupt sources nonmaskable internal interrupt power supply voltage v dd = 2.7 to 5.5 v operating ambient temperature t a = -20 to + 60 c package 100-pin plastic lqfp (fine pitch) (14 14 mm)
data sheet u13477ej1v0ds 6 pd78f9831 contents 1. pin configuration (top view) ................................................................................................7 2. block diagram ................................................................................................................ ............9 3. pin functions ................................................................................................................ ..............10 3.1 port pins................................................................................................................... ............................. 10 3.2 non-port pins............................................................................................................... ......................... 11 3.3 pin input/output circuits and handling of unused pins .................................................................. 12 4. memory space ................................................................................................................. ...........15 5. interrupt functions .......................................................................................................... .....16 6. flash memory programming................................................................................................18 6.1 selecting the transmission method ........................................................................................... ........ 18 6.2 flash memory programming functions .......................................................................................... ... 19 6.3 connecting the flashpro iii ................................................................................................. ................ 19 6.4 example of settings for flashpro iii (pg-fp3) ............................................................................... .... 20 7. instruction set overview ..................................................................................................... 21 7.1 legend...................................................................................................................... ............................. 21 7.2 operations.................................................................................................................. ........................... 23 8. electrical characteristics................................................................................................28 9. package drawings ............................................................................................................. ......38 10. recommended soldering conditions...............................................................................39 appendix a differences between the pd78f9831 and masked rom product .......40 appendix b development tools...............................................................................................41 appendix c related documents ..............................................................................................43
data sheet u13477ej1v0ds 7 pd78f9831 1. pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14 mm) pd78f9831gc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 s23 s24 s25 s26 s27 s28 s29 s30 s31 p57/s32 p56/s33 p55/s34 p54/s35 p53/s36 p52/s37 p51/s38 p50/s39 p17 p16 p15 p14 p13 p12 p11 p10 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 p20/intp0 p21/intp1 p22/intp2/buz p23/pcl p24 p25/txd00 p26/rxd00 nc ic0 nc p40/intp3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p41/intp4 xt1 xt2 v dd0 v ss0 x1 x2 reset v pp ic2 p00 p01 p02 p03 p04 p05 p06 p07 p30 p31 p32 p33 p34 v ss1 v dd1 84 83 82 81 80 79 78 77 76 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 com14 com15 cautions 1. in normal operation mode, connect the v pp pin directly to the v ss0 or v ss1 pin. 2. connect the ic0 (internally connected) pin directly to the v ss0 or v ss1 pin. 3. leave the ic2 pin open.
data sheet u13477ej1v0ds 8 pd78f9831 buz : buzzer clock pcl : programming clock com0-com15 : common output reset : reset ic0, ic2 : internally connected rxd00 : receive data intp0-intp4 : external interrupt input s0-s39 : segment output nc : non-connection txd00 : transmit data p00-p07 : port 0 v dd0 , v dd1 : power supply p10-p17 : port 1 v pp : programming power supply p20-p26 : port 2 v ss0 , v ss1 : ground p30-p34 : port 3 x1, x2 : crystal (main system clock) p40, p41 : port 4 xt1, xt2 : crystal (subsystem clock) p50-p57 : port 5
data sheet u13477ej1v0ds 9 pd78f9831 2. block diagram v dd0 v dd1 v ss0 v ss1 ic0 ic2 v pp 78k/0s cpu core flash memory ram 8-bit timer counter 00 p00-p07 port0 p10-p17 port1 p20-p26 port2 p30-p34 port3 pcl/buzzer unit(pbu) rxd00/p26 txd00/p25 uart00 watch timer watchdog timer buz/p22 pcl/p23 16-bit timer counter 40 s0-s31 s32/p57-s39/p50 com0-com15 lcd controller/ driver p50-p57 port5 system control reset x1 x2 xt1 xt2 p40, p41 port4 interrupt control intp0/p20 intp1/p21 intp2/p22 intp3/p40 intp4/p41
data sheet u13477ej1v0ds 10 pd78f9831 3. pin functions 3.1 port pins pin name i/o function when reset also used as p00-p07 i/o port 0 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by software. input ? p10-p17 i/o port 1 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by software. input ? p20 i/o input intp0 p21 intp1 p22 intp2/buz p23 pcl p24 ? p25 txd00 p26 port 2 7-bit input/output port can be set to either input or output in 1-bit units p24 can be used as an n-ch open-drain input/output port pin. rxd00 p30-p34 i/o input ? port 3 5-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the on-chip pull-up resistor is to be used can be specified by software. p40 intp3 p41 i/o port 4 2-bit input/output port can be set to either input or output in 1-bit units input intp4 p50-p57 i/o port 5 8-bit input/output port can be set to either input or output in 1-bit units input s39-s32
data sheet u13477ej1v0ds 11 pd78f9831 3.2 non-port pins pin name i/o function when reset also used as intp0 input input p20 intp1 p21 intp2 p22/buz intp3 p40 intp4 external interrupt input for which effective edges (rising and/or falling edges) can be specified p41 rxd00 input serial data input to asynchronous serial interface input p26 txd00 output serial data output from asynchronous serial interface input p25 buz output buzzer output input p22/intp2 pcl output clock output input p23 s0-s31 output segment signal output from lcd controller/driver output ? s32-s39 p57-p50 com0- com15 output common signal output from lcd controller/driver output ? x1 input connected to crystal for main system clock oscillation ?? x2 ? ?? xt1 input connected to crystal for sub system clock oscillation ?? xt2 ? ?? reset input system reset input input ? v dd0 ? positive supply voltage for ports ?? v dd1 ? positive supply voltage for circuits other than ports ?? v ss0 ? port section ground potential ?? v ss1 ? ground potential of circuits other than ports ?? nc ? this pin is not internally connected. connect this pin directly to the v ss0 or v ss1 pin (it can also be left open). ?? ic0 input this pin is internally connected. connect this pin directly to the v ss0 or v ss1 pin. ?? ic2 ? this pin is internally connected. leave this pin open. ?? v pp ? this pin is used to set flash memory programming mode and applies a high voltage when a program is written or verified. in normal operation mode, connect this pin directly to the v ss0 or v ss1 pin. ??
data sheet u13477ej1v0ds 12 pd78f9831 3.3 pin input/output circuits and handling of unused pins table 3-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 3-1 shows the configuration of each type of input/output circuit. table 3-1. type of input/output circuit for each pin and handling of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00-p07 i/o p10-p17 5-h connect these pins to the v dd0 , v dd1 , v ss0 , or v ss1 pin via the respective resistor. p20/intp0 p21/intp1 p22/intp2/buz 8-h connect these pins to the v ss0 or v ss1 pin via the respective resistor. p23/pcl 5-s p24 13-ab p25/txd00 5-s p26/rxd00 8-h p30-p34 8-c connect these pins to the v dd0 , v dd1 , v ss0 , or v ss1 pin via the respective resistor. p40/intp3 p40/intp4 8-h connect these pins to the v ss0 or v ss1 pin via the respective resistor. p50/s39- p57/s32 17-i connect these pins to the v dd0 , v dd1 , v ss0 , or v ss1 pin via the respective resistor. s0-s31 17-h com0-com15 18-c output leave these pins open. xt1 16 input connect this pin to the v ss0 or v ss1 pin. xt2 ? leave this pin open. reset 2 input ? nc ?? connect this pin directly to the v ss0 or v ss1 pin, or leave it open. ic0 ? input connect this pin directly to the v ss0 or v ss1 pin. ic2 2-b ? leave this pin open. v pp ?? connect this pin directly to the v ss0 or v ss1 pin.
data sheet u13477ej1v0ds 13 pd78f9831 figure 3-1. pin input/output circuits (1/2) schmitt trigger input with hysteresis type 2 in type 5-h pull-up enable v dd0 p-ch p-ch in/out data output disable input enable v dd0 n-ch v ss0 pull-up enable v dd0 p-ch data v dd0 p-ch output disable in/out n-ch v ss0 type 8-c type 5-s data output disable input enable v dd0 n-ch v ss0 in/out data output disable v dd0 p-ch in/out n-ch v ss0 type 8-h p-ch type 2-b in input enable
data sheet u13477ej1v0ds 14 pd78f9831 figure 3-1. pin input/output circuits (2/2) type 16 type 17-h type 17-i type 18-c xt2 xt1 feedback cut-off p-ch n-ch p-ch n-ch p-ch n-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch p-ch n-ch n-ch n-ch n-ch p-ch p-ch n-ch p-ch v lc0 v lc3 v lc2 v ss1 seg data n-ch data output disable p-ch v dd0 v ss0 n-ch input enable in/out p-ch n-ch n-ch n-ch p-ch n-ch p-ch p-ch n-ch out v lc0 v lc3 v lc1 v lc0 seg data v ss1 v ss1 v lc4 out com data v lc2 p-ch output disable in/out n-ch v ss0 v dd0 p-ch rd data port read input buffer with intermediate withstand voltage type 13-ab
data sheet u13477ej1v0ds 15 pd78f9831 4. memory space the pd78f9831 can access up to 64 kbytes of memory space. figure 4-1 shows the memory map. figure 4-1. memory map c000h bfffh special function register 256 8 bits internal high-speed ram 1,024 8 bits lcd data ram 40 16 bits ffffh ff00h feffh fb00h faffh 0000h program memory space data memory space bfffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area unusable 0020h 001fh vector table area internal flash memory fa50h fa4fh fa00h f9ffh unusable 49,152 8 bits unusable internal low-speed ram 1,024 8 bits f700h f6ffh f300h f2ffh
data sheet u13477ej1v0ds 16 pd78f9831 5. interrupt functions there are two types and 17 sources of interrupt functions as shown below. ? nonmaskable interrupt: 1 source ? maskable interrupts : 16 sources table 5-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 nonmaskable ? intwdt watchdog timer overflow (watchdog timer mode 1 selected) internal 0004h (a) maskable 0 intwdt watchdog timer overflow (interval timer mode selected) (b) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intser00 occurrence of serial interface (uart00) reception error internal 000ch (b) 5 intsr00 end of serial interface (uart00) reception 000eh 6 intst00 end of serial interface (uart00) transmission 0010h 7 inttm40 generation of 16-bit timer 40 match signal 0012h 8 inttm41 occurrence of 16-bit timer 40 overflow 0014h 9 inttm4 logical or of 16-bit timer 40 match signal and overflow signal 0016h 10 inttm00 generation of 8-bit timer 00 match signal 0018h 11 intwti interval timer interrupt 001ah 12 intwt watch timer interrupt 001ch 13 intkr00 key return signal detection external 001eh (c) 14 intp3 0020h 15 intp4 pin input edge detection 0022h notes 1. priorities are intended for the priority for two or more simultaneously generated maskable interrupts. 0 is the highest priority and 15 is the lowest priority. 2. basic configuration types (a) to (c) correspond to (a) to (c) of figure 5-1. remark only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected.
data sheet u13477ej1v0ds 17 pd78f9831 figure 5-1. basic configuration of interrupt function (a) internal nonmaskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, intm1, krm00 interrupt request edge detector vector table address generator standby release signal intm0 : external interrupt mode register 0 intm1 : external interrupt mode register 1 krm00 : key return mode register 00 if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag
data sheet u13477ej1v0ds 18 pd78f9831 6. flash memory programming flash memory is used as the built-in program memory of the pd78f9831. the flash memory can be written even while the device is mounted in the target system (on-board write). to write a program into the flash memory, connect the dedicated flash writer (flashpro iii (model number: fl-pr3, pg-fp3)) to both the host machine and target system. remark the fl-pr3 is manufactured by naito densei machida mfg. co., ltd. 6.1 selecting the transmission method the flashpro iii writes into flash memory by means of serial transmission. the transmission method to be used for writing is selected from those listed in table 6-1. to select a transmission method, use the format shown in figure 6-1, according to the number of v pp pulses listed in table 6-1. table 6-1. transmission methods transmission method pins note 1 number of v pp pulses uart txd00/p25 rxd00/p26 8 pseudo 3-wire mode note 2 p10 (serial clock input) p11 (serial data input) p12 (serial data output) 12 notes 1. when flash memory programming mode is set, all pins not used for memory programming enter the same state as that immediately after a reset. therefore, when the external device connected to a port cannot recognize that state of the port immediately after a reset, the pins must be connected to the v dd0 or v dd1 pin, or the v ss0 or v ss1 pin via a resistor. 2. serial transfer by controlling the ports using software caution to select a transmission method, always use the corresponding number of v pp pulses listed in table 6-1. figure 6-1. format of transmission method selection v dd v ss 10 v 12 n v pp v dd v ss reset
data sheet u13477ej1v0ds 19 pd78f9831 6.2 flash memory programming functions flash memory writing and other operations can be performed by transmitting/receiving commands and data according to the selected transmission method. table 6-2 lists the main flash memory programming functions. table 6-2. main flash memory programming functions function description batch erase erases the entire contents of memory. batch blank check checks that the entire contents of memory have been erased. data write write to the flash memory according to the specified write start address and number of bytes of data to be written. batch verify compares the entire contents of memory with the input data. 6.3 connecting the flashpro iii the connection between the flashpro iii and pd78f9831 varies with the transmission method (uart or pseudo 3-wire). figures 6-2 and 6-3 show the connection for each transmission method. figure 6-2. flashpro iii connection in uart mode v pp n note v dd reset so si gnd v pp v dd0 , v dd1 reset rxd00 txd00 v ss0 , v ss1 flashpro iii pd78f9831 note n: 1 or 2 figure 6-3. flashpro iii connection in pseudo 3-wire mode v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 reset p10 (serial clock) p11 (serial input) p12 (serial output) v ss0 , v ss1 flashpro iii pd78f9831 note n: 1 or 2
data sheet u13477ej1v0ds 20 pd78f9831 6.4 example of settings for flashpro iii (pg-fp3) when writing to flash memory using flashpro iii (pg-fp3), make the following settings. <1> load a parameter file. <2> select the mode of serial communication and serial clock with a type command. <3> make the settings according to the example of settings for pg-fp3 shown below. table 6-3. example of settings for pg-fp3 communication mode example of settings for pg-fp3 v pp pulse number note 1 comm port uart-ch0 cpu clk on target board on target board 4.1943 mhz uart uart bps 9,600 bps note 2 8 comm port port a on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 khz in flashpro 4.0 mhz pseudo 3-wire mode sio clk 1.0 khz 12 notes 1 . this is the number of v pp pulses that are supplied by the flashpro iii at serial communication initialization. the pins that will be used for communication are determined according to this number. 2. select one of 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps. remark comm port : serial port selection sio clk : serial clock frequency selection cpu clk : input cpu clock source selection
data sheet u13477ej1v0ds 21 pd78f9831 7. instruction set overview the instruction set for the pd78f9831 is listed later. 7.1 legend 7.1.1 operand formats and descriptions the description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform with the assembly specification). if more than one operand format is listed for an instruction, one is selected. uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ and ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or a pair of [ and ]. operand registers, expressed as r or rp in the formats, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed in table 7-1). table 7-1. operand formats and descriptions format description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh: immediate data or label fe20h to ff1fh: immediate data or label (even addresses only) addr16 addr5 0000h to ffffh: immediate data or label (only even address for 16-bit data transfer instructions) 0040h to 007fh: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
data sheet u13477ej1v0ds 22 pd78f9831 7.1.2 descriptions of the operation field a : a register (8-bit accumulator) x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair (16-bit accumulator) bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : flag to indicate that a nonmaskable interrupt is being handled () : contents of a memory location indicated by a parenthesized address or register name x h , x l : upper and lower 8 bits of a 16-bit register : logical product (and) : logical sum (or) : exclusive or ? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 7.1.3 description of the flag operation field (blank) : no change 0 : to be cleared to 0 1 : to be set to 1 : to be set or cleared according to the result r : to be restored to the previous value
data sheet u13477ej1v0ds 23 pd78f9831 7.2 operations flag mnemonic operand byte clock operation zaccy mov r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 24a r r, a note 1 24r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) [hl + byte], a 2 6 (hl + byte) a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 3 1 4 ax rp rp, ax note 3 14rp ax notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u13477ej1v0ds 24 pd78f9831 flag mnemonic operand byte clock operation zaccy xchw ax, rp note 18 ax ? rp add a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) a, [hl + byte] 2 6 a, cy a + (hl + byte) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy sub a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) a, [hl + byte] 2 6 a, cy a ? (hl + byte) subc a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy and a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) a, [hl + byte] 2 6 a a (hl + byte) note only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u13477ej1v0ds 25 pd78f9831 flag mnemonic operand byte clock operation zaccy or a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) a, [hl + byte] 2 6 a a (hl + byte) xor a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) a, [hl + byte] 2 6 a a (hl + byte) cmp a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word inc r 2 4 r r + 1 saddr 2 4 (saddr) (saddr) + 1 dec r 2 4 r r ? 1 saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u13477ej1v0ds 26 pd78f9831 flag mnemonic operand byte clock operation zaccy set1 saddr. bit 3 6 (saddr. bit) 1 sfr. bit 3 6 sfr. bit 1 a. bit 2 4 a. bit 1 psw. bit 3 6 psw. bit 1 [hl]. bit 2 10 (hl). bit 1 clr1 saddr. bit 3 6 (saddr. bit) 0 sfr. bit 3 6 sfr. bit 0 a. bit 2 4 a. bit 0 psw. bit 3 6 psw. bit 0 [hl]. bit 2 10 (hl). bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr push psw 1 2 (sp ? 1) psw, sp sp ? 1 rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 pop psw 1 4 psw (sp), sp sp + 1 r r r rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, ax 2 8 sp ax ax, sp 2 6 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 1 6 pc h a, pc l x remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u13477ej1v0ds 27 pd78f9831 flag mnemonic operand byte clock operation zaccy bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u13477ej1v0ds 28 pd78f9831 8. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rated value unit supply voltage v dd ? 0.3 to +6.5 v v pp ? 0.3 to +10.5 v input voltage v i1 pins other than p24 ? 0.3 to v dd + 0.3 note v v i2 p24 n-ch open drain ? 0.3 to +13 v output voltage v o ? 0.3 to v dd + 0.3 note v high-level output current i oh each pin ? 10 ma total for all pins ? 30 ma low-level output current i ol each pin 30 ma total for all pins 160 ma during normal operation ? 20 to +60 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ? 40 to +125 c note 6.5 v or less caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated.
data sheet u13477ej1v0ds 29 pd78f9831 characteristics of the main system clock oscillation circuit (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillator frequency (f x ) note 1 2.0 5.0 mhz ceramic resonator x2 x1 ic0 c2 c1 oscillation settling time note 2 time after v dd reaches min. of the oscillation voltage range 4ms oscillator frequency (f x ) note 1 2.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal x2 x1 ic0 c2 c1 oscillation settling time note 2 30 ms x1 input frequency (f x ) note 1 2.0 5.0 mhz external clock x1 open x2 x1 input high/low level width (t xh , t xl ) 85 250 ns notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle once a reset sequence ends or stop mode is deselected. cautions 1. when using the main system clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. ? keep the wiring as short as possible. ? do not allow signal wires to cross one another. ? keep the wiring away from wires that carry a high, non-stable current. ? keep the grounding point of the capacitors at the same level as v ss0 . ? do not connect the grounding point to a grounding wire that carries a high current. ? do not extract a signal from the oscillation circuit. 2. before switching from the subsystem clock back to the main system clock, always allow sufficient time for the oscillation to settle by specifying it in the program. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
data sheet u13477ej1v0ds 30 pd78f9831 characteristics of the subsystem clock oscillation circuit (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillator frequency (f xt ) note 1 32 32.768 35 khz oscillation settling time note 2 v dd = 4.5 to 5.5 v 1.2 2 s crystal xt2 xt1 ic0 c4 c3 r 10 xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high/low level width (t xth , t xtl ) 14.3 15.6 s notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle after v dd reaches the min. value of the oscillation voltage range. cautions 1. when using the subsystem clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. ? keep the wiring as short as possible. ? do not allow signal wires to cross one another. ? keep the wiring away from wires that carry a high, non-stable current. ? keep the grounding point of the capacitors at the same level as v ss0 . ? do not connect the grounding point to a grounding wire that carries a high current. ? do not extract a signal from the oscillation circuit. 2. the subsystem clock oscillation circuit is designed to have a low amplification degree so as to maintain a low current drain. therefore, it is more likely to malfunction as a result of noise than the main system clock oscillation circuit. when using the subsystem clock, therefore, pay particularly careful attention to how it is wired. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
data sheet u13477ej1v0ds 31 pd78f9831 dc characteristics (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin -1 ma output current, high i oh total for all pins -15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v ih1 p00-p07, p10-p17, p23, p25, p50-p57 0.7v dd v dd v v ih2 reset, p20-p22, p26, p30-p34, p40, p41 0.8v dd v dd v v ih3 p24 (n-ch open drain) 0.7v dd 12 v v dd = 4.5 to 5.5 v v dd - 0.5 v dd v high-level input voltage v ih4 x1, x2, xt1, xt2 v dd - 0.1 v dd v v il1 p00-p07, p10-p17, p23, p25, p50-p57 0 0.3v dd v v il2 reset, p20-p22, p26, p30-p34, p40, p41 0 0.2v dd v v il3 p24 (n-ch open drain) 0 0.3v dd v v il4 v dd = 4.5 to 5.5 v 0 0.4 v low-level input voltage x1, x2, xt1, xt2 00.1v i oh = -1 ma v dd = 4.5 to 5.5 v v dd - 1.0 v high-level output voltage v oh i oh = -100 av dd - 0.5 v 4.5 < v dd < 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than the p24 pin 2.7 < v dd < 4.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v low-level output voltage v ol2 p24 (n-ch open drain) 2.7 < v dd < 4.5 v, i ol = 1.6 ma 0.4 v i lih1 v in = v dd p00-p07, p10-p17, p20-p23, p25, p26, p30-p34, p40, p41, p50-p57, reset 3 a i lih2 x1, x2, xt1, xt2 20 a high-level input leakage current i lih3 v in = 12 v p24 (n-ch open drain) 20 a i lil1 p00-p07, p10-p17, p20-p23, p25, p26, p30-p34, p40, p41, p50-p57, reset, p24 (when an input instruction is not executed) -3 a i lil2 x1, x2, xt1, xt2 -20 a low-level input leakage current i lil3 v in = 0 v p24 (n-ch open drain) when an input instruction is executed -30 a remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated.
data sheet u13477ej1v0ds 32 pd78f9831 dc characteristics (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd 3 a low-level output leakage current i lol v out = 0 v -3 a software-specified pull-up resistor r 1 v in = 0 v, p00-p07, p10-p17, p30-p34 50 100 200 k ? i dd1 v dd = 5.0 v 10% note 2 510ma 5.0-mhz crystal oscillation operating mode v dd = 3.0 v 10% note 3 36ma i dd2 v dd = 5.0 v 10% note 2 0.8 1.6 ma 5.0-mhz crystal oscillation halt mode v dd = 3.0 v 10% note 3 0.4 0.8 ma i dd3 v dd = 5.0 v 10% 120 240 a 32.768-khz crystal oscillation operating mode note 4 v dd = 3.0 v 10% 80 160 a i dd4 v dd = 5.0 v 10% 25 55 a 32.768-khz crystal oscillation halt mode note 4 v dd = 3.0 v 10% 10 20 a i dd5 v dd = 5.0 v 10% 0.1 10 a power supply current note 1 stop mode v dd = 3.0 v 10% 0.05 10 a notes 1. neither the power supply current flowing when lcd is active (lcdon20 = 1, lips20 = 1) nor the port current (including the current flowing through the on-chip pull-up resistor) is included. 2. during high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h) 3. during low-speed mode operation (when the pcc is set to 02h) 4. while the main system clock is stopping remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated.
data sheet u13477ej1v0ds 33 pd78f9831 lcd characteristics (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = v lcd vaon20 = 0 3.5 5.5 v lcd drive voltage v lcd vaon20 = 1 2.7 5.5 v v ods when the output level is v lc0 v lcd v when the output level is v lc2 3/5v lcd v segment output voltage note 1 when the output level is v lc3 2/5v lcd v v odc when the output level is v lc0 v lcd v when the output level is v lc1 4/5v lcd v common output voltage note 1 when the output level is v lc4 1/5v lcd v segment output on resistance r seg v lcn sp, i o = | 20 a | 5.0 12.5 k ? common output on resistance r com v lcn comq, i o = | 20 a | 4.0 10.0 k ? vaon20 = 1 32 78.13 khz lcd input frequency f lcd vaon20 = 0 7.81 78.13 khz i lcd1 v dd = 5.0 v 10%, vaon20 = 0 30 65 a lcd operating current note 2 i lcd2 v dd = 3.0 v 10%, vaon20 = 1 17 40 a notes 1. voltages when no load is applied 2. total current flowing through the v dd0 pin (including the current flowing through the lcd divider resistor) when lcdon20 = 0 and lips20 = 0 (the display is turned off and the internal drive power is not supplied), the power supply current is included in the power supply current i dd5 (stop mode) in the dc characteristics. remark n = 0 to 4 p = 0 to 39 q = 0 to 15
data sheet u13477ej1v0ds 34 pd78f9831 ac characteristics (1) basic operations (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit t cy operation based on main system clock 0.4 4.0 s cycle time (minimum instruction execution time) operation based on subsystem clock 114 122 125 s interrupt input high/low level width t inth , t intl intp0 to intp4 10 s reset low level width t rsl 10 s t cy vs v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operating range 4.0 (2) serial interface (uart00) (t a = -20 to +60 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit transfer rate operation at f x = 5.0 mhz 78,125 bps
data sheet u13477ej1v0ds 35 pd78f9831 ac timing measurement points (except the x1 and xt1 inputs) 0.8v dd 0.2v dd measurement points 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) interrupt input timing intp0-intp4 t intl t inth reset input timing reset t rsl
data sheet u13477ej1v0ds 36 pd78f9831 data memory stop mode low supply voltage data retention characteristics (t a = -20 to +60 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x ms oscillation stabilization wait time note 1 t wait release by interrupt request note 2 ms notes 1. oscillation stabilization wait time is a time for stopping the cpu operation to prevent the unstable operation when the oscillation is started. 2. selection of 2 12 /f x , 2 15 /f x , and 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
data sheet u13477ej1v0ds 37 pd78f9831 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit operating frequency f x 25mhz write current note (v dd pin) i ddw when v pp supply voltage = v pp1 5.0-mhz crystal oscillation operation mode 13 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 20 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 5.0-mhz crystal oscillation operation mode 13 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma erase time t er 20 s write count erase/write are regarded as 1 cycle. 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the port current (including the current that flows to the on-chip pull-up resistors) is not included.
data sheet u13477ej1v0ds 38 pd78f9831 9. package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u13477ej1v0ds 39 pd78f9831 10. recommended soldering conditions the pd78f9831 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 10-1. surface mounting type soldering conditions pd78f9831gc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), count: twice or less vp15-00-2 partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) ? caution do not use different soldering methods together (except for partial heating).
data sheet u13477ej1v0ds 40 pd78f9831 appendix a differences between the pd78f9831 and masked rom product the pd78f9831 is produced by replacing the internal rom of the masked rom product pd789830 with larger flash memory, and by adding i/o ports to the pd789830. unlike bare chips of masked rom products, the shipped pd78f9831 is contained in a 100-pin plastic lqfp package. table a-1 lists differences between the pd78f9831 and pd789830. table a-1. differences between the pd78f9831 and pd789830 flash memory product masked rom product item pd78f9831 pd789830 flash memory/rom 48 kbytes 24 kbytes ram 2 kbytes 1 kbyte internal memory lcd display ram 40 16 bits i/o ports total: 38 port pins p00-p07, p10-p17, p20-p26, p30- p34, p40, p41, p50-p57 total: 30 port pins p00-p07, p10, p11, p20-p26, p30- p34, p50-p57 external interrupt input pins total: 5 pins intp0-intp4 total: 3 pins intp0-intp2 interrupt sources 17 15 v pp pin yes no form of shipment 100-pin plastic lqfp 88-pin bare chip electrical characteristics refer to individual related data sheets.
data sheet u13477ej1v0ds 41 pd78f9831 appendix b development tools the following development tools are available for system development using the pd78f9831. language processing software ra78k0s notes 1, 2, 3 assembler package common to 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to 78k/0s series df789831 notes 1, 2, 3 device file for pd789830 subseries cc78k0s-l notes 1, 2, 3 c compiler library source file common to 78k/0s series flash memory writing tools flashpro lil (part no. fl-pr3 note 4 , pg-fp3) flash programmer dedicated to on-chip flash memory microcontroller fa-100gc-8eu note 4 flash memory writing adapter for 100-pin plastic lqfp (fine pitch) (gc-8eu type) debugging tools ie-78k0s-ns in-circuit emulator this in-circuit emulator is used to debug hardware or software when application systems which use the 78k/0s series are devel oped. the ie-78k0s-ns supports the integrated debugger (id78k0s-ns). the ie-78k0s-ns is used in combination with an interface adapter for connection to an ac adapter, emulation probe, or host machine. ie-70000-mc-ps-b ac adapter this adapter is used to supply power from a 100 to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when a pc-9800 series pc (except notebook type) is used as the host machine for the ie-78k0s-ns (c bus supported). ie-70000-cd-if-a pc card/interface these pc card and interface cable are required when a notebook pc is used as the host machine for the ie-78k0s-ns (pcmcia socket supported). ie-70000-pc-if-c interface adapter this adapter is required when an ibm pc/at tm or compatible is used as the host machine for the ie-78k0s-ns (isa bus supported). ie-70000-pci-if-a interface adapter this adapter is required when a pci bus incorporated personal computer is used as the host machine for the ie-78k0s-ns. ie-789831-ns-em1 emulation board this board is used to emulate the peripheral hardware specific to the device. the ie-789046-ns-em1 is used in combination with the in-circuit emulator. board to connect an in-circuit emulator to the target system. this is used in combination with the tgc-100sdw. np-100gc emulation probe tgc-100sdw note 5 conversion adapter conversion socket to connect the np-100gc to a target system board on which a 100-pin plastic lqfp (fine pitch) (gc-8eu type) can be mounted. sm78k0s notes 1, 2 system simulator common to 78k/0s series id78k0s-ns notes 1, 2 integrated debugger common to 78k/0s series df789831 notes 1, 2 device file for pd789830 subseries
data sheet u13477ej1v0ds 42 pd78f9831 real-time os mx78k0s notes 1, 2 os for 78k/0s series notes 1. based on the pc-9800 series (japanese windows ? ) 2. based on the ibm pc/at and compatibles (japanese/english windows) 3. based on the hp9000 series 700 ? (hp-ux ? ) and sparcstation ? (sunos ? , solaris ? ) 4. products made by naito densei machida mfg. co., ltd. (044-822-3813). 5. product made by tokyo eletec corporation for further information, consult: tokyo electronic div. (tel 03-3820-7112) or osaka electronic div. (tel 06-6244-6672) daimaru kogyo corporation. remark the ra78k0s, cc78k0s, and sm78k0s are used in combination with the df789831.
data sheet u13477ej1v0ds 43 pd78f9831 appendix c related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789830 data sheet u13284e pd78f9831 data sheet this document pd789830 subseries user?s manual u13679e 78k/0s series user?s manual, instruction u11047e 78k/0, 78k/0s series flash memory writing u14458e documents related to development tools (user?s manuals) document name document no. operation u11622e language u11599e ra78k0s assembler package structured assembly language u11623e operation u11816e cc78k0s c compiler language u11817e sm78k0s, sm78k0 system simulator ver.2.10 or later windows based operation u14611e sm78k series system simulator ver.2.10 or later external part user open interface specifications to be created id78k0-ns, id78k0s-ns integrated debugger ver.2.20 or later windows based operation u14910e ie-78k0s-ns in-circuit emulator u13549e ie-789831-ns-em1 emulation board u14202e pg-fp3 flash memory programmer u13502e documents related to embedded software (user?s manuals) document name document no. 78k/0s series os mx78k0s fundamental u12938e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u13477ej1v0ds 44 pd78f9831 other related documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u13477ej1v0ds 45 pd78f9831 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip is a registered trademark of nec corporation. eeprom is a trademark of nec corporation. windows is a registered trademark or trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos and solaris are trademarks of sun microsystems, inc.
data sheet u13477ej1v0ds 46 pd78f9831 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
data sheet u13477ej1v0ds 47 pd78f9831 [memo]
pd78f9831 m8e 00. 4 the information in this document is current as of february, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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