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february 2007 rev 3 1/54 1 m65kg512ab 512mbit (4 banks x 8 mb x 16) 1.8 v supply, ddr low power sdram features 512mbit synchronous dynamic ram ? organized as 4 banks of 8 mwords, each 16 bits wide double data rate (ddr) ? 2 data transfers/clock cycle ? data rate: 332 mbit/s max. for 6ns speed class supply voltage ?v dd = 1.7 to 1.9 v (1.8 v typical in accordance with jedec standard) ?v ddq = 1.7 to 1.9 v for inputs/outputs synchronous burst read and write ? fixed burst lengths: 2-, 4-, 8-, 16 words ? burst types: sequential and interleaved. ? clock frequency: 133 mhz (7.5 ns speed class), 166 mhz (6 ns speed class) ? clock valid to output delay (cas latency): 3 at the maximum clock frequency ? burst read control by burst read terminate and precharge commands automatic precharge byte write controlled by ldqm and udqm low-power features ? partial array self refresh (pasr) ? automatic temperature compensated self refresh (atcsr) ? driver strength (ds) ? deep power-down mode ? auto refresh and self refresh lvcmos interface compat ible with multiplexed addressing operating temperature: ? ? 30 to 85 c ? ? 30 to 105 c the m65kg512ab is only available as part of a multi-chip package product. wafer www.st.com
contents m65kg526ab 2/54 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 column address strobe (cas ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 row address strobe (ras ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 clock inputs (k, k ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 lower/upper data input mask (ldqm, udqm) . . . . . . . . . . . . . . . . . . . . 10 2.11 lower/upper data read/write strobe input/output (ldqs, udqs) . . . . 10 2.12 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 mode register set command (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 extended mode register set command (emrs) . . . . . . . . . . . . . . . . . . . 12 3.3 bank(row) activate command (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 read command (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 read with auto precharge command (reada) . . . . . . . . . . . . . . . . . . . . 13 3.6 burst read terminate command (bst) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 write command (writ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 write with auto precharge command (writa) . . . . . . . . . . . . . . . . . . . . 14 3.9 precharge selected bank/precharge all banks command (pre/pall) . 14 3.10 self refresh entry command (self) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.11 self refresh exit command (selfx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
m65kg526ab contents 3/54 3.12 auto refresh command (ref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.13 power-down entry command (pden) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.14 power-down exit command (pdex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.15 deep power-down entry command (dpden) . . . . . . . . . . . . . . . . . . . . . 16 3.16 device deselect command (desl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.17 no operation command (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 extended mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
list of tables m65kg526ab 4/54 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bank selection using ba0-ba1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. minimum delay between two commands in concurrent auto precharge mode . . . . . . . . . 18 table 5. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. dc characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. dc characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. self refresh current (i dd6 ) in normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. ac characteristics - t j = -30 to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16. ac characteristics - t j = -30 to 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. ac characteristics measured in clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
m65kg526ab list of figures 5/54 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. simplified command state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 6. definition of command and address inputs timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. definition of read timings 1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. definition of read timings 2/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. consecutive bank(row) activate command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. read followed by read in same bank and row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. read followed by read in a different bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. read followed by auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14. read operation (burst lengths = 2, 4 and 8, cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. burst terminate during read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 16. write followed by write in same bank and row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. write followed by write in a different bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18. write operation with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. write with auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. write operation (burst lengths = 2, 4 and 8, cas latency = 1) . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. ac write ac waveforms (data masking using ldqm/udqm). . . . . . . . . . . . . . . . . . . . . . . 42 figure 22. mode register/extended mode register set commands ac waveforms . . . . . . . . . . . . . . 43 figure 23. read followed by write using the burst read terminate command (bst) . . . . . . . . . . . . 44 figure 24. write followed by read (write completed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 25. write followed by read in the same bank and row (write interrupted). . . . . . . . . . . . . . . 46 figure 26. power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 27. auto refresh command ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 28. self refresh entry and exit commands ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 29. deep power-down entry command ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 30. deep power-down exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
description m65kg526ab 6/54 1 description the m65kg512ab is a 512mbit double data rate (ddr) low power synchronous dram (lpsdram). the memory array is organized as 4 banks of 8,388,608 words of 16 bits each. the device achieves low power consumption and very high-speed data transfer using the 2- bit prefetch pipeline architecture that allows doubling the data input/output rate. command and address inputs are synchronized with the rising edge of the clock while data inputs/outputs are transferred on both edges of the system clock. the m65kg512ab is well suited for handheld battery powered applications like pdas, 2.5 and 3g mobile phones and handheld computers. the device architecture is illustrated in figure 2: functional block diagram . it uses burst mode to read and write data. it is capable of two, four, and eight-word, sequential and interleaved burst. to minimize current consumption during self refresh operations, the m65kg512ab includes three mechanisms configured via the extended mode register: automatic temperature compensated self refresh (atcsr) adapts the refresh frequency according to the operating temperature provided by a built-in temperature sensor. partial array self refresh (pasr) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. the deep power-down (dpd) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array. the device is programmable through two registers, the mode register and the extended mode register: the mode register is used to select the cas latency, the burst type (sequential, interleaved) and the burst length. for more details, refer to table 7: mode register definition , and to section 3.1: mode register set command (mrs) . partial array self refresh (pasr) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. the extended mode register is used to configure the low-power features (pasr, atcsr and driver strength) to reduce the current consumption during the self refresh operations. for more details, refer to table 8: extended mode register definition , and to section 3.2: extended mode register set command (emrs) .
m65kg526ab description 7/54 figure 1. logic diagram table 1. signal names a0-a12 address inputs ba0-ba1 bank select inputs dq0-dq15 data inputs/outputs k, k clock inputs ke clock enable input e chip enable input w write enable input ras row address strobe input cas column address strobe input udqm upper data input mask ldqm lower data input mask udqs upper data read/ write strobe i/o ldqs lower data read/write strobe i/o v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground ai12443 13 a0-a12 dq0-dq15 v dd m65kg512ab e cas v ss 16 ras v ddq ba0-ba1 2 k ke w v ssq udqm ldqm k udqs ldqs
description m65kg526ab 8/54 figure 2. functional block diagram extended mode register tcsr, pasr self refresh logic & timer internal row counter row pre- decoders k ke e ras cas w udqm/ldqm statemachine refresh column active bank select address registers address buffers 8 mb x 16 bank d 8 mb x 16 bank c 8 mb x 16 bank b 8 mb x 16 bank a row decoders row decoders row decoders row decoders memory cell array column decoders sense amp & i/o gate i/o buffer & logic dq0 dq15 ... ... ... column pre- decoders ... a0 a12 ba1 ba0 ... column add counter mode register cas latency data out control burst counter burst length ai12450 row active k clock generator udqs/ldqs
m65kg526ab signal descriptions 9/54 2 signal descriptions see figure 1: logic diagram , and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a12) the a0-a12 address inputs are used to select the row or column to be made active. if a row is selected, all thirteen, a0-a12 address inputs are used. if a column is selected, only the ten least significant address inputs, a0-a9, are used. in this latter case, a10 determines whether auto precharge is used: during a read or write operation: ? if a10 is high (set to ?1?), the read or write operation includes an auto precharge cycle. ? if a10 is low (set to ?0?), the read or write cycle does not include an auto precharge cycle. when issuing a precharge command: ? if a10 is low, only the bank sele cted by ba1-ba0 will be precharged. ? if a10 is high, all the banks will be precharged. the address inputs are latched at the cross point of k rising edge and k falling edge. 2.2 bank select address inputs (ba0-ba1) the banks select address inputs, ba0 and ba1, are used to select the bank to be made active (see table 2: bank selection using ba0-ba1 ). when selecting the addresses, the device must be enabled, the row address strobe, ras , must be low, v il , the column address strobe, cas , and w must be high, v ih . 2.3 data inputs/outputs (dq0-dq15) the data inputs/outputs output the data stored at the selected address during a read operation, or to input the data during a write operation. 2.4 chip enable (e ) the chip enable input, e , activates the memory state machine, address buffers and decoders when driven low, v il . when e is high, v ih , the device is not selected. 2.5 column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a0-a9 and ba1-ba0, to select the starting column location prior to a read or write operation.
signal descriptions m65kg526ab 10/54 2.6 row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a0-a12 and ba1-ba0, to select the starting address location prior to a read or write. 2.7 write enable (w ) the write enable input, w , controls writing. 2.8 clock inputs (k, k ) the clock signals, k and k , are the master clock inputs. all input signals except udqm/ldqm, udqs/ldqs and dq0-dq15 are referred to the cross point of k rising edge and k falling edge. during read operations, udqs /ldqs and dq0-dq15 are referred to the cross point of k rising edge and k falling edge. during write operations, udqm/ldqm and dq0-dq15 are referred to the cross point of udqs/ldqs and v ref, and udqs/ldqs to the cross point of k rising edge and k falling edge. 2.9 clock enable (ke) when driven low, v il , the clock enable input, ke, is used to suspend the clock k, to switch the device to self refresh, powe r-down or deep power-down mode. the clock enable, ke, must be stable for at least one clock cycle. this means that, if ke level changes on k rising edge and k falling edge with a setup time of t as , it must be at the same level by the next k rising edge with a hold time of t ah . 2.10 lower/upper data input mask (ldqm, udqm) lower data input mask and upper data input mask are input signals used to mask the data input during write operations. udqm and ldqm are sampled when udqs/ldqs level crosses v ref . when ldqm is low, v il , dq0 to dq7 inputs are selected. when udqm is low, v il , dq8 to dq15 inputs are selected. 2.11 lower/upper data read/write strobe input/output (ldqs, udqs) ldqs and udqs act as write data strobe (as input) and read data strobe (as output) respectively. ldqs and udqs are the strobe signals for dq0 to dq7 and dq8 to dq15, respectively. during read operations, the device outputs the data strobe through ldqs/udqs pins simultaneously with data (see figure 10 ). data is output at both the rising and falling edge of the data strobe. during write operations, ldqs/udqs should be input as the strobe for the input data together with ldqm/udqm (see figure 18 ). the inputs data should be synchronized with the high and low pulse of ldqs/udqs.
m65kg526ab signal descriptions 11/54 2.12 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read and write). 2.13 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently of v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid certain conditions that would result in data corruption. 2.14 v ss ground ground, v ss, is the reference for the core power supply. it must be connected to the system ground. 2.15 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inhere ntly low inductance capacitors should be as close as possible to the package). table 2. bank selection using ba0-ba1 selected bank ba0 ba1 bank a v il v il bank b v ih v il bank c v il v ih bank d v ih v ih
commands m65kg526ab 12/54 3 commands the m65kg512ab recognizes a set of commands that are obtained by specific statuses of chip enable, e , column address strobe, cas , row address strobe, ras , write enable, w , and address inputs. refer to table 3: commands , in conjunction with the text descriptions below. figure 3: simplified command state diagram shows the operations that are performed when each command is issued at each state of the ddr lpsdram. 3.1 mode register set command (mrs) the mode register set command is used to configure the burst length, burst type and cas latency of the device by programming the mode register. the command is issued with ke held high, with ba0, ba1 and a10 set to ?0?, and e , ras , cas and w driven low, v il . the value of address inputs a0 to a7 determines the burst length, burst type and cas latency of the device (see table 7: mode register definition and figure 22: mode register/extended mode register set commands ac waveforms ): the burst length (2, 4, 8, 16 words) is programmed using the address inputs a2-a0 the burst type (sequential or interleaved) is programmed using a3. the cas latency (3 clock cycles) is programmed using a6-a4. it is required to execute a mode register set command at the end of the power-up sequence. once the command has been issued, it is necessary to wait for at least two clock cycles before issuing another command. 3.2 extended mode register set command (emrs) the extended mode register set command is used to configure the low-power features of the device by programming the extended mode register. the command is issued with ke held high, ba0 at ?0?, ba1 at ?1?, a10 at ?0?, by driving e , ras , cas and w , low, v il . the value of address inputs a0 to a9 determines the driver strength, the part of the array that is refreshed during self refresh and the automatic temperature compensated self refresh feature (see table 8: extended mode register definition and figure 22: mode register/extended mode register set commands ac waveforms ): the part of the array to be refreshed (all banks, bank a and b, bank a only) during self refresh is set using a2-a0. the driver strength (full, 1/2 strength, 1/4 strength, 1/8 strength) is set using bits a6-a5 the automatic temperature compensated self refresh feature is always enabled (a9 set to ?0?). it is required to execute an extended mode register set command at the end of the power- up sequence. once the command has been issued, it is necessary to wait for at least two clock cycles before issuing another command.
m65kg526ab commands 13/54 3.3 bank(row) activate command (act) the bank(row) activate command is used to switch a row in a specific bank of the device from the idle to the active mode. the bank is selected by ba0 and ba1 and the row by a0 to a12 (see table 2: bank selection using ba0-ba1 ). this command is initiat ed by driving ke high, v ih , with e and ras low, v il, and cas and w high. a minimum delay of t rcd is required after issuing the bank (row) activate command prior to initiating read and write operations from and to the active bank. a minimum time of t rc is required between two bank(row) activate commands to the same bank (see figure 9: consecutive bank(row) activate command ). 3.4 read command (read) the read command is used to read from the memory array in burst read mode. in this mode, data is output in bursts synchronized with the cross points of the clock signals, k and k . the start address of the burst read is determined by the column address, a0 to a12, and the bank address, ba0-ba1, at the beginning of the burst read operation. a valid read command is initiated by driving e and cas low, v il , and w and ras high, v ih . 3.5 read with auto precharge command (reada) this command is identical to the read command except that a precharge is automatically performed at the end of the read operation. the precharge starts t rpd (burst length/2 clock periods) after the read with auto precharge command is input. a t ras(min) delay elapses between the bank (row) activate and the auto precharge commands. this lock-out mechanism allows a read with auto precharge command to be issued to a bank that has been activated (opened) but has not yet satisfied the t ras(min) requirement. the ddr lpsdram supports the concurrent auto precharge mode: a read with auto- precharge can be followed by any command to another active bank, as long as that command does not interrupt the read data transfer, and that all other related limitations apply (e.g. contention between read data and written data must be avoided). ta b l e 4 : minimum delay between two commands in concurrent auto precharge mode shows the minimum delays between a read with auto precharge command to one bank and a command to a different bank. refer to figure 13 for a description of read operation with auto precharge.
commands m65kg526ab 14/54 3.6 burst read terminate command (bst) the burst read terminate command is used to terminate a burst read operation. it is issued with ke held high, by driving e and w low and cas and ras high. t bstz after issuing the burst read terminate command, dq0-dq15 and ldqs, udqs revert to the high impedance state (see figure 15: burst terminate during read operation ). there is no such command for burst write operations. 3.7 write command (writ) this write command is used to write to the memory array in burst write mode. in this mode, data is input synchronized with the cross points of the clock signals, k and k . the start address of the burst write is determined by the column address, a0 to a9, and the address of the selected bank, ba0-ba1, at the beginning of the burst read operation. a valid write command is initiated by driving e , cas and w low, v il , and ras high, v ih . 3.8 write with auto precharge command (writa) this command is identical to the write command except that a precharge is automatically performed at the end of the write operation. the precharge starts t wpd (burst length/2 +3 clock periods) after the write with auto precharge command is input. refer to figure 19 for a description of write operation with auto precharge. 3.9 precharge selected bank/precharge all banks command (pre/pall) the precharge selected bank and precharge all banks are used to place the bank selected by ba0 and ba1 (see table 2: bank selection using ba0-ba1 ) and all banks in idle mode, respectively. the precharge commands are issued by driving e , ras and w low, with cas and ke held high. the value on a10 determines whether either the selected bank or all the banks will be precharged: if a10 is high, ba0-ba1 are don?t care and all the banks are precharged. if a10 is low when, only the bank selected by ba0-ba1 is precharged. the bank(s) is/are placed in the idle mode t rp after issuing the precharge command. once the bank is in idle mode, the bank (row) activate command has to be issued to switch the bank back to active mode. the precharge commands can be issued during burst read or burst write in which case the burst read or write operation is terminated and the selected bank placed in idle mode. the device needs to be in idle mode before entering self refresh, auto refresh, power- down and deep power-down.
m65kg526ab commands 15/54 3.10 self refresh en try command (self) the self refresh entry command is used to start a self refresh operation. before starting a self refresh, the device must be idle. the self refresh entry command is issued by driving ke low, with e , ras , and cas low, and w high (see figure 28: self refresh entry and exit commands ac waveforms ). during the self refresh operation, the internal memory controller generated the addresses of the row to be refreshed. the self refresh operation goes on as long as the clock enable signal, ke, is held low. 3.11 self refresh exit command (selfx) the self refresh exit command is used to exit from self refresh mode. there are two ways to exit from self refresh mode: driving ke low to high, with e high, ras , cas and w don?t care, driving e low and r as , cas and w high. non-read commands can be executed 3t ck + t rc after the end of the self refresh operation, where t ck is the clock period and t rc the ras cycle time. see figure 28 for a description of self refresh exit ac waveforms. 3.12 auto refresh command (ref) this command performs an auto refresh. the device is placed in auto refresh mode from idle by holding ke high, v ih , driving e , ras and cas low and driving w high. the address bits are ?don?t care? because the addresses of the bank and row to be refreshed are internally determined by the internal refresh controller. the output buffer becomes high-z after the auto refresh has started. precharge operations are automatically completed after the auto refresh. a bank(row) activate, a mode register set or an extended mode register set command can be issued t rfc after the last auto refresh command (see figure 27: auto refresh command ac waveforms ). the average refresh cycle is t ref (see table 16: ac characteristics - tj = -30 to 105 c ). to optimize the operation scheduling, a flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be issued to the ddr lpsdram and the maximum absolute interval between two auto refresh commands 8t ref . 3.13 power-down entry command (pden) the ddr lpsdram is caused to enter power-down mode from idle by driving either: ke low and e high (other signals are don?t care), ke low and ras , cas and w high with e low. the power-down mode continues as long as ke remains low.
commands m65kg526ab 16/54 3.14 power-down exit command (pdex) the ddr lpsdram exits from power- down mode by driving ke high. 3.15 deep power-down entry command (dpden) the device is placed in deep power-down mode by driving ke low, with e and w low and ras and cas high (see figure 29: deep power-down entry command ac waveforms ). all banks must be precharged or in idle state before entering the deep power-down mode. after the command execution, the device rema ins in deep power-do wn mode while ke is low. deep power-down exit (dpdex) the m65kg512ab exits deep power-down mode by asserting ke high. a special sequence is then required before the device can take any new command into account: 1. maintain no operation status conditions for a minimum of 200s, 2. issue a precharge all banks command (see section 3.9: precharge selected bank/precharge all banks command (pre/pall) for details), 3. once all banks are precharged and after the minimum t rp delay is satisfied, issue 2 or more auto refresh commands, 4. issue a mode register set command to initialize the mode register bits, 5. issue an extended mode register set command to initialize the extended mode register bits. the deep power-down mode exit sequence is illustrated in figure 30: deep power-down exit ac waveforms . 3.16 device desel ect command (desl) when the chip enable, e , is high at the cross point of the clock k rising edge with v ref , all input signals are ignored and the device internal status is held. 3.17 no operation command (nop) the device is placed in the no operation mode, by driving cas , ras and w high, with e low and ke high. as long as this command is input at the cross point of the clock k rising edge with the v ref level, address and data input are ignored and the device internal status is held.
m65kg526ab commands 17/54 table 3. commands (1)(2) command symbol ke n-1 ke n e ras cas w ba1 ba0 a0-a9, a11-a12 a10 mode register set mrs v ih v ih v il v il v il v il v il v il mr/emr data (3) v il extended mode register set emrs v ih mr/emr data (3) bank (row) activate act v ih v ih v il v il v ih v ih v v row address read read v ih v ih v il v ih v il v ih vv column address v il (4) read with auto precharge reada v ih (5) burst read terminate bst v ih v ih v il v ih v ih v il xx x write writ v ih v ih v il v ih v il v il v v column v il (4) write with auto precharge writa v ih (4) precharge selected bank pre v ih v ih v il v il v ih v il v (6) v (6) xv il (6) precharge all banks pall x (7) x (7) xv ih (7) self-refresh entry (8) self v ih v il v il v il v il v ih xx x x self refresh exit selfx v il v ih v ih xxx xx x v il v ih v ih v ih auto refresh (8) ref v ih v ih v il v il v il v ih xx x power-down entry (8) pden v ih v il v ih xxx xx x v il v ih v ih v ih power-down exit pdex v il v ih v ih xxx xx x v il v ih v ih v ih deep power-down entry (8) dpden v ih v il v il v ih v ih v il xx x deep power-down exit dpdex v il v ih xx x xx x x 1. x = don?t care (v il or v ih ); v = valid address input. 2. clock enable ke must be stable at least for one clock cycle. 3. mr and emr data is the value to be written in the mode register and extended mode register, respectively. 4. if a10 is low, v il , when issuing the command, the row remains active at the end of the operation. 5. if a10 is high, v ih , when issuing the command, an automatic precharge cycle is performed at the end of the operation and the row reverts to the idle mode. 6. if a10 is low, v il , when issuing the command, only the bank select ed by ba0-ba1 is precharged (ba0-ba1 should be valid). 7. if a10 is high, v ih , when issuing the command, all the banks are precharged and ba0-ba1 are don?t care. 8. all the banks must be idle before executing this command.
commands m65kg526ab 18/54 table 4. minimum delay between two commands in concurrent auto precharge mode from command to command minimum delay between the 2 commands in concurrent auto precharge mode (1) unit reada read or reada bl/2 t ck write or writea cas latency (rounded up) + bl/2 t ck pre or act 1 t ck writea read or reada 1 + bl/2 + t wtr t ck write or writea bl/2 t ck pre or act 1 t ck 1. bl = burst length. table 5. burst type definition start addr. (a0- a3) burst length = 2 words burst length = 4 words burst length = 8 words burst length = 16 words sequen- tial inter- leaved sequen- tial inter- leaved sequential interleaved sequential interleaved 00h 0-1 0-1 0-1-2-3 0-1-2-3 0- 1-2-3-4-5-6-7 0-1-2-3-4-5-6 -7 0-1-2-..d-e-f 0-1-2-..d-e-f 01h 1-0 1-0 1-2-3-0 1-0-3-2 1-2- 3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3..d-e-f-0 1-0-3-..c-f-e 02h 2-3-0-1 2-3-0-1 2-3-4-5- 6-7-0-1 2-3-0-1-6-7-4-5 2-3- 4..e-f-0-1 2-3-0- ..f-c-d 03h 3-0-1-2 3-2-1-0 3-4-5-6- 7-0-1-2 3-2-1-0-7-6-5-4 3- 4-5..f-0-1-2 3-2-1-..e-d-c 04h 4-5-6-7-0-1-2-3 4-5-6-7-0-1 -2-3 4-5-6..0-1-2-3 4-5-6-..9-a-b 05h 5-6-7-0-1-2-3-4 5-4-7-6-1-0 -3-2 5-6-7..1-2-3-4 5-4-7..8-b-a 06h 6-7-0-1-2-3-4-5 6-7-4-5-2-3 -0-1 6-7-8..2-3-4-5 6-7-4-..b-8-9 07h 7-0-1-2-3-4-5-6 7-6-5-4-3-2 -1-0 7-8-9..3-4-5-6 7-6-5-..a-9-8 08h 8-9-a..4-5-6-7 8-9-a..5-6-7 09h 9-a-b..5-6-7-8 9-8-a..4-7-6 0ah a-b-c..6-7-8-9 a-b-8..7-4-5 0bh b-c-d..7-8-9-a b-a-9..6-5-4 0ch c-d-e..8-9-a-b c-d-e..1-2-3 0dh d-e-f..9-a-b-c d-c-f..0-3-2 0eh e-f-0..a-b-c-d e-f-c..3-0-1 0fh f-0-1..b-c-d-e f-e-d..2-1-0
m65kg526ab commands 19/54 figure 3. simplified command state diagram ai11204b idle power-down deep power-down extended mode register set mode register set auto refresh self refresh row active active power-down read write reada writea precharge power-on automatic sequence manual input deep power-down exit sequence emrs mrs self self exit ref deep power-down exit sequence dpden pdex pden act pden pdex write read write read bst read pre write with auto precharge read with auto precharge pre (precharge termination) pre (precharge termination) precharge reada writea
operating modes m65kg526ab 20/54 4 operating modes there are 7 operating modes that control the memory. each of these is composed by a sequence of commands (see table 6: operating modes for a summary). 4.1 power-up the ddr lpsdram has to be powered up and initialized in a well determined manner: 1. after applying power to v dd and v ddq an initial pause of at least 200s is required before the signals can be toggled. 2. the precharge command must then be issued to all banks. until the command is issued ke and udqm /ldqm must be held high to make sure that dq0-dq15 remain high impedance. 3. t rp after precharging all the banks, the mode register and the extended mode register must be set by issuing a mode register set command and an extended mode register set command, respectively. a minimum pause of t mrd must be respected after each register set command. 4. after the two registers are configured, two or more auto refresh cycles must be executed before the device is ready for normal operation. the third and fourth steps can be swapped. refer to figure 26 for a detailed description of the power-up ac waveforms. 4.2 burst read the m65kg512ab is switched in burst read mode by issuing a bank (row) activate command to set the bank and row addresses to be read from, followed by a read command (see section 3.3: bank(row) activate command (act) and section 3.4: read command (read) for details). burst read can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the burst read command is issued, the burst read operation will be followed by an auto precharge cycle. if a10 is low (set to ?0?), the row will remain active for subsequent accesses. burst read operations are performed at word level only. different burst types (sequential or interleaved), burst lengths (2, 4, 8, and 16 words) can be programmed using the mode register bits. only a cas latency of 3 clock cycles is available. refer to section 5.1 , and to section 3.1: mode register set command (mrs) , for details on the mode register bits and how to program them. the burst read starts 2t ck + t ac after the clock k rising edge where the read command is latched, where t ck is the clock period and t ac is the access time from k or k . data strobe, udqs/ldqs, are output simultaneously with data. t rpre prior to the first rising edge of the data strobe, the udqs/ldqs signals go from high-z to low state. this low pulse is referred to as the read preamble. the burst data are then output synchronized with the rising and falling edge of the data strobe. udqs/ldqs become high-z on the next clock cycle after the burst read is completed. t rpst from the last falling ed ge of the data strobe, the dqs pins become high-z. this low peri od of dqs is referred as read postamble.
m65kg526ab operating modes 21/54 see ta b l e 5 , ta bl e 1 6 , ta bl e 1 7 , figure 12 and figure 14 , for a detailed description of burst read operation and characteristics. burst read can be terminated by issuing a burst read terminate command (see section 3.6: burst read terminate command (bst) and section figure 15.: burst terminate during read operation ). the interval between burst read to burst read and burst read to burst write commands are described in figure 10 , figure 11 and figure 23 . 4.3 burst write the m65kg512ab is switched in burst write mode by issuing a bank (row) activate command to set the bank and row addresses to be written to, followed by a write command (see section 3.3: bank(row) activate command (act) and section 3.7: write command (writ) for details). burst write can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the write command is issued, the write operation will be followed by an au to precharge cycle. if a10 is low (set to ?0?), auto precharge is not selected and the row will remain active for subsequent accesses. burst write operations can be performed either at byte or at word level. the cas latency for burst write operations is fixed to 1 clock cycle. udqs/ldqs input act as the strobe for the input data and udqm/ldqm select the byte to be written. udqs/ldqs must be low t wpre prior to their first rising edge; and can be changed to high-z t wpst after their last falling edge. these two periods of ti me are referred to as write preamble and write postamble, respectively. see ta bl e 1 6 , ta b l e 1 7 , figure 18 , figure 20 , and figure 21 , and for a detailed description of burst write ac waveforms and characteristics. the interval between burst write to burst write commands are described in figure 16 , figure 17 , figure 24 and figure 25 . 4.4 self refresh in the self refresh mode, the data contained in the ddr lpsdram memory array is retained and refreshed. the size of the memory array to be refreshed is programmed in the extended mode register. only the data contained in the part of the array selected for self refresh will be retained and refreshed. in this respect, this is a power saving feature. the self refresh mode is entered and exited by issuing a self refresh entry and self refresh exit command, respectively (see section 3: commands ). when in this mode, the device is not clocked any more. when the automatic temperature compensated self refresh mode (atcsr) is enabled, the internal refresh is adjusted according to die temperature in order to reduce power consumption.
operating modes m65kg526ab 22/54 4.5 auto refresh this command performs the auto refresh of the memory array. the bank and the row addresses to be refreshed are internally determined by the internal refresh controller. issuing an auto refresh command, caused the device to execute an auto refresh (see section 3: commands ). 4.6 power-down in power-down mode, the current is reduced to the active standby current (i dd3p ). the power-down mode is initiated by issuing a power-down entry command. t pden (1 clock cycle) after the cycle when this command wa s issued, the ddr lpsdram enters into power-down mode. in power-down mode, power consumption is reduced by deactivating the input initial circuit. there is no internal refresh when the device is in the power-down mode. the device can exit from power-down t pdex (1 cycle minimum) after issuing a power-down exit command. see section 3: commands for details on the power-down entry and exit commands. 4.7 deep power-down in deep power-down mode, the power consumption is reduced to the standby current (i dd7 ). before putting the device in the deep power-down mode all the banks must be idle or have been precharged. the deep power-down mode is entered and exited by issuing a deep power-down entry and a deep power-down exit command. see section 3: commands for details on the power-down entry and exit commands. table 6. operating modes (1) operating mode ken-1 ken e ras cas w a10 a10, a11 a0-a9 ba0-ba1 burst read v ih v ih v il v ih v il v ih v il (2) x start column address bank select burst write v ih v ih v il v ih v il v il v il (2) x start column address bank select self refresh v ih v il v il v il v il v ih xx auto refresh v ih v ih v il v il v il v ih xx power-down v ih v il v il v ih v ih v ih xx v ih xxx deep power-down v ih v il v il v ih v ih v il xx 1. x = don?t care v il or v ih . 2. if a10 = v il the burst read or write operation is not followed by an auto precharge cycle. if a10 = v ih , the burst read or write operation is followed by an auto prec harge cycle to the bank selected by ba0-ba1.
m65kg526ab registers description 23/54 5 registers description the ddr mobile ram has the two mode registers, the mode register and the extended mode register. 5.1 mode register description the mode register is used to select the cas latency, burst type, and burst length of the device: the cas latency defines the number of clock cycles afte r which the first data will be output during a burst read operation. the burst type specifies the or der in which the burst data will be addressed. this order is programmable either to sequential or interleaved (see table 5: burst type definition ). the burst length is the numb er of words that will be output or input during a burst read or write operation. it can be configured as 2, 4, 8, or 16 words. the mode register must be programmed at the end of the power-up sequence prior to issuing any command. it is loaded by issuing a section 3.1: mode register set command (mrs) , with ba0-ba1 are set to ?00? to select the mode register. table 7: mode register definition shows the available mode register configurations. table 7. mode register definition address bits mode register bit register description value description a12-a7 - - 000000 a6-a4 mr6-mr4 cas latency bits (read operations) 011 3 clock cycles other configurations reserved a3 mr3 burst type bit 0 sequential 1 interleaved a2-a0 mr2-mr0 burst length bit 001 2 words 010 4 words 011 8 words 100 16 words other configurations reserved ba1-ba0 - - 00
registers description m65kg526ab 24/54 5.2 extended mode re gister description the extended mode register is used to program the low-power self refresh operation of the device: partial array self refresh driver strength automatic temperature compensated self refresh. it is loaded by issuing a section 3.2: extended mode register set command (emrs) with ba0-ba1 set to ?01? to select the extended mode register. table 8: extended mode register definition shows the available extended mode register configurations. table 8. extended mode register definition address bits mode register bit description value description a12-a10 - - 000 a9 emr9 automatic temperature compensated self refresh bits 0 enabled 1reserved a8-a7 - - 00 a6-a5 emr6-emr5 driver strength bits 00 full strength 01 1/2 strength 10 1/4 strength 11 1/8 strength a4-a3 - - 00 a2-a0 emr2-emr0 partial array self refresh bits 000 all banks 001 bank a and bank b (ba1=0) 010 bank a (ba0 and ba1 =0) other configurations reserved ba1-ba0 - - 10
m65kg526ab maximum rating 25/54 6 maximum rating stressing the device above the ratings listed in table 9: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 9. absolute maximum ratings symbol parameter value unit min max t j junction temperature temperature range option 8 (1) ? 30 85 c temperature range option 9 (1) ? 30 105 c t stg storage temperature ? 55 125 c v io input or output voltage ? 0.5 2.3 v v dd , v ddq supply voltage ? 0.5 2.3 v i os short circuit output current 50 ma pd power dissipation 1.0 w 1. see table 18: ordering information scheme .
dc and ac parame ters m65kg526ab 26/54 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 10: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 10. operating and ac measurement conditions (1) 1. all voltages are referenced to v ss . symbol parameter m65kg512ab units min typ max v dd supply voltage 1.7 1.8 1.9 v v ddq (2) 2. v ddq must be equal to v dd . input/output supply voltage 1.7 1.8 1.9 v c l load capacitance 15 pf v il input pulses voltages 0.2 v v ih input pulses voltages 1.6 v v ref (3) 3. generated internally. input and output timing ref. voltages v ddq /2 v v id input differential voltage (k and k )1.4v v ix input differential cross point voltage (k and k )v ddq /2 with v dd =v ddq v t or ? v i / ? t r input signal slew rate 1 v/ns ai10238 v ddq output transition timing reference voltage 0v v ref clock timing reference voltage k v ref k input transition timing voltage ? t vih vil ? t input signal slew rate = vih - vil vix
m65kg526ab dc and ac parameters 27/54 figure 5. ac measurement load circuit ai12451 c l output table 11. capacitance symbol parameter signal m65kg512ab unit min max c i1 (1) input capacitance k, k 2.0 4.5 pf c i2 (1) all other input pins 2.0 4.5 pf c io (1)(2) data i/o capacitance dq0-dq15, udqs/ldqs, ldqm/udqm 3.5 6.0 pf c di1 (1) delta input capacitance k, k 0.25 pf c di2 (1) all other input pins 0.5 pf 1. t j = 25 c; v dd and v ddq = 1.7 to 1.9 v; f = 100 mhz; v out = v ddq /2; ? v out = 0.2 v. 2. data output are disabled. table 12. dc characteristics 1 symbol parameter test condition (1) m65kg512ab unit min max i li input leakage current 0v v in v ddq -2.0 2.0 a i lo output leakage current 0v v out v ddq , dq0-dq15 disabled. -1.5 1.5 a v ih (2) input high voltage v in = 0 v 0.8v ddq v ddq +0.3 v v il (3) input low voltage v in = 0 v -0.3 0.2v ddq v v ol output low voltage i out = 100 a 0.1v ddq v v oh output high voltage i out = ? 100 a 0.9v ddq v v in input voltage level for k and k inputs -0.3 v ddq +0.3 v ix input differential cross point voltage for k and k inputs 0.4v ddq 0.5v ddq 0.6v ddq v v id input differential voltage for k and k inputs 0.4v ddq v ddq +0.6 v 1. v dd and v ddq = 1.7 to 1.9 v; v ss and v ssq = 0 v. 2. v ih maximum value = 2.3 v (pulse width 5 ns). 3. v il minimum value = -0.5 v (pulse width 5 ns).
dc and ac parame ters m65kg526ab 28/54 table 13. dc characteristics 2 (1) symbol parameter test condition m65kg512ab unit ? 30 to 85c ? 85 to 105c max i dd1 (2) operating current burst length = 2, one bank active t rc t rc (min), i ol = 0 ma 133 mhz 70 75 ma 166 mhz 80 ma i dd2p precharge standby current in power-down mode ke v il (max), t ck = t ck(min) 0.8 1.4 ma i dd2ps ke v il (max), t ck = 0.6 1.2 i dd2n precharge standby current in non power- down mode ke v ih (min), e v ih (min), t ck = t ck(min) , input signals changed once in 2 clock cycles. 133 mhz 4.0 4.6 ma 166 mhz 5.0 6.0 i dd2ns ke v ih (min), t ck = , input signals are stable 2.0 2.6 i dd3p active standby current in power-down mode ke v il (max), t ck = t ck(min) 133 mhz 3.0 3.1 ma 166 mhz 3.0 4.0 i dd3ps ke v il (max), t ck = 1.2 1.8 i dd3n active standby current in non power-down mode ke v ih (min), e v ih (min), t ck = t ck(min) , input signals are changed once in 2 clock cycles. 10.0 ma i dd3ns ke v ih (min), t ck = , input signals are stable 7.0 i dd4 (2) burst mode current t ck t ck (min), i ol = 0 ma all banks active, burst length = 4 133 mhz 90.0 140 ma 166 mhz 180 ma i dd5 (3) auto refresh current t rrc t rrc (min) 90.0 ma i dd6 self refresh current ke 0.2 v see ta b l e 1 4 a i dd7 standby current in deep power-down mode ke 0 .2 v (see section 4.7: deep power- down ) 10 a 1. v dd and v ddq = 1.7 to 1.9v, v ss = v ssq = 0v. 2. i dd1 and i dd4 depend on output loading and cycle rates. specifi ed values are measured with the output open. 3. addresses change only once during t ck .
m65kg526ab dc and ac parameters 29/54 table 14. self refresh current (i dd6 ) in normal operating mode temperature in c memory array (1) unit all banks 2 banks 1 banks typmaxtypmaxtypmax 85 t j 105 2.2 1.2 0.8 a 70 t j 85 800 650 490 40 t j 70 550 380 290 ?30 t j 40 300 240 210 1. v dd and v ddq = 1.7 to 1.9 v, v ss = v ssq = 0v; ke 0.2 v. table 15. ac characteristics (1) - t j = ? 30 to 85 c symbol alt parameter m65kg512ab unit min max t ac (2) data output access time from k and k 2.0 6.0 ns t as (3) t is address and control input setup time 1.3 ns t ah (3) t ih address control input hold time 1.3 ns t ck clock cycle time 7.5 ns t dal autoprecharge write recovery and precharge time t wr +t rp ns t dqsck (2) udqs/ldqs access time from k and k 2.0 6.0 ns t dipw data output and ldqm/udqm inputs pulse width 1.75 ns t dqshz (4) udqs/ldqs high-z time from k and k 1.5 6.0 ns t dqslz (6) udqs/ldqs low-z time from k and k 1.5 6.0 ns t dqsq (3) udqs/ldqs to data output skew 0.65 ns t ds (3) data input and udqm/ldqm setup time 0.8 ns t dh (3) data input and udqm/ldqm hold time 0.8 ns t ipw addresses and control pulse width 3 ns t ohz (4) t hz data output high-z time from k and k 1.0 6.0 ns t olz (5) t lz data output low-z time from k and k 1.0 6.0 ns t qh data and ldqs/udqs output hold time from dqs t hp -t qhs ns t qhs data hold skew factor 0.75 ns t ras ras active time (bank (row) activa te to bank precharge) 45 120000 ns t rc ras cycle time (bank (row) activate to bank activate in auto refresh mode) 75 ns t rfc ras cycle time (auto refresh to bank active in auto refresh mode) 108 ns t rcd delay time, from ras active to cas active 30 ns t rrd delay time, from ras active to ras bank active 15 ns
dc and ac parame ters m65kg526ab 30/54 t rp ras precharge time 22.5 ns t ref average periodic refresh time 7.8 s t sre t srex self refresh exit time 165 ns t wpres write preamble setup time 0 ns 1. the above timings are meas ured according to the te st conditions shown in table 10: operating and ac measurement conditions with driver strength set to ?full strength? (emr5 to emr6 = ?00?). 2. these timings define the signal transition delays from k or k cross point, that is when k or k signal crosses v ref . 3. the timing reference level is v ref . 4. t ohz and t dqshz define the transition time from low-z to high-z of dq0-dq15 and udqs/ldqs, at the end of a burst read operation, respectively. they specify when data outputs stop being driven. 5. t olz and t dqslz define the transition time from high-z to low-z of dq0-dq15 and udqs/ldqs, at the end of a burst read operation. they specify when data outputs begin to be driven. table 15. ac characteristics (1) - t j = ? 30 to 85 c (continued) symbol alt parameter m65kg512ab unit min max table 16. ac characteristics (1) - t j = ? 30 to 105 c symbol alt parameter m65kg512ab unit 133mhz 166mhz min max min max t ac (2) data output access time from k and k 1.5 6.0 2.0 5.0 ns t as (3) t is address and control input setup time 1.4 1.4 ns t ah (3) t ih address control input hold time 1.4 1.4 ns t ck clock cycle time 7.5 6.0 ns t dqsck (2) udqs/ldqs access time from k and k 1.5 6.0 2.0 5.0 ns t dipw data output and ldqm/udqm inputs pulse width 1.8 1.75 ns t dqshz (4) udqs/ldqs high-z time from k and k 1.5 6.0 1.5 4.5 ns t dqslz (6) udqs/ldqs low-z time from k and k 1.5 6.0 1.5 4.5 ns t dqsq (3) udqs/ldqs to data output skew 0.65 0.5 ns t ds (3) data input and udqm/ldqm setup time 0.9 0.9 ns t dh (3) data input and udqm/ldqm hold time 0.9 0.9 ns t dal data input valid to precharge command 2t ck +22.5 t wr +t rp ns t ipw addresses and control pulse width 2.8 2.7 ns t ohz (4) t hz data output high-z from k and k 1.5 6.0 1.0 5.5 ns t olz (5) t lz data output low-z from k and k 1.5 6.0 1.0 5.5 ns t qh data and ldqs/udqs output hold time from dqs t hp -t qhs t hp -t qhs ns t qhs data hold skew factor 0.75 0.65 ns t ras ras active time (bank (row) activate to bank precharge) 60 120000 54 120000 ns
m65kg526ab dc and ac parameters 31/54 t rc ras cycle time (bank (row) activate to bank activate in auto refresh mode) 90 84 ns t rfc ras cycle time (auto refresh to bank active in auto refresh mode) 150 150 ns t rcd delay time, from ras active to cas active 37.5 36 ns t rrd delay time, from ras active to ras bank active 15 18 ns t rp ras precharge time 22.5 24 ns t ref average periodic refresh time t j = ? 30 to 85 c 7.8 7.8 s t j = 85 to 105 c 1.95 1.95 s t sre t srex self refresh exit time 165 165 ns t wpres write preamble setup time 0 0 ns 1. the above timings are meas ured according to the te st conditions shown in table 10: operating and ac measurement conditions with driver strength set to ?full strength? (emr5 to emr6 = ?00?). 2. these timings define the signal transition delays from k or k cross point, that is when k or k signal crosses v ref . 3. the timing reference level is v ref . 4. t ohz and t dqshz define the transition time from low-z to high-z of dq0-dq15 and udqs/ldqs, at the end of a burst read operation, respectively. they specif y when data outputs stop being driven. 5. t olz and t dqslz define the transition time from high-z to low-z of dq0-dq15 and udqs/ldqs, at the end of a burst read operation. they specify when data outputs begin to be driven. table 16. ac characteristics (1) - t j = ? 30 to 105 c (continued) symbol alt parameter m65kg512ab unit 133mhz 166mhz min max min max table 17. ac characteristics measured in clock period symbol alt parameter m65kg512ab unit 133mhz 166mhz min max min max t bstw (1) burst read terminate command to write command delay time 33t ck t bstz (1) burst read terminate command to data output hi-z 33t ck t chw t hp clock high pulse width 0.45 0.55 0.45 0.55 t ck t clw clock low pulse width 0.45 0.55 0.45 0.55 t ck t cke clock enable pulse width 2 2 t ck t dmd udqm/ldqm to data input latency 0 0 t ck t dsc ldqs/udqs cycle time 0.9 1.1 0.9 1.1 t ck t dqss write command to first udqs/ldqs latching transition 0.75 1.25 0.75 1.25 t ck
dc and ac parame ters m65kg526ab 32/54 t dss (4) udqs/ldqs falling edge to k setup time 0.2 0.2 t ck t dsh (4) udqs/ldqs falling edge hold time from k 0.2 0.2 t ck t dqsh udqs/ldqs high pulse width 0.35 0.35 t ck t dqsl udqs/ldqs low pulse width 0.35 0.35 t ck t dpe t pden power-down entry time 2 2 t ck t dpx t pdex power-down exit time 1 1 t ck t mrd mode register set cycle time 2 2 t ck t proz (1) t hzp precharge command to data output high-z 3 3 t ck t rpd delay time from read to precharge command (same bank) bl/2 (2) bl/2 (2) t ck t rwd delay time from read to write command (all data output) 3+bl/2 (2) 3+bl/2 (2) t ck t rpre read preamble time 0.9 1.1 0.9 1.1 t ck t rpst read postamble time 0.4 0.6 0.4 0.6 t ck t sre t srex self refresh exit time t j = ? 30 to 85 c 16 t ck t j = ? 30 to 105 c 22 27 t ck t wpd delay time from write to precharge command (same bank) 3+bl/2 (2) 3+bl/2 (3) t ck t wrd delay time from write to read command (all data input) 2+bl/2 (2) 2+bl/2 (2) t ck t wcd write command to da ta input latency 1 1 t ck t wr write recovery time t j = ? 30 to 85 c 2 t ck t j = ? 30 to 105 c 3 t ck t wtr internal write to read command delay t j = ? 30 to 85 c 1 t ck t j = ? 30 to 105 c 2 2 t ck t wpre write preamble 0.25 0.25 t ck t wpst (4) data strobe low pulse width (write postamble) 0.4 0.6 0.4 0.6 t ck 1. cas latency equals 3 clock cycles. 2. bl stands for burst length. 3. bl stands for burst length. 4. the transition for low-z to high-z occur when the device outputs become floating. no specific reference voltage is given in this document. table 17. ac characteristics measured in clock period (continued) symbol alt parameter m65kg512ab unit 133mhz 166mhz min max min max
m65kg526ab dc and ac parameters 33/54 figure 6. definition of command and address inputs timings figure 7. definition of read timings 1/2 figure 8. definition of read timings 2/2 k ai12455 k command (ras, cas, w, e) tas tah addresses k ai12456b k command read dq0-dq15 (output) hi-z tolz(min) tohz(max) udqs, ldqs hi-z hi-z tdqslz(max) tdqshz(min) tdqslz(min) tdqshz(max) tolz(max) tohz(min) k ai12457 k dq0-dq15 (output) hi-z udqs, ldqs hi-z hi-z tdqsck hi-z tac(min) tdqsq tac(max) tdsc tqh
dc and ac parame ters m65kg526ab 34/54 figure 9. consecutive bank(row) activate command 1. the above figure shows consecut ive bank(row) activate commands issued to different banks. a t rrd delay must be respected between two consecut ive bank(row) activate commands (act) to different banks. if the destination row is already active, the bank must be precharged to cl ose the row; the act command can then be issued t rp after the pre command. 2. consecutive act commands to the same bank must be issued at a t rc interval and separated by a precharge command (pre). figure 10. read followed by read in same bank and row 1. the consecutive read command must be issued after a minimum delay of t ck to interrupt the previous read operation. 2. to issue the consecutive read to a di fferent row, precharge the bank (pre) to interrupt the previous read operation. t rp after the pre command, issue the act command. the consecutive read command can be issued t rcd after the act command. ba0-ba1 row 0 address row 1 act act nop command k k ai11210 trrd pre trc bank a active nop act nop row 0 bank d active precharge bank a bank a active act read read command k k d oa0 d oa1 udqs, ldqs dq0-dq15 d ob0 d ob1 ai11205 note: 1. burst length = 4 2. cas latency = 3 3. bank = bank a nop row column b address ba0-ba1 nop t0 t1 t2 t3 t4 t5 t6 t7 t8 column a d ob2 bank a active read from column a data read from column a data read from column b d ob3 read from column b
m65kg526ab dc and ac parameters 35/54 figure 11. read followed by read in a different bank 1. if the consecutive read operation targets an active row, the second read command must be issued after a minimum delay of t ck to interrupt the previous read operation. 2. if the consecutive read operation targets an idle row, precha rge the bank (pre) without interrupting the previous read operation. t rp after the pre command, issue the act command. the consecutive read command can be issued t rcd after the act command. figure 12. read with auto precharge act act nop command k k d oa0 d oa1 udqs/ ldqs dq0-dq15 d ob0 d ob1 ai11206 note: 1. burst length = 4 2. cas latency = 3 row 0 address ba0-ba1 nop t0 t1 t2 t3 t4 t5 t6 t7 t8 row 1 d ob2 bank a active read from bank a data read from bank a data read from bank d d ob3 t9 t10 read read nop column a column b bank d active read from bank d read from column a read from column b act reada nop command k k d o0 d o1 udqs, ldqs dq0-dq15 d o2 d o3 ai10586 note: burst length = 2 trcd act trpd tras trp (min) tac tdqsck start of internal auto precharge cycle
dc and ac parame ters m65kg526ab 36/54 figure 13. read followed by auto precharge ac waveforms 1. burst length = 4 words, cas latency = 3 clock cycles. a10 dq0-dq15 k tck hi-z d o0 ai11212b w d o1 d o2 d o3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tas tah trcd tras trp trc bank(row) activate in bank a read from bank a precharge in bank a tac, tdqsck k ldqs/ udqs trpre trpst tas tah tas tah tas tah tdqslz tdqshz tdqsq tdv bank(row) activate in bank a
m65kg526ab dc and ac parameters 37/54 figure 14. read operation (burst lengths = 2, 4 and 8, cas latency = 3) figure 15. burst terminate during read operation nop act nop read nop command k k row address column address a0-a12 ba0-ba1 d o0 d o1 udqs, ldqs (1) dq0-dq15 (1) d o0 d o1 udqs, ldqs (2) dq0-dq15 (2) d o2 d o3 d o0 d o1 udqs, ldqs (2) dq0-dq15 (2) d o2 d o3 d o4 d o5 d o6 d o7 ai10552 notes: 1. burst length = 2 2. burst length = 4 3. burst length = 8. 4. in all cases, cas latency = 3. trpre trpst tac tdqsck t0 t1 t2 t3 t4 t5 t6 trcd command k k d o1 udqs, ldqs dq0-dq15 read bst nop t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 tbstz d o0 ai10585
dc and ac parame ters m65kg526ab 38/54 figure 16. write followed by write in same bank and row 1. the consecutive writ command must be issued after a minimum delay of t ck to interrupt the previous write operation. 2. to issue the consecutive write to a di fferent row, precharge the bank (pre) to interrupt the previous write operation. t rp after the pre command, issue the act command. the consecutive writ command can be issued t rcd after the act command. act writ writ command k k d ia0 d ia1 udqs, ldqs dq0-dq15 d ib0 d ib1 ai11207 note: 1. burst length = 4 2. bank = bank a nop row column b address ba0-ba1 nop t0 t1 t2 t3 t4 t5 t6 t7 t8 column a d ib2 bank a active data written to column a data written to column b d ib3
m65kg526ab dc and ac parameters 39/54 figure 17. write followed by write in a different bank 1. if the consecutive write operation target s an active row, the second writ command must be issued after a minimum delay of t ck to interrupt the previous write operation. 2. if the consecutive write operation targets an idle row, prec harge the bank (pre) without in terrupting the previous write operation. t rp after the pre command, issue the act command. the consecutive writ command can be issued t rcd after the act command. figure 18. write operation with auto precharge act act nop command k k d ia0 d ia1 udqs/ ldqs dq0-dq15 d ib0 d ib1 ai11208b note: 1. burst length = 4 row 0 address ba0-ba1 nop row 1 d ib2 bank a active data read from bank a data read from bank d d ib3 writ writ nop column a column b bank d active trcd act nop writea nop command k k d i0 d i1 udqs, ldqs dq0-dq15 d i2 d i3 ai10587c note: burst length = 4 twpd trcd act udqm, ldqm trp tras(min) start of internal auto precharge cycle
dc and ac parame ters m65kg526ab 40/54 figure 19. write with auto precharge ac waveforms 1. burst length = 4 words, cas latency = 1 clock cycle. a10 dq0-dq15 k tck hi-z d in ai11213d w d in+2 d in+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tas tah trcd tras trp trc bank a active write to bank a precharge in bank a k ldqs/ udqs tas tah tas tah tas tah tdqss tdh tds tdqsl twpst tdsh tdqsh twpre twr tdipw tdipw bank a active
m65kg526ab dc and ac parameters 41/54 figure 20. write operation (burst lengths = 2, 4 and 8, cas latency = 1) nop act nop write nop command k k row address column address a0-a12 ba0-ba1 d i0 d i1 udqs, ldqs (1) dq0-dq15 (1) d i0 d i1 udqs, ldqs (2) dq0-dq15 (2) d i2 d i3 d i0 d i1 udqs, ldqs (2) dq0-dq15 (2) d i2 d i3 d i4 d i5 d i6 d i7 ai10553 notes: 1. burst length = 2 2. burst length = 4 3. burst length = 8. 4. in all cases, cas latency = 1. twpre twpres twpst t0 t1 t2 t3 t4 t5 t6 trcd
dc and ac parame ters m65kg526ab 42/54 figure 21. ac write ac waveforms (data masking using ldqm/udqm) 1. burst length = 4 words. hi-z dq8-dq15 bank/row activate in bank d udqm a10 k hi-z ai11218b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 ke e ras cas ba0 ba1 address ldqm dq0-dq7 high read from bank d lower byte read upper byte read upper byte write lower byte write upper byte write read from bank d upper byte read upper byte read k tck tchw tclw tas tah tas tah tas tah tas tah ldqs/ udqs tdqss tdqsl twpst twpre
m65kg526ab dc and ac parameters 43/54 figure 22. mode register/extended mode register set commands ac waveforms 1. to program the extended mode register, ba0 and ba1 must be set to ?0? and ?1? respectively, and a0 to a11 to the extended mode register data. 2. mr data is the value to be written to the mode register. ba0-ba1 a10 dq0-dq15 (out) k hi-z ai11214b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas address ldqm/ udqm high tmrd mr data (2) trp precharge (optionnal) mode register set bank d active k ldqs/ udqs hi-z read to bank d precharge bank d
dc and ac parame ters m65kg526ab 44/54 figure 23. read followed by write usi ng the burst read terminate command (bst) 1. if the write operation is performed to the same bank and row than the read operation, the burst read terminate command (bst) must be issued to terminate the read operation.the writ command can then be issued t bstw (?t bstw ) after the bst command. 2. if the write operation is performed to the same bank but to a different row, the bank must be precharged to interrupt the read operation. t rp after the precharge command, issue the act comm and. the writ command can then be issued t rcd after the act command. 3. if the write operation is performed to a different bank and to an active row, the sequence is identical to the one described in note 1 4. if the write operation is performed to a different bank and to an idle row, the bank must be precharged independently from the read operation. t rp after the precharge command, issue the act command. the writ command can then be issued t rcd after the act command. command k k d o1 udqs, ldqs dq0-dq15 read bst nop t0 t1 t2 t3 t4 t5 tbstw ( tbstz) d o0 ai11209b t6 t7 t8 writ nop note: 1. burst length = 4 2. cas latency = 3 (cl) udqm, ldqm d i0 d i1 d i2 d i3 tbstz ( = cl) data output data input
m65kg526ab dc and ac parameters 45/54 figure 24. write followed by read (write completed) 1. if the read operation is performed to the same bank and row than the write operation, the read command should be performed t wrd after the writ command to complete the write operation. 2. if the read operation is performed to the same bank but to a different row, the bank must be precharged t wpd after the write operation. t rp after the precharge command, issue the act command. the read command can then be issued t rcd after the act command. 3. if the read operation is performed to a different bank and to an active row, the sequence is identical to the one described i n note 1 4. if the read operation is performed to a different bank and to an idle row, the bank must be precharged independently from the write operation. t rp after the precharge command, issue the act command. the writ command can then be issued t rcd after the act command. command k k d i1 udqs, ldqs dq0-dq15 writ nop t0 t1 t2 t3 t4 t5 twrdmin (3) d i0 ai10838b t6 t7 t8 read nop note: 1. burst length = 4 2. cas latency = 3 (cl) 3. twrd = bl/2 + 2 clock cycles udqm, ldqm d o0 d o1 d o2 data input data output d i2 d i3 d o3
dc and ac parame ters m65kg526ab 46/54 figure 25. write followed by read in the same bank and row (write interrupted) 1. udqm/ldqm must be input 1 clock cycle prior to the read command to prevent invalid data from being written. if the read command is input on the next cycle after th e writ command, udqm/ldqm are not necessary. 2. if the read operation is issued to a different row in the same bank, or to an idle row in a different bank, a precharge command (pre) must be issued before the read command. in th is case, the read operation does not interrupt the write operation. 3. if the read operation is issued to a differ ent bank, and to an active row, the sequence is identical to the one described in note 1 . command k k d i1 udqs, ldqs dq0-dq15 writ t0 t1 t2 t3 t4 t5 d i0 ai10839 t6 t7 t8 read nop note: 1. burst length = 4 2. cas latency = 3 (cl) udqm, ldqm d o0 d o1 d o2 data input masked data output d i2 d o3
m65kg526ab dc and ac parameters 47/54 figure 26. power-up sequence 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. mr data (1) a10 ai11211b w ke e ras cas ba0 ba1 address ldqm/ udqm hi-z dq0-dq15 bank(row) activate precharge all banks cbr auto refresh 1 clock cycle needed 2 refresh cycles needed emr data (1) high high mode register set extended mode register set cbr auto refresh tmrd tmrd trp trfc trfc k k
dc and ac parame ters m65kg526ab 48/54 figure 27. auto refresh command ac waveforms 1. burst length = 4 words, cas latency = 3 clock cycles. a10 k ai11215b w t0 t1 t2 t3 t4 t5 t6 tm tm+1 tm+2 tm+3 ke e ras cas ba0 ba1 address ldqm/ udqm tm+4 tm+5 tm+6 hi-z dq0-dq15 (out) precharge (optional) read from bank a tm+7 high auto refresh bank a active trp trfc k ldqs/ udqs hi-z tm+8 tm+9 hi-z dq0-dq15 (in)
m65kg526ab dc and ac parameters 49/54 figure 28. self refresh entry and exit commands ac waveforms 1. burst length = 4 words. a10 k w t0 t1 t2 t3 t4 tn+2 tm tm+1 tn+1 ke e ras cas ba0 ba1 address ldqm/ udqm dq0-dq15 (out) precharge (optional) tn self refresh entry self refresh exit bank a active trp tsre k t5 tm+2 tm+3 tm+4 tm+5 udqs/ ldqs dq0-dq15 (in) hi-z read to bank a ai11216c tas tah hi-z hi-z tcke
dc and ac parame ters m65kg526ab 50/54 figure 29. deep power-down entry command ac waveforms 1. ba0, ba1 and address bits a0 to a11 (exc ept a10) are ?don?t care?. upper and low er data input mask signals, udqm and ldqm are low, v il . a10 dq0-dq15 hi-z k ke e ras cas w ai10847b precharge all banks deep power-down entry t0 t1 t2 t3 t4 t5 trp k udqm/ ldqm low
m65kg526ab dc and ac parameters 51/54 figure 30. deep power-down exit ac waveforms 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. mr data (1) a10 k ai11217b w t0 t1 t2 t3 t4 t5 t6 t9 t10 t11 t12 t13 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address ldqm/ udqm t18 t19 t20 hi-z dq0-dq15 deep power-down exit bank/row activate t7 t21 precharge all banks auto refresh 1 clock cycle needed 2 refresh cycles needed emr data (1) high level nedeed high 200s mode register set extended mode register set auto refresh tmrd tmrd trp trfc trfc k
part numbering m65kg526ab 52/54 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 18. ordering information scheme example: m65kg512ab 8 w 8 device type m65 = low-power sdram architecture k = bare die operating voltage g = v dd = v ddq = 1.8 v, ddr lpsdram, x16 array organization 512 = 4 banks x 8 mbit x 16 number of chip enable inputs a = one chip enable die version b = b-die speed 8 = 7.5ns (clock frequency 133 mhz) 6 = 6.0ns (clock frequency 166 mhz) delivery form w = wafer form temperature range 8 = ? 30 to 85 c (1) 1. only available with speed class 133 mhz. 9 = ? 30 to 105 c
m65kg526ab revision history 53/54 9 revision history table 19. document revision history date revision changes 31-jan-2006 1.0 initial release. 04-sep-2006 2 speed class 166mhz added. temperature range ? 25 to 85c changed to ? 30 to 85c, and associated to speed class 7.5ns (133mhz). temperature range ? 30 to 105c added for both 6.0ns (166mhz) and 7.5ns (133mhz). figure 3: simplified command state diagram updated. ambient temperature t a changed to junction temperature t j . table 9: absolute maximum ratings , table 13: dc characteristics 2 , table 14: self refresh current (idd6) in normal operating mode , table 15: ac characteristics - tj = -30 to 85 c , table 16: ac characteristics - tj = -30 to 105 c , and table 17: ac characteristics measured in clock period , updated accordingly. figure 7 , figure 13 , figure 19 , figure 21 , figure 21 , figure 26 , figure 27 , figure 28 , figure 29 , and figure 30 updated. new speed classes and temperature range options added in table 18: ordering information scheme . 01-feb-2007 3 section 2.10: lower/upper data input mask (ldqm, udqm) and section 2.11: lower/upper data read/write strobe input/output (ldqs, udqs) modified. section 3.3: bank(row) ac tivate command (act) and section 3.5: read with auto precharge command (reada) updated. column address updated in section 3.7: write command (writ) , section 4.2: burst read and section 4.3: burst write . interval between auto refresh commands modified in section 3.12: auto refresh command (ref) . ta b l e 4 updated and note 1 removed. section 4.2: burst read , section 4.4: self refresh and section 4.5: auto refresh updated. t sre added in ta b l e 1 5 and ta b l e 1 6 . figure 17 , figure 18 , figure 21 , figure 23 , and figure 24 updated.
m65kg526ab 54/54 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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