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description the cxa1386p/k are 8-bit high-speed flash a/d converter ics capable of digitizing analog signals at the maximum rate of 75msps. the digital i/o levels of these a/d converters are compatible with the ecl 100k/10kh/10k. the cxa1386p/k is pin-compatible with the earlier models cxa1056p/k, cxa1016p/k, respectively. they can be replaced by the cxa1386p/k without any design changes, in most cases. compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout. features differential linearity error: 1/2lsb or less integral linearity error: 1/2lsb or less high-speed operation with maximum conversion rate of 75msps (min.) wide analog input bandwidth: 150mhz (min. for full-scale input) low power consumption: 580mw (typ.) single power supply: ?.2v low input capacitance: 17pf (typ.) built-in integral linearity conpensation circuit low error rate operable at 50% clock duty cycle good temperature characteristics capable of driving 50 ? loads pin configuration pins with name are nc pins (not connected). structure bipolar silicon monolithic ic applications digital oscilloscopes hdtv (high-definition tvs) other apparatus requiring high-speed a/d conversion ?1 cxa1386p/k e90114e33 8-bit 75msps flash a/d converter sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxa1386k 44 pin lcc (ceramic) cxa1386p 28 pin dip (plastic) 22 23 24 25 26 27 28 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 11 12 13 14 1 cxa1386p av ee clk v rt av ee agnd v in agnd v rm agnd v in agnd av ee v rb clk linv dv ee dv ee dgnd (lsb) d0 d1 d2 d3 d4 d5 d6 dgnd minv (msb) d7 (lsb) d0 8 9 10 11 12 13 14 15 16 17 cxa1386k 7 d1 d2 d3 d4 d5 d6 (msb) d7 dgnd2 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 39 40 41 42 43 44 1 2 3 4 5 6 av ee av ee v rb clk clk minv dv ee dgnd1 av ee av ee v rt av ee dgnd2 linv dv ee dgnd1 agnd v in agnd v rm agnd v in agnd
?2 cxa1386p/k absolute maximum ratings (ta = 25?) supply voltage av ee , dv ee ? to +0.5 v analog input voltage v in ?.7 to +0.5 v reference input voltage v rt , v rb , v rm ?.7 to +0.5 v i v rt ?v rb i2.5v digital input voltage clk, clk, minv, linv ? to +0.5 v i clk ?clk i 2.7 v v rm pin input current i vrm ? to +3 ma digital output current id 0 to id 7 ?0 to 0 ma storage temperature tstg ?5 to +150 ? recommended operating conditions min. typ. max. unit supply voltage av ee , dv ee ?.5 ?.2 ?.95 v av ee ?dv ee ?.05 0 +0.05 v agnd ?dgnd ?.05 0 +0.05 v reference input voltage v rt ?.1 0 +0.1 v v rb ?.2 ?.0 ?.8 v analog input voltage v in v rb v rt pulse width of clock t pw1 6.6 ns t pw0 6.6 ns operating temperature tc (cxa1386k) ?0 +100 ? ta (cxa1386p) ?0 +75 ?
?3 cxa1386p/k block diagram 255 126 127 128 129 191 192 193 254 63 64 65 1 2 clock driver r 3 r 1 r 2 r/2 r r r r r r r r r r r r r r r/2 d7 (msb) d6 d4 d3 d5 d2 d1 d0 (lsb) output encode logic minv v rt v in v rm v in v rb clk clk linv comparator
?4 cxa1386p/k pin description and i/o pin equivalent circuit anlog gnd. used as gnd for input buffers and latches of comparators. isolated from dgnd or dgnd 1/2. 19, 21, 23, 25 31, 33, 35, 37 agnd 0v 18, 26, 28 16 15 3, 12 dgnd 0v 22 clk 23 clk i ecl 27, 28, 40, 41, 44 av ee ?.2v analog v ee ?.2v (typ.). internally connected with dv ee (resistance: 4 to 6 ? ). ceramic chip capacitors of at least 0.1f should be used to connect to agnd and be placed near the pins. clk input input complementary to clk. with open connection, kept at threshold voltage (?.3v). device is operable without clk input, but use of complementary inputs of clk and clk is recommended to obtain the stable high- speed operation. digital gnd (used for internal circuits and output transistors) pin no dip lcc symbol i/o standard voltage level equivalent circuit description r r r r r r dgnd (dgnd1) clk clk dv ee 5, 19 dgnd1 0v digital gnd (used for internal circuits) 6, 16 dgnd2 0v digital gnd (used for output buffers)
?5 cxa1386p/k 2, 13 4, 20 dv ee ?.2v digital v ee internally connected with av ee (resistance: 4 to 6 ? ) ceramic chip capacitors of at least 0.1f should be used to connect to dgnd and be placed near the pins. lsb of data outputs. external pull-down resistor is required. data outputs. external pull-down resistors are required. msb of data outputs. external pull-down resistor is required. input pin for d0 (lsb) to d6 output polarity inversion (see output code table). with open connection, kept at "l" level. input pin for d7 (msb) output polarity inversion (see output code table). with open connection, kept at "l" level. 4 11 1 14 21 minv i ecl 3 linv i ecl 15 d7 5 6 7 8 9 10 9 10 11 12 13 14 d1 d2 d3 d4 d5 d6 8d0 o ecl dgnd (dgnd2) dv ee di r r r r linv or minv dv ee ?.3v dgnd (dgnd1) pin no dip lcc symbol i/o standard voltage level equivalent circuit description
?6 cxa1386p/k reference voltage (bottom) typically ?v a ceramic capacitor of at least 0.1f and a tantalus capacitor of at least 10f should be used to connect to agnd and be placed near the pins. reference voltage mid point be used as a pin for integral linearity compensation reference voltage (top) typically 0v when a voltage different from agnd is applied to this pin, a ceramic capacitor of at least 0.1f and a tantalus capacitor of at least 10f should be used to connect to agnd and be placed near the pins. unused pins no internal connections have been made to these pins. connecting them to agnd or dgnd on pc board is recommended. 17 22 27 1, 2, 7, 17, 18, 24, 25, 29, 30, 38 39, 43 nc 42 v rt i0v 34 v rm iv rb /2 26 v rb i ?v pin no. dip lcc symbol i/o standard voltage level equivalent circuit description comparator 1 comparator 2 comparator 127 comparator 128 comparator 129 comparator 130 comparator 255 r/2 r r r r r r r r/2 r 3 r 2 r 1 v rt v rm v rb analog input pins. these two pins must be connected externally, since they are not internally connected. see application note for precautions. 20, 24 32, 36 v in i v rt to v rb agnd av ee v in v in
?7 cxa1386p/k electrical characteristics (ta = 25?, av ee = dv ee = ?.2v, v rt = 0v, v rb = ?v) item resolution dc characteristics integral linearity error differential linearity error analg input analog input capacitance analog input resistance input bias current reference inputs reference resistance offset voltage v rt v rb digital inputs logic h level logic l level logic h current logic l current input capacitance switching characteristics maximum conversion rate aperture jitter sampling delay output delay h pulse width of clock l pulse width of clock digital outputs logic h level logic l level output rising time output falling time dynamic characteristics input bandwidth s/n ratio error rate differential gain error differential phase error power supply supply current power consumption ? 2 n e il e dl c in r in i in r ref e ot e ob v ih v il i ih i il fc taj tds tdo t pw1 t pw0 v oh v ol tr tf dg dp i ee pd fc = 75msps fc = 75msps v in = ?v + 0.07vrms v in = ?v input connected to ?.8v input connected to ?.6v error rate 10 ? tps ? 1 r l = 620 ? to dv ee r l = 620 ? to dv ee r l = 620 ? to dv ee , 20% to 80% r l = 620 ? to dv ee , 80% to 20% v in = 2vp-p input frequency at ?db input = 1mhz, fs clock = 75mhz input = 18.75mhz, fs clock = 75mhz input = 18.749mhz, fs error > 16lsb clock = 75mhz ntsc 40ire mod. ramp, fc = 75msps 75 8 0 ?.13 0 ?0 75 4.0 6.6 6.6 ?.03 150 ?50 8 ?.3 ?.3 17 390 110 18 10 7 10 3.0 6.5 0.9 2.1 46 40 1.0 0.5 ?04 580 0.5 0.5 200 155 32 24 ?.50 50 50 9.0 ?.62 10 ? bits lsb lsb pf k ? ? ? mv mv v v ? ? pf msps ps ns ns ns ns v v ns ns mhz db db tps ? 1 % deg ma mw symbol condition min. typ. max. unit { { } { ? 1 tps: times per sample ? 2 pd = i ee ?v ee + r ref (v rt ?v rb ) 2
?8 cxa1386p/k output code table v in ? 0v ?v ?v 0 1 127 128 254 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 : : 0 1 1 1 1 1 0 0 0 0 : : 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 : : 1 1 1 1 1 0 0 0 0 0 : : 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 : : 0 0 0 0 0 1 1 1 1 1 : : 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 : : 1 0 0 0 0 0 1 1 1 1 : : 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 step minv 1 linv 1 d7 d0 d7 d0 d7 d0 d7 d0 0 1 1 0 0 0 ? v rt = 0v, v rb = ?v timing diagram tds tr tf 80% 20% 80% n + 1 20% n n 1 tdo tpw0 tpw1 n + 1 n + 2 n analog input clk clk digital output
?9 cxa1386p/k electrical characteristics test circuit maximum conversion rate test circuit comparator a > b pulse counter cxa1386 p/k signal source ecl latch ecl latch 1/4 + signal source f clk 4 ?1khz 2vp-p sin w ave f clk v in clk clk 8 data 16 a b differential gain error test circuit differential phase error test circuit dut cxa1386 p/k ecl latch 10bit d/a vector scope delay amp ntsc signal source sg (cw) 50 clk clk 10 ? v in 8 8 v bb dg.dp (cx20202a-1) integral linearity error test circuit differential linearity error test circuit dut cxa1386 p/k a < b a > b comparator a8 to a1 a0 b8 to b1 b0 buffer controller dvm 8 8 8 "1" "0" 00000000 to 11111110 clk (75mhz) v in +v ? s2 s1 s1: on when a < b s2: on when a > b
?10 cxa1386p/k power supply current test circuit analog input bias current test circuit cxa1386p a a 22 23 24 25 26 27 28 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 11 12 13 14 1 i in i ee ?.2v ?v ?v 8 9 10 11 12 13 14 15 16 17 cxa1386k 7 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 39 40 41 42 43 44 1 2 3 4 5 6 ?v a ?v i in a i ee ?.2v sampling delay test circuit aperture jitter test circuit aperture jitter test method cxa1386 p/k osc1 : variable osc2 logic analizer 37.5mhz 37.5mhz amp ecl buffer clk v in 8 fr 1024 samples v in (lsb) clk v in clk t ? v ? t 0v ?v ?v 129 128 127 126 125 aperture jitter where (unit: lsb) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. taj = / = /( ), ? t ? 2 256 2 f aperture jitter is defined as follows:
?11 cxa1386p/k 8bit 75msps adc and dac evaluation board it is necessary to equip "the cxa1396d/p evaluation board with dac" with "a1396d ?a1386p adapter" in order to evaluate cxa1386p. in addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed dac, and the 20-pin cable connector for digital outputs. this evaluation board provides full performance of the cxa1386p and it is designed to facilitate evaluation. features resolution: 8bits maximum conversion rate: 75msps supply voltage: +5.0v, ?.2v, ?.0v two analog inputs (direct input, buffer amplifier input) clock level converter: sine wave to ecl level signal reference voltage adjustment circuit for the a/d converter built-in clock frequency decimation circuit: (1/1 to 1/16) fig. 1. block diagram buffer data latch linv minv v rb v rm vin clk cxa1386p vin offset decimator d/a converter vrb ?v sw3 clk sw1 sw2 l h ?.2v (a) ?.2v (a) v r2 (2k) v r1 (2k) amp.in dir.in clk 240 51 51 0.1 j1 a b c d v r3 (1k) 1k 8 8 8 (d 7 to d 0 ) digital out (connector) 8 (d 7 to d 0 ) 2 (clk.clk) clk d/a out 1/1 to 1/16 x (?) ?.2v (d) dgnd ?v (d) ?.2v (a) agnd +5v
?12 cxa1386p/k supply current item min. typ. max. unit ?.2v +5.0v ?.0v 0.85 15 0.45 1.0 30 0.6 a ma a ( note: supply current ?.0v is the value when rn10, rn11 and rn12 are not mounted.) analog input (dir. in, amp. in) item min. typ. max. unit input voltage (dir. in) (amp. in) ? 1 input impedance ?.0 ?.5 50 0 +0.5 v v ? ( ? 1 : adjustable by vr1) clock input (clk) item min. typ. max. unit input voltage (peak to peak) input impedance 2.0 50 vp-p ? digital output (d0 to d7) ecl 10kh level clock output ecl 10kh level, complementary output output code table v in 1 1 1 1 1 1 1 1 1 0 : : 1 0 0 0 0 0 1 1 1 1 : : 0 0 0 0 1 0 0 0 0 0 0v : : : : : : : : ?v 1 0 0 0 0 1 0 0 0 1 : : 1 1 1 1 1 0 0 0 0 0 : : 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 : : 0 0 0 0 0 1 1 1 1 1 : : 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 : : 0 1 1 1 1 1 0 0 0 0 : : 1 1 1 1 0 1 1 1 1 1 minv linv 0 1 0 0 1 0 1 1
?13 cxa1386p/k fig. 2. timing chart n 1 n n ?2 n ?1 n tdh 1.8ns (typ) tdh 1.8ns (typ) n n 2 n 4 n + 1 n a/d input pin pcb input pin a/d clock a/d output pcb output pin pcb output pin pcb output pin pcb output pin vin (dir. in, amp. in) clk clk clk d7 to d0 (for 1/1 frequency division) clkn clk (for 1/1 frequency division) d7 to d0 data out (for 1/2 frequency division) clkn clk (for 1/2 frequency division) adjustment methods and notes on operation 1) vin offset (vr1) the volume to adjust the signal range (0v center assumed) with the a/d converter input range when a waveform is input through amp. in. 2) a/d full scale (vr2) the volume to adjust a/d converter vrb voltage. 3) linearity (vr3) the volume to adjust vrm (linearity) voltage.
4) d/a full scale (vr4) the volume to adjust d/a output full scale (?v) 5) j1 (input selection) a: shorts to adjust vrm voltage. b: shorts to supply dc voltage to vin. c: shorts to select amp.in input. d: shorts to select dir. in input. 6) sw1 the switch for linv high/low 7) sw2 the switch for minv high/low 8) sw3 (decimation) the switch to select clock frequency decimation. switch position: decimation ratio 0: 1/1 1: 1/2 2: 1/4 3: 1/8 4: 1/16 9) sw4 (d/a inv) the switch for d/a converter output inversion. 10) rn10, rn11 and rn12 are not mounted at shipment. they are not required during evaluation. 11) waveform probe pins p5 and p8 through p28 are devised to facilitate gnd connection in order to reduce the distortion. as shown in the diagram below, the distance between the probe point and the gnd is 300 mils, and there is 1.2mm throughhole at each. the signal and gnd locations are suit for a tektronix gnd tip (part number 013-1185-00). 12) d/a converter (ic13) input data (waveform probe pins p21 through p28) are the complementary signals of the decimated a/d converter outputs. those are inverted again in the d/a converter so that the direction of reproduced waveform can agree with the a/d input signal converter. 13) the part number of the digital output connector is kel 8830e-020-170s. a corresponding connector and cable assembly is junkosha kb0020mcg50bi. ?14 cxa1386p/k [jumper poisition at shipment] j1 a b c d 1.2mm probe point gnd 300mil fig. 3.

?19 cxa1386p/k parts layout
?20 cxa1386p/k 1st layer component plane (top view) 4th layer solder plane (top view) printed pattern
?21 cxa1386p/k 2nd layer gnd plane (top view) 3rd layer power supply plane (top view)
?22 cxa1386p/k package outline unit: mm cxa1386p sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy dip-28p-03 dip028-p-0600 4.2g 28pin dip (plastic) 37.8 ?0.1 + 0.4 28 15 114 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 4.6 ?0.1 + 0.4 15.24 13.0 ?0.1 + 0.3 0.25 ?0.05 + 0.1 0 ? to 15 ? 1.all mat surface type. two kinds of package surface: 2.center part is mirror surface. lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy dip-28p-03 dip028-p-0600 4.2g 28pin dip (plastic) 37.8 ?0.1 + 0.4 28 15 114 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 4.6 ?0.1 + 0.4 15.24 13.0 ?0.1 + 0.3 0.25 ?0.05 + 0.1 0 ? to 15 ? 1.all mat surface type. two kinds of package surface: 2.center part is mirror surface.
?23 cxa1386p/k package outline unit: mm cxa1386k sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass ceramic gold plating package structure 44pin lcc (ceramic) 1.8g c1.016 c0.508 r0.2 12.7 0.1 + 0.35 16.51 ?0.25 1.27 0.1 1.905 0.25 12.5 0.2 0.3 1.651 0.18 1.951 0.25 1.27 0.635 0.07 pin no.1 index 2.159 0.5 lcc-44c-01 ? qfn044-c-s650-a 1.8g

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