1 lt 685 685fa resistance ( ? ) 100 200 500 1 hysteresis (mv) 10 100 1k 2k 5k 10k lt685 ?ta02 hysteresis is zero if pin left open features descriptio u applicatio s u typical applicatio u high speed comparator ultrafast (5.5ns typ) complementary ecl output 50 ? line driving capability low offset voltage output latch capability external hysteresis control pin compatible with am685 high speed a-to-d converters high speed sampling circuits oscillators the lt 685 is an ultrafast comparator with differential inputs and complementary outputs fully compatible with ecl logic levels. the output current capability is adequate for driving transmission lines terminated in 50 ? . the low input offset and high resolution make this comparator ideally suited for analog-to-digital signal processing applications. a latch function is provided to allow the comparator to be used in a sample-hold mode. when the latch enable input is ecl high, the comparator functions normally. when the latch enable is driven low, the comparator outputs are locked in their existing logical states. if the latch function is not used, the latch enable must be connected to ground or ecl high. the device is pin-compatible with the am685. hysteresis has been added to improve switching time with slow input signals as well as to minimize oscillation. a single resistor between the hysteresis pin and v adds input hysteresis voltage as more current is drawn. if hysteresis is not required, the pin can be left unconnected. , ltc and lt are registered trademarks of linear technology corporation. comparator with hysteresis hysteresis + l t685 6v ?.2v r r l v t r l gnd1 gnd2 q q hysteresis latch enable lt685 ?ta01 v + v v in
2 685fa lt 685 output current ...................................................... 30ma power dissipation (note 2) ................................ 500mw operating temperature lt685c ......................................... ?0 c t a 85 c lt685m (obsolete) ................. ?5 c t a 125 c positive supply voltage ............................................. 7v negative supply voltage .......................................... ?v input voltage ........................................................... 4v differential input voltage ......................................... 6v latch pin voltage .............................................. 2v to v hysteresis pin voltage ...................................... 0v to v (note 1) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. obsolete package consider the n16 package as an alternate source obsolete package consider the n16 package as an alternate source top view gnd #2 gnd #1 latch enable v 10 9 8 6 4 2 1 5 h package to-5 metal can 7 3 q output q output hysteresis inverting input noninverting input v + + j16 package (hermetic) 16-lead pdip n16 package 16-lead cerdip 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd #1 v + non-inverting input inverting input nc latch enable nc v gnd #2 nc nc nc q output q output nc hysteresis order part number order part number lt685ch lt685mh lt685cn order part number lt685cj lt685mj lt685 ?poi01
3 lt 685 685fa electrical characteristics l t685c lt685m symbol parameter conditions min typ max min typ max units v os input offset voltage t a = 25 c 1.0 2.0 1.0 2.0 mv 2.5 3.0 mv dv os /dt input offset voltage drift (note 3) 10 10 v/ c l os input offset current t a = 25 c 0.3 1.0 0.3 1.0 a 1.3 1.6 a i b input bias current t a = 25 c510 510 a 13 16 a r in input resistance t a = 25 c (note 3) 6.0 6.0 k ? c in input capacitance t a = 25 c (note 3) 3.0 3.0 pf v cm lnput voltage range 3.3 3.3 v cmrr common mode rejection 80 80 db svrr supply voltage rejection 70 70 db v oh output high voltage t a = 25 c 0.960 0.810 0.960 0.810 v t a = t min 1.060 0.890 1.100 0.920 v t a = t max 0.890 0.700 0.850 0.620 v v ol output low voltage t a = 25 c ?.850 ?.650 ?.850 ?.650 v t a = t min ?.890 ?.675 ?.910 ?.690 v t a = t max ?.825 ?.625 ?.810 ?.575 v i + positive supply current 22 22 ma i negative supply current 26 26 ma p diss power dissipation 300 300 mw v + = 6.0v, v = 5.2v, v t = ?v, r l = 50 ? , r = over the operating temp- erature ranges, unless otherwise noted.
4 685fa lt 685 l t685c lt685m symbol parameter conditions min typ max min typ max units t pd propagation delay t a = 25 c 4.5 5.5 6.5 4.5 5.5 6.5 ns (note 4) t a = t max 5.0 9.5 5.5 12 ns t a = t min 4.0 6.5 3.5 6.5 ns t pd(e) latch enable to t a = 25 c 4.5 5.5 6.5 4.5 5.5 6.5 ns output delay t a = t max 5.0 9.5 5.5 12 ns (note 3) t a = t min 4.0 6.5 3.5 6.5 ns t s minimum set-up time t min t a 25 c 3.0 3.0 ns (note 3) t a = t max 4.0 6.0 ns t h minimum hold time t min t a t max 1.0 1.0 ns (note 3) t pw(e) minimum latch enable t min t a 25 c 3.0 3.0 ns pulse width (note 3) t a = t max 4.0 5.0 ns (v in = 100mv step, 5mv overdrive) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: for the metal can package, derate at 6.8mw/ c for operation at ambient temperatures above 100 c; for the hermetic dual-in-line package, derate at 9mw/ c for operation at ambient temperatures above 105 c. note 3: guaranteed by design, but not tested. note 4: sample tested at 25 c only. definitions: t pd : the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of the output transition. t pd(e) : the propagation delay measured from the 50% point of the latch enable signal positive transition to the 50% point of the output transition. t s : the minimum time before the negative transition of the latch enable signal that an input signal change must be present in order to be acquired and held at the outputs. t h : the minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. t pw (e) : the minimum time that the latch enable signal must be high in order to acquire and hold an input signal change. switchi g characteristics u
5 lt 685 685fa sche atic diagra w w r2 300 ? r1 300 ? r6 525 ? r5 525 ? r7 275 ? r17 150 ? v v + r16 2.1k r15 2.1k r13 3.0k r20 3.8k r21 846 ? r3 1.4k r4 2.4k r19 2.4k r14 3k r18 150 ? r10 880 ? r12 200 ? r11 430 ? r8 275 ? q14 q13 q18 q1 q2 q17 q23 q output q output q21 q22 q25 q26 q28 q10 q5 q11 q12 q29 q16 q9 q8 noninverting input inverting input latch enable hysteresis q6 q7 d6 q15 q27 q24 q19 q20 gnd #2 d4 d1 d2 d3 d5 d7 d8 gnd #1 r23 1.7k q33 q4 q3 q31 q32 q30 r22 2.9k lt685 ?s01
6 685fa lt 685 typical perfor a ce characteristics uw u package descriptio h package 10-lead to-5 metal can (reference ltc dwg # 05-08-1322) obsolete package propagation delays as a function of temperature hysteresis as a function of temperature temperature ( c) ?0 2 propagation (ns) 6 12 0 50 75 ltc685 ?tpc01 4 10 8 ?5 25 100 125 v od = 2.5mv v od = 20mv v od = 5mv v od = 10mv temperature ( c) ?0 0 hysteresis (mv) 40 100 0 50 75 ltc685 ?tpc02 20 80 60 10 50 30 90 70 ?5 25 100 125 r = 200 ? r = 500 ? r = 1000 ? 0.050 (1.270) max 0.016 ?0.021** (0.406 ?0.533) 0.010 ?0.045* (0.254 ?1.143) seating plane 0.040 (1.016) max 0.165 ?0.185 (4.191 ?4.699) gauge plane reference plane 0.500 ?0.750 (12.700 ?19.050) 0.305 ?0.335 (7.747 ?8.509) 0.335 ?0.370 (8.509 ?9.398) dia 0.230 ( 5.842) typ 0.027 ?0.045 (0.686 ?1.143) 0.028 ?0.034 (0.711 ?0.864) 0.110 ?0.160 (2.794 ?4.064) insulating standoff 36 bsc h10(to-5) 1197 lead diameter is uncontrolled between the reference plane and 0.045" below the reference plane for solder dip lead finish, lead diameter is 0.016 ?0.024 (0.406 ?0.610) * ** pin 1
7 lt 685 685fa u package descriptio j16 1298 0.015 ?0.060 (0.380 ?1.520) 0.100 (2.54) bsc 0.014 ?0.026 (0.360 ?0.660) 0.045 ?0.065 (1.143 ?1.651) 0.200 (5.080) max 0.125 (3.175) min 0.008 ?0.018 (0.203 ?0.457) 0 ?15 1 23 4 5 6 78 0.220 ?0.310 (5.588 ?7.874) 0.840 (21.336) max 0.005 (0.127) min 16 13 9 10 11 12 14 15 0.025 (0.635) rad typ 0.300 bsc (0.762 bsc) 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) note: lead dimensions apply to solder dip/plate or tin plate leads j package 16-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) obsolete package information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8 685fa lt 685 linear technology corporation 1 630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com lw/tp 0902 1k rev a ?printed in usa ? l inear technology corporation 1988 u package descriptio n16 1098 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 (2.54) bsc 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 + 0.035 0.015 + 0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n package 16-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510)
|
