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1 features applications description pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 24-bit, 96-/192-khz, asynchronous, 4-channel/4-channel audio codec with 2-v rms driver, headphone driver, and 6 audio interface ports power-supply voltage: 234 2- or 2.4-v rms output (typ), 2-v rms input (typ) ? 9 v for 2-v rms driver asynchronous operation for 2 stereo dacs ? 3.3 v for digital and analog and 2 stereo adcs power consumption: 6 audio interface ports with mux and bypass ? 360 mw at f s = 48-khz operation performance: ? 25.5 m w in power-down mode ? thd+n (f s = 48 khz): pop noise reduction at clock halt 0.01% (adc), 0.01% (dac) short-circuit protection for headphone output ? snr/dr (f s = 48 khz): flexible gpio port: 95 db (adc), 100 db (dac) ? internal mute flag ? line input (stereo x6): ? internal zero flag available for 2-v rms input ? headphone insertion detection status ? line output (stereo x2): ? headphone short-circuit protection status available for 2-v rms or 2.4-v rms output ? logic functions (and, nand, or, nor, ? headphone output: buf, inv) > 20 mw into 32 ? , > 30 mw into 16 ? package: 64-pin htqfp powerpad? ? sampling rate: 96 khz (adc), 192 khz (dac) operating temperature range: ? 25 c to +85 c ? system clock: 128 f s , 192 f s , 256 f s , 384 f s , 512 f s , 768 f s digital tv ? digital filter passband ripple: dvd recorder 0.05 db (adc), 0.04 db (dac) ip-stb (set top box) ? digital filter stop band attenuation: ? 65 db (adc), ? 50 db (dac) i 2 c? interface the pcm5310 is a four-channel/four-channel audio multifunctions: codec with a 2-v rms driver, headphone amplifier, ? audio interface: analog multiplexer (mux), and six audio interface i 2 s?, left-justified, and right-justified ports for digital tv applications. ? digital attenuation: the pcm5310 accepts left-justified, right-justified, 0 db to ? 100 db in 0.5-db steps (dac), and i 2 s audio data formats with 16 or 24 bits. the 20 db to ? 100 db in 0.5-db steps (adc) pcm5310 also incorporates many functions through ? digital soft mute: 1.0-db steps to mute the i 2 c interface, such as an analog bypass mode, analog volume control, analog level control, analog ? digital de-emphasis filter: 32, 44.1, 48 khz multiplexer, gpio, zero flag, short protection, ? digital audio interface mux and bypass de-emphasis filter, high-pass filter, and digital ? line input level control: 9, 6, 3, 0 db attenuator. the six audio interface ports each have a built-in digital mux and bypass functions to reduce the ? line output level control: 0, ? 0.5, ? 1.0 db need for additional dsp ports or other devices. ? headphone output volume control: 12 db to ? 70 db in 1-db steps ? oversampling rate control for dac 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. 3 i2c, i2s are trademarks of nxp semiconductors. 4 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. pcm5310 burr-brown audio
packaging/ordering information absolute maximum ratings (1) recommended operating conditions pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted). parameter pcm5310 unit v ccda , v ccad , v ccp , v dd ? 0.3 to 4.0 v supply voltage v cch ? 0.3 to 10 v ground voltage differences: agndad, agndda, pgnd, hgnd, dgnd 0.1 v input voltage ? 0.3 to 4.0 v input current (all pins except supplies) 10 ma ambient temperature under bias ? 40 to +125 c storage temperature ? 55 to +150 c junction temperature +150 c lead temperature (soldering, 5s) +260 c package temperature (ir reflow, peak) +260 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted). parameter min nom max unit analog supply voltage, v ccad , v ccda , v ccp 3.0 3.3 3.6 v analog supply voltage, v cch 8.55 9 9.45 v digital supply voltage, v dd 3.0 3.3 3.6 v analog input voltage, full-scale ( ? 0 db) 2 v rms analog output voltage, full-scale ( ? 0 db) 2 2.4 v rms digital input logic family cmos adc system clock 4.096 36.864 mhz adc sampling clock 32 96 khz digital input clock frequency dac system clock 4.096 36.864 mhz dac sampling clock 32 192 khz analog output load resistance 10 k ? analog output load capacitance 30 pf digital output load capacitance 10 pf operating free-air temperature, t a ? 25 +85 c 2 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
electrical characteristics pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s (1) = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. pcm5310 parameter test conditions min typ max unit audio data data format audio data bit length 16, 24 bits audio data interface format i 2 s, left-justified, right-justified audio data format msb, twos complement adc 108 khz sampling frequency dac 216 khz adc 256 f s , 384 f s , 512 f s , 768 f s mhz system clock dac 128 f s , 192 f s , 256 f s , 384 f s , 512 f s , 768 f s mhz adc 48 f s , 64 f s mhz bit clock dac 32 f s , 48 f s , 64 f s mhz digital input/output logic family cmos-compatible v ih input logic high level 0.7 v dd v v il input logic low level 0.3 v dd v i ih input logic high current 10 m a i il input logic low current ? 10 m a v oh output logic high level i oh = 2 ma 0.75 v dd v v ol output logic low level i oh = ? 2 ma 0.25 v dd v dac line output dynamic performance digital input = 0 db, g242, g241 2 v rms = low full-scale output voltage digital input = 0 db, g242, g241 2.4 v rms = high dynamic range eiaj, a-weighted 90 100 db snr signal-to-noise ratio eiaj, a-weighted 90 100 db channel separation 88 97 db digital input = 0 db, g242, g241 thd+n total harmonic distortion + noise 0.01 0.02 % = low load resistance ac load 10 k ? dc accuracy digital input = 0 db, g242, g241 gain error 3 13 % of fsr = low gain mismatch, 3 13 % of fsr channel-to-channel bipolar zero error zero data input 40 120 mv center voltage zero data input 0.5 v ccda v analog gain control gain range 0, ? 0.5, ? 1.0 db gain error 0.5 db (1) f s = sampling rate. copyright ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com electrical characteristics (continued) all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. pcm5310 parameter test conditions min typ max unit dac headphone output dynamic performance full-scale output voltage digital input = 0 db, vol = 0db 1 v rms dynamic range eiaj, a-weighted 85 96 db snr signal-to-noise ratio eiaj, a-weighted 85 96 db channel separation r l = 32 ? 88 db r l = 32 ? , vol = 0 db 0.1 0.18 % thd+n total harmonic distortion + noise r l = 16 ? , vol = 0 db 1 3 % load resistance 16 ? dc accuracy gain error digital input = 0 db, vol = 0db 3 13 % of fsr gain mismatch, 3 13 % of fsr channel-to-channel bipolar zero error zero data input 27 80 mv center voltage zero data input 0.5 v ccda v analog volume gain range ? 70 12 db gain error 0.5 db gain step 1.0 db adc line input dynamic performance full-scale input voltage digital input = 0 db, vol = 0db 2 v rms dynamic range eiaj, a-weighted 85 95 db snr signal-to-noise ratio eiaj, a-weighted 85 95 db channel separation 93 db analog input = ? 1 db, vol = thd+n total harmonic distortion + noise 0.01 0.018 % 0db dc accuracy gain error analog input = 0 db, vol = 0db 3 13 % of fsr gain mismatch, 3 13 % of fsr channel-to-channel bipolar zero error zero data input 17 50 mv center voltage zero data input 0.5 v ccad v analog input input impedance 37.6 47 56.4 k ? analog gain control gain range 9, 6, 3, 0 db gain error 0.5 db 4 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 electrical characteristics (continued) all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. pcm5310 parameter test conditions min typ max unit analog input to analog output path (bypass) dynamic performance full-scale input voltage analog input = 0 db, vol = 0db 2 v rms analog input = 0 db, g242, full-scale output voltage 2 v rms g241 = low dynamic range eiaj, a-weighted 90 100 db snr signal-to-noise ratio eiaj, a-weighted 90 100 db channel separation 88 97 db analog input = 0 db, g242, thd+n total harmonic distortion + noise 0.003 0.006 % g241 = low dc accuracy analog input = 0 db, g242, gain error 3 13 % of fsr g241 = low gain mismatch, 3 13 % of fsr channel-to-channel bipolar zero error zero data input 20 60 mv analog input zero data input 0.5 v ccad v center voltage analog output zero data input 0.5 v ccda v analog input input impedance 37.6 47 56.4 k ? filters interpolation filters for dac passband 0.454 f s khz stop band 0.546 f s khz passband ripple 0.04 db stop-band attenuation ? 50 db group delay 20/f s s de-emphasis error 0.1 db analog filter for dac frequency response f c = 20 khz 0.1 db cutoff frequency gain = ? 3 db 190 khz decimation filter for adc passband 0.454 f s khz stop band 0.583 f s khz passband ripple 0.05 db stop-band attenuation ? 65 db group delay 17.4/f s s analog filter for adc frequency response f c = 20 khz 0.01 db cutoff frequency gain = ? 3 db 500 khz high-pass filter for adc frequency response gain = ? 3 db 0.91 hz copyright ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com electrical characteristics (continued) all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. pcm5310 parameter test conditions min typ max unit power-supply requirements v dd digital voltage range 3 3.3 3.6 v v ccad dac voltage range 3 3.3 3.6 v v ccda adc voltage range 3 3.3 3.6 v v ccp headphone driver voltage range 3 3.3 3.6 v v cch 2-v rms driver voltage range 8.55 9 9.45 v zero data input, all active 98 120 ma supply current all power-down 6 100 m a zaro data input, all active 360 450 mw power dissipation all power-down 25.5 350 m w temperature range operating temperature range ? 25 +85 c q ja thermal resistance htqfp-64 21 c/w 6 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
pin assignments pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 pap package htqfp-64 (top view) pin descriptions pin name no. i/o description ain1l 1 i line input 1 l-channel ain1r 2 i line input 1 r-channel ain2l 3 i line input 2 l-channel ain2r 4 i line input 2 r-channel ain3l 5 i line input 3 l-channel ain3r 6 i line input 3 r-channel ain4l 7 i line input 4 l-channel ain4r 8 i line input 4 r-channel ain5l 9 i line input 5 l-channel ain5r 10 i line input 5 r-channel ain6l 11 i line input 6 l-channel ain6r 12 i line input 6 r-channel lo1l 13 o line output 1 l-channel lo1r 14 o line output 1 r-channel lo2l 15 o line output 2 l-channel copyright ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): pcm5310 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 bck5sck5 data4 lrck4 bck4 sck4 dgnd vdd data3 lrck3 bck3 sck3 data2 lrck2 bck2 sck2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain1l ain1r ain2l ain2r ain3l ain3r ain4l ain4r ain5l ain5r ain6l ain6r lo1l lo1r lo2l lo2r vcomad hgnd vrefad2 vcch vref ad1 hpol agndad vccp vccad pgnd amute hpor rstb vccda gpio3 agndda gpio2 vcomda gpio1 agnds data6 sda lrck6 scl bck6 sck1 sck6 bck1 data5 lrck1 lrck5 da ta1 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 pcm5310 powerpad
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com pin descriptions (continued) pin name no. i/o description lo2r 16 o line output 2 r-channel hpol 19 o headphone output l-channel hpor 22 o headphone output r-channel vcomda 25 ? common voltage for dac vcomad 64 ? common voltage for adc vrefad1 62 ? reference voltage 1 for adc vrefad2 63 ? reference voltage 2 for adc vccad 60 ? power supply for adc (3.3-v typical) agndad 61 ? ground for adc vccda 23 ? power supply for dac (3.3-v typical) agndda 24 ? ground for dac vccp 20 ? power supply for headphone (3.3-v typical) pgnd 21 ? ground for headphone vdd 41 ? power supply for digital (3.3-v typical) dgnd 42 ? digital ground vcch 18 ? power supply for 2-v rms driver (9.0-v typical) hgnd 17 ? ground for 2-v rms driver agnds 26 ? analog ground sck1 29 i/o port-1 system clock bck1 30 i/o port-1 serial bit clock lrck1 31 i/o port-1 left and right channel clock data1 32 i/o port-1 serial audio data sck2 33 i/o port-2 system clock bck2 34 i/o port-2 serial bit clock lrck2 35 i/o port-2 left and right channel clock data2 36 i/o port-2 serial audio data sck3 37 i/o port-3 system clock bck3 38 i/o port-3 serial bit clock lrck3 39 i/o port-3 left and right channel clock data3 40 i/o port-3 serial audio data sck4 43 i/o port-4 system clock bck4 44 i/o port-4 serial bit clock lrck4 45 i/o port-4 left and right channel clock data4 46 i/o port-4 serial audio data sck5 47 i/o port-5 system clock bck5 48 i/o port-5 serial bit clock lrck5 49 i/o port-5 left and right channel clock data5 50 i/o port-5 serial audio data sck6 51 i/o port-6 system clock bck6 52 i/o port-6 serial bit clock lrck6 53 i/o port-6 left and right channel clock data6 54 i/o port-6 serial audio data scl 28 i clock for i 2 c interface sda 27 i/o data for i 2 c interface gpio1 55 i/o general-purpose input and output 1 gpio2 56 i/o general-purpose input and output 2 gpio3 57 i/o general-purpose input and output 3 rstb 58 i reset (active low) amute 59 i analog mute control for all analog outputs (active high) 8 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
functional block diagram pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 copyright ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): pcm5310 mux digital audio interface with mux and bypass vcom vref ain1l ain1 r ain2 l ain2 r ain3l ain3r ain4l ain4r ain5l ain5r ain6l ain6r power supply agnds dgndvdd pgnd vccp hgnd vcch agndda vccda agndad (vccad) sck6bck6 lrck6 data6 sck5bck5 lrck5 data5 sck4bck4 lrck4 da ta4 sck3bck3 lrck3 da ta3 sck2bck2 lrck2 da ta2 sck1bck1 lrck1 data1 sclsda gpio1gpio2 gpio3 rstb amute stereo dac mux lo1l lo1r lo2l lo2r hpol hpor vcomda vcomad refadn refadp hp hp i c gpio 2 decimation filter and high-pass filter (hpf) interpolation filter and de-emphasis stereo dac stereo adc stereo adc
typical characteristics: digital filter (dac) sharp, slow typical characteristics: analog filter (dac) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. frequency response frequency response, passband (0 f s to 4 f s ) (0 f s to 0.5 f s ) figure 1. figure 2. all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. frequency response frequency response (0 hz to 10 mhz) (0 hz to 100 khz) figure 3. figure 4. 10 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0 0.1 0.2 0.3 0.4 0.5 normalized frequency (x f ) s amplitude (db) - 160 - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0 1 2 3 4 normalized frequency (x f ) s amplitude (db) - 100 - 80 - 60 - 40 - 20 0 1 100 10 10 k 100 k 1 k 1 m 10 m frequency (hz) amplitude (db) - 2 - 1 0 1 2 1 10 100 1 k 10 k 100 k frequency (hz) amplitude (db)
typical characteristics: digital filter (adc) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. frequency response frequency response, passband (0 f s to 32 f s ) (0 f s to 0.5 f s ) figure 5. figure 6. high-pass filter response high-pass filter response (0 f s to 0.4 f s ) (0 f s to 0.1 f s ) figure 7. figure 8. copyright ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): pcm5310 - 160 - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0 4 8 12 16 20 24 28 32 normalized frequency (x f ) s amplitude (db) - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0 0.1 0.2 0.3 0.4 0.5 normalized frequency (x f ) s amplitude (db) - 50 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 0.1 0.2 0.3 0.4 normalized frequency (x f ) s amplitude (db) - 50 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 0.02 0.04 0.06 0.08 0.10 normalized frequency (x f ) s amplitude (db)
typical characteristics: analog performance (dac) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. total harmonic distortion + noise signal-to-noise ratio and data rate vs v cc supply voltage vs v cc supply voltage figure 9. figure 10. total harmonic distortion + noise signal-to-noise ratio and data rate vs temperature vs temperature figure 11. figure 12. 12 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 0.001 0.01 0.1 3.0 3.3 3.6 v (v) cc thd+n (%) thd+n_48(%) thd+n_96(%) thd+n_192(%) 85 90 95 100 105 110 3.0 3.3 3.6 snr, dr (db) snr_48(db) snr_96(db) snr_192(db) dr_48(db) dr_96(db) dr_192(db) v (v) cc 0.001 0.01 0.1 - 25 0 25 50 75 100 temperature ( c) thd+n (%) thd+n_48(%) thd+n_96(%) thd+n_192(%) 85 90 95 100 105 110 - 25 0 25 50 75 100 temperature ( c) snr, dr (db) snr_48(db) snr_96(db) snr_192(db) dr_48(db) dr_96(db) dr_192(db)
typical characteristics: analog performance (adc) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. total harmonic distortion + noise signal-to-noise ratio and data rate vs v cc supply voltage vs v cc supply voltage figure 13. figure 14. total harmonic distortion + noise signal-to-noise ratio and data rate vs temperature vs temperature figure 15. figure 16. copyright ? 2009, texas instruments incorporated submit documentation feedback 13 product folder link(s): pcm5310 0.001 0.01 0.1 3.0 3.3 3.6 v (v) cc thd+n_48(%) thd+n_96(%) thd+n (%) 85 90 95 100 105 110 3.0 3.3 3.6 v (v) cc snr, dr (db) snr_48(db) snr_96(db) dr_48(db) dr_96(db) 0.001 0.01 0.1 - 25 0 25 50 75 100 temperature ( c) thd+n (%) thd+n_48(%) thd+n_96(%) 85 90 95 100 105 110 - 25 0 25 50 75 100 temperature ( c) snr, dr (db) snr_48(db) snr_96(db) dr_48(db) dr_96(db)
typical characteristics: analog performance (headphone) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. total harmonic distortion + noise total harmonic distortion + noise vs output power vs output power (48 khz, 16 ? ) (48 khz, 32 ? ) figure 17. figure 18. total harmonic distortion + noise total harmonic distortion + noise vs output power vs output power (48 khz, 0 db, 6 db, 12 db, 16 ? ) (48 khz, 0 db, 6 db, 12 db, 32 ? ) figure 19. figure 20. 14 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 0.01 0.1 1 10 100 10 20 30 40 50 60 output power (mw) thd+n (%) thd+n_3v(%) thd+n_3.3v(%) thd+n_3.6v(%) 0.01 0.1 1 10 100 10 20 30 40 50 60 70 80 90 100 output power (mw) thd+n (%) thd+n_3v(%) thd+n_3.3v(%) thd+n_3.6v(%) 0.01 0.1 1 10 10 20 30 40 50 60 70 output power (mw) thd+n (%) thd+n_0db(%) thd+n_6db(%) thd+n_12db(%) 0.01 0.1 1 10 10 15 20 25 30 35 40 output power (mw) thd+n (%) thd+n_0db(%) thd+n_6db(%) thd+n_12db(%)
typical characteristics: output spectrum (dac) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. amplitude vs frequency amplitude vs frequency (0 db, 0 khz to 20 khz) ( ? 60 db, 0 khz to 20 khz) figure 21. figure 22. amplitude vs frequency amplitude vs frequency (zero data input, 0 khz to 20 khz) (zero data input, 0 khz to 130 khz) figure 23. figure 24. copyright ? 2009, texas instruments incorporated submit documentation feedback 15 product folder link(s): pcm5310 - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0 5 10 15 20 frequency (khz) amplitude (db) - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0 5 10 15 20 frequency (khz) amplitude (db) - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0 5 10 15 20 frequency (khz) amplitude (db) - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 20 0 20 40 60 80 100 120 frequency (khz) amplitude (db)
typical characteristics: output spectrum (adc) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com all specifications at t a = +25 c, v dd = v ccad = v ccda = v ccp = 3.3 v, v cch = 9 v, f s = 48 khz, system clock = 256 f s , and 24-bit data, unless otherwise noted. amplitude vs frequency amplitude vs frequency (0 db, 0 khz to 20 khz) ( ? 60 db, 0 khz to 20 khz) figure 25. figure 26. amplitude vs frequency (zero data input, 0 khz to 20 khz) figure 27. 16 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 20 0 5 10 15 20 frequency (khz) amplitude (db) - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 20 0 5 10 15 20 frequency (khz) amplitude (db) - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 20 0 5 10 15 20 frequency (khz) amplitude (db)
detailed description analog inputs pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 includes a four-channel analog-to-digital converter (adc) with a programmable gain amplifier (pga) and six stereo analog inputs with a 2-v rms input. pins ain1l/1r to ain6l/6r are connected to the adc left (l) or right (r) channel through the analog multiplexer (mux) and pga, as shown in figure 28 . if the analog input voltage level is less than 2 v rms , it can be amplified by using the pga. the gain level can be set to 9 db, 6 db, or 3 db. the descriptions for the analog input registers are shown in table 1 . figure 28. analog inputs table 1. analog input registers register description register number register bits analog input mux selection for adc1l/1r 20 ax1r[2:0], ax1l[2:0] analog input mux selection for adc2l/2r 21 ax2r[2:0], ax2l[2:0] analog input gain control for adc1l/1rw 22 ag1r[1:0], ag1l[1:0] analog input gain control for adc2l/2r 23 ag2r[1:0], ag2l[1:0] copyright ? 2009, texas instruments incorporated submit documentation feedback 17 product folder link(s): pcm5310 1l -mux 1r-mux 2l -mux 2r-mux pga-ad2l pga-ad1l pga-ad1rpga-ad2r adc-1l adc-1r adc-2l adc-2r ain1lain2l ain3l ain4l ain5l ain6l ain1r ain2r ain3r ain4r ain5r ain6r
analog outputs pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the pcm5310 includes a four-channel digital-to-analog converter (dac), two stereo line outputs with analog level control, a headphone output with analog volume control, and an analog multiplexer (mux) with analog direct input path. line outputs (lo1l, lo1r, lo2l, lo2r) have a 2-v rms capability without external amplifiers. if an audio application requires a higher output voltage level, the pcm5310 can achieve a 2.4-v rms output. the headphone output (hpol, hpor) has a driving capability of more than 30 mw of output power into a 16- ? load at 0.1% thd, and an analog volume with zero crossing that can be controlled from ? 70 db to 12 db. for audio applications that require it, the analog volume for the the l- and r-channels can be set simultaneously using the headphone output update control. the line outputs and headphone output can select analog input sources from all the analog inputs and each dac channel, as shown in figure 29 . the descriptions for the analog output registers are shown in table 2 . figure 29. analog outputs table 2. analog output registers register description register number register bits gain level control for line outputs 27 gl2r[1:0], gl2l[1:0], gl1r[1:0], gl1l[1:0] 2.0 v rms or 2.4 v rms selection for line outputs 28 g242, g241 headphone volume zero crossing update control 30 hupe, hsur, hsul, hzrs headphone output volume level setting 31, 32 hmul, hmur, hvol[6:0], hvor[6:0] analog output mux selection for line output 1 24 al1r[3:0], al1l[3:0] analog output mux selection for line output 2 25 al2r[3:0], al2l[3:0] analog output mux selection for headphone output 26 ahpr[3:0], ahpl[3:0] 18 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 dac-1l mux - l o1l pga-l01l ain1lain2l ain3l ain4l ain5l ain6l ain1rain2r ain3r ain4r ain5r ain6r pga-l01r pga-l02l pga-l02r pga-hpol pga-hpor dac-1r dac-2l dac-2r hp hp mux - l o1r mux - l o2l mux - l o2r mux-hpol mux-hpor
system clock input, output, and f s automatic detection pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 has six system clock input ports: sck1, sck2, sck3, sck4, sck5, and sck6. each input port can receive an independent clock at various frequencies. these ports are used for the internal clock of the digital filters and delta-sigma modulators, which are combined into a single common audio clock. the pcm5310 automatically detects the input clock rate at 128 f s , 192 f s , 256 f s , 384 f s , 512 f s or 768 f s (where f s is the audio sampling rate); if necessary, automatic clock rate detection can be disabled. the descriptions for the system clock input, output, and f s automatic detection registers are shown in table 3 . table 4 shows the frequency of the common audio clock. figure 30 and table 5 shows the timing requirements for the system clock input. table 3. system clock input, output, and f s automatic detection registers register description register number register bits master or slave with f s detection for dac12 44 dms12[3:0] audio interface format for dac12 44 dfm12[1:0] master or slave with f s detection for dac34 54 dms34[3:0] audio interface format for dac34 54 dfm34[1:0] master or slave with f s detection for adc12 84 ams12[3:0] audio interface format for adc12 84 afm12[1:0] master or slave with f s detection for adc34 94 ams34[3:0] audio interface format for adc34 94 afm34[1:0] sck6 clock output selection 07 psc6[2:0] table 4. system clock frequencies for the common audio clock sampling system clock frequency (mhz) frequency (khz) 128 f s (1) 192 f s (1) 256 f s 384 f s 512 f s 768 f s 32 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 44.1 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688 48 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 88.2 11.2896 16.9344 22.5792 33.8688 not supported not supported 96 12.2880 18.4320 24.5760 36.8640 not supported not supported 176.4 (1) 22.5792 33.8688 not supported not supported not supported not supported 192 (1) 24.5760 36.8640 not supported not supported not supported not supported (1) this sampling frequency and system clock frequency are supported only for the dac. figure 30. system clock input timing table 5. timing characteristics for figure 30 parameter min max unit t scy system clock cycle time 25 ns t sch system clock high time 0.4 t scy ns t scl system clock low time 0.4 t scy ns system clock duty cycle 40 60 % copyright ? 2009, texas instruments incorporated submit documentation feedback 19 product folder link(s): pcm5310 sck1 to 6 low high 0.8 v 2.0 v t scl t sch t scy
power on/off reset pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the power-on reset (por) circuit generates a reset signal at typically 2.2 v; this circuit does not depend on the other power supplies: v ccda , v ccad , v cch , and v ccp . the internal circuit is cleared to default status, then all analog and digital outputs have no signal. it is recommended to turn the device on and off as shown in figure 31 , in order to avoid loud, audible pop noises when powering the device on or off. (1) rstb is active low. 100 ns (minimum) is needed for an effective reset to the internal circuit. figure 31. power on/off reset 20 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 vdd power-on reset 2.2 v typical (1.6 v to 2.8 v) 0 s (min) rstb i c setting 2 1 ms (min) power-up for adcs and dacs (1) sckx internal reset for adcs and dacs clock input 1.6 v typical (1.0 v to 2.0 v) clock input clock input i c setting is effective 2 1024 clocks
register reset and system reset (register 01) rstb control pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 register reset (mrst) clears all register data to the default setting. the mrst register is automatically set to '1' after the reset. system reset (srst) clears all internal circuits, including all register data, to default status simultaneously. the srst register is automatically set to '1' after the reset. note that the pcm5310 may have audible pop noises on the analog and digital outputs when enabling mrst and srst. the descriptions for the register reset and system reset registers are shown in table 6 . table 6. reset registers register description register number register bits reset register data only 01 mrst reset for all circuits including register data 01 srst taking rstb (pin 58) from high to low clears all internal circuits to default status. if an application does not require reset control, rstb should be connected with an rc passive delay circuit to the digital power supply (v dd ). note that the pcm5310 may have audible pop noises on the analog and digital outputs when enabling rstb. the rstb control status descriptions are shown in table 6 . table 7. rstb control rstb (pin 58) status description low reset all circuits including register data high reset release copyright ? 2009, texas instruments incorporated submit documentation feedback 21 product folder link(s): pcm5310
power-supply sequence and power on/off sequence pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com in order to reduce audible pop noise, a register setting sequence is required after turning on all power supplies and before turning off all power supplies. any modules that are not used in the application or system should be powered down after the recommended power-on sequence. before the power-off sequence, all modules should be in a power-on state. the recommended power-supply sequence is shown in figure 32 . the recommended register settings are shown in table 8 and table 9 . (1) ramp up/down time for the analog output can be changed through the register setting (see register 18, pdtm[2:0]). (2) a 1.0- m f capacitor should be connected to the vcomad and vcomda pins. figure 32. recommended power on/off sequence table 8. recommended register settings when powered on register setting step address data description 1 ? ? turn on all power supplies 2 11 00 analog bias power up 3 1f 49 headphone output l-channel mute disable and level ( ? 42 db) setting (1) 4 20 49 headphone output r-channel mute disable and level ( ? 42 db) setting (1) 5 1e b0 headphone volume update control 6 1b 00 line output gain (0 db) control from dac (1) 7 1c 00 line output 2 v rms and 2.4 v rms mode select 8 2a ff dac12 l-channel digital attenuation level (0 db) setting (1) 9 2b ff dac12 r-channel digital attenuation level (0 db) setting (1) 10 29 00 dac12 digital mute setting and digital gain boost 11 28 b1 dac12 digital attenuation/mute control and zero crossing enable 12 34 ff dac34 l-channel digital attenuation level (0 db) setting (1) 13 35 ff dac34 r-channel digital attenuation level (0 db) setting (1) 14 33 00 dac34 digital mute setting and digital gain (0 db) boost 15 32 b1 dac34 digital attenuation/mute control and zero crossing enable 16 52 d5 adc12 l-channel digital attenuation level (0 db) setting (1) 17 53 d5 adc12 r-channel digital attenuation level (0 db) setting (1) (1) any level is acceptable for volume, gain, and attenuation. the level should be resumed by register data recorded when the system powers off. 22 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 vdd, vccp, vccad, vccda vcch (9 v) i c register setting 2 analog output (1) digital output 75 ms to 2000 ms (2) 37.5 ms to 1000 ms half of power-supply voltage recommended power-on sequence recommended power-off sequence
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 table 8. recommended register settings when powered on (continued) register setting step address data description 18 51 00 adc12 digital mute disable 19 50 01 adc12 digital attenuation/mute control and zero crossing enable 20 5c d7 adc34 l-channel digital attenuation level (0 db) setting (1) 21 5d d7 adc34 r-channel digital attenuation level (0 db) setting (1) 22 5b 00 adc34 digital mute disable 23 5a 01 adc34 digital attenuation/mute control and zero crossing enable 24 18 77 line output 1 l-/r-channel mux select 25 19 00 line output 2 l-/r-channel mux select 26 1a 88 headphone output l-/r-channel mux select 27 14 11 adc12 analog input mux select (ain1l/r) (2) 28 15 22 adc34 analog input mux select (ain2l/r) (2) 29 16 00 adc12 analog input gain level (0 db) setting (1) 30 17 00 adc34 analog input gain level (0 db) setting (1) 31 65 98 audio interface (lrckx/bckx) port-1 and port-2 setting (adc12/34, master) (3) 32 66 98 audio interface (datax) port-1 and port-2 setting (data output of adc12/34) (3) 33 67 10 audio interface (sckx) port-1 and port-2 setting (input of sck1/2) (4) audio interface (lrckx/bckx) port-3 and port-4 setting (input of lrck3/4, 34 68 32 bck3/4) (4) 35 69 32 audio interface (datax) port-3 and port-4 setting (input of data3/4) (4) 36 6a 32 audio interface (sckx) port-3 and port-4 setting (input of sck3/4) (4) audio interface (lrckx/bckx) port-5 and port-6 setting (input of lrck3/4, 37 6b 54 bck3/4) (4) 38 6c 54 audio interface (datax) port-5 and port-6 setting (input of data5/6) (4) 39 6d 54 audio interface (sckx) port-5 and port-6 setting (input of sck5/6) (4) 40 6e 43 dac12 and dac34 lrck/bck select (4) 41 6f 43 dac12 and dac34 data select (4) 42 70 43 dac12 and dac34 sck select (4) 43 74 89 adc12 and adc34 lrck/bck select (adc12/34, master) (4) 44 75 10 adc12 and adc34 sck select (4) 45 76 76 gpio control or gpio1 and gpio2 audio data select 46 2c 80 dac12 audio interface and master/slave select (5) 47 36 80 dac34 audio interface and master/slave select (5) 48 54 40 adc12 audio interface and master/slave select (master, 256 f s ) (5) 49 5e 40 adc34 audio interface and master/slave select (master, 256 f s ) (5) 50 12 11 analog back-end and front-end power-up 51 2e 00 dac12 power-up 52 38 00 dac34 power-up 53 55 00 adc12 power-up 54 5f 00 adc34 power-up 55 12 01 common voltage (v com ) power-up and ramp up/down time setting (2) any input terminals are acceptable for input of adc12 and adc34. (3) these settings are not required if application does not use audio interface mux and bypass selection. (4) these settings are not required if application does not use audio interface mux and bypass selection. (5) these settings are not required if application uses slave mode for audio interface and sck automatic f s detection. copyright ? 2009, texas instruments incorporated submit documentation feedback 23 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com table 9. recommended register setting when powered off register setting step address data description 1 18 00 line output1 l- and r-channel mux select 2 19 00 line output2 l- and r-channel mux select 3 1a 00 headphone output l- and r-channel mux select 4 14 00 adc12 analog input mux select 5 15 00 adc34 analog input mux select 6 12 11 common voltage (v com ) power-down and ramp up/down time setting 7 55 80 adc12 power-down 8 5f 80 adc34 power-down 9 2e 80 dac12 power-down 10 38 80 dac34 power-down 11 12 71 analog back-end and front-end power-down 12 11 80 analog bias power-down 13 ? ? turn off all power supplies 24 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
audio serial interface pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 has six audio interface ports: sckx, bckx, lrckx, and datax (bidirectional). each port or signal can be connected to any adc or dac. if an audio system application wants to bypass an audio signal, the pcm5310 can bypass from any port to any port. refer to figure 33 for a diagram of the of the audio inteface port and mux. see figure 47 to figure 52 for detailed diagrams of port-1 to port-6. the audio interface consists of lrcks, bcks, and datas. the sampling rate (f s ), left channel and right channel data are present on the lrcks. the datas receive the serial audio data from the interpolation filter for the dac, and the datas transmit the serial data to the decimation filter. the bcks are used to receive and transmit the serial audio data on the datas by high-to-low transition. the bcks and lrcks should be synchronized with the system clocks, scks. the pcm5310 operates with the lrcks/bcks synchronized with the scks; however, the pcm5310 does not need a specific phase between the bcks/lrcks and the scks. each audio interface port can select either the master or slave mode, and generate the lrcks and bcks from the scks in master mode. the descriptions for the audio serial interface registers are shown in table 6 . table 10. audio serial interface registers register description register number register bits master or slave with f s detection for dac12 44 dms12[3:0] audio interface format for dac12 44 dfm12[1:0] master or slave with f s detection for dac34 54 dms34[3:0] audio interface format for dac34 54 dfm34[1:0] master or slave with f s detection for adc12 84 ams12[3:0] audio interface format for adc12 84 afm12[1:0] master or slave with f s detection for adc34 94 ams34[3:0] audio interface format for adc34 94 afm34[1:0] lrck/bck selection of port-1 and port-2 101 lbs2[3:0], lbs1[3:0] data selection of port-1 and port-2 102 dts2[3:0], dts1[3:0] sck selection of port-1 and port-2 103 scs2[2:0], scs1[2:0] lrck/bck selection of port-3 and port-4 104 lbs4[3:0], lbs3[3:0] data selection of port-3 and port-4 105 dts4[3:0], dts3[3:0] sck selection of port-3 and port-4 106 scs4[2:0], scs3[2:0] lrck/bck selection of port-5 and port-6 107 lbs6[3:0], lbs5[3:0] data selection of port-5 and port-6 108 dts6[3:0], dts5[3:0] sck selection of port-5 and port-6 109 scs6[2:0], scs5[2:0] lrck/bck selection of dac12 and dac34 110 d34lb[3:0], d12lb[3:0] data selection of dac12 and dac34 111 d34dt[3:0], d12dt[3:0] sck selection of dac12 and dac34 112 d34s[2:0], d12s[2:0] lrck/bck selection of adc12 and adc34 116 a34lb[3:0], a12lb[3:0] sck selection of adc12 and adc34 117 a34sc[2:0], a12sc[2:0] gpio-1 and gpio-2 audio data selection 118 gp2s[3:0], gp1s[3:0] copyright ? 2009, texas instruments incorporated submit documentation feedback 25 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com figure 33. audio interface port and mux 26 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 adc12 adc34 mux_ad 12 port-1 lrck1 bck1 data1 sck1 lrck, bck at master gpio1gpio2 data for dac12/34 from gpio1 and gpio2 adc12 data from data for adc12/34 to gpio1 and gpio2 mux_ad 34 mux _da12 mux _da34 reg 116 a12lb[3:0] reg 117 a12s[2:0] lrck, bck, data, sck from port-1 lrck, bck, data, sck from port-2 lrck, bck, data, sck from port-3 lrck, bck, data, sck from port-4 lrck, bck, data, sck from port-5 lrck, bck, data, sck from port-6 lrck2 bck2 data2 sck2 lrck3 bck3 data3 sck3 lrck4 bck4 data4 sck4 lrck5 bck5 data5 sck5 lrck6 bck6 data6 sck6 gpio1gpio2 reg 116 a34lb[3:0] reg 117 a34s[2:0] reg 110 d12lb[3:0] reg 111 d12dt[3:0] reg 112 d12s[2:0] port-2 port-3 port-4 port-5 port-6 adc34 data from lrck, bck, sck for adc12 lrck, bck at master lrck, bck, sck for adc34 lrck, bck at master lrck, bck, sck for dac12 lrck, bck at master lrck, bck, sck for dac34 reg 110 d34lb[3:0] reg 111 d34dt[3:0] reg 112 d34s[2:0] dac12dac34 to register mapping bck/lrck master bck/lrck master bck/lrck master bck/lrck master
audio data formats and timing pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 supports i 2 s, left-justified, and right-justified data formats with 32 f s , 48 f s , or 64 f s bck rates for digital input, and 48 f s or 64 f s bck rates for the adc. the data formats are shown in figure 34 and can be selected through the i 2 c interface. all formats require binary twos complement, msb first audio data. the default format is 16- to 24-bits i 2 s. figure 35 and figure 36 show detailed timing diagrams. the descriptions for the audio interface data format registers are shown in table 11 . table 11. audio interface data format registers register description register number register bits audio interface format for dac12 44 dfm12[1:0] audio interface format for dac34 54 dfm34[1:0] audio interface format for adc12 84 afm12[1:0] audio interface format for adc34 94 afm34[1:0] figure 34. audio data input and output formats copyright ? 2009, texas instruments incorporated submit documentation feedback 27 product folder link(s): pcm5310 (a) right-justified data format; l-channel = high, r-channel = low lrck bck (= 32 f , 48 f , or 64 f ) s s s r-channel l-channel data lrck bck (= 32 f , 48 f , or 64 f ) s s s data lrck bck (= 32 f , 48 f , or 64 f ) s s s data msb lsb msb lsb 1/f s (b) i s data format; l-channel = low, r-channel = high 2 l-channel msb lsb r-channel msb lsb 1/f s (c) left-justified data format; l-channel = high, r-channel = low r-channel l-channel msb lsb msb lsb 1/f s
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com (1) load capacitance of output is 20 pf. figure 35. audio interface timing (slave mode) table 12. timing requirements for figure 35 parameter min max unit t bcy bckx cycle time 75 ns t bch bckx pulse width high 35 ns t bcl bckx pulse width low 35 ns t lrs lrckx set-up time to bckx rising edge 15 ns t lrh lrckx hold time to bckx rising edge 10 ns t dis datax setup time to bckx rising edge 10 ns t dih datax hold time to bckx rising edge 10 ns t dod datax delay time from bckx falling edge 0 30 ns 28 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 datax (1) (output mode) 0.5 v dd 1. 4 v lrckx (input) bckx (input) 1. 4 v datax (input mode) 1. 4 v t bch t bcl t bcy t lrh t lrs t dis t dih t dod
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 (1) load capacitance of output is 20 pf. figure 36. audio interface timing (master mode) table 13. timing requirements for figure 36 parameter min typ max unit t bcy bckx cycle time 1/(64 f s ) t bch bckx pulse width high 0.4 t bcy 0.5 t bcy 0.6 t bcy t bcl bckx pulse width low 0.4 t bcy 0.5 t bcy 0.6 t bcy t lrd lrckx delay time from bckx falling edge ? 15 20 ns t dis datax setup time to bckx rising edge 10 ns t dih datax hold time to bckx rising edge 10 ns t dod datax delay time from bckx falling edge ? 10 20 ns copyright ? 2009, texas instruments incorporated submit documentation feedback 29 product folder link(s): pcm5310 0.5 v dd 0.5 v dd lrckx (output) bckx (output) 0.5 v dd 1.4 v t bch t dod datax (1) (output mode) datax (input mode) t bcl t bcy t lrd t dis t dih
adc and filter pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the analog-to-digital converter (adc) and digital filter include a delta-sigma modulator, decimation filter, high-pass filter (hpf), digital gain control, digital attenuation control, and digital soft mute, as shown in figure 37 . the hpf eliminates dc offset of the adc analog section with 0.91 hz as the cutoff frequency at a 48-khz sampling rate. the digital gain or attenuation control can be adjusted from 20 db to ? 100 db in 0.5-db steps. the descriptions for the adc and filter registers are shown in table 14 . figure 37. adcs and filters table 14. adc and filter registers register description register number register bits digital attenuation and gain update control for adc12 80 a12e, auc2, auc1, az12 digital soft mute setting for adc12 81 amu2, amu1 digital attenuation and gain level setting for adc12 82, 83 aat2[7:0], aat1[7:0] high-pass filter disable for adc12 84 hf12 digital attenuation and gain update control for adc34 90 a34e, auc4, auc3, az34 digital soft mute setting for adc34 91 amu4, amu3 digital attenuation and gain level setting for adc34 92, 93 aat4[7:0], aat3[7:0] high-pass filter disable for adc34 94 hf34 30 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 adc-1l pga-ad1l decimation filter hpf att mute adc-1r pga-ad1r decimation filter hpf att mute adc-2l pga-ad2l decimation filter hpf att mute adc-2r pga-ad2r decimation filter hpf att mute
dac and filter pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the digital-to-analog converter (dac) and digital filter include a delta-sigma modulator, interpolation filter, de-emphasis filter (dem), digital gain control, digital attenuation control, digital soft mute, and digital gain boost, as shown in figure 38 . the digital gain or attenuation control can be adjusted from 20 db to ? 100 db in 0.5-db steps. to play back low-volume recorded audio data, the digital gain can be used with a boost of either 6 db, 12 db, or 18 db selected through the i 2 c interface. the descriptions for the dac and filter registers are shown in table 14 . figure 38. dacs and filters table 15. dac and filter registers register description register number register bits digital attenuation and gain update control for dac12 40 d12e, duc2, duc1, dz12 digital soft mute and boost setting for dac12 41 dmu2, dmu1, db12[1:0] digital attenuation and gain level setting for dac12 42, 43 dat2[7:0], dat1[7:0] de-emphasis filter setting for dac12 45 dm12, df12[1:0] digital attenuation and gain update control for dac34 50 d34e, duc4, duc3, dz34 digital soft mute setting for dac34 51 dmu4, dmu3 digital attenuation and gain level setting for dac34 52, 53 dat4[7:0], dat3[7:0] de-emphasis filter setting for dac34 55 dm34, df34[1:0] copyright ? 2009, texas instruments incorporated submit documentation feedback 31 product folder link(s): pcm5310 dac-1l interpolation filter dem dac-1r interpolation filter dem dac-2l interpolation filter dem dac-2r interpolation filter att mute gain dem att mute gain att mute gain att mute gain
gpio control pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the pcm5310 has three general-purpose input/output (gpio) pins (pins 55, 56, and 57) that can be assigned to various functions and internal status reads shown in table 16 , table 17 , table 18 , and figure 39 . table 16. gpio control registers register description register number register bits gpio1 select, bypass port-4 09 gbp4, gsl1[4:0] gpio2 select, bypass port-5 10 gbp5, gsl2[4:0] gpio3 select 11 gsl3[4:0] table 17. register data read through the gpio pins register description register number register bits external device control 08 gpo3, gpo2, gpo1 headphone short-circuit protection status 16 sshr, sshl headphone insertion detect status 35 rhpi mute status for headphone 35 rhmur, rhmul system clock f s detect for dac12, dac34 35, 36 rd12fs[2:0], rd34[2:0] system clock f s detect for adc12, adc34 37, 38 ra12fs[2:0], ra34[2:0] digital mute status for dac12 and dac34 36 rdm4, rdm3, rdm2, rdm1 digital mute status for adc12 and adc34 37 ram4, ram3, ram2, ram1 zero crossing timeout for dac12 and dac34 38 rdz4, rdz3, rdz2, rdz1 zero crossing timeout for adc12 and adc34 39 raz4, raz3, raz2, raz1 zero crossing timeout for headphone 39 rhzr, rhzl table 18. other gpio pin functions gpio pin function description zero flag for digital input read the status for each dac channel or all dac channels logic or, and, nor, nand, buffer, inverter audio data bypass audio data to port-4 and port-5 from gpio pins figure 39. gpio control 32 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 gpio control hp insertion hp protection zero flag register out logic in/out mux connect to port gpio1 gpio2 gpio3 gpio2gpio3 gpio1
headphone short-circuit protection pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 has short-circuit protection for each headphone output. the short-circuit status can be read from the gpio pins and the register data can be read through the i 2 c interface. the short-circuit detection time can be internally adjusted to avoid the headphone amplifier shutting down when inserting or removing the headphone jack. the descriptions for the headphone and short-circuit protection registers are shown in table 19 . the headphone short-circuit protection sequence is shown in figure 40 . table 19. headphone short-circuit protection registers register description register number register bits headphone short-circuit protection enable/disable 13 srcr, shcr, spdr, srcl, shcl, spdl headphone short-cicuit protection detect time 14 sdtr[1:0], sdtl[1:0] headphone short-circuit protection release time 15 srtr[1:0], srtl[1:0] headphone short-circuit protection status read 16 sshr, sshl figure 40. headphone short-circuit protection sequence when the short-circuit protection is enabled, it is recommended to insert a small protection resistor to limit over-current flow. table 20 shows the headphone output power with a small resistor. table 20. headphone amplifier output power load r l = 32 ? + protection resistor 32 ? + 4 ? 32 ? + 8 ? 32 ? + 16 ? 0.1% thd 28 mw 22 mw 16 mw 10% thd 37 mw 31 mw 22 mw copyright ? 2009, texas instruments incorporated submit documentation feedback 33 product folder link(s): pcm5310 headphone jack hpol or hpor protection resistor headphone 16 or 32 w w currentmonitor increment or decrement counter short or not gpio control headphoneamplifier enable/disable internal clock internal resistor gpio1, gpio2, or gpio3 detect/release time 4096 f : 85.2 ms at f = 48 khz s s 8192 f s s : 1704 ms at f = 48 khz 16384 f s s : 340.8 ms at f = 48 khz 32768 f s s : 681.6 ms at f = 48 khz
headphone insertion detection pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the descriptions for the headphone insertion detection registers are shown in table 21 . the pcm5310 detects the insertion status of a headphone plug using the gpio pins through the register setting and writes the status to the register, which can be read by the i 2 c interface. the status can also output to the gpio pins, as shown in figure 41 . table 21. headphone insertion detection registers register description register number register bits gpio1 selection 09 gsl1[4:0] gpio2 selection 10 gsl2[4:0] gpio3 selection 11 gsl3[4:0] read status for headphone insertion 35 ripi figure 41. headphone insertion detection 34 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 hporpgnd headphone jack dsp vdd sdascl gpio1, gpio2, or gpio3 hpol headphoneamplifier gpio control i c register 2
zero flag detection amute control pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 detects continuous zero data input to either dac12, dac34, or both dac12 and dac34. the gpio pins can output the status to an external device by the register setting. the flag changes from low to high when the l-and r-channel data are zero after 1024 f s . the descriptions for the zero flag detection registers are shown in table 22 . figure 42 shows the zero flag detection operation. table 22. zero flag registers register description register number register bits gpio1 selection 09 gsl1[4:0] gpio2 selection 10 gsl2[4:0] gpio3 selection 11 gsl3[4:0] figure 42. zero flag detection the pcm5310 has an amute pin (pin 59) that controls the digital and analog mute function linked to register 19 (13h). if these settings are disabled and the amute pin goes from low to high, the pcm5310 holds the digital and analog mute disabled. if these settings are enabled and the amute pin goes from low to high, the pcm5310 enables digital and analog mute. the mute function set by the amute pin is effective, regardless of the setting in register 19. copyright ? 2009, texas instruments incorporated submit documentation feedback 35 product folder link(s): pcm5310 lrck4 bck4 data4 lrck5 bck5 data5 port-4 dac12 dac34 zero data or not zero data or not increment counter gpio control gpio1gpio2 gpio3 increment counter port-5
mute control timing during clock changes pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the pcm5310 has six audio interface ports and can change from the current source to another source. however, the analog output or digital output may have an audible pop noise when changing or stopping clocks. it is recommend to use the mute control with zero data input and waiting time to avoid pop noise and clean up the internal circuit via i 2 c. figure 43 illustrates the details. note that the digital and analog inputs should be zero data initially. after that, use the following steps: 1. disable zero crossing detection. 2. enable the analog or digital output mute. 3. change the clock source. 4. disable the analog or digital mute. (1) value depends on attenuation level setting in registers 82, 83, 92, and 93. figure 43. mute control timing during clock changes 36 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 i c setting 2 clock source b clock source a 241 8 f (adc) 1 f (dac) (1) s s the digital and analog inputs should be zero data at first. then use the following setting procedure: a) disable zero crossing detection. b) enable analog or digital output mute. c) change the clock source. d) disable the analog or digital mute. note: 35 f (adc) 25 f (dac) s s
analog mux changing to reduce audible noise pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the pcm5310 has an analog multiplexer (mux) that can select six stereo analog inputs. the adc output may have audible noise when selecting without mute control via i 2 c. it is recommend to use digital soft mute before changing the analog input, as shown in figure 44 . (1) enable digital soft mute of adc. (2) change analog input source. (3) disable digital soft mute of adc. (4) maximum mute time is [241 8 f s ] seconds; however, this time depends on the wave form if zero crossing is enabled. it is recommended to read the status of this mute from register 35 to 39 via i 2 c. then if the status is high, disable mute. figure 44. analog mux changing to reduce audible noise copyright ? 2009, texas instruments incorporated submit documentation feedback 37 product folder link(s): pcm5310 (2) (1) ain1lain2l i c setting 2 adc output (3) (4) (4)
two-wire interface (i 2 c) slave address packet protocol pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com the pcm5310 supports the i 2 c serial bus and the data transmission protocol for the i 2 c standard as a slave device. this protocol is explained in the i 2 c specification 2.0. in i 2 c mode, the control terminals are changed as shown in table 23 . table 23. control pins pin name input/output description sda input/output i 2 c data scl input i 2 c clock the pcm5310 has its own 7-bit slave address, as shown in table 24 . the first six bits (msbs) of the slave address are factory preset to '1000110'. the last bit of the address byte is the device select bit, which can be user-defined by the adr terminal. a maximum of two pcm5310s can be connected on the same bus simultaneously. each pcm5310 responds when it receives its own slave address. table 24. slave address msb lsb 1 0 0 0 1 1 0 r/ w the master device must control packet protocol, which consists of a start condition, a slave address with read/write (r/ w) bit, data (if write) or acknowledgement (if read), and a stop condition, as shown in figure 45 . the pcm5310 supports only a slave receiver and slave transmitter. table 25 shows a basic i 2 c write operation. table 26 shows a basic i 2 c read operation. figure 45. basic i 2 c framework table 25. basic i 2 c write operation transmitter m m m s m s m s m slave data type st r/ w ack data ack data ack sp address legend: m = master device, s = slave device, st = start condition, sp = stop condition, r/ w = read/write, ack = acknowledge. table 26. basic i 2 c read operation transmitter m m m s m s m s m slave data type st r/ w ack data nack data nack sp address legend: m = master device, s = slave device, st = start condition, sp = stop condition, r/ w = read/write, ack = acknowledge, nack = not acknowledge. 38 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 sda scl st 1-7 slave address start condition stop condition r/w ack data 8 9 1-8 9 1-8 9 sp ack data ack r/ : read operation if 1; otherwise, write operation. ack: acknowledgement of a byte if 0. data: 8 bits (1 byte). w
write operation read operation pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the master can write to any pcm5310 register in a single access. the master sends a pcm5310 slave address with a write bit, a register address, and data. when undefined registers are accessed, the pcm5310 does not send any acknowledgement. table 27 shows the framework for a write operation. table 27. framework for write operation transmitter m m m s m s m s m slave register data type st w ack ack write data ack sp address address legend: m = master device, s = slave device, st = start condition, sp = stop condition, w = write, ack = acknowledge. the master can read any pcm5310 register. the value of the register address is stored in an indirect index register in advance. the master sends the pcm5310 slave address with a read bit after storing the register address. the pcm5310 then transfers the data to the address specified by the index register. table 28 shows the framework for a read operation. table 28. framework for read operation transmitter m m m s m s m m m s s m m slave register slave read data type st w ack ack sr r ack nack sp address address address data legend: m = master device, s = slave device, st = start condition, sr = repeated start condition, sp = stop condition, w = write, r = read, ack = acknowledge, nack = not acknowledge. copyright ? 2009, texas instruments incorporated submit documentation feedback 39 product folder link(s): pcm5310
i 2 ctiming diagram pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com figure 46. i 2 c timing table 29. timing characteristics for figure 46 parameter i 2 c specification min max unit f scl scl clock frequency standard 100 khz t (buf) bus free time between stop and start condition standard 4.7 m s t (low) scl clock low period standard 4.7 m s t (hi) scl clock high period standard 4 m s t (rs-su) start condition setup time standard 4.7 m s t (s-hd) start condition hold time standard 4 m s t (d-su) data setup time standard 250 ns t (d-hd) data hold time standard 0 900 ns t (scl-r) scl signal rise time standard 20 + 0.1 c b 1000 ns rise time of scl signal after a repeated start t (scl-r1) standard 20 + 0.1 c b 1000 ns condition and after an acknowledge bit t (scl-f) scl signal fall time standard 20 + 0.1 c b 1000 ns t (sda-r) sda signal rise time standard 20 + 0.1 c b 1000 ns t (sda-f) sda signal fall time standard 20 + 0.1 c b 1000 ns t (p-su) stop condition setup time standard 4 m s c b capacitive load for sda and scl line 400 pf t (sp) suppressed spike pulse duration 25 ns 40 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 sda scl t (buf) t (d-su) t (sda-r) t (sda-f) t (p-su) t (low) t (d-hd) t (s-hd) t (scl-f) t (scl-r) t (rs-su) t (rs-hd) stop condition start condition t (sp) t (hi)
register map pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the mode control register map is shown in table 30 . each register includes an index (or address) indicated by the idx[6:0] bits. table 30. mode control register map reg hex description b7 b6 b5 b4 b3 b2 b1 b0 01 01h reset function mrst srst rsv (1) rsv rsv rsv rsv rsv 08 08h gpio pin output control rsv rsv rsv rsv rsv gpo3 gpo2 gpo1 09 09h gpio port-1 selection rsv rsv rsv gsl1[4:0] 10 0ah gpio port-2 selection rsv rsv rsv gsl2[4:0] 11 0bh gpio port-3 selection rsv rsv rsv gsl3[4:0] 12 0ch not assigned rsv rsv rsv rsv rsv rsv rsv rsv 13 0dh headphone short-circuit protection enable/disable rsv srcr shcr spdr rsv srcl shcl spdl 14 0eh headphone short-circuit protection detect time rsv rsv sdtr[1:0] rsv rsv sdtl[1:0] headphone short-circuit protection release time, auto 15 0fh rsv sadr srtr[1:0] rsv sadl srtl[1:0] control 16 10h headphone short-circuit protection status read rsv rsv rsv sshr rsv rsv rsv sshl 17 11h power up/down (bias) pbis rsv rsv rsv rsv pdcf[1:0] pdcs 18 12h power up/down (analog), power up/down time rsv pabe pafe pcom rsv pdtm[2:0] 19 13h mute control linked to amute pin md12 md34 mhpr mhpl ml2r ml2l ml1r ml1l 20 14h analog input mux selection for adc12 rsv ax1r[2:0] rsv ax1l[2:0] 21 15h analog input mux selection for adc34 rsv ax2r[2:0] rsv ax2l[2:0] 22 16h analog input gain control for adc12 rsv rsv ag1r[1:0] rsv rsv ag1l[1:0] 23 17h analog input gain control for adc12 rsv rsv ag2r[1:0] rsv rsv ag2l[1:0] 24 18h analog output mux selection for line output 1 al1r[3:0] al1l[3:0] 25 19h analog output mux selection for line output 2 al2r[3:0] al2l[3:0] 26 1ah analog output mux selection for headphone output ahpr[3:0] ahpl[3:0] 27 1bh gain control for line output gl2r[1:0] gl2l[1:0] gl1r[1:0] gl1l[1:0] 28 1ch 2.0 v rms and 2.4 v rms selection for line output rsv rsv rsv g242 rsv rsv rsv g241 29 1dh clock halt detection control rsv rsv rsv rsv rsv rsv acth chde 30 1eh headphone output volume control hupe rsv hsur hsul rsv rsv rsv hzrs headphone mute and volume level setting for 31 1fh hmul hvol[6:0] r-channel headphone mute and volume level setting for 32 20h hmur hvor[6:0] l-channel 33 21h system clock output disable rsv rsv sc6d sc5d sc4d rsv sc2d sc1d 34 22h lrck and bck output disable at master mode rsv rsv lb6d lb5d lb4d lb3d lb2d lb1d 35 23h read internal flag rsv rd12fs[2:0] rhmr rhml rsv rhpi 36 24h read internal flag rsv rd34fs[2:0] rdm4 rdm3 rdm2 rdm1 37 25h read internal flag rsv ra12fs[2:0] ram4 ram3 ram2 ram1 38 26h read internal flag rsv ra34fs[2:0] rdz4 rdz3 rdz2 rdz1 39 27h read internal flag cgld rsv rhzr rhzl raz4 raz3 raz2 raz1 40 28h digital attenuation and mute control for dac12 d12e rsv duc2 duc1 rsv rsv rsv dz12 41 29h digital gain boost and digital soft mute for dac12 rsv rsv rsv rsv db12[1:0] dmu2 dmu1 42 2ah digital attenuation level setting for dac12 l-channel dat1[7:0] 43 2bh digital attenuation level setting for dac12 r-channel dat2[7:0] 44 2ch master/slave interface format for dac12 dms12[3:0] rsv rsv dfm12[1:0] 45 2dh de-emphasis filter control for dac12 rsv rsv rsv rsv dm12 rsv df12[1:0] 46 2eh power up/down, oversampling rate control for dac12 pd12 rsv ov12[1:0] zr12 rsv rsv rsv (1) rsv = reserved (write ' 0 ' data). copyright ? 2009, texas instruments incorporated submit documentation feedback 41 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com table 30. mode control register map (continued) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 50 32h digital attenuation and mute control for dac34 d34e rsv duc4 duc3 rsv rsv rsv dz34 51 33h digital gain boost and digital soft mute for dac34 rsv rsv rsv rsv db34[1:0] dmu4 dmu3 52 34h digital attenuation level setting for dac34 l-channel dat3[7:0] 53 35h digital attenuation level setting for dac34 r-channel dat4[7:0] 54 36h master/slave interface format for dac34 dms34[3:0] rsv rsv dfm34[1:0] 55 37h de-emphasis filter control for dac34 rsv rsv rsv rsv dm34 rsv df34[1:0] 56 38h power up/down, oversampling rate control for dac34 pd34 rsv ov34[1:0] zr34 rsv rsv rsv 80 50h digital attenuation and mute control for adc12 a12e rsv auc2 auc1 rsv rsv rsv az12 81 51h digital soft mute for adc12 rsv fs12 rsv rsv rsv rsv amu2 amu1 82 52h digital attenuation level setting for adc12 l-channel aat1[7:0] 83 53h digital attenuation level setting for adc12 r-channel aat2[7:0] 84 54h master/slave interface format for adc12 ams12[3:0] hf12 rsv afm12[1:0] 85 55h power up/down for adc12 pa12 rsv rsv rsv rsv rsv rsv rsv 90 5ah digital attenuation and mute control for adc34 a34e rsv auc4 auc3 rsv rsv rsv az34 91 5bh digital soft mute for adc34 rsv fs34 rsv rsv rsv rsv amu4 amu3 92 5ch digital attenuation level setting for adc34 l-channel aat3[7:0] 93 5dh digital attenuation level setting for adc34 r-channel aat4[7:0] 94 5eh master/slave, interface format for adc34 ams34[3:0] hf34 rsv afm34[1:0] 95 5fh power up/down for adc34 pa34 rsv rsv rsv rsv rsv rsv rsv 101 65h lrck/bck selection of port-1 and port-2 lbs2[3:0] lbs1[3:0] 102 66h data selection of port-1 and port-2 dts2[3:0] dts1[3:0] 103 67h sck selection of port-1 and port-2 rsv scs2[2:0] rsv scs1[2:0] 104 68h lrck/bck selection of port-3 and port-4 lbs4[3:0] lbs3[3:0] 105 69h data selection of port-3 and port-4 dts4[3:0] dts3[3:0] 106 6ah sck selection of port-3 and port-4 rsv scs4[2:0] rsv scs3[2:0] 107 6bh lrck/bck selection of port-5 and port-6 lbs6[3:0] lbs5[3:0] 108 6ch data selection of port-5 and port-6 dts6[3:0] dts5[3:0] 109 6dh sck selection of port-5 and port-6 rsv scs6[2:0] rsv scs5[2:0] 110 6eh lrck/bck selection of dac12 and dac34 d34lb[3:0] d12lb[3:0] 111 6fh data selection of dac12 and dac34 d34dt[3:0] d12dt[3:0] 112 70h sck selection of dac12 and dac34 rsv d34s[2:0] rsv d12s[2:0] 113 71h not assigned rsv rsv rsv rsv rsv rsv rsv rsv 114 72h not assigned rsv rsv rsv rsv rsv rsv rsv rsv 115 73h not assigned rsv rsv rsv rsv rsv rsv rsv rsv 116 74h lrck/bck selection of adc12 and adc34 a34lb[3:0] a12lb[3:0] 117 75h sck selection of adc12 and adc34 rsv a34sc[2:0] rsv a12sc[2:0] 118 76h gpio1 and gpio2 audio data selection gp2s[3:0] gp1s[3:0] 42 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register descriptions register 01 (01h) register 08 (08h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 01 01h reset function mrst srst rsv rsv rsv rsv rsv rsv mrst: reset of all registers except for other internal circuit this bit enables the reset signal for register data only. all registers are initialized to default data by setting mrst = '0'. after the reset sequence completes, mrst is automatically set to '1'. defalut value: 1 0 reset (set to '0' automatically after set to '1') 1 not reset (default) srst: reset of all internal circuits including all registers this bit enables the internal system reset. all circuits including the registers are initialized by setting srst = '0'. after completing the reset sequence, srst is automatically set to '1'. defalut value: 1 0 reset (set to '0' automatically after set to '1') 1 not reset (default) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 08 08h gpio pin output control rsv rsv rsv rsv rsv gpo3 gpo2 gpo1 42 2ah digital attenuation level setting for dac12 l-channel dat1[7:0] gpo1: general-purpose output (pin 55) gpo2: general-purpose output (pin 56) gpo3: general-purpose output (pin 57) these three bits control the three gpio pins that control external devices. these register data are effective by setting '01000', '01001', or '01010' to bits gsl1[4:0], gsl2[4:0] and gsl[4:0] of registers 9 to 11. default value: 0 0 low level output (default) 1 high level output copyright ? 2009, texas instruments incorporated submit documentation feedback 43 product folder link(s): pcm5310
registers 09-12 (09h-0ch) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 09 09h gpio port-1 selection rsv rsv rsv gsl1[4:0] 10 0ah gpio port-2 selection rsv rsv rsv gsl2[4:0] 11 0bh gpio port-3 selection rsv rsv rsv gsl3[4:0] 12 0ch not assigned rsv rsv rsv rsv rsv rsv rsv rsv gsl1[4:0]: gpo1 function selection (pin 55) gsl2[4:0]: gpo2 function selection (pin 56) gsl3[4:0]: gpo3 function selection (pin 57) the three gpio pins can be used as an input flag, output flag, and logic function, as shown in table 31 . default value: 00000 table 31. gpio functions gsl1-3[4:0] gsl1[4:0]/gpio1 gsl2[4:0]/gpio2 gsl3[4:0]/gpio3 00000 no assigned and input mode (default) no assigned and input mode (default) no assigned and input mode (default) 00001 headphone insertion detection input headphone insertion detection input headphone insertion detection input 00010 headphone insertion detection output headphone insertion detection output headphone insertion detection output 00011 headphone short detection status l-channel headphone short detection status l-channel headphone short detection status l-channel 00100 headphone short detection status r-channel headphone short detection status r-channel headphone short detection status r-channel 00101 zero flag output for digital input (dac12) zero flag output for digital input (dac12) zero flag output for digital input (dac12) 00110 zero flag output for digital input (dac34) zero flag output for digital input (dac34) zero flag output for digital input (dac34) 00111 zero flag output for digital input (dac12 and zero flag output for digital input (dac12 and zero flag output for digital input (dac12 and dac34) dac34) dac34) 01000 output register data to gpio1 pin output register data to gpio1 pin output register data to gpio1 pin 01001 output register data to gpio2 pin output register data to gpio2 pin output register data to gpio2 pin 01010 output register data to gpio3 pin output register data to gpio3 pin output register data to gpio3 pin 01011 and logic (gpio1 = output, gpio2,3 = input) and logic (gpio2 = output, gpio1,3 = input) and logic (gpio2 = output, gpio1,3 = input) 01100 nand logic (gpio1 = output, gpio2,3 = nand logic (gpio2 = output, gpio1,3 = nand logic (gpio2 = output, gpio1,3 = input) input) input) 01101 or logic (gpio1 = output, gpio2,3 = input) or logic (gpio2 = output, gpio1,3 = input) or logic (gpio2 = output, gpio1,3 = input) 01110 nor logic (gpio1 = output, gpio2,3 = input) nor logic (gpio2 = output, gpio1,3 = input) nor logic (gpio2 = output, gpio1,3 = input) 01111 buffer logic (gpio1 = output, gpio2 = input) buffer logic (gpio2 = output, gpio1 = input) buffer logic (gpio2 = output, gpio1 = input) 10000 buffer logic (gpio1 = output, gpio3 = input) buffer logic (gpio2 = output, gpio3 = input) buffer logic (gpio2 = output, gpio3 = input) 10001 inverter logic (gpio1 = output, gpio2 = input) inverter logic (gpio2 = output, gpio1 = input) inverter logic (gpio2 = output, gpio1 = input) 10010 inverter logic (gpio1 = output, gpio3 = input) inverter logic (gpio2 = output, gpio3 = input) inverter logic (gpio2 = output, gpio3 = input) others reserved reserved reserved 44 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 13-16 (0dh-10h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 13 0dh headphone short-circuit protection enable/disable rsv srcr shcr spdr rsv srcl shcl spdl 14 0eh headphone short-circuit protection detect time rsv rsv sdtr[1:0] rsv rsv sdtl[1:0] headphone short-circuit protection release time, 15 0fh rsv sadr srtr[1:0] rsv sadl srtl[1:0] auto control 16 10h headphone short-circuit protection status read rsv rsv rsv sshr rsv rsv rsv sshl srcr: reset short-circuit protection for headphone output r-channel srcl: reset short-circuit protection for headphone output l-channel these bits initialize the short-circuit protection for the headphone outputs by setting srcr = srcl = '1'. after completing the initialization, the data of both registers are automatically set to '1'. default value: 1 0 reset (set to '1' automatically after set to '0') 1 normal operation (default) spdr: short-circuit protection disable for headphone output r-channel spdl: short-circuit protection disable for headphone output l-channel these bits disable the short-circuit protection for the headphone outputs. default value: 0 0 enable (default) 1 disable sdtr[1:0]: short-circuit protection detect time control for headphone output r-channel sdtl[1:0]: short-circuit protection detect time control for headphone output l-channel these bits define the continuous time until a short-circuit is detected on the headphone outputs. if the short-circuit time does not reach the defined time, the pcm5310 does not enable short-circuit protection. default value: 11 00 4096 f s , 85.2 ms at f s = 48 khz 01 8192 f s , 170.4 ms at f s = 48 khz 10 16384 f s , 340.8 ms at f s = 48 khz 11 32768 f s , 681.6 ms at f s = 48 khz (default) srtr[1:0]: short-circuit protection release time control for headphone output r-channel srtl[1:0]: short-circuit protection release time control for headphone output l-channel these bits define the time until the short-circuit protection is released after detecting a short-circuit. default value: 11 00 4096 f s , 85.2 ms at f s = 48 khz 01 8192 f s , 170.4 ms at f s = 48 khz 10 16384 f s , 340.8 ms at f s = 48 khz 11 32768 f s , 681.6 ms at f s = 48 khz (default) copyright ? 2009, texas instruments incorporated submit documentation feedback 45 product folder link(s): pcm5310
registers 17 and 18 (11h and 12h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com sadr: short-circuit protection automatic release disable for headphone output r-channel sadl: short-circuit protection automatic release disable for headphone output l-channel these bits disable the automatic power down when a short-circuit is detected. default value: 0 0 enable (default) 1 disable sshr: short-circuit status read for headphone output r-channel sshl: short-circuit status read for headphone output l-channel these bits are used to read the short-circuit status on the headphone through the i 2 c interface. if the status is '1', then the headphone output is in short-circuit. default value: 0 0 not shorted (default) 1 short-circuit reg hex description b7 b6 b5 b4 b3 b2 b1 b0 17 11h power up/down (bias) pbis rsv rsv rsv rsv pdcf[1:0] pdcs 18 12h power up/down (analog), power up/down time rsv pabe pafe pcom rsv pdtm[2:0] pbis: power up/down control for analog bias circuit this bit is used to power up/down the analog bias circuit. default value: 1 0 power up 1 power down (default) pdcf[1:0]: power up/down time control these bits set the power up/down time for each sampling rate. set this register when the sampling rate is greater than 48 khz at power up/down. default value: 00 00 x1 (default) 01 x1/2 10 x1/4 11 reserved pdcs: power up/down clock selection the pcm5310 has six clock inputs for the four dac and four adc channels. the power on/off sequence starts using the dac12 clock or the dac34 clock. the appropriate clock source must be selected for the power up/down sequence. default value: 0 0 use the dac12 clock for power up/down (default) 1 use the dac34 clock for power up/down 46 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 pafe: power up/down control for input mux and gain amplifier this bit powers up/down the input mux and the gain amplifier. default value: 1 0 power up 1 power down (default) pabe: power up/down control for output mux, line amp, and headphone amplifier this bit powers up/down the output mux, the line amplifiers, and the headphone amplifier. default value: 1 0 power up 1 power down (default) pcom: power up/down control for common voltage circuit this bit powers up/down the common voltage circuit for the adc and dac channels. default value: 1 0 power up 1 power down (default) pdtm[2:0]: power up/down time control the power-up time selection for the pcm5310 can be from ground level to common voltage for analog outputs. the power-down time selection can be from the common voltage to ground level for analog outputs at the power on/off sequence. the time described in figure 32 is defined for a 48-khz sampling rate. set bits pdcf[1:0] in register 17 when the sampling rate is more than 48 khz at the power up/down sequence. default value: 001 pdtm[2:0] power-up time power-down time 000 37.5 ms 75 ms 001 75 ms (default) 150 ms 010 150 ms 300 ms 011 300 ms 600 ms 100 1000 ms 2000 ms 101 reserved reserved 110 reserved reserved 111 reserved reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 47 product folder link(s): pcm5310
register 19 (13h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 19 13h mute control linked to the amute pin md12 md34 mhpr mhpl ml2r ml2l ml1r ml1l md12: mute enable/disable linked to the amute pin for digital input (dac12) md34: mute enable/disable linked to the amute pin for digital input (dac34) the pcm5310 has a mute control pin (amute, 59 pin). when amute = '1' and md12 = '1' or md34 = '1', the digital soft mute of digital input data is enabled. when amute = '0', mute is disabled. default value: 0 0 mute disabled if the amute pin is at a high or lo2w level (default) 1 mute enabled if the amute pin is at a high level mhpr: mute enable/disable linked amute pin for headphone output, r-channel mhpl: mute enable/disable linked amute pin for headphone output, l-channel the pcm5310 has a mute control pin (amute, 59 pin). when amute = '1' and mhpr = '1' or mhpl = '1', the analog mute for headphone outputs hpol and hpor is enabled. when amute = '0', mute is disabled. default value: 1 0 mute disabled if the amute pin is at a high or low level 1 mute enabled if the amute pin is at a high level (default) ml1r: mute enable/disable linked amute pin for line output 1, r-channel ml1l: mute enable/disable linked amute pin for line output 1, l-channel the pcm5310 has a mute control pin (amute, 59 pin). when amute = '1' and ml1r = '1' or ml1l = '1', the analog mute for line outputs lo1l and lo1r are enabled. when amute = '0', mute is disabled. default value: 1 0 mute disabled if amute pin is high or low level 1 mute enabled if amute pin is high level (default) mml2r: mute enable/disable linked amute pin for line output 2, r-channel mml2l: mute enable/disable linked amute pin for line output 2, l-channel the pcm5310 has a mute control pin (amute, 59 pin). when amute = '1' and ml2r = '1' or ml2l = '1', the analog mute for line outputs lo2l and lo2r are enabled. when amute = '0', mute is disabled. default value: 1 0 mute disabled if amute pin is high or low level 1 mute enabled if amute pin is high level (default) 48 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 20 and 21 (14h and 15h) registers 22 and 23 (16h and 17h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 20 14h analog input mux selection for adc12 rsv ax1r[2:0] rsv ax1l[2:0] 21 15h analog input mux selection for adc34 rsv ax2r[2:0] rsv ax2l[2:0] ax1r[2:0]: analog input mux selection for adc12, r-channel ax1l[2:0]: analog input mux selection for adc12, l-channel ax2r[2:0]: analog input mux selection for adc34, r-channel ax2l[2:0]: analog input mux selection for adc34, l-channel the pcm5310 has six stereo inputs that can select one stereo input for each adc. it is recommended to use the digital soft mute to reduce audible noise when the analog inputs are changed; see figure 44 for details. default value: 000 000 no connection (default) 001 ain1l or ain1r 010 ain2l or ain2r 011 ain3l or ain3r 100 ain4l or ain4r 101 ain5l or ain5r 110 ain6l or ain6r others reserved reg hex description b7 b6 b5 b4 b3 b2 b1 b0 22 16h analog input gain control for adc12 rsv rsv ag1r[1:0] rsv rsv ag1l[1:0] 23 17h analog input gain control for adc34 rsv rsv ag2r[1:0] rsv rsv ag2l[1:0] ag1r[1:0]: analog input gain control for adc12, r-channel ag1l[1:0]: analog input gain control for adc12, l-channel ag2r[1:0]: analog input gain control for adc34, r-channel ag2l[1:0]: analog input gain control for adc34, l-channel the pcm5310 has analog gain amplifiers in front of each adc input that can be programmed to between 0 db to +9 db in 3-db steps; refer to figure 28 for details. default value: 00 00 0 db (default) 01 3 db 10 6 db 11 9 db copyright ? 2009, texas instruments incorporated submit documentation feedback 49 product folder link(s): pcm5310
registers 24-26 (18h-1ah) register 27 (1bh) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 24 18h analog output mux selection for line output 1 al1r[3:0] al1l[3:0] 25 19h analog output mux selection for line output 2 al2r[3:0] al2l[3:0] 26 1ah analog output mux selection for headphone output ahpr[3:0] ahpl[3:0] al1r[3:0]: analog output mux selection for line output 1, r-channel al1l[3:0]: analog output mux selection for line output 1, l-channel al2r[3:0]: analog output mux selection for line output 2, r-channel al2l[3:0]: analog output mux selection for line output 2, l-channel ahpr[3:0]: analog output mux selection for headphone output, r-channel ahpl[3:0]: analog output mux selection for headphone output, l-channel analog outputs lo1l/lo1r, lo2l/lo2r, and hpol/hpor can be selected as one of all the analog inputs and dac outputs; see figure 29 for details. default value: 0000 0000 no connection (default) 0001 ain1l or ain1r 0010 ain2l or ain2r 0011 ain3l or ain3r 0100 ain4l or ain4r 0101 ain5l or ain5r 0110 ain6l or ain6r 0111 dac12-l-channel or dac12-r-channel 1000 dac34-l-channel or dac34-r-channel others reserved reg hex description b7 b6 b5 b4 b3 b2 b1 b0 27 1bh gain control for line output gl2r[1:0] gl2l[1:0] gl1r[1:0] gl1l[1:0] gl2r[1:0]: gain control for line output 2, r-channel gl2l[1:0]: gain control for line output 2, l-channel gl1r[1:0]: gain control for line output 1, r-channelt gl1l[1:0]: gain control for line output 1, l-channel the gain level for line outputs lo1l, lo1r, lo2l, and lo2r can be each be selected as 0 db, ? 0.5 db, or ? 1.0 db. default value: 00 00 0 db (default) 01 ? 0.5 db 10 ? 1.0 db 11 0 db when selecting analog input to line output 50 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 28 (1ch) register 29 (1dh) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 28 1ch 2.0 vrms and 2.4 vrms selection for line output rsv rsv rsv g242 rsv rsv rsv g241 g242: 2-v rms or 2.4-v rms output mode selection for line output 2 g241: 2-v rms or 2.4-v rms output mode selection for line output 1 the line outputs can drive a 2-v rms or 2.4-v rms output with 10 k ? . the 2.4-v rms setting is recommend for use when the equipment requires greater than 2-v rms output. default value: 0 0 2 v rms (default) 1 2.4 v rms reg hex description b7 b6 b5 b4 b3 b2 b1 b0 29 1dh clock halt detection control rsv rsv rsv rsv rsv rsv acth chde acth: activate control for clock halt detection chde: enable clock halt detection acth is used to control the power up/down for clock halt detection and chde is used to enable it. setting acth = chde = '1' activates and enables clock halt detection. clock halt detection can reduce audible noise. the analog outputs are muted when the clock input to dac12 and dac34 is suddenly stopped. default value: 0 acth = 0 deactivate clock halt detection (default) acth = 1 activate clock halt detection chde = 0 clock halt detection disabled (default) chde = 1 clock halt detection enabled copyright ? 2009, texas instruments incorporated submit documentation feedback 51 product folder link(s): pcm5310
register 30 (1eh) register 31 and 32 (1fh and 20h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 30 1eh headphone output volume control hupe rsv hsur hsul rsv rsv rsv hzrs hupe: headphone volume update control enable hsur: headphone volume setting update for headphone output, r-channel hsul: headphone volume setting update for headphone output, l-channel hzrs: headphone volume zero cross enable the volume level of the headphone output can be changed independently to any level by setting hmul/hmur and hvol[6:0]/hvor[6:0] when hupe = '0'. when hupe = '1', the volume level is changed to any level at the same time when hsur = '1' or hsul = '1'. both bits are automatically set to '0' after being set to '1'. hsur and hsul must be set to '1' for every volume level setting during hupe = '1'. default value of hupe and hzrs: 1. default value of hsur and hsul: 0 hupe = 0 headphone volume update control disable hupe = 1 headphone volume update control enable (default) hsur, hsul = 0 no update volume setting data (default) hsur, hsul = 1 update volume setting data (set to '0' automatically after setting to '1') hzrs = 0 headphone volume zero crossing disable hzrs = 1 headphone volume zero crossing enable (default) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 headphone mute and volume level setting for 31 1fh hmul hvol[6:0] r-channel headphone mute and volume level setting for 32 20h hmur hvor[6:0] l-channel hmul: headphone volume mute control for l-channel hmur: headphone volume mute control for r-channel the headphone output can be independently muted to zero level when hmul and hmur = '1'. these settings take precedence over volume level settings by hvol and hvor. the headphone output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 30, hzrs). default value: 0 0 mute disabled (default) 1 mute enabled hvol[6:0]: headphone volume level control for l-channel hvor[6:0]: headphone volume level control for r-channel the headphone output can be independently programmed to between 12 db to ? 70 db in 1-db steps. the headphone output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 30, hzrs). default value: 010 1101 52 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 table 32. headphone volume level control hp volume hp volume hp volume hvol[6:0] level hvol[6:0] level hvol[6:0] level hvor[6:0] control hvor[6:0] control hvor[6:0] control 111 1111 7f 12 db 110 0010 62 ? 17 db 100 0101 45 ? 46 db 111 1110 7e 11 db 110 0001 61 ? 18 db 100 0100 44 ? 47 db 111 1101 7d 10 db 110 0000 60 ? 19 db 100 0011 43 ? 48 db 111 1100 7c 9 db 101 1111 5f ? 20 db 100 0010 42 ? 49 db 111 1011 7b 8 db 101 1110 5e ? 21 db 100 0001 41 ? 50 db 111 1010 7a 7 db 101 1101 5d ? 22 db 100 0000 40 ? 51 db 111 1001 79 6 db 101 1100 5c ? 23 db 011 1111 3f ? 52 db 111 1000 78 5 db 101 1011 5b ? 24 db 011 1110 3e ? 53 db 111 0111 77 4 db 101 1010 5a ? 25 db 011 1101 3d ? 54 db 111 0110 76 3 db 101 1001 59 ? 26 db 011 1100 3c ? 55 db 111 0101 75 2 db 101 1000 58 ? 27 db 011 1011 3b ? 56 db 111 0100 74 1 db 101 0111 57 ? 28 db 011 1010 3a ? 57 db 111 0011 73 0 db 101 0110 56 ? 29 db 011 1001 39 ? 58 db 1110010 72 ? 1 db 101 0101 55 ? 30 db 011 1000 38 ? 59 db 111 0001 71 ? 2 db 101 0100 54 ? 31 db 011 0111 37 ? 60 db 111 0000 70 ? 3 db 101 0011 53 ? 32 db 011 0110 36 ? 61 db 110 1111 6f ? 4 db 101 0010 52 ? 33 db 011 0101 35 ? 62 db 110 1110 6e ? 5 db 101 0001 51 ? 34 db 011 0100 34 ? 63 db 110 1101 6d ? 6 db 101 0000 50 ? 35 db 011 0011 33 ? 64 db 110 1100 6c ? 7 db 100 1111 4f ? 36 db 011 0010 32 ? 65 db 110 1011 6b ? 8 db 100 1110 4e ? 37 db 011 0001 31 ? 66 db 110 1010 6a ? 9 db 100 1101 4d ? 38 db 011 0000 30 ? 67 db 110 1001 69 ? 10 db 100 1100 4c ? 39 db 010 1111 2f ? 68 db 110 1000 68 ? 11 db 100 1011 4b ? 40 db 010 1110 2e ? 69 db 110 0111 67 ? 12 db 100 1010 4a ? 41 db 010 1101 2d ? 70 db (default) 110 0110 66 ? 13 db 100 1001 49 ? 42 db 010 1100 2c 110 0101 65 ? 14 db 100 1000 48 ? 43 db ? ? mute 110 0100 64 ? 15 db 100 0111 47 ? 44 db 000 0000 00 110 0011 63 ? 16 db 100 0110 46 ? 45 db copyright ? 2009, texas instruments incorporated submit documentation feedback 53 product folder link(s): pcm5310
register 33 (21h) register 34 (22h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 33 21h system clock output disable rsv rsv sc6d sc5d sc4d sc3d sc2d sc1d sc6d: sck6 output disable sc5d: sck5 output disable sc4d: sck4 output disable sc3d: sck3 output disable sc2d: sck2 output disable sc1d: sck1 output disable these bits are used to disable (low-level output) the clock ports (sck1, sck2, sck3, sck4, sck5 and sck6) in output mode. it is necessary to use these bits with register 103 (scs2[2:0], scs1[2:0]), register 106 (scs4[2:0], scs3[2:0]), and register 109 (scs6[2:0], scs5[2:0]). each clock port is set to input mode at the default setting. default value: 1 0 normal output 1 disable, low-level output (default) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 34 22h lrck and bck output disable at master mode rsv rsv lb6d lb5d lb4d lb3d lb2d lb1d lb6d: lrck6 and bck6 output disable lb5d: lrck5 and bck5 output disable lb4d: lrck4 and bck4 output disable lb3d: lrck3 and bck3 output disable lb2d: lrck2 and bck2 output disable lb1d: lrck1 and bck1 output disable these bits are used to disable (low-level output) the lrck/bck ports (lrck1/bck1, lrck2/bck2, lrck3/bck3, lrck4/bck4, lrck5/bck5 and lrck6/bck6) in output mode. it is necessary to use these bits with register 101 (lbs2[3:0], lbs1[3:0]), register 104 (lbs4[3:0], lbs3[3:0]), and register 107 (lbs6[3:0], lbs5[3:0]). each lrck/bck port is set to input mode at the default setting. default value: 1 0 normal output 1 disable, low-level output (default) 54 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 35-39 (23h-27h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 35 23h read internal flag rsv rd12fs[2:0] rhmr rhml rsv rhpi 36 24h read internal flag rsv rd34fs[2:0] rdm4 rdm3 rdm2 rdm1 37 25h read internal flag rsv ra12fs[2:0] ram4 ram3 ram2 ram1 38 26h read internal flag rsv ra34fs[2:0] rdz4 rdz3 rdz2 rdz1 39 27h read internal flag cgld rsv rhzr rhzl raz4 raz3 raz2 raz1 rd12fs[2:0]: read system clock f s rate detection status for dac12 rd34fs[2:0]: read system clock f s rate detection status for dac34 ra12fs[2:0]: read system clock f s rate detection status for adc12 ra34fs[2:0]: read system clock f s rate detection status for adc34 the pcm5310 includes automatic clock rate detection, which provides a divided clock to the adc and dac channels. the result of the detected clock rate can be read through the i 2 c port. default value: 111 000 reserved 001 128 f s (default) 010 192 f s 011 256 f s 100 384 f s 101 512 f s 110 768 f s 111 reserved (default) rhmr: read mute status for headphone output r-channel rhml: read mute status for headphone output l-channel these bits are used to read the mute status of the headphone output. the results can be read through the i 2 c port. default value: 0 0 mute disabled (default) 1 mute enabled rhpi: read headphone insertion detection status for headphone output this bit is used to read the headphone output insertion detection status through the i 2 c port. headphone insertion is set by register 09 to register 11 (gsl1[4:0], gsl2[4:0], gsl3[4:0]) with the gpio port. default value: 0 0 headphone not inserted (default) 1 headphone inserted copyright ? 2009, texas instruments incorporated submit documentation feedback 55 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com rdm4: read digital mute status for dac34, r-channel rdm3: read digital mute status for dac34, l-channel rdm2: read digital mute status for dac12, r-channel rdm1: read digital mute status for dac12, l-channel these bits are used to read the digital soft mute status for each dac channel through the i 2 c port. default value: 1 0 mute disabled 1 mute enabled (default) ram4: read digital mute status for adc34, r-channel ram3: read digital mute status for adc34, l-channel ram2: read digital mute status for adc12, r-channel ram1: read digital mute status for adc12, l-channel these bits are used to read the digital soft mute status for each adc channel through the i 2 c port. default value: 1 0 mute disabled 1 mute enabled (default) rrhzr: read volume zero cross time out status for headphone, r-channel rhzl: read volume zero cross time out status for headphone, l-channel rdz4: read digital attenuation/mute zero cross timeout status for dac34, r-channel rdz3: read digital attenuation/mute zero cross timeout status for dac34, l-channel rdz2: read digital attenuation/mute zero cross timeout status for dac12, r-channel rdz1: read digital attenuation/mute zero cross timeout status for dac12, l-channel raz4: read digital attenuation/mute zero cross timeout status for adc34, r-channel raz3: read digital attenuation/mute zero cross timeout status for adc34, l-channel raz2: read digital attenuation/mute zero cross timeout status for adc12, r-channel raz1: read digital attenuation/mute zero cross timeout status for adc12, l-channel these bits are used to read the zero-crossing timeout status of digital soft mute and digital attenuation for each adcs and dacs channel and for headphone output volume through the i 2 c port. default value: 0 0 not timed out (default) 1 timed out cgld: glitch reduction disable when changing clock source this bit disables the glitch reduction circuit, which reduces audible pop noise when changing the clock input from any sckx to sckx. default value: 0 0 enabled (default) 1 disabled 56 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 40 and 41 (28h and 29h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 40 28h digital attenuation and mute control for dac12 d12e rsv duc2 duc1 rsv rsv rsv dz12 41 29h digital gain boost and digital soft mute for dac12 rsv rsv rsv rsv db12[1:0] dmu2 dmu1 d12e: digital attenuation and mute update control enable for dac12 duc2: digital attenuation and mute setting update for dac12, r-channel duc1: digital attenuation and mute setting update for dac12, l-channel the digital attenuation and mute levels of dac12 can be changed independently to any level by setting bits dmu2 and dmu1 of register 41, bits dat1[7:0] of register 42, and bits dat2[7:0] of register 43 when d12e = '0'. when d12e = '1', the level is changed to any level at the same time when duc2 = '1' or duc1 = '1'. both bits are automatically set to '0' after being set to '1'. duc2 and duc1 must be set to '1' for every volume level setting while hupe = '1'. default value of d12e: 1. default value of duc2 and duc1: 0 d12e = 0 digital attenuation and mute update control disabled d12e = 1 digital attenuation and mute update control enabled (default) duc2, duc1 = 0 no update level (default) duc2, duc1 = 1 update level (set to '0' automatically after setting to '1') dz12: digital attenuation and mute zero crossing enable for dac12 this bit enables zero-crossing detection, which reduces zipper noise while the dac digital attenuator and mute settings are being changed. if no zero-crossing data are input for a 512/f s period (10.6 ms at a 48-khz sampling rate), then a timeout occurs and the pcm5310 volume level changes. zero-crossing detection cannot be used with continuous zero and dc data. default value: 1 0 disabled 1 enabled (default) db12[1:0]: digital gain boost for dac12 these bits boost the gain for the digital data input to the dac12 channels before the digital attenuation. default value: 00 00 0db (default) 01 6 db 10 12 db 11 18 db dmu2: digital mute control for dac12, r-channel dmu1: digital mute control for dac12, l-channel the pcm5310 can independently mute the dacs digital input data to zero level when dmu2 and dmu1 = '1'. these settings take precedence over the attenuation level settings set by bits dat1[7:0] and dat2[7:0] in regsiter 42. the analog outputs may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 40, dz12). default value: 0 0 mute disabled (default) 1 mute enabled copyright ? 2009, texas instruments incorporated submit documentation feedback 57 product folder link(s): pcm5310
registers 42 and 43 (2ah and 2bh) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 42 2ah digital attenuation level setting for dac12 l-channel dat1[7:0] 43 2bh digital attenuation level setting for dac12 r-channel dat2[7:0] dat1[7:0]: digital attenuation setting for dac12, l-channel dat2[7:0]: digital attenuation setting for dac12, r-channel the digital attenuator of dac12 can be independently set from 0 db to ? 100 db in 0.5-db steps. the dac12 output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero crossing detection (register 40, dz12). default value : 1111 1111 table 33. digital attenuation level setting for dac12 digital att digital att digital att digital att dat1[7:0] level dat1[7:0] level dat1[7:0] level dat1[7:0] level dat2[7:0] setting dat2[7:0] setting dat2[7:0] setting dat2[7:0] setting 1111 1111 ff 0 db (default) 1100 1100 cc ? 25.5 db 1001 1001 99 ? 51 db 0110 0110 66 ? 76.5 db 1111 1110 fe ? 0.5 db 1100 1011 cb ? 26 db 1001 1000 98 ? 51.5 db 0110 0101 65 ? 77 db 1111 1101 fd ? 1 db 1100 1010 ca ? 26.5 db 1001 0111 97 ? 52 db 0110 0100 64 ? 77.5 db 1111 1100 fc ? 1.5 db 1100 1001 c9 ? 27 db 1001 0110 96 ? 52.5 db 0110 0011 63 ? 78 db 1111 1011 fb ? 2 db 1100 1000 c8 ? 27.5 db 1001 0101 95 ? 53 db 0110 0010 62 ? 78.8 db 1111 1010 fa ? 2.5 db 1100 0111 c7 ? 28 db 1001 0100 94 ? 53.5 db 0110 0001 61 ? 79 db 1111 1001 f9 ? 3 db 1100 0110 c6 ? 28.5 db 1001 0011 93 ? 54 db 0110 0000 60 ? 79.5 db 1111 1000 f8 ? 3.5 db 1100 0101 c5 ? 29 db 1001 0010 92 ? 54.5 db 0101 1111 5f ? 80 db 1111 0111 f7 ? 4 db 1100 0100 c4 ? 29.5 db 1001 0001 91 ? 55 db 0101 1110 5e ? 80.5 db 1111 0110 f6 ? 4.5 db 1100 0011 c3 ? 30 db 1001 0000 90 ? 55.5 db 0101 1101 5d ? 81 db 1111 0101 f5 ? 5 db 1100 0010 c2 ? 30.5 db 1000 1111 8f ? 56 db 0101 1100 5c ? 81.5 db 1111 0100 f4 ? 5.5 db 1100 0001 c1 ? 31 db 1000 1110 8e ? 56.5 db 0101 1011 5b ? 82 db 1111 0011 f3 ? 6 db 1100 0000 c0 ? 31.5 db 1000 1101 8d ? 57 db 0101 1010 5a ? 82.5 db 1111 0010 f2 ? 6.5 db 1011 1111 bf ? 32 db 1000 1100 8c ? 57.5 db 0101 1001 59 ? 83 db 1111 0001 f1 ? 7 db 1011 1110 be ? 32.5 db 1000 1011 8b ? 58 db 0101 1000 58 ? 83.5 db 1111 0000 f0 ? 7.5 db 1011 1101 bd ? 33 db 1000 1010 8a ? 58.5 db 0101 0111 57 ? 84 db 1110 1111 ef ? 8 db 1011 1100 bc ? 33.5 db 1000 1001 89 ? 59 db 0101 0110 56 ? 84.5 db 1110 1110 ee ? 8.5 db 1011 1011 bb ? 34 db 1000 1000 88 ? 59.5 db 0101 0101 55 ? 85 db 1110 1101 ed ? 9 db 1011 1010 ba ? 34.5 db 1000 0111 87 ? 60 db 0101 0100 54 ? 85.5 db 1110 1100 ec ? 9.5 db 1011 1001 b9 ? 35 db 1000 0110 86 ? 60.5 db 0101 0011 53 ? 86 db 1110 1011 eb ? 10 db 1011 1000 b8 ? 35.5 db 1000 0101 85 ? 61 db 0101 0010 52 ? 86.5 db 1110 1010 ea ? 10.5 db 1011 0111 b7 ? 36 db 1000 0100 84 ? 61.5 db 0101 0001 51 ? 87 db 1110 1001 e9 ? 11 db 1011 0110 b6 ? 36.5 db 1000 0011 83 ? 62 db 0101 0000 50 ? 87.5 db 1110 1000 e8 ? 11.5 db 1011 0101 b5 ? 37 db 1000 0010 82 ? 62.5 db 0100 1111 4f ? 88 db 1110 0111 e7 ? 12 db 1011 0100 b4 ? 37.5 db 1000 0001 81 ? 63 db 0100 1110 4e ? 88.5 db 1110 0110 e6 ? 12.5 db 1011 0011 b3 ? 38 db 1000 0000 80 ? 63.5 db 0100 1101 4d ? 89 db 1110 0101 e5 ? 13 db 1011 0010 b2 ? 38.5 db 0111 1111 7f ? 64 db 0100 1100 4c ? 89.5 db 1110 0100 e4 ? 13.5 db 1011 0001 b1 ? 39 db 0111 1110 7e ? 64.5 db 0100 1011 4b ? 90 db 1110 0011 e3 ? 14 db 1011 0000 b0 ? 39.5 db 0111 1101 7d ? 65 db 0100 1010 4a ? 90.5 db 1110 0010 e2 ? 14.5 db 1010 1111 af ? 40 db 0111 1100 7c ? 65.5 db 0100 1001 49 ? 91 db 1110 0001 e1 ? 15 db 1010 1110 ae ? 40.5 db 0111 1011 7b ? 66 db 0100 1000 48 ? 91.5 db 1110 0000 e0 ? 15.5 db 1010 1101 ad ? 41 db 0111 1010 7a ? 66.5 db 0100 0111 47 ? 92 db 1101 1111 df ? 16 db 1010 1100 ac ? 41.5 db 0111 1001 79 ? 67 db 0100 0110 46 ? 92.5 db 58 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 44 and 45 (2ch and 2dh) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 table 33. digital attenuation level setting for dac12 (continued) digital att digital att digital att digital att dat1[7:0] level dat1[7:0] level dat1[7:0] level dat1[7:0] level dat2[7:0] setting dat2[7:0] setting dat2[7:0] setting dat2[7:0] setting 1101 1110 de ? 16.5 db 1010 1011 ab ? 42 db 0111 1000 78 ? 67.5 db 0100 0101 45 ? 93 db 1101 1101 dd ? 17 db 1010 1010 aa ? 42.5 db 0111 0111 77 ? 68 db 0100 0100 44 ? 93.5 db 1101 1100 dc ? 17.5 db 1010 1001 a9 ? 43 db 0111 0110 76 ? 68.5 db 0100 0011 43 ? 94 db 1101 1011 db ? 18 db 1010 1000 a8 ? 43.5 db 0111 0101 75 ? 69 db 0100 0010 42 ? 94.5 db 1101 1010 da ? 18.5 db 1010 0111 a7 ? 44 db 0111 0100 74 ? 69.5 db 0100 0001 41 ? 95 db 1101 1001 d9 ? 19 db 1010 0110 a6 ? 44.5 db 0111 0011 73 ? 70 db 0100 0000 40 ? 95.5 db 1101 1000 d8 ? 19.5 db 1010 0101 a5 ? 45 db 0111 0010 72 ? 70.5 db 0011 1111 3f ? 96 db 1101 0111 d7 ? 20 db 1010 0100 a4 ? 45.5 db 0111 0001 71 ? 71 db 0011 1110 3e ? 96.5 db 1101 0110 d6 ? 20.5 db 1010 0011 a3 ? 46 db 0111 0000 70 ? 71.5 db 0011 1101 3d ? 97 db 1101 0101 d5 ? 21 db 1010 0010 a2 ? 46.5 db 0110 1111 6f ? 72 db 0011 1100 3c ? 97.5 db 1101 0100 d4 ? 21.5 db 1010 0001 a1 ? 47 db 0110 1110 6e ? 72.5 db 0011 1011 3b ? 98 db 1101 0011 d3 ? 22 db 1010 0000 a0 ? 47.5 db 0110 1101 6d ? 73 db 0011 1010 3a ? 98.5 db 1101 0010 d2 ? 22.5 db 1001 1111 9f ? 48 db 0110 1100 6c ? 73.5 db 0011 1001 39 ? 99 db 1101 0001 d1 ? 23 db 1001 1110 9e ? 48.5 db 0110 1011 6b ? 74 db 0011 1000 38 ? 99.5 db 1101 0000 d0 ? 23.5 db 1001 1101 9d ? 49 db 0110 1010 6a ? 74.5 db 0011 0111 37 ? 100 db 1100 1111 cf ? 24 db 1001 1100 9c ? 49.5 db 0110 1001 69 ? 75 db 0011 0110 36 1100 1110 ce ? 24.5 db 1001 1011 9b ? 50 db 0110 1000 68 ? 75.5 db ? ? mute 0000 0000 00 1100 1101 cd ? 25 db 1001 1010 9a ? 50.5 db 0110 0111 67 ? 76 db reg hex description b7 b6 b5 b4 b3 b2 b1 b0 44 2ch master/slave interface format for dac12 dms12[3:0] rsv rsv dfm12[1:0] 45 2dh de-emphasis filter control for dac12 rsv rsv rsv rsv dm12 rsv df12[1:0] dms12[3:0]: master/slave audio interface setting for dac12 these bits set the master or slave mode. dac12 receives lrck and bck from port-1, port-2, port-3, port-4, port-5 or port-6 in slave mode, and generates lrck and bck from sck in master mode. default value: 1000 master/slave audio interface setting for master/slave audio interface setting for dms12[3:0] dac12 dms12[3:0] dac12 0000 reserved 1000 slave and system clock f s auto-detect mode (default) 0001 master and system clock 768 f s 1001 slave and system clock 768 f s 0010 master and system clock 512 f s 1010 slave and system clock 512 f s 0011 master and system clock 384 f s 1011 slave and system clock 384 f s 0100 master and system clock 256 f s 1100 slave and system clock 256 f s 0101 master and system clock 192 f s 1101 slave and system clock 192 f s 0110 master and system clock 128 f s 1110 slave and system clock 128 f s 0111 reserved 1111 reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 59 product folder link(s): pcm5310
register 46 (2eh) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com dfm12[1:0]: audio interface format for dac12 these bits select the dac12 audio data format as i 2 s, right-justified, or left-justified. default value: 00 00 16 to 24 bits, i 2 s (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified dm12: de-emphasis filter enable for dac12 this bit enables the dac12 de-emphasis filter. the frequency can be selected by setting bits df12[1:0] of register 45. default value: 0 0 disable (default) 1 enable df12[1:0]: de-emphasis filter sampling rate selection for dac12 a digital de-emphasis filter is in front of the interpolation filter. one of three de-emphasis filters can be selected corresponding to the sampling rate: 32 khz, 44.1 khz, or 48 khz. default value: 00 00 44.1 khz (default) 01 48 khz 10 32 khz 11 reserved reg hex description b7 b6 b5 b4 b3 b2 b1 b0 46 2eh power up/down, oversampling rate control for dac12 pd12 rsv ov12[1:0] zr12 rsv rsv rsv pd12: power up/down control for dac12 this bit controls the power up/down for dac12, including the interpolation filter. default value: 1 0 power up 1 power down (default) ov12[1:0]: oversampling rate control for dac12 these bits are used to control the oversampling rate of the dac12 delta-sigma modulator. default value: 01 system clock rate ov12 128 f s , 192 f s 256 f s , 384 f s 128 f s , 192 f s 00 16 f s 32 f s 64 f s 01 (default) 32 f s 64 f s 128 f s 10 ? ? 11 32 f s 128 f s (1) 128 f s (1) (1) less than f s = 48 khz 60 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 50 and 51 (32h and 33h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 zr12: zero flag reverse this bit reverses the polarity of the zero flag output. the zero flag goes from low to high after the digital input data are continuously zero during 1024 f s when zr12 = '0'. the zero flag can output from the gpio pins by setting registers 9 to 11 (gsl1[4:0], gsl2[4:0], gsl3[4:0]). default value: 0 0 buffered output (default) 1 inverted output reg hex description b7 b6 b5 b4 b3 b2 b1 b0 50 32h digital attenuation and mute control for dac34 d34e rsv duc4 duc3 rsv rsv rsv dz34 51 33h digital gain boost and digital soft mute for dac34 rsv rsv rsv rsv db34[1:0] dmu4 dmu3 d34e: digital attenuation and mute update control enable for dac34 duc4: digital attenuation and mute setting update for dac34, r-channel duc3: digital attenuation and mute setting update for dac34, l-channel the digital attenuation and mute levels of dac34 can be changed independently to any level by setting bits dmu4 and dmu3 in register 51, bits dat3[7:0] in register 52, and bits dat4[7:0] in register 53 when d34e = '0'. when d34e = '1', the level is changed to any level at the same time when duc4 = '1' or duc3 = '1'. both bits are automatically set to '0' after they are set to '1'. duc4 and duc3 must be set to '1' for every volume level setting while d34e = '1'. default value of d34e: 1. default value of duc4 and duc3: 0 d34e = 0 digital attenuation and mute update control disabled d34e = 1 digital attenuation and mute update control enabled (default) duc4, duc3 = 0 no update level (default) duc4, duc3 = 1 update level (set to '0' automatically after setting to '1') dz34: digital attenuation and mute zero cross enable for dac34 this bit enables zero-crossing detection, which reduces zipper noise while the dac digital attenuator and mute settings are being changed. if no zero-crossing data are input for a 512/f s period (10.6 ms at a 48-khz sampling rate), then a timeout occurs and the pcm5310 volume level changes. zero-crossing detection cannot be used with continuous zero and dc data. default value: 1 0 disable 1 enable (default) db34[1:0]: digital gain boost for dac34 these bits are used to boost the gain of digital data input to the dacs in front of the digital attenuator. default value: 00 00 0 db (default) 01 6 db 10 12 db 11 18 db copyright ? 2009, texas instruments incorporated submit documentation feedback 61 product folder link(s): pcm5310
registers 52 and 53 (34h and 35h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com dmu4: digital mute control for dac34, r-channel dmu3: digital mute control for dac34, l-channel the pcm5310 can independently mute the dac digital input data to a zero level when dmu4 and dmu3 = '1'. these settings take precedence over the attenuation level settings of bits dat3[7:0] and dat4[7:0] in registers 52 and 53. the analog outputs may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 50, dz34). default value: 0 0 mute disabled (default) 1 mute enabled reg hex description b7 b6 b5 b4 b3 b2 b1 b0 52 34h digital attenuation level setting for dac34 l-channel dat3[7:0] 53 35h digital attenuation level setting for dac34 r-channel dat4[7:0] dat3[7:0]: digital attenuation setting for dac34, l-channel dat4[7:0]: digital attenuation setting for dac34, r-channel the digital attenuator of dac34 can be independently set from 0 db to ? 100 db in 0.5-db steps. the dac34 output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero crossing detection (register 50, dz34). default value : 1111 1111 table 34. digital attenuation level setting for dac34 digital att digital att digital att digital att dat3[7:0] level dat3[7:0] level dat3[7:0] level dat3[7:0] level dat4[7:0] setting dat4[7:0] setting dat4[7:0] setting dat4[7:0] setting 1111 1111 ff 0 db (default) 1100 1100 cc ? 25.5 db 1001 1001 99 ? 51 db 0110 0110 66 ? 76.5 db 1111 1110 fe ? 0.5 db 1100 1011 cb ? 26 db 1001 1000 98 ? 51.5 db 0110 0101 65 ? 77 db 1111 1101 fd ? 1 db 1100 1010 ca ? 26.5 db 1001 0111 97 ? 52 db 0110 0100 64 ? 77.5 db 1111 1100 fc ? 1.5 db 1100 1001 c9 ? 27 db 1001 0110 96 ? 52.5 db 0110 0011 63 ? 78 db 1111 1011 fb ? 2 db 1100 1000 c8 ? 27.5 db 1001 0101 95 ? 53 db 0110 0010 62 ? 78.8 db 1111 1010 fa ? 2.5 db 1100 0111 c7 ? 28 db 1001 0100 94 ? 53.5 db 0110 0001 61 ? 79 db 1111 1001 f9 ? 3 db 1100 0110 c6 ? 28.5 db 1001 0011 93 ? 54 db 0110 0000 60 ? 79.5 db 1111 1000 f8 ? 3.5 db 1100 0101 c5 ? 29 db 1001 0010 92 ? 54.5 db 0101 1111 5f ? 80 db 1111 0111 f7 ? 4 db 1100 0100 c4 ? 29.5 db 1001 0001 91 ? 55 db 0101 1110 5e ? 80.5 db 1111 0110 f6 ? 4.5 db 1100 0011 c3 ? 30 db 1001 0000 90 ? 55.5 db 0101 1101 5d ? 81 db 1111 0101 f5 ? 5 db 1100 0010 c2 ? 30.5 db 1000 1111 8f ? 56 db 0101 1100 5c ? 81.5 db 1111 0100 f4 ? 5.5 db 1100 0001 c1 ? 31 db 1000 1110 8e ? 56.5 db 0101 1011 5b ? 82 db 1111 0011 f3 ? 6 db 1100 0000 c0 ? 31.5 db 1000 1101 8d ? 57 db 0101 1010 5a ? 82.5 db 1111 0010 f2 ? 6.5 db 1011 1111 bf ? 32 db 1000 1100 8c ? 57.5 db 0101 1001 59 ? 83 db 1111 0001 f1 ? 7 db 1011 1110 be ? 32.5 db 1000 1011 8b ? 58 db 0101 1000 58 ? 83.5 db 1111 0000 f0 ? 7.5 db 1011 1101 bd ? 33 db 1000 1010 8a ? 58.5 db 0101 0111 57 ? 84 db 1110 1111 ef ? 8 db 1011 1100 bc ? 33.5 db 1000 1001 89 ? 59 db 0101 0110 56 ? 84.5 db 1110 1110 ee ? 8.5 db 1011 1011 bb ? 34 db 1000 1000 88 ? 59.5 db 0101 0101 55 ? 85 db 1110 1101 ed ? 9 db 1011 1010 ba ? 34.5 db 1000 0111 87 ? 60 db 0101 0100 54 ? 85.5 db 1110 1100 ec ? 9.5 db 1011 1001 b9 ? 35 db 1000 0110 86 ? 60.5 db 0101 0011 53 ? 86 db 1110 1011 eb ? 10 db 1011 1000 b8 ? 35.5 db 1000 0101 85 ? 61 db 0101 0010 52 ? 86.5 db 1110 1010 ea ? 10.5 db 1011 0111 b7 ? 36 db 1000 0100 84 ? 61.5 db 0101 0001 51 ? 87 db 1110 1001 e9 ? 11 db 1011 0110 b6 ? 36.5 db 1000 0011 83 ? 62 db 0101 0000 50 ? 87.5 db 62 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 table 34. digital attenuation level setting for dac34 (continued) digital att digital att digital att digital att dat3[7:0] level dat3[7:0] level dat3[7:0] level dat3[7:0] level dat4[7:0] setting dat4[7:0] setting dat4[7:0] setting dat4[7:0] setting 1110 1000 e8 ? 11.5 db 1011 0101 b5 ? 37 db 1000 0010 82 ? 62.5 db 0100 1111 4f ? 88 db 1110 0111 e7 ? 12 db 1011 0100 b4 ? 37.5 db 1000 0001 81 ? 63 db 0100 1110 4e ? 88.5 db 1110 0110 e6 ? 12.5 db 1011 0011 b3 ? 38 db 1000 0000 80 ? 63.5 db 0100 1101 4d ? 89 db 1110 0101 e5 ? 13 db 1011 0010 b2 ? 38.5 db 0111 1111 7f ? 64 db 0100 1100 4c ? 89.5 db 1110 0100 e4 ? 13.5 db 1011 0001 b1 ? 39 db 0111 1110 7e ? 64.5 db 0100 1011 4b ? 90 db 1110 0011 e3 ? 14 db 1011 0000 b0 ? 39.5 db 0111 1101 7d ? 65 db 0100 1010 4a ? 90.5 db 1110 0010 e2 ? 14.5 db 1010 1111 af ? 40 db 0111 1100 7c ? 65.5 db 0100 1001 49 ? 91 db 1110 0001 e1 ? 15 db 1010 1110 ae ? 40.5 db 0111 1011 7b ? 66 db 0100 1000 48 ? 91.5 db 1110 0000 e0 ? 15.5 db 1010 1101 ad ? 41 db 0111 1010 7a ? 66.5 db 0100 0111 47 ? 92 db 1101 1111 df ? 16 db 1010 1100 ac ? 41.5 db 0111 1001 79 ? 67 db 0100 0110 46 ? 92.5 db 1101 1110 de ? 16.5 db 1010 1011 ab ? 42 db 0111 1000 78 ? 67.5 db 0100 0101 45 ? 93 db 1101 1101 dd ? 17 db 1010 1010 aa ? 42.5 db 0111 0111 77 ? 68 db 0100 0100 44 ? 93.5 db 1101 1100 dc ? 17.5 db 1010 1001 a9 ? 43 db 0111 0110 76 ? 68.5 db 0100 0011 43 ? 94 db 1101 1011 db ? 18 db 1010 1000 a8 ? 43.5 db 0111 0101 75 ? 69 db 0100 0010 42 ? 94.5 db 1101 1010 da ? 18.5 db 1010 0111 a7 ? 44 db 0111 0100 74 ? 69.5 db 0100 0001 41 ? 95 db 1101 1001 d9 ? 19 db 1010 0110 a6 ? 44.5 db 0111 0011 73 ? 70 db 0100 0000 40 ? 95.5 db 1101 1000 d8 ? 19.5 db 1010 0101 a5 ? 45 db 0111 0010 72 ? 70.5 db 0011 1111 3f ? 96 db 1101 0111 d7 ? 20 db 1010 0100 a4 ? 45.5 db 0111 0001 71 ? 71 db 0011 1110 3e ? 96.5 db 1101 0110 d6 ? 20.5 db 1010 0011 a3 ? 46 db 0111 0000 70 ? 71.5 db 0011 1101 3d ? 97 db 1101 0101 d5 ? 21 db 1010 0010 a2 ? 46.5 db 0110 1111 6f ? 72 db 0011 1100 3c ? 97.5 db 1101 0100 d4 ? 21.5 db 1010 0001 a1 ? 47 db 0110 1110 6e ? 72.5 db 0011 1011 3b ? 98 db 1101 0011 d3 ? 22 db 1010 0000 a0 ? 47.5 db 0110 1101 6d ? 73 db 0011 1010 3a ? 98.5 db 1101 0010 d2 ? 22.5 db 1001 1111 9f ? 48 db 0110 1100 6c ? 73.5 db 0011 1001 39 ? 99 db 1101 0001 d1 ? 23 db 1001 1110 9e ? 48.5 db 0110 1011 6b ? 74 db 0011 1000 38 ? 99.5 db 1101 0000 d0 ? 23.5 db 1001 1101 9d ? 49 db 0110 1010 6a ? 74.5 db 0011 0111 37 ? 100 db 1100 1111 cf ? 24 db 1001 1100 9c ? 49.5 db 0110 1001 69 ? 75 db 0011 0110 36 1100 1110 ce ? 24.5 db 1001 1011 9b ? 50 db 0110 1000 68 ? 75.5 db ? ? mute 0000 0000 00 1100 1101 cd ? 25 db 1001 1010 9a ? 50.5 db 0110 0111 67 ? 76 db copyright ? 2009, texas instruments incorporated submit documentation feedback 63 product folder link(s): pcm5310
registers 54 and 55 (36h and 37h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 54 36h master/slave interface format for dac34 dms34[3:0] rsv rsv dfm34[1:0] 55 37h de-emphasis filter control for dac34 rsv rsv rsv rsv dm34 rsv df34[1:0] dms34[3:0]: master/slave audio interface setting for dac34 these bits set the master or slave mode. dac34 receives lrck and bck from port-1, port-2, port-3, port-4, port-5 or port-6 in slave mode, and generates lrck and bck from sck in master mode. default value: 1000 master/slave audio interface setting for master/slave audio interface setting for dms34[3:0] dac34 dms34[3:0] dac34 0000 reserved 1000 slave and system clock f s auto-detect mode (default) 0001 master and system clock 768 f s 1001 slave and system clock 768 f s 0010 master and system clock 512 f s 1010 slave and system clock 512 f s 0011 master and system clock 384 f s 1011 slave and system clock 384 f s 0100 master and system clock 256 f s 1100 slave and system clock 256 f s 0101 master and system clock 192 f s 1101 slave and system clock 192 f s 0110 master and system clock 128 f s 1110 slave and system clock 128 f s 0111 reserved 1111 reserved dfm34[1:0]: audio interface format for dac34 these bits select the dac34 audio data format as i 2 s, right-justified, or left-justified. default value: 00 00 16 to 24 bits, i 2 s (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified dm34: de-emphasis filter enable for dac34 this bit enables the dac34 de-emphasis filter. the frequency can be selected by setting bits df34[1:0] of register 55. default value: 0 0 disable (default) 1 enable df34[1:0]: de-emphasis filter sampling rate selection for dac34 a digital de-emphasis filter is in front of the interpolation filter. one of three de-emphasis filters can be selected corresponding to the sampling rate: 32 khz, 44.1 khz, or 48 khz. default value: 00 00 44.1 khz (default) 01 48 khz 10 32 khz 11 reserved 64 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 56 (38h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 56 38h power up/down, oversampling rate control for dac34 pd34 rsv ov34[1:0] zr34 rsv rsv rsv pd34: power up/down control for dac34 this bit controls the power up/down for dac34, including the interpolation filter. default value: 1 0 power up 1 power down (default) ov34[1:0]: oversampling rate control for dac34 these bits control the oversampling rate of the dac34 delta-sigma modulator. default value: 01 system clock rate ov34 128 f s , 192 f s 256 f s , 384 f s 128 f s , 192 f s 00 16 f s 32 f s 64 f s 01 (default) 32 f s 64 f s 128 f s 10 ? ? 11 32 f s 128 f s (1) 128 f s (1) (1) less than f s = 48 khz zr34: zero flag reverse this bit reverses the polarity of the zero flag output. the zero flag is high after input data are zero during 1024 f s when zr34 = '0', and is set with the gpio port by bits gsl1[4:0], gsl2[4:0], gsl3[4:0] in registers 09 to 11. default value: 0 0 buffered output (default) 1 inverted output copyright ? 2009, texas instruments incorporated submit documentation feedback 65 product folder link(s): pcm5310
registers 80 and 81 (50h and 51h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 80 50h digital attenuation and mute control for adc12 a12e rsv auc2 auc1 rsv rsv rsv az12 81 51h digital soft mute for adc12 rsv fs12 rsv rsv rsv rsv amu2 amu1 a12e: digital attenuation and mute update control enable for adc12 auc2: digital attenuation and mute setting update for adc12, r-channel auc1: digital attenuation and mute setting update for adc12, l-channel the digital attenuation and mute levels of adc12 can be changed independently to any level by setting bits amu2 and amu1 in register 81, bits aat1[7:0] in register 82, and bits aat2[7:0] in register 83 when a12e = '0'. when a12e = '1', the level is changed to any level at the same time when auc2 = '1' or auc1 = '1'. both bits are automatically set to '0' after they are set to '1'. auc2 and auc1 must be set to '1' for every volume level setting while a12e = '1'. default value of a12e: 1. default value of auc2 and auc1: 0 a12e = 0 digital attenuation and mute update control disabled a12e = 1 digital attenuation and mute update control enabled (default) auc2, auc1 = 0 no update level (default) auc2, auc1 = 1 update level (set to '1' automatically after setting to '0') az12: digital attenuation and mute zero crossing enable for adc12 this bit enables zero-crossing detection, which reduces zipper noise while the adc digital attenuator and mute settings are being changed. if no zero-crossing data are input for a 512/f s period (10.6 ms at a 48-khz sampling rate), then a timeout occurs and the pcm5310 volume level changes. zero-crossing detection cannot be used with continuous zero and dc data. default value: 1 0 disable 1 enable (default) fs12: sampling rate selection for adc12 this bit is used to select the ads12 sampling rate. fs12 must be set to '1' when the sampling rate is greater than 48 khz. default value: 0 0 f s 48 khz (default) 1 f s > 48 khz amu2: digital mute control for adc12, r-channel amu1: digital mute control for adc12, l-channel the pcm5310 can independently mute the dac digital input data to a zero level when amu2 and amu1 = '1'. these settings take precedence over the attenuation level settings of bits aat1[7:0] and aat2[7:0] in registers 82 and 83. the analog outputs may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 80, az12). default value: 0 0 mute disabled (default) 1 mute enabled 66 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
registers 82 and 83 (52h and 53h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 82 52h digital attenuation level setting for adc12 l-channel aat1[7:0] 83 53h digital attenuation level setting for adc12 r-channel aat2[7:0] aat1[7:0]: digital attenuation setting for adc12, l-channel aat2[7:0]: digital attenuation setting for adc12, r-channel the digital attenuator of adc12 can be independently set from 20 db to ? 100 db in 0.5-db steps. the adc12 output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero crossing detection (register 80, az12). default value : 1101 0111 table 35. digital attenuation level setting for adc12 digital att digital att digital att digital att aat1[7:0] level aat1[7:0] level aat1[7:0] level aat1[7:0] level aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting 1111 1111 ff 20 db 1100 0010 c2 ? 10.5 db 1000 0101 85 ? 41 db 0100 1000 48 ? 71.5 db 1111 1110 fe 19.5 db 1100 0001 c1 ? 11 db 1000 0100 84 ? 41.5 db 0100 0111 47 ? 72 db 1111 1101 fd 19 db 1100 0000 c0 ? 11.5 db 1000 0011 83 ? 42 db 0100 0110 46 ? 72.5 db 1111 1100 fc 18.5 db 1011 1111 bf ? 12 db 1000 0010 82 ? 42.5 db 0100 0101 45 ? 73 db 1111 1011 fb 18 db 1011 1110 be ? 12.5 db 1000 0001 81 ? 43 db 0100 0100 44 ? 73.5 db 1111 1010 fa 17.5 db 1011 1101 bd ? 13 db 1000 0000 80 ? 43.5 db 0100 0011 43 ? 74 db 1111 1001 f9 17 db 1011 1100 bc ? 13.5 db 0111 1111 7f ? 44 db 0100 0010 42 ? 74.5 db 1111 1000 f8 16.5 db 1011 1011 bb ? 14 db 0111 1110 7e ? 44.5 db 0100 0001 41 ? 75 db 1111 0111 f7 16 db 1011 1010 ba ? 14.5 db 0111 1101 7d ? 45 db 0100 0000 40 ? 75.5 db 1111 0110 f6 15.5 db 1011 1001 b9 ? 15 db 0111 1100 7c ? 45.5 db 0011 1111 3f ? 76 db 1111 0101 f5 15 db 1011 1000 b8 ? 15.5 db 0111 1011 7b ? 46 db 0011 1110 3e ? 76.5 db 1111 0100 f4 14.5 db 1011 0111 b7 ? 16 db 0111 1010 7a ? 46.5 db 0011 1101 3d ? 77 db 1111 0011 f3 14 db 1011 0110 b6 ? 16.5 db 0111 1001 79 ? 47 db 0011 1100 3c ? 77.5 db 1111 0010 f2 13.5 db 1011 0101 b5 ? 17 db 0111 1000 78 ? 47.5 db 0011 1011 3b ? 78 db 1111 0001 f1 13 db 1011 0100 b4 ? 17.5 db 0111 0111 77 ? 48 db 0011 1010 3a ? 78.8 db 1111 0000 f0 12.5 db 1011 0011 b3 ? 18 db 0111 0110 76 ? 48.5 db 0011 1001 39 ? 79 db 1110 1111 ef 12 db 1011 0010 b2 ? 18.5 db 0111 0101 75 ? 49 db 0011 1000 38 ? 79.5 db 1110 1110 ee 11.5 db 1011 0001 b1 ? 19 db 0111 0100 74 ? 49.5 db 0011 0111 37 ? 80 db 1110 1101 ed 11 db 1011 0000 b0 ? 19.5 db 0111 0011 73 ? 50 db 0011 0110 36 ? 80.5 db 1110 1100 ec 10.5 db 1010 1111 af ? 20 db 0111 0010 72 ? 50.5 db 0011 0101 35 ? 81 db 1110 1011 eb 10 db 1010 1110 ae ? 20.5 db 0111 0001 71 ? 51 db 0011 0100 34 ? 81.5 db 1110 1010 ea 9.5 db 1010 1101 ad ? 21 db 0111 0000 70 ? 51.5 db 0011 0011 33 ? 82 db 1110 1001 e9 9 db 1010 1100 ac ? 21.5 db 0110 1111 6f ? 52 db 0011 0010 32 ? 82.5 db 1110 1000 e8 8.5 db 1010 1011 ab ? 22 db 0110 1110 6e ? 52.5 db 0011 0001 31 ? 83 db 1110 0111 e7 8 db 1010 1010 aa ? 22.5 db 0110 1101 6d ? 53 db 0011 0000 30 ? 83.5 db 1110 0110 e6 7.5 db 1010 1001 a9 ? 23 db 0110 1100 6c ? 53.5 db 0010 1111 2f ? 84 db 1110 0101 e5 7 db 1010 1000 a8 ? 23.5 db 0110 1011 6b ? 54 db 0010 1110 2e ? 84.5 db 1110 0100 e4 6.5 db 1010 0111 a7 ? 24 db 0110 1010 6a ? 54.5 db 0010 1101 2d ? 85 db 1110 0011 e3 6 db 1010 0110 a6 ? 24.5 db 0110 1001 69 ? 55 db 0010 1100 2c ? 85.5 db 1110 0010 e2 5.5 db 1010 0101 a5 ? 25 db 0110 1000 68 ? 55.5 db 0010 1011 2b ? 86 db 1110 0001 e1 5 db db 1010 0100 a4 ? 25.5 db 0110 0111 67 ? 56 db 0010 1010 2a ? 86.5 db 1110 0000 e0 4.5 db 1010 0011 a3 ? 26 db 0110 0110 66 ? 56.5 db 0010 1001 29 ? 87 db 1101 1111 df 4 db 1010 0010 a2 ? 26.5 db 0110 0101 65 ? 57 db 0010 1000 28 ? 87.5 db copyright ? 2009, texas instruments incorporated submit documentation feedback 67 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com table 35. digital attenuation level setting for adc12 (continued) digital att digital att digital att digital att aat1[7:0] level aat1[7:0] level aat1[7:0] level aat1[7:0] level aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting 1101 1110 de 3.5 db 1010 0001 a1 ? 27 db 0110 0100 64 ? 57.5 db 0010 0111 27 ? 88 db 1101 1101 dd 3 db 1010 0000 a0 ? 27.5 db 0110 0011 63 ? 58 db 0010 0110 26 ? 88.5 db 1101 1100 dc 2.5 db 1001 1111 9f ? 28 db 0110 0010 62 ? 58.5 db 0010 0101 25 ? 89 db 1101 1011 db 2 db 1001 1110 9e ? 28.5 db 0110 0001 61 ? 59 db 0010 0100 24 ? 89.5 db 1101 1010 da 1.5 db 1001 1101 9d ? 29 db 0110 0000 60 ? 59.5 db 0010 0011 23 ? 90 db 1101 1001 d9 1 db 1001 1100 9c ? 29.5 db 0101 1111 5f ? 60 db 0010 0010 22 ? 90.5 db 1101 1000 d8 0.5 db 1001 1011 9b ? 30 db 0101 1110 5e ? 60.5 db 0010 0001 21 ? 91 db 1101 0111 d7 0 db (default) 1001 1010 9a ? 30.5 db 0101 1101 5d ? 61 db 0010 0000 20 ? 91.5 db 1101 0110 d6 ? 0.5 db 1001 1001 99 ? 31 db 0101 1100 5c ? 61.5 db 0001 1111 1f ? 92 db 1101 0101 d5 ? 1 db 1001 1000 98 ? 31.5 db 0101 1011 5b ? 62 db 0001 1110 1e ? 92.5 db 1101 0100 d4 ? 1.5 db 1001 0111 97 ? 32 db 0101 1010 5a ? 62.5 db 0001 1101 1d ? 93 db 1101 0011 d3 ? 2 db 1001 0110 96 ? 32.5 db 0101 1001 59 ? 63 db 0001 1100 1c ? 93.5 db 1101 0010 d2 ? 2.5 db 1001 0101 95 ? 33 db 0101 1000 58 ? 63.5 db 0001 1011 1b ? 94 db 1101 0001 d1 ? 3 db 1001 0100 94 ? 33.5 db 0101 0111 57 ? 64 db 0001 1010 1a ? 94.5 db 1101 0000 d0 ? 3.5 db 1001 0011 93 ? 34 db 0101 0110 56 ? 64.5 db 0001 1001 19 ? 95 db 1100 1111 cf ? 4 db 1001 0010 92 ? 34.5 db 0101 0101 55 ? 65 db 0001 1000 18 ? 95.5 db 1100 1110 ce ? 4.5 db 1001 0001 91 ? 35 db 0101 0100 54 ? 65.5 db 0001 0111 17 ? 96 db 1100 1101 cd ? 5 db 1001 0000 90 ? 35.5 db 0101 0011 53 ? 66 db 0001 0110 16 ? 96.5 db 1100 1100 cc ? 5.5 db 1000 1111 8f ? 36 db 0101 0010 52 ? 66.5 db 0001 0101 15 ? 97 db 1100 1011 cb ? 6 db 1000 1110 8e ? 36.5 db 0101 0001 51 ? 67 db 0001 0100 14 ? 97.5 db 1100 1010 ca ? 6.5 db 1000 1101 8d ? 37 db 0101 0000 50 ? 67.5 db 0001 0011 13 ? 98 db 1100 1001 c9 ? 7 db 1000 1100 8c ? 37.5 db 0100 1111 4f ? 68 db 0001 0010 12 ? 98.5 db 1100 1000 c8 ? 7.5 db 1000 1011 8b ? 38 db 0100 1110 4e ? 68.5 db 0001 0001 11 ? 99 db 1100 0111 c7 ? 8 db 1000 1010 8a ? 38.5 db 0100 1101 4d ? 69 db 0001 0000 10 ? 99.5 db 1100 0110 c6 ? 8.5 db 1000 1001 89 ? 39 db 0100 1100 4c ? 69.5 db 0000 1111 0f ? 100 db 1100 0101 c5 ? 9 db 1000 1000 88 ? 39.5 db 0100 1011 4b ? 70 db 0000 1110 0e 1100 0100 c4 ? 9.5 db 1000 0111 87 ? 40 db 0100 1010 4a ? 70.5 db ? ? mute 0000 0000 00 1100 0011 c3 ? 10 db 1000 0110 86 ? 40.5 db 0100 1001 49 ? 71 db 68 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 84 (54h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 84 54h master/slave interface format for adc12 ams12[3:0] hf12 rsv afm12[1:0] ams12[3:0]: master/slave audio interface setting for adc12 these bits set the master or slave mode. adc12 receives lrck and bck from port-1, port-2, port-3, port-4, port-5 or port-6 in slave mode, and generates lrck and bck from sck in master mode. default value: 1000 master/slave audio interface setting for master/slave audio interface setting for ams12[3:0] adc12 ams12[3:0] adc12 0000 reserved 1000 slave and system clock f s auto-detect mode (default) 0001 master and system clock 768 f s 1001 slave and system clock 768 f s 0010 master and system clock 512 f s 1010 slave and system clock 512 f s 0011 master and system clock 384 f s 1011 slave and system clock 384 f s 0100 master and system clock 256 f s 1100 slave and system clock 256 f s 0101 reserved 1101 reserved 0110 reserved 1110 reserved 0111 reserved 1111 reserved hf12: high-pass filter disable for adc12 this bit disables the digital high-pass filter of adc12. default value: 0 0 (0.019 f s /1000) hz (default) 1 off afm12[1:0]: audio interface format for adc12 these bits select the adc12 audio data format as i 2 s, right-justified, or left-justified. default value: 00 00 16 to 24 bits, i 2 s (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified copyright ? 2009, texas instruments incorporated submit documentation feedback 69 product folder link(s): pcm5310
register 85 (55h) register 90 (5ah) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 85 55h power up/down for adc12 pa12 rsv rsv rsv rsv rsv rsv rsv pa12: power up/down control for adc12 this bit controls the power up/down for adc12, including the decimation filter. default value: 1 0 power up 1 power down (default) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 90 5ah digital attenuation and mute control for adc34 a34e rsv auc4 auc3 rsv rsv rsv az34 a34e: digital attenuation and mute update control enable for adc34 auc4: digital attenuation and mute setting update for adc34, r-channel auc3: digital attenuation and mute setting update for adc34, l-channel the digital attenuation and mute levels of adc12 can be changed independently to any level by setting bits amu4 and amu3 in register 91, bits aat3[7:0] in register 92, and bits aat4[7:0] in register 93 when a34e = '0'. when a34e = '1', the level is changed to any level at the same time when auc4 = '1' or auc3 = '1'. both bits are automatically set to '0' after they are to '1'. auc4 and auc3 must be set to '1' for every volume level setting while a34e = '1'. default value of a34e: 1. default value of auc4 and auc3: 0 a34e = 0 digital attenuation and mute update control disabled a34e = 1 digital attenuation and mute update control enabled (default) auc4, auc3 = 0 no update level (default) auc4, auc3 = 1 update level (set to '0' automatically after setting to '1') az34: digital attenuation and mute zero cross enable for adc34 this bit enables zero-crossing detection, which reduces zipper noise while the adc digital attenuator and mute settings are being changed. if no zero-crossing data are input for a 512/f s period (10.6 ms at a 48-khz sampling rate), then a timeout occurs and the pcm5310 volume level changes. zero-crossing detection cannot be used with continuous zero and dc data. default value: 1 0 disable 1 enable (default) 70 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 91 (5bh) registers 92 and 93 (5ch and 5dh) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 91 5bh digital soft mute for adc34 rsv fs34 rsv rsv rsv rsv amu4 amu3 fs34: sampling rate selection for adc34 this bit sets the ads34 sampling rate. fs34 must be set to '1' when the sampling rate is greater than 48 khz. default value: 0 0 f s 48 khz (default) 1 f s > 48 khz amu4: digital mute control for adc34, r-channel amu3: digital mute control for adc34, l-channel the pcm5310 can independently mute the dac digital input data to a zero level when amu4 and amu3 = '1'. these settings take precedence over the attenuation level settings of bits aat3[7:0] and aat4[7:0] in registers 92 and 93. the analog outputs may have audible zipper noise while changing levels. this noise can be reduced by selecting zero-crossing detection (register 90, az34). default value: 0 0 mute disabled (default) 1 mute enabled reg hex description b7 b6 b5 b4 b3 b2 b1 b0 92 5ch digital attenuation level setting for adc34 l-channel aat3[7:0] 93 5dh digital attenuation level setting for adc34 r-channel aat4[7:0] aat3[7:0]: digital attenuation setting for adc34, l-channel aat4[7:0]: digital attenuation setting for adc34, r-channel the digital attenuator of adc34 can be independently set from 20 db to ? 100 db in 0.5-db steps. the adc34 output may have audible zipper noise while changing levels. this noise can be reduced by selecting zero crossing detection (register 90, az34). default value : 1101 0111 table 36. digital attenuation level setting for adc34 digital att digital att digital att digital att aat1[7:0] level aat1[7:0] level aat1[7:0] level aat1[7:0] level aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting 1111 1111 ff 20 db 1100 0010 c2 ? 10.5 db 1000 0101 85 ? 41 db 0100 1000 48 ? 71.5 db 1111 1110 fe 19.5 db 1100 0001 c1 ? 11 db 1000 0100 84 ? 41.5 db 0100 0111 47 ? 72 db 1111 1101 fd 19 db 1100 0000 c0 ? 11.5 db 1000 0011 83 ? 42 db 0100 0110 46 ? 72.5 db 1111 1100 fc 18.5 db 1011 1111 bf ? 12 db 1000 0010 82 ? 42.5 db 0100 0101 45 ? 73 db 1111 1011 fb 18 db 1011 1110 be ? 12.5 db 1000 0001 81 ? 43 db 0100 0100 44 ? 73.5 db 1111 1010 fa 17.5 db 1011 1101 bd ? 13 db 1000 0000 80 ? 43.5 db 0100 0011 43 ? 74 db 1111 1001 f9 17 db 1011 1100 bc ? 13.5 db 0111 1111 7f ? 44 db 0100 0010 42 ? 74.5 db 1111 1000 f8 16.5 db 1011 1011 bb ? 14 db 0111 1110 7e ? 44.5 db 0100 0001 41 ? 75 db 1111 0111 f7 16 db 1011 1010 ba ? 14.5 db 0111 1101 7d ? 45 db 0100 0000 40 ? 75.5 db 1111 0110 f6 15.5 db 1011 1001 b9 ? 15 db 0111 1100 7c ? 45.5 db 0011 1111 3f ? 76 db 1111 0101 f5 15 db 1011 1000 b8 ? 15.5 db 0111 1011 7b ? 46 db 0011 1110 3e ? 76.5 db 1111 0100 f4 14.5 db 1011 0111 b7 ? 16 db 0111 1010 7a ? 46.5 db 0011 1101 3d ? 77 db 1111 0011 f3 14 db 1011 0110 b6 ? 16.5 db 0111 1001 79 ? 47 db 0011 1100 3c ? 77.5 db 1111 0010 f2 13.5 db 1011 0101 b5 ? 17 db 0111 1000 78 ? 47.5 db 0011 1011 3b ? 78 db 1111 0001 f1 13 db 1011 0100 b4 ? 17.5 db 0111 0111 77 ? 48 db 0011 1010 3a ? 78.8 db copyright ? 2009, texas instruments incorporated submit documentation feedback 71 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com table 36. digital attenuation level setting for adc34 (continued) digital att digital att digital att digital att aat1[7:0] level aat1[7:0] level aat1[7:0] level aat1[7:0] level aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting aat2[7:0] setting 1111 0000 f0 12.5 db 1011 0011 b3 ? 18 db 0111 0110 76 ? 48.5 db 0011 1001 39 ? 79 db 1110 1111 ef 12 db 1011 0010 b2 ? 18.5 db 0111 0101 75 ? 49 db 0011 1000 38 ? 79.5 db 1110 1110 ee 11.5 db 1011 0001 b1 ? 19 db 0111 0100 74 ? 49.5 db 0011 0111 37 ? 80 db 1110 1101 ed 11 db 1011 0000 b0 ? 19.5 db 0111 0011 73 ? 50 db 0011 0110 36 ? 80.5 db 1110 1100 ec 10.5 db 1010 1111 af ? 20 db 0111 0010 72 ? 50.5 db 0011 0101 35 ? 81 db 1110 1011 eb 10 db 1010 1110 ae ? 20.5 db 0111 0001 71 ? 51 db 0011 0100 34 ? 81.5 db 1110 1010 ea 9.5 db 1010 1101 ad ? 21 db 0111 0000 70 ? 51.5 db 0011 0011 33 ? 82 db 1110 1001 e9 9 db 1010 1100 ac ? 21.5 db 0110 1111 6f ? 52 db 0011 0010 32 ? 82.5 db 1110 1000 e8 8.5 db 1010 1011 ab ? 22 db 0110 1110 6e ? 52.5 db 0011 0001 31 ? 83 db 1110 0111 e7 8 db 1010 1010 aa ? 22.5 db 0110 1101 6d ? 53 db 0011 0000 30 ? 83.5 db 1110 0110 e6 7.5 db 1010 1001 a9 ? 23 db 0110 1100 6c ? 53.5 db 0010 1111 2f ? 84 db 1110 0101 e5 7 db 1010 1000 a8 ? 23.5 db 0110 1011 6b ? 54 db 0010 1110 2e ? 84.5 db 1110 0100 e4 6.5 db 1010 0111 a7 ? 24 db 0110 1010 6a ? 54.5 db 0010 1101 2d ? 85 db 1110 0011 e3 6 db 1010 0110 a6 ? 24.5 db 0110 1001 69 ? 55 db 0010 1100 2c ? 85.5 db 1110 0010 e2 5.5 db 1010 0101 a5 ? 25 db 0110 1000 68 ? 55.5 db 0010 1011 2b ? 86 db 1110 0001 e1 5 db db 1010 0100 a4 ? 25.5 db 0110 0111 67 ? 56 db 0010 1010 2a ? 86.5 db 1110 0000 e0 4.5 db 1010 0011 a3 ? 26 db 0110 0110 66 ? 56.5 db 0010 1001 29 ? 87 db 1101 1111 df 4 db 1010 0010 a2 ? 26.5 db 0110 0101 65 ? 57 db 0010 1000 28 ? 87.5 db 1101 1110 de 3.5 db 1010 0001 a1 ? 27 db 0110 0100 64 ? 57.5 db 0010 0111 27 ? 88 db 1101 1101 dd 3 db 1010 0000 a0 ? 27.5 db 0110 0011 63 ? 58 db 0010 0110 26 ? 88.5 db 1101 1100 dc 2.5 db 1001 1111 9f ? 28 db 0110 0010 62 ? 58.5 db 0010 0101 25 ? 89 db 1101 1011 db 2 db 1001 1110 9e ? 28.5 db 0110 0001 61 ? 59 db 0010 0100 24 ? 89.5 db 1101 1010 da 1.5 db 1001 1101 9d ? 29 db 0110 0000 60 ? 59.5 db 0010 0011 23 ? 90 db 1101 1001 d9 1 db 1001 1100 9c ? 29.5 db 0101 1111 5f ? 60 db 0010 0010 22 ? 90.5 db 1101 1000 d8 0.5 db 1001 1011 9b ? 30 db 0101 1110 5e ? 60.5 db 0010 0001 21 ? 91 db 1101 0111 d7 0 db (default) 1001 1010 9a ? 30.5 db 0101 1101 5d ? 61 db 0010 0000 20 ? 91.5 db 1101 0110 d6 ? 0.5 db 1001 1001 99 ? 31 db 0101 1100 5c ? 61.5 db 0001 1111 1f ? 92 db 1101 0101 d5 ? 1 db 1001 1000 98 ? 31.5 db 0101 1011 5b ? 62 db 0001 1110 1e ? 92.5 db 1101 0100 d4 ? 1.5 db 1001 0111 97 ? 32 db 0101 1010 5a ? 62.5 db 0001 1101 1d ? 93 db 1101 0011 d3 ? 2 db 1001 0110 96 ? 32.5 db 0101 1001 59 ? 63 db 0001 1100 1c ? 93.5 db 1101 0010 d2 ? 2.5 db 1001 0101 95 ? 33 db 0101 1000 58 ? 63.5 db 0001 1011 1b ? 94 db 1101 0001 d1 ? 3 db 1001 0100 94 ? 33.5 db 0101 0111 57 ? 64 db 0001 1010 1a ? 94.5 db 1101 0000 d0 ? 3.5 db 1001 0011 93 ? 34 db 0101 0110 56 ? 64.5 db 0001 1001 19 ? 95 db 1100 1111 cf ? 4 db 1001 0010 92 ? 34.5 db 0101 0101 55 ? 65 db 0001 1000 18 ? 95.5 db 1100 1110 ce ? 4.5 db 1001 0001 91 ? 35 db 0101 0100 54 ? 65.5 db 0001 0111 17 ? 96 db 1100 1101 cd ? 5 db 1001 0000 90 ? 35.5 db 0101 0011 53 ? 66 db 0001 0110 16 ? 96.5 db 1100 1100 cc ? 5.5 db 1000 1111 8f ? 36 db 0101 0010 52 ? 66.5 db 0001 0101 15 ? 97 db 1100 1011 cb ? 6 db 1000 1110 8e ? 36.5 db 0101 0001 51 ? 67 db 0001 0100 14 ? 97.5 db 1100 1010 ca ? 6.5 db 1000 1101 8d ? 37 db 0101 0000 50 ? 67.5 db 0001 0011 13 ? 98 db 1100 1001 c9 ? 7 db 1000 1100 8c ? 37.5 db 0100 1111 4f ? 68 db 0001 0010 12 ? 98.5 db 1100 1000 c8 ? 7.5 db 1000 1011 8b ? 38 db 0100 1110 4e ? 68.5 db 0001 0001 11 ? 99 db 1100 0111 c7 ? 8 db 1000 1010 8a ? 38.5 db 0100 1101 4d ? 69 db 0001 0000 10 ? 99.5 db 1100 0110 c6 ? 8.5 db 1000 1001 89 ? 39 db 0100 1100 4c ? 69.5 db 0000 1111 0f ? 100 db 1100 0101 c5 ? 9 db 1000 1000 88 ? 39.5 db 0100 1011 4b ? 70 db 0000 1110 0e 1100 0100 c4 ? 9.5 db 1000 0111 87 ? 40 db 0100 1010 4a ? 70.5 db ? ? mute 0000 0000 00 1100 0011 c3 ? 10 db 1000 0110 86 ? 40.5 db 0100 1001 49 ? 71 db 72 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 94 (5eh) register 95 (5fh) register 101 (65h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 94 5eh master/slave interface format for adc34 ams34[3:0] hf34 rsv afm34[1:0] ams34[3:0]: master/slave audio interface setting for adc34 these bits set the master or slave mode. adc34 receives lrck and bck from port-1, port-2, port-3, port-4, port-5 or port-6 in slave mode, and generates lrck and bck from sck in master mode. default value: 1000 master/slave audio interface setting for master/slave audio interface setting for ams34[3:0] adc34 ams34[3:0] adc34 0000 reserved 1000 slave and system clock f s auto-detect mode (default) 0001 master and system clock 768 f s 1001 slave and system clock 768 f s 0010 master and system clock 512 f s 1010 slave and system clock 512 f s 0011 master and system clock 384 f s 1011 slave and system clock 384 f s 0100 master and system clock 256 f s 1100 slave and system clock 256 f s 0101 reserved 1101 reserved 0110 reserved 1110 reserved 0111 reserved 1111 reserved hf34: high-pass filter disable for adc34 this bit disables the digital high-pass filter of adc34. default value: 0 0 (0.019 f s /1000) hz (default) 1 off afm34[1:0]: audio interface format for adc34 these bits select the adc34 audio data format as i 2 s, right-justified, or left-justified. default value: 00 00 16 to 24 bits, i 2 s (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified reg hex description b7 b6 b5 b4 b3 b2 b1 b0 95 5fh power up/down for adc34 pa34 rsv rsv rsv rsv rsv rsv rsv pa34: power up/down control for adc34 this bit controls the power up/down for adc34, including the decimation filter. default value: 1 0 power up 1 power down (default) reg hex description b7 b6 b5 b4 b3 b2 b1 b0 101 65h lrck/bck selection of port-1 and port-2 lbs2[3:0] lbs1[3:0] copyright ? 2009, texas instruments incorporated submit documentation feedback 73 product folder link(s): pcm5310
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com lbs2[3:0]: lrck/bck selection of port-2 (mux_p2bl) these bits are used for routing lrck and bck of port-2. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-2. figure 47 shows a detailed diagram of port-2. default value: 0001 0000 output lrck1 and bck1 0001 input lrck2 and bck2 (default) 0010 output lrck3 and bck3 0011 output lrck4 and bck4 0100 output lrck5 and bck5 0101 output lrck6 and bck6 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 47. detailed diagram of port-2 74 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 lrck2 bck2 lrck1 bck1 lrck3 bck3 lrck4 bck4 lrck, bck from adc12 at masterlrck, bck from adc34 at master lrck, bck from dac12 at master data from gpio1 data from adc12 lrck, bck from dac34 at master data from gpio2 data from adc34 sck2 sck1 sck3 sck4 data2 data1 data3 data4 lrck/bck to mux_adcxx and muxdacxxsck to mux_adcxx and muxdacxx data to muxdacxx lrck5 bck5 lrck6 bck6 sck5 sck6 data5 data6 mux -p2bl mux-p2sc mux-p2dt register 102dts2[3:0] register 103 scs2[2:0] register 101lbs2[3:0] port-2
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 lbs1[3:0]: lrck/bck selection of port-1 (mux_p2bl) these bits are used for routing lrck and bck of port-1. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-1. figure 48 shows a detailed diagram of port-1. default value: 0000 0000 input lrck1 and bck1 (default) 0001 output lrck2 and bck2 0010 output lrck3 and bck3 0011 output lrck4 and bck4 0100 output lrck5 and bck5 0101 output lrck6 and bck6 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 48. detailed diagram of port-1 copyright ? 2009, texas instruments incorporated submit documentation feedback 75 product folder link(s): pcm5310 mux -p1bl lrck, bck from adc12 at master lrck, bck from adc34 at master lrck, bck from dac12 at master lrck, bck from dac34 at master data from adc12 data from adc34 lrck/bck to mux_adcxx and muxdacxx port-1 sck to mux_adcxx and muxdacxx data to muxdacxx dat a from gpio1 dat a from gpio2 register 101 lbs1[3:0] register 103 scs1[2:0] register 102 dts1[3:0] lrck1 bck1 lrck2 bck2 lrck3 bck3 lrck4 bck4 lrck5 bck5 lrck6 bck6 sck1 sck2sck3 sck4 sck5 sck6 data1 data2 data3 data4 data5 data6 mux -p1s c mux -p1dt
register 102 (66h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 102 66h data selection of port-1 and port-2 dts2[3:0] dts1[3:0] dts2[3:0]: data selection of port-2 (mux_p2dt) these bits are used for routing data of port-2. any combination of data1 to data6 and data of adcs in master mode can be connected to port-2. refer to figure 47 for more details. default value: 0001 0000 output data1 0001 input data2 (default) 0010 output data3 0011 output data4 0100 output data5 0101 output data6 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved dts1[3:0]: data selection of port-1 (mux_p1dt) these bits are used for routing data of port-1. any combination of data1 to data6 and data of adcs in master mode can be connected to port-1. refer to figure 48 for more details. default value: 0000 0000 input data1 (default) 0001 output data2 0010 output data3 0011 output data4 0100 output data5 0101 output data6 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved 76 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 103 (67h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 103 67h sck selection of port-1 and port-2 rsv scs2[3:0] rsv scs1[3:0] scs2[3:0]: sck selection of port-2 (mux_p2sc) these bits are used for routing sck of port-2. any combination of sck1 to sck6 and sck can be connected to port-2. refer to figure 47 for more details. default value: 001 000 output sck1 001 input sck2 (default) 010 output sck3 011 output sck4 100 output sck5 101 output sck6 others reserved scs1[3:0]: sck selection of port-1 (mux_p1sc) these bits are used for routing sck of port-2. any combination of sck1 to sck6 and sck can be connected to port-1. refer to figure 48 for more details. default value: 000 000 input sck1 (default) 001 output sck2 010 output sck3 011 output sck4 100 output sck5 101 output sck6 others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 77 product folder link(s): pcm5310
register 104 (68h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 104 68h lrck/bck selection of port-3 and port-4 lbs4[3:0] lbs3[3:0] lbs4[3:0]: lrck/bck selection of port-4 (mux_p4bl) these bits are used for routing lrck and bck of port-4. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-4. figure 49 shows a detailed diagram of port-4. default value: 0011 0000 output lrck1 and bck1 0001 output lrck2 and bck2 0010 output lrck3 and bck3 0011 input lrck4 and bck4 (default) 0100 output lrck5 and bck5 0101 output lrck6 and bck6 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 49. detailed diagram of port-4 78 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 lrck4 bck4 lrck1 bck1 lrck2 bck2 lrck3 bck3 lrck, bck from adc12 at masterlrck, bck from adc34 at master lrck, bck from dac12 at master data from gpio1 data from adc12 lrck, bck from dac34 at master data from gpio2 data from adc34 sck4 sck1 sck2 sck3 data4 data1 data2 data3 lrck/bck to mux_adcxx and muxdacxxsck to mux_adcxx and muxdacxx data to muxdacxx lrck5 bck5 lrck6 bck6 sck5 sck6 data5 data6 mux -p4bl mux -p4sc mux-p4dt register 105dts4[3:0] register 106 scs1[2:0] register 104lbs4[3:0] port-4
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 lbs3[3:0]: lrck/bck selection of port-3 (mux_p3bl) these bits are used for routing lrck and bck of port-3. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-3. figure 50 shows a detailed diagram of port-3. default value: 0010 0000 output lrck1 and bck1 0001 output lrck2 and bck2 0010 input lrck3 and bck3 (default) 0011 output lrck4 and bck4 0100 output lrck5 and bck5 0101 output lrck6 and bck6 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 50. detailed diagram of port-3 copyright ? 2009, texas instruments incorporated submit documentation feedback 79 product folder link(s): pcm5310 lrck3 bck3 lrck1 bck1 lrck2 bck2 lrck4 bck4 lrck, bck from adc12 at masterlrck, bck from adc34 at master lrck, bck from dac12 at master data from gpio1 data from adc12 lrck, bck from dac34 at master data from gpio2 data from adc34 sck3 sck1 sck2 sck4 data3 data1 data2 data4 lrck/bck to mux_adcxx and muxdacxxsck to mux_adcxx and muxdacxx data to muxdacxx lrck5 bck5 lrck6 bck6 sck5 sck6 data5 data6 mux-p4bl mux -p3sc mux-p3dt register 105dts3[3:0] register 106 scs3[2:0] register 104lbs3[3:0] port-3
register 105 (69h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 105 69h data selection of port-3 and port-4 dts4[3:0] dts3[3:0] dts4[3:0]: data selection of port-4 (mux_p4dt) these bits are used for routing data of port-4. any combination of data1 to data6 and data of adcs in master mode can be connected to port-4. refer to figure 49 for more details. default value: 0011 0000 output data1 0001 output data2 0010 output data3 0011 input data4 (default) 0100 output data5 0101 output data6 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved dts3[3:0]: data selection of port-3 (mux_p3dt) these bits are used for routing data of port-3. any combination of data1 to data6 and data of adcs in master mode can be connected to port-3. refer to figure 50 for more details. default value: 0010 0000 output data1 0001 output data2 0010 input data3 (default) 0011 output data4 0100 output data5 0101 output data6 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved 80 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 106 (6ah) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 106 6ah sck selection of port-3 and port-4 rsv scs4[3:0] rsv scs3[3:0] scs4[3:0]: sck selection of port-4 (mux_p4sc) these bits are used for routing sck of port-4. any combination of sck1 to sck6 and sck can be connected to port-4. refer to figure 49 for more details. default value: 011 000 output sck1 001 output sck2 010 output sck3 011 input sck4 (default) 100 output sck5 101 output sck6 others reserved scs3[3:0]: sck selection of port-3 (mux_p3sc) these bits are used for routing sck of port-3. any combination of sck1 to sck6 and sck can be connected to port-3. refer to figure 50 for more details. default value: 010 000 output sck1 001 output sck2 010 input sck3 (default) 011 output sck4 100 output sck5 101 output sck6 others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 81 product folder link(s): pcm5310
register 107 (6bh) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 107 6bh lrck/bck selection of port-5 and port-6 lbs6[3:0] lbs5[3:0] lbs6[3:0]: lrck/bck selection of port-6 (mux_p6bl) these bits are used for routing lrck and bck of port-6. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-6. figure 51 shows a detailed diagram of port-6. default value: 0101 0000 output lrck1 and bck1 0001 output lrck2 and bck2 0010 output lrck3 and bck3 0011 output lrck4 and bck4 0100 output lrck5 and bck5 0101 input lrck6 and bck6 (default) 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 51. detailed diagram of port-6 82 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 lrck6 bck6 lrck1 bck1 lrck2 bck2 lrck3 bck3 lrck, bck from adc12 at masterlrck, bck from adc34 at master lrck, bck from dac12 at master data from gpio1 data from adc12 lrck, bck from dac34 at master data from gpio2 data from adc34 sck6 sck1 sck2 sck3 data6 data1 data2 data3 lrck/bck to mux_adcxx and muxdacxxsck to mux_adcxx and muxdacxx data to muxdacxx lrck4 bck4 lrck5 bck5 sck4 sck5 data4 data5 mux -p6bl mux-p6sc mux -p6dt register 108dts6[3:0] register 109 scs6[2:0] register 107lbs6[3:0] port-6
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 lbs5[3:0]: lrck/bck selection of port-5 (mux_p5bl) these bits are used for routing lrck and bck of port-5. any combination of lrck1/bck1 to lrck6/bck6 and lrck/bck of adcs/dacs in master mode can be connected to port-5. figure 52 shows a detailed diagram of port-5. default value: 0100 0000 output lrck1 and bck1 0001 output lrck2 and bck2 0010 output lrck3 and bck3 0011 output lrck4 and bck4 0100 input lrck5 and bck5 (default) 0101 output lrck6 and bck6 0110 output lrck and bck from dac12 in master mode 0111 output lrck and bck from dac34 in master mode 1000 output lrck and bck from adc12 in master mode 1001 output lrck and bck from adc34 in master mode others reserved figure 52. detailed diagram of port-5 copyright ? 2009, texas instruments incorporated submit documentation feedback 83 product folder link(s): pcm5310 lrck5 bck5 lrck1 bck1 lrck2 bck2 lrck3 bck3 lrck, bck from adc12 at masterlrck, bck from adc34 at master lrck, bck from dac12 at master data from gpio1 data from adc12 lrck, bck from dac34 at master data from gpio2 data from adc34 sck5 sck1 sck2 sck3 data5 data1 data2 data3 lrck/bck to mux_adcxx and muxdacxxsck to mux_adcxx and muxdacxx data to muxdacxx lrck4 bck4 lrck6 bck6 sck4 sck6 data4 data6 mux-p5bl mux-p5sc mux-p5dt register 108dts5[3:0] register 109 scs5[2:0] register 107lbs5[3:0] port-5
register 108 (6ch) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 108 6ch data selection of port-5 and port-6 dts6[3:0] dts5[3:0] dts6[3:0]: data selection of port-6 (mux_p6dt) these bits are used for routing data of port-6. any combination of data1 to data6 and data of adcs in master mode can be connected to port-6. refer to figure 51 for more details. default value: 0101 0000 output data1 0001 output data2 0010 output data3 0011 output data4 0100 output data5 0101 input data6 (default) 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved dts5[3:0]: data selection of port-5 (mux_p5dt) these bits are used for routing data of port-5. any combination of data1 to data6 and data of adcs in master mode can be connected to port-5. refer to figure 52 for more details. default value: 0100 0000 output data1 0001 output data2 0010 output data3 0011 output data4 0100 input data5 (default) 0101 output data6 0110 output gpio1 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 others reserved 84 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 109 (6dh) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 109 6dh sck selection of port-5 and port-6 rsv scs6[3:0] rsv scs5[3:0] scs6[3:0]: sck selection of port-6 (mux_p6sc) these bits are used for routing sck of port-6. any combination of sck1 to sck6 and sck can be connected to port-6. refer to figure 51 for more details. default value: 101 000 output sck1 001 output sck2 010 output sck3 011 output sck4 100 output sck5 101 input sck6 (default) others reserved scs5[3:0]: sck selection of port-5 (mux_p5sc) these bits are used for routing sck of port-5. any combination of sck1 to sck6 and sck can be connected to port-5. refer to figure 52 for more details. default value: 100 000 output sck1 001 output sck2 010 output sck3 011 output sck4 100 input sck5 (default) 101 output sck6 others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 85 product folder link(s): pcm5310
register 110 (6eh) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 110 6eh lrck/bck selection of dac12 and dac34 d34lb[3:0] d12lb[3:0] d34lb[3:0]: lrck/bck selection of dac34 (mux_da34) these bits are used for routing lrck and bck from each audio interface port to dac34, or routing lrck and bck from dacs/adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0100 0000 select lrck and bck from port-1 0001 select lrck and bck from port-2 0010 select lrck and bck from port-3 0011 select lrck and bck from port-4 0100 select lrck and bck from port-5 (default) 0101 select lrck and bck from port-6 0110 select lrck and bck from dac12 in master mode 0111 select lrck and bck from dac34 in master mode 1000 select lrck and bck from adc12 in master mode 1001 select lrck and bck from adc34 in master mode others reserved d12lb[3:0] lrck/bck selection of dac12 (mux_da12) these bits are used for routing lrck and bck from each audio interface port to dac12, or routing lrck and bck from dacs/adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0011 0000 select lrck and bck from port-1 0001 select lrck and bck from port-2 0010 select lrck and bck from port-3 0011 select lrck and bck from port-4 (default) 0100 select lrck and bck from port-5 0101 select lrck and bck from port-6 0110 select lrck and bck from dac12 in master mode 0111 select lrck and bck from dac34 in master mode 1000 select lrck and bck from adc12 in master mode 1001 select lrck and bck from adc34 in master mode others reserved 86 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 111 (6fh) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 111 6fh data selection of dac12 and dac34 d34dt[3:0] d12dt[3:0] d34dt[3:0] data selection of dac34 (mux_da34) these bits are used for routing data from each audio interface port to dac34, or routing data from adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0100 0000 select data from port-1 0001 select data from port-2 0010 select data from port-3 0011 select data from port-4 0100 select data from port-5 (default) 0101 select data from port-6 0110 select data from gpio1 0111 select data from gpio2 1000 select data from adc12 1001 select data from adc34 others reserved d12dt[3:0] data selection of dac12 (mux_da12) these bits are used for routing data from each audio interface port to dac12, or routing data from adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0011 0000 select data from port-1 0001 select data from port-2 0010 select data from port-3 0011 select data from port-4 (default) 0100 select data from port-5 0101 select data from port-6 0110 select data from gpio1 0111 select data from gpio2 1000 select data from adc12 1001 select data from adc34 others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 87 product folder link(s): pcm5310
register 112 (70h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 112 70h sck selection of dac12 and dac34 rsv d34sc[3:0] rsv d12sc[3:0] d34sc[2:0] sck selection of dac34 (mux_da34) these bits are used for routing sck from each audio interface port to dac34. refer to figure 33 for more details. default value: 100 000 select sck from port-1 001 select sck from port-2 010 select sck from port-3 011 select sck from port-4 100 select sck from port-5 (default) 101 select sck from port-6 others reserved d12sc[2:0] sck selection of dac12 (mux_da12) these bits are used for routing sck from each audio interface port to dac12. refer to figure 33 for more details. default value: 011 000 select sck from port-1 001 select sck from port-2 010 select sck from port-3 011 select sck from port-4 (default) 100 select sck from port-5 101 select sck from port-6 others reserved 88 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 116 (74h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 116 74h lrck/bck selection of adc12 and adc34 a34lb[3:0] a12lb[3:0] a34lb[3:0]: lrck/bck selection of adc34 (mux_ad34) these bits are used for routing lrck and bck from each audio interface port to adc34, or routing lrck and bck from dacs/adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0001 0000 select lrck and bck from port-1 0001 select lrck and bck from port-2 (default) 0010 select lrck and bck from port-3 0011 select lrck and bck from port-4 0100 select lrck and bck from port-5 0101 select lrck and bck from port-6 0110 select lrck and bck from dac12 in master mode 0111 select lrck and bck from dac34 in master mode 1000 select lrck and bck from adc12 in master mode 1001 select lrck and bck from adc34 in master mode others reserved a12lb[3:0] lrck/bck selection of adc12 (mux_ad12) these bits are used for routing lrck and bck from each audio interface port to adc12, or routing lrck and bck from dacs/adcs to each audio interface port in master mode. refer to figure 33 for more details. default value: 0000 0000 select lrck and bck from port-1 (default) 0001 select lrck and bck from port-2 0010 select lrck and bck from port-3 0011 select lrck and bck from port-4 0100 select lrck and bck from port-5 0101 select lrck and bck from port-6 0110 select lrck and bck from dac12 in master mode 0111 select lrck and bck from dac34 in master mode 1000 select lrck and bck from adc12 in master mode 1001 select lrck and bck from adc34 in master mode others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 89 product folder link(s): pcm5310
register 117 (75h) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com reg hex description b7 b6 b5 b4 b3 b2 b1 b0 117 75h sck selection of adc12 and adc34 rsv a34sc[3:0] rsv a12sc[3:0] a34sc[2:0] sck selection of adc34 (mux_ad34) these bits are used for routing sck from each audio interface port to adc34. refer to figure 33 for more details. default value: 001 000 select sck from port-1 001 select sck from port-2 (default) 010 select sck from port-3 011 select sck from port-4 100 select sck from port-5 101 select sck from port-6 others reserved a12sc[2:0] sck selection of adc12 (mux_ad12) these bits are used for routing sck from each audio interface port to adc12. refer to figure 33 for more details. default value: 000 000 select sck from port-1 (default) 001 select sck from port-2 010 select sck from port-3 011 select sck from port-4 100 select sck from port-5 101 select sck from port-6 others reserved 90 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
register 118 (76h) pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 reg hex description b7 b6 b5 b4 b3 b2 b1 b0 118 76h gpio1 and gpio2 audio data selection gp2s[3:0] gp1s[3:0] gp2s[3:0] gpio2 audio data selection default value: 0111 0000 output data1 0001 output data2 0010 output data3 0011 output data4 0100 output data5 0101 output data6 0110 output gpio1 0111 input gpio2 (default) 1000 output data from adc12 1001 output data from adc34 1010 use gpio function others reserved gp1s[3:0] gpio1 audio data selection default value: 0110 0000 output data1 0001 output data2 0010 output data3 0011 output data4 0100 output data5 0101 output data6 0110 input gpio1 (default) 0111 output gpio2 1000 output data from adc12 1001 output data from adc34 1010 use gpio function others reserved copyright ? 2009, texas instruments incorporated submit documentation feedback 91 product folder link(s): pcm5310
basic connection diagrams pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com (1) see figure 54 for the line input. (2) see figure 55 for the line output. (3) see figure 56 for the headphone output. figure 53. basic connections 92 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 ain1l (1)ain1r (2) ain2l (3) ain2r (4) ain3l (5) ain3r (6) ain4l (7) ain4r (8) ain5l (9) ain5r (10) ain6l (11) ain6r (12) (13) lo1l (14) lo1r (15) lo2l (16) lo2r (19) hpol (22) hpor (25) vcomda (64) vcomad (62) vrefad1 (63) vrefad2 (58) rstb (59) amute (27) sda (28) scl (55) gpio1 (26) gpio2 (27) gpio3 (26) agnds sck1 (29)bck1 (30) lrck1 (31) data1 (32) sck2 (33) bck2 (34) lrck2 (35) data2 (36) sck3 (37) bck3 (38) lrck3 (39) data3 (40) sck4 (43) bck4 (44) lrck4 (45) data4 (46) sck5 (47) bck5 (48) lrck5 (49) data5 (50) sck6 (51) bck6 (52) lrck6 (53) data6 (54) 22 to 100 w w external circuit external circuit external circuitexternal circuit external circuit external circuit external circuit external circuit external circuit external circuit external circuit line input control interface audio interface and clocks (1) (2) external circuitexternal circuit external circuit external circuit external circuit + 1.0 f m + 1.0 f m + 1.0 f m (41) vdd (42) dgnd (23) vccda (24) agndda (60) vccad (61) agndad (20) vccp (21) pgnd (18) vcch (17) hgnd ++ + + + 3.3 v9.0 v > 4.7 f m > 4.7 f m > 4.7 f m > 4.7 f m > 4.7 f m power supply reference voltage (3) line outputheadphone output external circuit external circuit
pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 r 1 , r 2 : greater than 100 k ? r 3 , r 4 : 100 ? to 1 k ? c 1 , c 2 , c 5 , c 6 : 1 m f to 47 m f c 3 , c 4 : 0.01 m f to 0.001 m f c 7 : less than 0.1 m f figure 54. external circuit for the line input copyright ? 2009, texas instruments incorporated submit documentation feedback 93 product folder link(s): pcm5310 + 47 k (typ) w r 1 r 3 c 1 c 3 to adc 47 k (typ) w ainl (1) + 47 k (typ) w r 2 r 4 c 2 c 4 to adc 47 k (typ) w ainr (2) (a) external circuit for line input with low-pass filter + 47 k (typ) w c 5 to adc 47 k (typ) w ainl (1) + 47 k (typ) w c 6 to adc 47 k (typ) w ainr (2) (b) external circuit for line input without low-pass filter 47 k (typ) w c 7 to adc 47 k (typ) w ainl (1) 47 k (typ) w to adc 47 k (typ) w ainr (2) (c) external circuit for not using analog input
pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com r 1 , r 2 , r 5 , r 6 : 270 ? r 3 , r 4 , r 7 : > 100 k ? c 1 , c 2 , c 5 , c 6 : 1 m f to 47 m f c 3 , c 4 , c 7 , c 8 : 6800 pf figure 55. external circuit for the line output r 1 , r 2 : 4 ? to 16 ? r 3 , r 4 , r 5 , r 6 : 22 ? c 1 , c 2 , c 5 , c 6 : 47 m f to 220 m f c 3 , c 4 , c 7 , c 8 : 0.022 m f figure 56. external circuit for the headphone output 94 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310 (a) external circuit for line output with low-pass filter (b) external circuit for line output with low-pass filter + r 3 r 1 c 3 from dac c 1 mute circuit lo1l (13) + r 4 r 2 c 4 from dac c 2 mute circuit lo1r (14) f = 85 khz c + r 5 from dac c 5 c 7 mute circuit lo1l (13) + from dac lo1r (14) f = 85 khz c r 7 r 6 c 6 c 8 mute circuit r 8 + from dac c 1 r 1 c 3 mute circuit hpol (19) r 3 + from dac c 2 r 2 c 4 mute circuit hpor (20) r 4 + from dac c 5 c 7 mute circuit hpol (19) r 5 + from dac c 6 c 8 mute circuit hpor (20) r 6 (a) external circuit with short-circuit protection resistor (b) external circuit without short-circuit protection resistor
board design and layout considerations power-supply pins analog input pins line output pins headphone output pins common voltage pins reference voltage pins digital output pins pcm5310 www.ti.com ............................................................................................................................................................................................ sles244 ? february 2009 the digital and analog power supplies (vcc, vccda, vccad, vccp, and vcch) to the pcm5310 should be bypassed to the corresponding ground pins with a 1- m f to 4.7- m f electrolytic or ceramic capacitor, placed as close to the pins as possible to maximize the dynamic performance of adc, dac, and other analog circuits. if the power supply includes high-frequency noise, it is recommended to add a 0.1 m f ceramic capacitor as close as possible to the power-supply lines to improve the dynamic performance. to maximize the dynamic performance of the adc, dac, and other analog circuits, the analog and ground pins (dgnd, agndda, agndad, pgnd, hgnd and agnds) are not connected internally. these grounds should have a low impedance to avoid digital noise feeding to the analog ground. therefore, they should be connected directly to each other under the device to reduce the potential of a noise problem. all analog input pins (ain1l/ain1r to ain6l/ain6r) are single-ended inputs with an analog multiplexer. antialiasing low-pass filters are included on the these inputs to remove the out-of-band nose from the audio. if the performance of these filters is not sufficient for a given application, appropriate external antialiasing filters are required. the passive rc filter (see figure 54 ) is used in general. any pins that are not used in a given application should be left open or connected to ground with a small, 0.1- m f ceramic capacitor. all line output pins (lo1l, lo1r, lo2l and lo2r) are single-ended outputs with a 2-v rms driver. an amplifier with a low-pass filter is not required as in a conventional dac; however, the delta-sigma modulator generates out-of-band noise. the passive rc filter (see figure 55 ) is used to remove this noise in general. if any line output pins are not used within a given application, they should be left open. the headphone output pins (hpol and hpor) are single-ended outputs with more than 30-mw output power into either a 16- ? or 32- ? load. if the headphone output pins are not used within a given application, they should be left open. adding a small resistor to these outputs is recommended (see figure 56 ). in order to protect the application and device from short-circuiting. a 1 m f ceramic capacitor should be connected between the common voltage pins (vcomad and vcomda) for the analog circuit and ground to ensure low source impedance of the adc and dac common voltages. this capacitor should be located as close as possible to these pins. a 1- m f ceramic capacitor should be connected between the vrefad1 pin and ground to ensure low source impedance of adc reference voltage. this capacitor should be located as close as possible to these pins. vrefad2 pin should be connected to directly ground. the audio interface pins (lrckx, bckx, sckx), clock pins (sckx) and general-purpose input/output (gpiox) pins change from input mode to output mode through register settings. in output mode, these pins have adequate load drive capability (see the electrical characteristics ); however, if the signal lines are long, placing a buffer near the pcm5310 and minimizing the load capacitor is recommended in order to optimize crosstalk between the digital and analog circuits, maximize the dynamic performance of the adc and dac, and reduce overall power consumption. the digital output pins should be open if they are not used in a given application. copyright ? 2009, texas instruments incorporated submit documentation feedback 95 product folder link(s): pcm5310
digital input pins powerpad (thermal pad) pcm5310 sles244 ? february 2009 ............................................................................................................................................................................................ www.ti.com series resistors (ranging from 22 ? to 100 ? ) are recommended for the sckx, lrckx, bckx, and datax pins. these series resistors combine with the stray printed circuit board (pcb) and device input capacitance to form a low-pass filter that removes high-frequency noise from the digital signal, thus reducing high-frequency emissions. all digital input pins should be connected to ground if they are not used in a given application. the pcm5310 is available in an htqfp-64 powerpad package. the powerpad is a heatsink, which is exposed metal at the bottom of the package. the powerpad works to conduct heat away from the silicon through thermal vias located at the bottom of the powerpad. the powerpad does not need to be soldered onto an exposed metal area of the pcb because the device works within the absolute maximum rating (junction temperature = +150 c) without soldering the powerpad. refer to application note slma002 , powerpad thermally enhanced package, when considering whether to solder the powerpad in order to reduce more heat from the device. 96 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): pcm5310
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) pcm5310pap active htqfp pap 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr PCM5310PAPR active htqfp pap 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-apr-2009 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant PCM5310PAPR htqfp pap 64 1000 330.0 24.4 13.0 13.0 1.4 16.0 24.0 q2 package materials information www.ti.com 5-mar-2009 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) PCM5310PAPR htqfp pap 64 1000 346.0 346.0 41.0 package materials information www.ti.com 5-mar-2009 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dlp? products www.dlp.com broadband www.ti.com/broadband dsp dsp.ti.com digital control www.ti.com/digitalcontrol clocks and timers www.ti.com/clocks medical www.ti.com/medical interface interface.ti.com military www.ti.com/military logic logic.ti.com optical networking www.ti.com/opticalnetwork power mgmt power.ti.com security www.ti.com/security microcontrollers microcontroller.ti.com telephony www.ti.com/telephony rfid www.ti-rfid.com video & imaging www.ti.com/video rf/if and zigbee? solutions www.ti.com/lprf wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2009, texas instruments incorporated

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