? semiconductor components industries, llc, 2001 october, 2001 rev. 5 1 publication order number: NTHS5445T1/d NTHS5445T1 power mosfet p-channel chipfet 5.2 amps, 8 volts features ? low r ds(on) for higher efficiency ? logic level gate drive ? miniature chipfet surface mount package saves board space applications ? power management in portable and batterypowered products; i.e., cellular and cordless telephones and pcmcia cards maximum ratings (t a = 25 c unless otherwise noted) rating symbol 5 secs steady state unit drainsource voltage v ds 8.0 v gatesource voltage v gs 8.0 v continuous drain current (t j = 150 c) (note 1.) t a = 25 c t a = 85 c i d 7.1 5.2 5.2 3.7 a pulsed drain current i dm 20 a continuous source current (note 1.) i s 2.1 1.1 a maximum power dissipation (note 1.) t a = 25 c t a = 85 c p d 2.5 1.3 1.3 0.7 w operating junction and storage temperature range t j , t stg 55 to +150 c 1. surface mounted on 1 x 1 fr4 board. device package shipping ordering information NTHS5445T1 chipfet 3000/tape & reel http://onsemi.com g d s d d d d d 1 2 3 4 5 6 7 8 pin connections g s d pchannel mosfet chipfet case 1206a style 1 marking diagram a5 a5 = specific device code 5.2 amps 8 volts r ds(on) = 35 m 1 2 3 4 8 7 6 5
NTHS5445T1 http://onsemi.com 2 thermal characteristics characteristic symbol typ max unit maximum junctiontoambient (note 2.) t 5 sec steady state r thja 40 80 50 95 c/w maximum junctiontofoot (drain) steady state r thjf 15 20 c/w electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 m a 0.45 v gatebody leakage i gss v ds = 0 v, v gs = 8.0 v 100 na zero gate voltage drain current i dss v ds = 6.4 v, v gs = 0 v 1.0 m a v ds = 6.4 v, v gs = 0 v, t j = 85 c 5.0 onstate drain current (note 3.) i d(on) v ds 5.0 v, v gs = 4.5 v 20 a drainsource onstate resistance (note 3.) r ds(on) v gs = 4.5 v, i d = 5.2 a 0.030 0.035 w () v gs = 2.5 v, i d = 4.5 a 0.040 0.047 v gs = 1.8 v, i d = 2.0 a 0.052 0.062 forward transconductance (note 3.) g fs v ds = 5.0 v, i d = 5.2 a 18 s diode forward voltage (note 3.) v sd i s = 1.1 a, v gs = 0 v 0.8 1.2 v dynamic (note 4.) total gate charge q g v 40v v 45v 17 26 nc gatesource charge q gs v ds = 4.0 v, v gs = 4.5 v, i d = 5.2 a 2.8 gatedrain charge q gd i d = 5 . 2 a 2.6 turnon delay time t d(on) 15 25 ns rise time t r v dd = 4.0 v, r l = 4 w i d 10a v gen =45v 45 70 turnoff delay time t d(off) i d 1.0 a, v gen = 4.5 v, r g = 6 w 110 165 fall time t f r g 6 w 65 100 sourcedrain reverse recovery time t rr i f = 1.1 a, di/dt = 100 a/ m s 30 60 2. surface mounted on 1 x 1 fr4 board. 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. guaranteed by design, not subject to production testing.
NTHS5445T1 http://onsemi.com 3 typical electrical characteristics q g, total gate charge (nc) v gs, gatetosource voltage (v) 20 16 12 8 4 0 0 0.5 1.0 1.5 2.0 2.5 3.0 1.5 v 2 v 20 16 12 8 4 0 0 0.5 1.0 1.5 2.0 2.5 t c = 55 c 25 c 125 c v gs = 1.8 v v gs = 2.5 v v gs = 4.5 v 5 4 3 2 1 0 0 8 12 16 20 0.10 0.08 0.06 0 048121620 3000 2500 2000 1500 1000 500 0 02468 c iss c oss c rss v ds = 4 v i d = 5.2 a 1.6 1.4 1.2 1.0 0.8 0.6 50 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 5.2 a 1 v 0.04 0.02 4 v ds , draintosource voltage (v) v gs , gatetosource voltage (v) i d, drain current (a) i d , drain current (a) v ds , draintosource voltage (v) c, capacitance (pf) r ds(on), onresistance ( w ) (normalized) t j , junction temperature ( c) i d, drain current (a) r ds(on), onresistance ( w ) v gs = 5 thru 2.5 v figure 1. output characteristics figure 2. transfer characteristics figure 3. onresistance vs. drain current figure 4. capacitance figure 5. gate charge figure 6. onresistance vs. junction temperature
NTHS5445T1 http://onsemi.com 4 typical electrical characteristics 1 20 0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j = 25 c 0.10 0.08 0.06 0.04 0 012 345 i d = 5.2 a 0.3 0.2 0.0 0.2 50 25 0 25 50 75 100 125 150 i d = 250 m a power (w) 50 40 30 20 10 10 10 3 2 1 10 1 10 100 600 time (sec) 10 0.4 0 0.02 0.1 0.1 v ds , draintosource voltage (v) i s, source current (a) v gs , gatetosource voltage (v) r ds(on), onresistance ( w ) t j , temperature ( c) v gs (th), varience (v) figure 7. sourcedrain diode forward voltage figure 8. onresistance vs. gatetosource voltage figure 9. threshold voltage figure 10. single pulse power
NTHS5445T1 http://onsemi.com 5 typical electrical characteristics 2 1 0.1 0.01 10 10 10 4 3 2 1 10 1 10 100 600 square wave pulse duration (sec) normalized effective transient thermal impedance duty cycle = 0.5 0.2 single pulse 0.1 0.05 0.02 1. duty cycle, d = 2. per unit base = r thja = 80 c/w 3. t jm t a = p dm z thja (t) 4. surface mounted t 1 t 2 p dm notes: t 1 t 2 2 1 0.1 0.01 10 10 10 4 3 2 1 10 1 10 0.02 square wave pulse duration (sec) duty cycle = 0.5 0.2 single pulse 0.1 0.05 normalized effective transient thermal impedance figure 11. normalized thermal transient impedance, junctiontoambient figure 12. normalized thermal transient impedance, junctiontofoot
NTHS5445T1 http://onsemi.com 6 package dimensions chipfet case 1206a01 issue a b s c d g l a 1234 8765 m j k 1 2 3 4 8 7 6 5 dim min max min max inches millimeters a 2.95 3.10 0.116 0.122 b 1.55 1.70 0.061 0.067 c 1.00 1.10 0.039 0.043 d 0.25 0.35 0.010 0.014 g 0.65 bsc 0.025 bsc j 0.10 0.15 0.004 0.008 k 0.30 0.45 0.012 0.018 l 0.55 bsc 0.022 bsc m 5 nom s --- 1.80 --- 0.071 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 0.05 (0.002) 5 nom style 1: pin 1. drain 2. drain 3. drain 4. gate 5. source 6. drain 7. drain 8. drain
NTHS5445T1 http://onsemi.com 7 80 mil 26 28 18 mil 25 mil figure 13. figure 14. 80 mil 26 28 68 mil mil mil mil mil basic pad patterns the basic pad layout with dimensions is shown in figure 14. this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. the minimum recommended pad pattern shown in figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
NTHS5445T1 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. NTHS5445T1/d chipfet is a trademark of vishay siliconix literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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