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asahi kasei [ak6516c] dap05e-00 2005/03 - 1 - ak6516c spi bus 256kbit serial cmos eeprom features ? advanced cmos eeprom technology ? single voltage supply: 1.6v to 5.5v ? 256kbits; 32768 x 8 organization ? spi serial interface compatible ? low power consumption 0.8 a max. (standby mode) ? high reliability endurance: 100k e/w cycles / address data retention: 10 years ? special features 64 byte page write mode block write protection (protect 1/4,1/2 or entire array) automatic write cycle time-out with auto-erase ? software and hardware controlled write protection ? self timed programming cycle: 5msec. max. ? ideal for low density data storage low cost, space saving, 8-pin sop package block diagram 256kbit 32768 8 data register instruction decode, control and clock generation instruction register eeprom si cs sck hold add. buffers vref vpp generator vpp sw decoder r/w amps and auto erase so status register wp
asahi kasei [ak6516c] dap05e-00 2005/03 - 2 - general description the ak6516c is a 262144-bit, serial, read/write, non-volatile memory device fabricated using an advanced cmos eeprom technology. the ak6516c has 262144-bits of memory organized as 32768 registers of 8 bits each. the ak6516c can operate all function under wide operating voltage range: 1.6v to 5.5v. the charge up circuit for high voltage generation needed for write operations is integrated. the ak6516c serial interface is compatible to a spi bus. the ak6516c has 6 instructions: read, write, wren (write enable), wrdi (write disable), rdsr (read status register), and wrsr (write status register). each instruction is organized by an op-code (8bits), address (16bits), and data (8bits). when input level of cs pin changed from high level to low level, ak6516c can receive instructions. ? pin configurations pin name functions cs chip select input sck serial clock input si serial data input so serial data output wp write protect input hold hold input vcc power supply gnd ground ? type of products model memory size temp. range vcc package AK6516CF 256k bits -40c to +85c 1.6v to 5.5v 8pin plastic sop AK6516CF 8pin sop gnd wp cs so 2 1 3 4 vcc 7 8 6 5si sck hold
asahi kasei [ak6516c] dap05e-00 2005/03 - 3 - ? data transfer an ic that outputs the clock is called "master", an ic that receives the clock is called "slave". the ak6516c operates as a slave. data is written to the si pin and read from so pin. the msb is transmitted first. after cs pin changes high level to low level, ak6516c receives the first data bit on the si pin synchronously with the rising edge of the input pulse of serial clock. while cs pin is high level, the data input to the si pin is don?t care and so pin indicates hi-z. all the functions are organized 8 bits of op-code, address, and data. if there is an invalid op-code, the ak6516c ignores the address and data information and so pin indicates hi-z. in order to input new op-code, cs pin should be toggled. ? hold ak6516c has a hold pin that can hold the data transfer. when hold changes high to low while sck is low, the data transfer stops. after the hold pin changes low to high while sck is low, the data transfer starts again. while the data transfer is paused, ak6516c ignores the clock on the sck line. ? write protect ak6516c has status registers. when the wpen bit in the status registers is "1", write protect function is enabled. when wpen bit is "1" and wp pin is low level, the status register is protected from write function. when wp pin becomes low level while the write to the status register instruction is written, the ak6516c doesn?t accept the instruction. when the wp pin changes low level while the internal programming, the programming function continues. when the wpen bit is "0", wp pin function is disabl ed. even if wp pin is fixed to low level, the write function to the status register can be done. when the wp pin is high level, ak6516c can accept all of read and write functions.
asahi kasei [ak6516c] dap05e-00 2005/03 - 4 - pin description cs (chip select input) when cs changes high level to low level, the ak6516c can receive the instructions. cs should be kept low level while receiving op-code, address and data, and while outputting data. when cs is high level, so indicate hi-z. sck (serial clock input) the sck clock pin is the synchronous clock input for input/output data. si (serial data input) the op-code, address, and data are written to the si pin. so (serial data output) the so pin outputs the data from memory array and status register. wp (write protect input) the wp pin controls the write function to the status register. when the wpen bit in the status register is "0", the function of wp pin becomes disable. then the status register can be programmable when the wen bit in the status register is "1". and it does not depend on the status of wp pin. when the wpen bit is "1", the function of wp is enabled. then the status register can not be programmable when the wen bit is "1" and the status of wp pin is low. when the wpen bit is "1", wp pin is high and wen bit is "1", ak6516c can accept the write instruction to the status registers. during the instruction input, wp pin should keep high or low level. hold (hold input) the hold pin can hold the data transfer. when the hold pin changes hi to low while the sck is low, the data transfer is held. and the transfer starts when the hold pin changes low to high while the sck is low. while the holding the data transfer, ak6516c ignores the clock signal on sck pin.
asahi kasei [ak6516c] dap05e-00 2005/03 - 5 - function description ak6516c has six instructions. the instruction can be input after the cs pin changes high to low. all the instructions are msb first. instruction op-code address data description read 0000 x011 x a14-a8 a7-a0 d7-d0 (out) read from memory array write 0000 x010 x a14-a8 a7-a0 d7-d0 (in) write to memory array wren 0000 x110 ------ ------ write enable wrdi 0000 x100 ------ ------ write disable rdsr 0000 x101 bit7-bit0 (out) ------ ------ read status register wrsr 0000 x001 bit7-bit0 (in) ------ ------ write status register x: don?t care table 1. instruction set for ak6516c wren (write enable) / wrdi (write disable) the write function can be accepted only in the st atus of write enable. after vcc is applied, ak6516c is in the status of write disable. af ter the function of wrdi, ak6516c cannot accept any programming function. wren wrdi 01234567 1 x 0 0 0 000 hi-z cs sc k si so x = don?t care 01234567 1 x 0 0 0 010 hi-z cs sc k si so x = don?t care
asahi kasei [ak6516c] dap05e-00 2005/03 - 6 - rdsr (read status register) the rdsr function is used to read the data in the status register. the status register has rdy bit, wen bit, bp0/bp1 bit and wpen bit. rds r function can be used to read ready/busy status bit, write enable/disable bit, and block protect bit. these bits can be set by wrsr function. rdsr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpen x x x bp1 bp0 wen rdy register definition wpen wp pin set bit (programmable) see table 3. bp0 / bp1 block protect bit for eeprom memory array (programmable) see table 4. wen write enable / disable bit (read only) this is set by wren/wrdi function. wen=0 : write disable wen=1 : write enable rdy ready/busy status bit (read only) rdy=0 : ready rdy=1 : busy table 2. status register configuration 01234567891011121314 1 x 0 0 0 001 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 hi-z cs sck si so x = don?t care
asahi kasei [ak6516c] dap05e-00 2005/03 - 7 - wrsr (write status register) the wrsr instruction can set the write protect block size of the memory array. ak6516c has 4 blocks of memory arrays. write protect block size can be selected from 1/4, 1/2 and whole memory array. the block, which is set by write protect, is read only. bp0 bit, bp1 bit, and wpen bit are programmable with eeprom memory cell bits. the characteristics of those bits (wren, te/w, rdsr) are same as the eeprom memory array. wp pin function can be set by wpen (write protect enable) bit which is defined by wrsr function. when wp pin is low level and wpen bit is "1", the write function to status register, which has wpen bit and bp0/bp1 bit, and to write disable block is not performed. then write function is performed only to the write enable block. when wp pin is "1" or wpen bit is "0", then the function of wp pin is disabled and write function to the status register is performed. wren function should be done before wrsr function. and after the programming function, ak6516c becomes write disable status automatically. wrsr wpen bit wp pin wen bit write protected block not protected block status register 0 x 0 write disable write disable write disable 0 x 1 write disable write enable write enable 1 low 0 write disable write disable write disable 1 low 1 write disable write enable write disable x high 0 write disable write disable write disable x high 1 write disable write enable write enable table 3. wpen function status register bits bp1 bp0 write protected block 0 0 none 0 1 6000h - 7fffh 1 0 4000h - 7fffh 1 1 0000h - 7fffh table 4. write protected block size hi-z 0123456789101112131415 0 0 0 0 001 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 cs sc k si so x = don?t care x
asahi kasei [ak6516c] dap05e-00 2005/03 - 8 - write (write sequence) write instruction can start the write function to the memory cell array. after cs pin changes high to low, op-code, address and data are input from si pin. after the instruction input, the internal programming cycle starts when cs pin changes low to high. after the instructions are inputted, cs pin should change low to high after the last data bit (d0) inputs and before next sck clock rises. write function can start only at this timing. ak6516c can indicate the busy status by using rds r instruction and read the rdy bit (bit0) in the status register. rdy is "1" indicates ak6516c is in the programming cycle, and rdy is "0" indicates ak6516c is in the ready status. ak6516c outputs the "ff" when rdsr instruction executes during the programming cycle. only rdsr instruction can be accepted during programming cycle. ak6516c has page write mode, which can write the data within 64 bytes with one programming cycle. the input data sent to the shift register within 64 bytes. if the number of bytes exceeded 64, the address counter rolls over to the first address of the page. internal programming cycle starts after cs pin changes low to high. after write instruction, ak6516c changes to writ e disable status automatically. ak6516c needs wren instruction before every write instruction. when write instruction is done while ak6516c is in write disable status, write instructions are ignored and ak6516c becomes standby status after cs changes to high. ak6516c can accept the next instruction after cs becomes low. write instruction cannot write the data into the address of the protected block. write hi-z 32 33 34 35 36 37 38 39 40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 23 22 0 0 0 0 0 1 0 a0 a1 a10 hi-z cs sck si so a11 24 25 30 31 d0 d1 d6 d7 data(n) cs sck si so x = don?t care data(n+1) d0 d1 d6 d7 d4 d5 d3 d2 d7 data(n+63) d0 d0 d1 d6 d7 d4 d5 d3 d2 a12 x x a 14 a13
asahi kasei [ak6516c] dap05e-00 2005/03 - 9 - read (read sequence) after cs changes high to low, the op-code and address are sent on si pin and the data (d7-d0) read from so pin. after 1 byte of data output, internal address regist er is incremented, and the next byte of data is outputted. after read the data in the highest address, the address register rolls over to the lowest address. after the last bit of the address shift into the register, the input data on si pin is ignored. read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 23 22 0 0 0 0 0 1 1 a0 a1 a10 hi-z cs sck si so a11 24 25 29 30 d0 d1 d2 d6 x = don?t care d7 a12 x x a14 a13
asahi kasei [ak6516c] dap05e-00 2005/03 - 10 - absolute maximum ratings parameter symbol min max unit power supply vcc -0.6 +6.5 v all input voltages with respect to ground vio -0.6 vcc+0.6 v ambient storage temperature tst -65 +150 c stress above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of the specificati on is not implied. exposure to absolute maximum conditions for extended periods may affect device reliability. recommended operating condition parameter symbol min max unit power supply vcc 1.6 5.5 v ambient operating temperature ta -40 +85 c
asahi kasei [ak6516c] dap05e-00 2005/03 - 11 - electrical characteristics (1) d.c. electrical characteristics (1.6v vcc 5.5v, -40c ta 85c, unless otherwise specified) parameter symbol condition min. max. unit icc1 vcc=5.5v,fsck=10.0mhz, *1 2.5 ma current dissipation (write) icc2 vcc=2.5v,fsck=5.0mhz, *1 2.0 ma icc3 vcc=1.6v,fsck=2.0mhz, *1 1.5 ma icc4 vcc=5.5v,fsck=10.0mhz, *1 2.0 ma current dissipation (read) icc5 vcc=2.5v,fsck=5.0mhz, *1 0.4 ma icc6 vcc=1.6v,fsck=2.0mhz, *1 0.2 ma current dissipation (standby) iccs vcc=5.5v *2 0.8 a vih1 2.5v vcc 5.5v 0.7xvcc vcc+0.5 v input high voltage vih2 1.6v vcc < 2.5v 0.8xvcc vcc+0.5 v vil1 2.5v vcc 5.5v -0.3 0.3xvcc v input low voltage vil2 1.6v vcc < 2.5v -0.3 0.2xvcc v output high voltage voh1 4.5v vcc 5.5v ioh=-2ma vcc-0.5 v voh2 2.5v vcc < 4.5v ioh=-0.4ma vcc-0.2 v voh3 1.6v vcc < 2.5v ioh=-0.1ma vcc-0.2 v output low voltage vol1 4.5v vcc 5.5v iol=3.0ma 0.4 v vol2 2.5v vcc < 4.5v iol=1.6ma 0.4 v vol3 2.5v vcc < 4.5v iol=1.0ma 0.2 v vol4 1.6v vcc < 2.5v iol=1.0ma 0.2 v ili vcc=5.5v, vin=vcc/gnd 1.0 a input leakage cs, sck, di pins wp, hold pins output leakage so pin ilo vcc=5.5v, vout=vcc/gnd 1.0 a *1: vin=vih/vil, so=open *2: cs=vcc, vin=vcc/gnd, wp,hold=vcc, so=open (2) capacitance (ta=25c, fsck=1mhz, vcc=5.0v) parameter symbol condition min. max. unit output capacitance so pin co vo=0v 8.0 pf input capacitance cs, sck, si pins cin vin=0v 6.0 pf note: these parameters are not 100% tested. these are the sample value.
asahi kasei [ak6516c] dap05e-00 2005/03 - 12 - (3) a.c. electrical characteristics 1 (1.6v vcc 5.5v, -40c ta 85c, unless otherwise specified) parameter symbol condition min. max. unit fsck1 4.5v 10.0 mhz sck frequency fsck2 2.5v vcc < 4.5v 5.0 mhz fsck3 1.6v vcc < 2.5v 2.0 mhz tsksh1 4.5v vcc 5.5v 20 ns sck setup time tsksh2 2.5v vcc < 4.5v 50 ns tsksh3 1.6v vcc < 2.5v 50 ns tcss1 4.5v vcc 5.5v 40 ns cs setup time tcss2 2.5v vcc < 4.5v 80 ns tcss3 1.6v vcc < 2.5v 200 ns tskw1 4.5v vcc 5.5v 40 ns sck pulse width tskw2 2.5v vcc < 4.5v 80 ns tskw3 1.6v vcc < 2.5v 200 ns sck rise time *3 trc 2 s sck fall time *3 tfc 2 s tdis1 4.5v vcc 5.5v 15 ns data setup time tdis2 2.5v vcc < 4.5v 20 ns tdis3 1.6v vcc < 2.5v 50 ns tdih1 4.5v vcc 5.5v 15 ns data hold time tdih2 2.5v vcc < 4.5v 30 ns tdih3 1.6v vcc < 2.5v 60 ns data rise time *3 trd 2 s data fall time *3 tfd 2 s tpd1 4.5v vcc 5.5v 25 ns so pin output delay tpd2 2.5v vcc < 4.5v 60 ns tpd3 1.6v vcc < 2.5v 100 ns toz1 4.5v vcc 5.5v 40 ns so pin hi-z time toz2 2.5v vcc < 4.5v 100 ns toz3 1.6v vcc < 2.5v 200 ns so pin output hold time tohd 0 ns tcsh1 4.5v vcc 5.5v 40 ns cs hold time tcsh2 2.5v vcc < 4.5v 80 ns tcsh3 1.6v vcc < 2.5v 200 ns tskh1 4.5v vcc 5.5v 20 ns sck hold time tskh2 2.5v vcc < 4.5v 50 ns tskh3 1.6v vcc < 2.5v 50 ns tcs1 4.5v vcc 5.5v 40 ns cs high time tcs2 2.5v vcc < 4.5v 100 ns tcs3 1.6v vcc < 2.5v 200 ns *3: these parameters are not 100% tested. these are the sample value.
asahi kasei [ak6516c] dap05e-00 2005/03 - 13 - (4) a.c. electrical characteristics 2 (1.6v vcc 5.5v, -40c ta 85c, unless otherwise specified) parameter symbol condition min. max. unit thfs1 4.5v ns hold setup time 1 thfs2 2.5v vcc < 4.5v 30 ns thfs3 1.6v vcc < 2.5v 90 ns thfh1 4.5v vcc 5.5v 15 ns hold hold time 1 thfh2 2.5v vcc < 4.5v 30 ns thfh3 1.6v vcc < 2.5v 90 ns thrs1 4.5v vcc 5.5v 15 ns hold setup time 2 thrs2 2.5v vcc < 4.5v 30 ns thrs3 1.6v vcc < 2.5v 90 ns thrh1 4.5v vcc 5.5v 15 ns hold hold time 2 thrh2 2.5v vcc < 4.5v 30 ns thrh3 1.6v vcc < 2.5v 90 ns thoz1 4.5v vcc 5.5v 25 ns hold low to output hi-z thoz2 2.5v vcc < 4.5v 100 ns thoz3 1.6v vcc < 2.5v 150 ns thpd1 4.5v vcc 5.5v 25 ns hold high to output low-z thpd2 2.5v vcc < 4.5v 50 ns thpd3 1.6v vcc < 2.5v 100 ns selftimed programming time twr 5 ms ? ac measurement condition load capacitance cl=100pf
asahi kasei [ak6516c] dap05e-00 2005/03 - 14 - synchronous data timing instruction input data output (read) cs tcs tcss tsksh tdis tdih 0 00 hi-z si so trc tfc sck tskw tskw tfd trd tskw tskw tdis tdih a0 hi-z d7 d6 "l" "h" tpd tpd sck cs si so a1 tohd
asahi kasei [ak6516c] dap05e-00 2005/03 - 15 - data output (read) data input (write) d0 toz d1 sck cs si so tcs tcss tsksh tpd tohd hi-z 0 tskh tcsh hi-z d2 d1 d0 tcsh sck cs si so tskh
asahi kasei [ak6516c] dap05e-00 2005/03 - 16 - hold thfs thoz n+1 hi-z "l" "h" sck cs si so hold thfh d n+1 d n thrs thrh n tdis thpd d n n-1 d n-1
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