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ADM6996L 6 port 10/100 mb/s single chip ethernet switch controller data sheet version 1.03 infineon -admtek co ltd inform atio n in th is do cu m e n t is p r ov id ed in conn ectio n with infin e o n -admtek co ltd pro d u c ts. in fi n e on- adm t e k c o l t d m a y m a ke c h an ges t o s p ec i f i cat i ons an d pr o duct de scri pt i o n s at any t i m e, wi t h o u t no t i ce. designers m u st not rely on t h e abse nc e or c h aracteristics of a n y feature s or i n st r u ct i o ns m a rked ?rese r ved? or ? u nde fi ne d ? . i n fi neo n - a dm t e k c o l t d rese rve s t h ese f o r f u t u re defi ni t i on a n d s h al l ha ve n o respon sib ility wh atso ev er fo r con f licts or i n co m p atib ili ties arising fro m fu ture ch ang e s t o th em the p r od uct s m a y cont ai n d e si gn defect s o r e r r o r s k n o w as er rat a , w h i c h m a y cause t h e p r od uct t o de vi at e fr om publ i s he d speci fi cat i o n s . c u r r e n t cha r acterized e rra ta are availabl e o n requ est. to ob tain latest doc um entation please c o ntact you local in f i n e on- ad mtek co ltd sales o f f i ce or v i sit in fin e on -ad m tek co lt d?s we bsi t e a t h ttp ://www.admtek . co m . tw *t hi rd - p art y b r an ds a n d nam e s are t h e pr o p e rt y of t h ei r res p ect i v e ow ne rs . ? cop y r i gh t 200 4 b y ad mtek in cor por ated a ll rig h t s reser v ed . an infineon technologies company
infineon-admtek co. ltd. v1.04 about this manual general release intended audience infineon-admtek co ltd?s custom ers structure this data sheet contains 6 chapters chapter 1 product overview chapter 2 interface descrip tion chapter 3 function description chapter 4. register description chapter 5. electrical specification chapter 6. packaging revision history d a t e v e r s i o n c h a n g e 02 se p 20 0 3 1.0 1. first release of ADM6996L 07 oct obe r 2 0 03 1.01 2. updated section 1.1 and 2.2.2 17 n o vem b er 20 0 3 1.02 3. updated section 4.3.12 & 3.4 1 2 jan u a r y 2004 1.03 4. updated section 5.3.3 - 8 2 8 apr il 20 04 1.04 updated infineon-admtek logo customer support infineon-admtek co ltd, 2f, no.2, li-hsin rd., science-based industrial park, hsinchu, 300, taiwan, r.o.c. sales information tel + 886-3-5788879 fax + 886-3-5788871
infineon-admtek co. ltd. v1.04 table of contents chapter 1 product overview ........................................................................................ 1-1 1 . 1 overview .......................................................................................................... 1-1 1 . 2 features ............................................................................................................ 1-2 1 . 3 applications ..................................................................................................... 1-2 1 . 4 b l o c k diagram ................................................................................................. 1 - 3 1 . 5 a b b r e v i a t i o n s ................................................................................................... 1 - 3 1 . 6 c o n v e n t i o n s ..................................................................................................... 1 - 5 1.6.1 data lengths ............................................................................................ 1-5 1.6.2 pin types .................................................................................................. 1-5 1.6.2 register types .......................................................................................... 1-5 chapter 2 interface description ................................................................................... 2-1 2 . 1 pin diagram ..................................................................................................... 2-1 2 . 2 pin description by function ............................................................................ 2-2 2.2.1 t w i s t e d p a i r i n t e r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2 6th port (mii) interfaces .......................................................................... 2-2 2.2.3 l e d i n t e r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.4 eeprom/management interface ............................................................ 2-5 2.2.5 power/ground, 48 pins ............................................................................ 2-5 2.2.6 misc ........................................................................................................ 2-6 chapter 3 function description ................................................................................... 3-1 3 . 1 functional descriptions ................................................................................... 3-1 3 . 2 10/100m phy block ....................................................................................... 3-1 3 . 3 100base-x module .......................................................................................... 3-1 3 . 4 100base-x receiver ........................................................................................ 3-2 3.4.1 a/d converter .......................................................................................... 3-2 3.4.2 adaptive equalizer and timing recovery module ................................... 3-2 3.4.3 nrzi/nrz and serial/parallel decoder .................................................. 3-2 3.4.4 d a t a d e - s c r a m b l i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4.5 symbol alignment .................................................................................... 3-3 3.4.6 symbol decoding ..................................................................................... 3-3 3.4.7 valid data signal ..................................................................................... 3-3 3.4.8 receive errors ......................................................................................... 3-4 3.4.9 100base-x link monitor .......................................................................... 3-4 3.4.10 carrier sense ........................................................................................... 3-4 3.4.11 bad ssd de tection ................................................................................... 3-4 3.4.12 far-end fault .......................................................................................... 3-5 3 . 5 100base-tx transceiver ................................................................................. 3-5 3.5.1 transmit drivers ...................................................................................... 3-5 3.5.2 twisted-pair receiver .............................................................................. 3-5 3 . 6 1 0 b a s e - t m o d u l e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.6.1 operation modes ..................................................................................... 3-6 3.6.2 manchester encoder/decoder ................................................................. 3-6 3.6.3 transmit driver and receiver ................................................................. 3-6 3.6.4 smart squelch .......................................................................................... 3-6 ADM6996L i 3 . 7 carrier sense .................................................................................................... 3-7
infineon-admtek co. ltd. v1.04 3 . 8 jabber function ................................................................................................ 3-7 3 . 9 link test f unction ........................................................................................... 3-7 3 . 1 0 autom a tic link polarity detection .............................................................. 3-8 3 . 1 1 clock synthesizer ........................................................................................ 3-8 3 . 1 2 auto negotiation .......................................................................................... 3-8 3 . 1 3 mem o ry bl ock ............................................................................................. 3-8 3 . 1 4 switch functional description ..................................................................... 3-9 3 . 1 5 basic operation ............................................................................................ 3-9 3.15.1 address learning ..................................................................................... 3-9 3.15.2 address recognition and packet forwarding ....................................... 3-10 3.15.3 address aging ........................................................................................ 3-10 3.15.4 back off algorithm ................................................................................. 3-10 3.15.5 inter-packet gap (ipg) ......................................................................... 3-10 3.15.6 illegal frames ........................................................................................ 3-11 3.15.7 half duplex flow control ..................................................................... 3-11 3.15.8 full duplex flow control ...................................................................... 3-11 3.15.9 broadcast storm filter ............................................................................ 3-11 3 . 1 6 auto tp mdix function ................................................................................ 3-11 3 . 1 7 p o r t l o c k i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3 . 1 8 vlan setting & tag/untag & port-base vlan ...................................... 3-12 3 . 1 9 priority setting ........................................................................................... 3-13 3 . 2 0 led display .............................................................................................. 3-13 chapter 4 register description .................................................................................... 4-1 4 . 1 eeprom content ............................................................................................ 4-1 4 . 2 eeprom register map ................................................................................... 4-1 4 . 3 eeprom register ........................................................................................... 4-2 4.3.1 signatur e register , of f s e t : 0 x 0 0 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.2 configuration registers, offset: 0x01h ~ 0x09h ...................................... 4-3 4.3.3 reserved register, offset: 0x0ah .............................................................. 4-3 4.3.4 configuration register, offset: 0x0bh ...................................................... 4-4 4.3.5 reserved register, offset: 0x0ch~0x0dh .................................................. 4-4 4.3.6 vlan priority map register, offset: 0x0eh ............................................. 4-4 4.3.7 tos priority map register, offset: 0x0fh ................................................. 4-4 4.3.8 packet with priority: no rmal packet content .......................................... 4-5 4.3.9 vlan pack et ............................................................................................ 4-5 4.3.10 tos ip packet .......................................................................................... 4-1 4.3.11 miscellaneous configuration register, offset: 0x10h .............................. 4-1 4.3.12 vlan mode select regi ster, offset: 0x11h ............................................... 4-2 4.3.13 miscellaneous configuration re gister, offset: 0x12h .............................. 4-5 4.3.14 vlan mapping table register s, offset: 0x22h ~ 0x13h ............................ 4-5 4.3.15 reserved register, offset: 0x27h ~ 0x23h ................................................ 4-5 4.3.16 port0, 1 pvid bit 11 ~ 4 configurati on register, offset: 0x28h ............. 4-1 4.3.17 port2, 3 pvid bit 11 ~ 4 configurati on register, offset: 0x29h ............. 4-1 4.3.18 port4, 5 pvid bit 11~4 configurati on register, offset: 0x2ah ............... 4-1 4.3.19 port6, 7 pvid bit 11~4 configurati on register, offset: 0x2bh ............... 4-1 ADM6996L ii 4.3.20 port8 pvid bit 11~4 & vlan group shift b its co nfiguration register .. 4-1
infineon-admtek co. ltd. v1.04 4.3.21 reserved register, offset: 0x2dh .............................................................. 4-2 4.3.22 reserved register, offset: 0x2eh .............................................................. 4-2 4.3.23 p h y r e s t a r t , o f f s e t : 0 x 2 f h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3.24 miscellaneous configuration register, offset: 0x30h .............................. 4-2 4.3.25 bandwidth contr o l register0~3, of fset: 0x31h ........................................ 4-3 4.3.26 bandwidth contr o l register 4~5, of fset: 0x32h ....................................... 4-3 4.3.27 bandwidth contr o l enable register , of fset: 0x33h .................................. 4-4 4 . 4 eeprom access ............................................................................................. 4-4 4 . 5 s e r i a l r e g i s t e r m a p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4 . 6 serial register description .............................................................................. 4-7 4.6.1 chip identifier register, offset: 0x00h ..................................................... 4-7 4.6.2 port status 0 regist er, offset: 0x01h ....................................................... 4-7 4.6.3 port status 1 regist er, offset: 0x02h ....................................................... 4-9 4.6.4 cable broken status re g i s t e r , o f f s e t : 0 x 0 3 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.6.5 over flow flag 0 register, offset: 0x3ah .............................................. 4-10 4.6.6 over flow flag 0: register 0x3bh ........................................................ 4-10 4.6.7 over flow flag 2 register, offset: 0x3ch .............................................. 4-11 4 . 7 serial interface tim i ng .................................................................................... 4-1 chapter 5 electrical s p ecification ................................................................................ 5-1 5 . 1 tx/fx interface ............................................................................................... 5-1 5.1.1 tp interface ............................................................................................. 5-1 5.1.2 fx interface ............................................................................................. 5-1 5 . 2 d c characteristics ........................................................................................... 5 - 2 5.2.1 absolute maximum rating ....................................................................... 5-2 5.2.2 recommended operatin g condition s ...................................................... 5-2 5.2.3 dc electrical characteristic s for 3.3v operation .................................. 5-2 5 . 3 ac characteristics ........................................................................................... 5-3 5.3.1 p o w e r o n r e s e t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.2 eeprom interface timing ...................................................................... 5-3 5.3.3 10base-tx mii input timing ................................................................... 5-4 5.3.4 10base-tx mii outpu t timing ................................................................ 5-4 5.3.5 100base-tx mii input t i ming ................................................................. 5-5 5.3.6 100base-tx mii outpu t timing .............................................................. 5-5 5.3.7 gpsi(7-wire) input timing ...................................................................... 5-6 5.3.8 gpsi(7-wire) output timing ................................................................... 5-6 c h a p t e r 6 p a c k a g i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6 . 1 128 pin pqfp outside di m e nsion ................................................................... 6-1 list of figures figure 1-1 ADM6996L bl ock diagram .......................................................................... 1-3 figure 2-1 5 tp/fx port + 1 m ii port 128 pin diagram .......................................... 2-1 ADM6996L iii
ADM6996L product review chapter 1 pr oduct overview 1.1 overview the ADM6996L is a high performance, low cost, highly integration (controller, phy and mem o r y ) five-port 10/100 mbps tx/fx pl us one 10/100 mac port ethernet switch controller w ith all ports supporting 10/ 100 mbps full/half duplex. the ADM6996L is intended for applications to stand alone bridge for low cost soho m a rket such as 5port, router application. ADM6996L provides most adva nce function such as: 802.1p(q.o.s.), 802.1q(vlan), port mac address locking, management , port s t atus, tp auto-mdix, 25m crystal & extra mii port function to m eet custom er request on switch dem a nd. the ADM6996L also supports back pressu re in half-duplex m ode and 802.3x fl ow control pau s e packet in full-d uplex m ode to prevent packet lost when b u ffer full. when back press u re is enab led, and there is no receive buffer availab l e for the inco m i ng packet, the ADM6996L will issue a jam pattern on the receiving port in half duplex mode and transm it the 802.3x pause packet back to receiving end in full duplex m o de. the built-in sram used for packet buffer a nd a ddress learn i ng table is divided into 256 bytes/block to achieve the optim ized m e mory utilization through com p licated link list on packets with various lengths. ADM6996L also supports prior ity features by port-bas e, vlan and ip tos field checking. u s er can be easy to set as different priority m ode in i ndividual port, through a sm all low-cost m i cro controller to initia liz e or on-the-f l y to conf igure. each output port supports four queues in the way of fixed n: 1 fairness queuing to fit the bandwidth dem a nd on various types of packet such as voice, video and data. 802.1q, tag/untag, and up to 16 groups of vlan also is supported. an intelligent address recognition algor ithm m a kes ADM6996L to recognize up to 2048 dif f e rent m a c addresse s and enable s f ilter i ng an d f o rwarding at f u ll wir e speed. port mac address locking function is also supported by ADM6996L to use on building intern et ac c e ss to pr eve n t m u ltiple u s ers sha r ing one port traf f i c. infineon-admtek co. ltd. 1-1
ADM6996L product review 1.2 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
ADM6996L product review 1.4 block diagram por t 0 por t 1 po r t 2 ... por t n m l t3 c onver ter di g i t a l eq ua l i z e r tx n 4 tx p 4 dri v e r a/ d co n v er t e r rx n 4 rx p 4 clock ge n e r a t o r bi as 10 /1 00 m ma c dat a hand le r p a rtit i on ha nd le r sc ra m b l e r tr a n s m i t st at e ma c h i n e le d di s p l a y co ntrol tw i s t e d pa i r in t e r f a c e le d in t e r f a c e ... 10 / 100 m ma c 10/ 1 00m ma c 10 / 100 m ma c s w i t c h i ng f abr i c e m be dde d mem o r y mi i in t e r f a c e me m o r y bist f i g u r e 1-1 a d m699 6l blo ck diag ram 1.5 abbreviations ber bit erro r rate cfi canonical f o rm at indicator col collis ion crc cyclic redundancy check crs carrier sense cs chip select da destination address di data input do data output edi eeprom data input edo eeprom data output infineon-admtek co. ltd. 1-3 eecs eeprom chip select
ADM6996L product review eesk eeprom clock esd end of stream delim iter fefi far end fault indication fet field effect transis t or flp fast link pulse gnd ground gpsi general purpose serial interface ipg inter-packe t gap lfsr linear feed back shift register mac media access controller mdix mdi crosso ver mii media ind e p e ndent in terface nrzi non return to zero inv e rter nrz non return to zero pcs physical coding sub-layer phy physical layer pll phase lock loop pma physical medium attachm e nt pmd physical medium dependent qos quality of servic e qfp quad flat package rst reset rxclk receive clo c k rxd receive data rxdv receive data valid rxer receive data errors rxn receive negative (anal og receive d i fferential signal) rxp receive pos itiv e (analo g rece ive dif f erentia l sig n al) sa source address soh o s m al l offi c e ho me o ffi ce ssd start of str e am delim iter sqe signal quality error tos type of service tp twisted pair ttl transistor transistor logic txclk transm ission clock txd transm ission data txen transm ission enable txn transm ission negative txp transm ission positive infineon-admtek co. ltd. 1-4
ADM6996L product review 1.6 conventi ons 1.6.1 data lengths qword 64-bits dword 32-bits word 16-bits byte 8 bits nibble 4 bits 1.6.2 pin types pin type description i input o output i/o bi-dire c tion a l od open drain sche schm itt trig ger pd internal pull-down pu internal pull-up 1.6.2 register types register ty pe description ro read-only wo w r ite-only infineon-admtek co. ltd. 1-5 rw read/w rite
ADM6996L interf ace description chapter 2 interface description 2.1 pin diagram f i g u r e 2-1 5 tp/f x port + 1 mii port 12 8 pin diag ram infineon-admtek co. ltd. 2-1 dup col 4 gnd o vcc 3 o dup col 3 dup col 2 ( b pe n) dup col 1 ( p hya s 1 ) dup col 0 ( r eca n en ) vcc ik gnd i k rc xi xo vcc pll gnd p ll con t rol vre f gnd b i a s rtx vcc b i as vcc a2 txp 0 txn 0 gnd a rxp 0 rxn 0 vcc ad gnd i k ( g f c en ) tx d0 p4 fx tx d1 tx d2 tx d3 ld spd 4 g ndo vcc 3 o ld spd 3 ld spd 2 vcc ik gnd i k ld spd 1 ld spd 0 te s t vcc ik gnd i k g ndo vcc a2 tx p4 tx n4 g nda rx p4 rx n4 vc cad vc cik t x en (p h yas0 ) txc l k rx er gn d gn do vc c3 o rx cl k rx dv rx d0 vc cik gn dik cr s co l edi ( l e d m o d e ) eec s e e s k (xov en ) vc cik gn dik edo c ko2 5m cf g 0 gn do vc c3 o s p dt np 5 lnk f p 5 d p ha l fp5 lnk a ct 4 gn dik vc cik lnk a ct 3 lnk a ct 2 lnk a ct 1 lnk a ct 0 gn do rx d1 rx d2 rx d3 a d m 6996l rx n3 rxp 3 gn da tx n3 tx p 3 vcc a 2 vcc a 2 nc nc gn da nc nc vc ca d rx n2 rxp 2 gn da tx n2 tx p 2 vcc a 2 vcc a 2 nc nc gn da nc nc vc ca d rx n1 rxp 1 gn da tx n1 tx p 1 vcc a 2 vcc a 2 nc nc gn da nc nc 10 4 10 3 10 5 11 2 11 1 11 0 10 9 10 8 10 7 10 6 11 3 11 4 11 6 11 5 11 7 12 4 12 3 12 2 12 1 12 0 11 9 11 8 12 5 12 6 12 8 12 7 68 69 70 71 72 73 74 75 76 77 67 66 65 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 40 41 39 63 64 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 1 31 32 33 34 35 36 37 38
ADM6996L interf ace description 2.2 pin description by function ADM6996L pins are categorized in to one of the following groups: section 2.2.1 twisted pair interface section 2.2. 2 6th port (mii) in terfaces section 2.2. 3 led interface section 2.2. 4 eeprom/ managem e nt interface section 2.2.5 power/ground, 48 pins section 2.2.6 misc note: ?section 1.6.2 pin types? can be used for reference. 2.2.1 tw isted pair interface pin name pin# t y pe des c ription s rxp[0:4] 126, 11, 24, 3 7 , 41 i/o, analog twi s ted pair re ceive input positive. rxn[0:4] 127, 12, 25, 3 8 , 40 i/o, analog twi s ted pair re ceive input negative. txp[0:4] 123, 8, 21, 34 , 44 i/o, analog twi s ted pair tran smit out put positive. txn[0:4] 124, 9, 22, 35 , 43 i/o, analog twi s ted pair tran smit out put neg a tive. 2.2.2 6th port (mii) interfaces infineon-admtek co. ltd. 2-2 pin name pin# t y pe des c ription s txd[0] setting gfce n 6 3 i / o , 8ma pu mii trans mit data 0 /gpsi t x d acts a s mii transmit data txd[0]. synchron ou s to the risi ng edge of txclk. setting gfce n: glo bal flo w co ntrol enabl e. at power-o n-reset, latch ed as full dupl e x flow co ntro l s e tting ?1? to en able flow-co n trol (default ), ?0 ? to disa ble flow- cont rol. txd[1] setting p5gpsi 6 1 i / o , 8ma pd mii trans mit data bit 1 synchrono us to the risin g e dge of txcl k. these pin s act as mii txd[1]. setting p5gpsi: port 5 gpsi enable. at power-o n-reset, latch ed as p5 gpsi enable. ?0? to di sabl e port 5 gpsi (default ), ?1 ? to enabl e po rt 5 gpsi. txd[3:2] 59, 60 i/o, mii transmit data bit 3~2
ADM6996L interf ace description pin name pin# t y pe des c ription s 8ma pd synchrono us to the risin g e dge of txcl k. these pin s act as mii txd[3:2]. p 4 f x 6 2 i pd port4 fx/tx mode sele ct. internal p u ll d o wn. 1: port4 as f x port. 0: port4 as t x port. xen setting phyas0 6 6 i / o 8ma pd mii transmit enable/gpsi txen. intern al pull do wn. setting phyas0: chi p physi cal address for mult iple chi p appli c ation on read eeprom data. internal pull down. power on reset value phyas0 c o mbines with phya s1 phyas1 phyas0 0 0 mas t er(93c46) if there is no eeprom then us er mus t us e 93c66 timing to write chip? s register. if user put 93 c46 with co rrect signatu r e then use r wri t es chip regi ster by 93c4 6 timing. if user put 93 c66 the n dat a put in bank0. use r can write chip regi ster by 93c6 6 timing. user mu st asse rt one sk cycle wh en cs at idle stage whe n write chip inte rnal regi ster. r x d [ 0 ] 7 4 i pd mii port recei v e data 0 /gpsi rxd the s e pin s a c t as mii rxd[0]. synchro nou s to the ri sing edge of rx clk. internal p u ll down. r x d [ 3 : 1 ] 1 0 2 , 1 0 1 , 100 i pd mii port recei v e data 3~1 the s e pin s a c t as mii rxd[3:1]. synch r on ou s to the risi ng edge of rx clk. internal p u ll down. r x d v 7 3 i pd mii rec e ive data valid. internal pull down. r x e r 6 8 i pd mii port rece iv e error. internal pull down. c o l 7 8 i pd mii port collision in put /gpsi collision input internal pull down. c r s 7 7 i pd mii port carrier sens e /gp s i carrier sens e internal pull down. r x c l k 7 2 i pd mii port rec e ive clock input /gpsi rx clk t x c l k 6 7 i pd mii port trans m it c l ock input /gpsi txc l k dha l f p 5 9 1 i pd mii port hard wa re duplex i nput pin. low: full dup l ex. high: hal f duplex. internal pull down. l n k f p 5 9 0 i pd mii port hardware link input pin. low: link ok . high: link off. internal pull down. s p d t n p 5 8 9 i pd mii port hard wa re spee d input pin. low: 10 0m. high: 10 m. internal pull down. infineon-admtek co. ltd. 2-3
ADM6996L interf ace description 2.2.3 led interface pin name pin# t y pe des c ription s lnkact[4:0] 92, 95, 96, 97 , 98 o, 8ma link/ activ i ty led[4:0 ] . ac tive low ?1? in dicates no link a c tivity on cable ?0? in dicates l i nk o k ay on cable, but no a c tivity and sig nals on idle sta ge. ?blinki ng ? indi cate s link a c ti vity on cable. dup co l [ 4 : 3 ] 1 0 3 , 1 0 6 o , 8ma duplex/ collision led[4:3]. ac tive low ?1? fo r half-d u p lex and ?blin king ? for collision indi cation ?0? fo r full-du plex indicatio n dup co l2 setting bpen 1 0 7 o , 8ma, pu duplex/ collision led2. ac tive low ?1? fo r half-d u p lex and ?blin king ? for collision indi cation ?0? fo r full-du plex indicatio n setting bpen: at po wer-on-reset, latched as b a ck pressure setting ?1? to en able back-pressu r e (defa u lted), ?0? to disable back press u re. at power-o n-reset, latch ed as ba ck pressu re setting ?1? to enabl e back-pressu r e (def aulted ) , ?0? to disabl e back press u re. dup co l1 setting phyas1 1 0 8 o , 8ma, pd duplex/ collision led1. ac tive low ?1? fo r half-d u p lex and ?blin king ? for collision indi cation ?0? fo r full-du plex indicatio n setting phyas1: power on reset latc h value combine with txen. internal p u ll d o wn. che ck p i n 66. dup co l0 setting anen 1 0 9 o , 8ma, pu duplex/ collision led0. ac tive low ?1? fo r half-d u p lex and ?blin king ? for collision indi cation ?0? fo r full-du plex indicatio n setting anen: on po we r-o n-re set, latched a s a u to neg o tiation capability for all port s . ?1? to en able auto neg o tiation ( defa u lte d by pulled u p internally ), ?0? to di sabl e auto neg o tiation. ldspd[4:0] 58, 55, 54, 51 , 50 o, 8ma speed led[4:0 ] . use d to indicate co rresp ondi ng po rt?s spe ed statu s . ?0? for 1 00m b/s, ?1? fo r 10 mb/s infineon-admtek co. ltd. 2-4
ADM6996L interf ace description 2.2.4 eeprom/management interface pin name pin# t y pe des c ription s e d o 8 4 i , ttl,pu eeprom data output. serial data input from eeprom. this pi n is int e rnally pull-up. e e c s 8 0 o , 4ma,pd eeprom chip select. this pin is a c tive high chip e nable for eeprom. when resetl is low, it will be tri-state. internally pull-down eeck setting xoven 8 1 i / o , 4ma pd serial clock . this pin is c l ock s o urc e for eeprom. when resetl is low, it will be tri-state. setting xoven: this pin is internal pull-d o wn. on power-on - reset, latche d as p4 ~0 auto mdi x enable o r n o t. ?0? to di sabl e mdix ( defaul ted ), ?1? to enabl e mdix. sugge st externally pull u p to enable m d ix for all ports. edi setting ledmo d e 7 9 i / o , 4ma pd eeprom serial data input. this pin i s output for serial data transfer. when resetl is low, it will be tri-state. setting ledmo d e: this pin i s internal pull - do wn . on powe r -o n- re set, latche d as du al col o r mode o r not . ?0? to set single c o lor mode for led. ?1? to set dua l colo r mode for led. 2.2.5 po w er/ground, 48 pins infineon-admtek co. ltd. 2-5 pin name pin# t y pe des c ription s gnda 3, 10, 16, 23, 29, 36, 42, 125 i gro und used by ad block. vcca2 6, 7, 19, 20, 32, 33, 45, 122 i 1.8v, power used by tx line driver. vcca d 1 3 , 2 6 , 39, 128 i 3.3v, power used by ad block. gndbias 119 i gro und used by bias block vccbias 121 i 3.3v, power used by bias block. gndpll 116 i gro und u s e d by pll vccpl l 115 i 1.8v, power use d by pll gndik 47, 52, 64, 76, 93, 83, 111 i gro und used by digital co re vccik 48, 53, 65, 75, 82, 94, 110 i 1.8v, power used by digit a l co re gndo 46, 57, 70, 87 , 99, 104 i gro und used by digital pad v c c 3 o 5 6 , 7 1 , 88, 105 i 3.3v, power used by digit a l pad. gnd 69 i gro und used by digital pad.
ADM6996L interf ace description 2.2.6 misc pin name pin# t y pe des c ription s cko2 5 m 8 5 o , 8ma 25m cloc k o u tpu t . cont r o l 1 1 7 o fet control signal. the pin i s used to cont rol fet for 3.3v to 1.8v regul ator. r t x 1 2 0 analog tx resis t or. add 1.1k %1 re siste r to gnd. v r e f 1 1 8 a n a l o g analog refe rence voltag e. r c 1 1 2 i , sche rc inpu t for po w e r on re set. reset input pin. x i 1 1 3 i , analog 25m cry s tal input. 25m cry s tal input. variation is l i mited to +/- 50p pm. x o 1 1 4 o , analog 25m cry s tal outpu t . when connected to o scillator, this pin s h ou ld le ft u n c o nn ec te d . cfg 0 8 6 i , ttl must conn ected to gnd. t e s t 4 9 i , ttl test value. at normal ap plicatio n co nn ect to gnd. nc 1, 2, 4,5, 14, 15,17, 18, 27,28, n c infineon-admtek co. ltd. 2-6
ADM6996L function description chapter 3 function description 3.1 functional descriptions the ADM6996L integrates five 100base- x physical sub-layer (phy), 100base-tx physical m e dium dependent (pmd) transceive rs, five com p lete 10base-t m odules, 6 port 10/100 switch controller and one 10/100 mii/g psi mac and m e mory into a single chip for both 10mbits/s, 100mbits/s ethernet swit ch operation. it also supports 100base-fx operation through external fiber-optic transcei vers. the device is capable of operating in either full duplex m o de or half-duplex m ode in 10mbits/s and 100mbits/s. operational modes can be selected by hardware configura tion pins, software settings of m a nage m e nt registers, or determ ined by the on-chip auto negotiation logic. the ADM6996L consists of three m a jor blocks: ? ? ? ? ? ? ? ? ? ?
ADM6996L function description 3.4 100base-x receiver the 100base-x receiver consists of functional blocks require d to recover and condition the 125mbits/s receive data stream. the ADM6996L imple m ents the 100base-x receiv i ng state m achine diagram as given in ansi/ieee standard 802.3u, clause 24. the 125mbits/s receive data stream m a y originate fro m the on-ch ip twisted-pair transceiver in a 100base-t x application. altern atively, the receive data stre am may be generated by an external optical receiver as in a 100b ase-fx application. the receiv e r block consists of the following functional sub - blocks: ? ? ? ? ? ? ? ? ? 3.4.1 a/d conve r ter high perform a nce a/d converter with 125mhz sam p ling rate converts signals received on rxp/rxn pins to 6 bits data stream s; be sides it possess auto-gai n-control capability that will further im prove receiv e perfor m a nce especially under long cable or harsh detrim ental signal in tegr ity. due to high pass characteristic on transf or m e r, built in base- line-wande r correc ting c i rcuit will c a n cel it out and restore its dc level. 3.4.2 adaptive equaliz er and timing recovery mod u le all digital d e sign is espe cial immune from noise environm ents and achieves better correlation between production and system te stin g. baud rate adaptive eq ualize r /tim ing recovery co mpensates line loss indu ced from twi s ted pair and tracks far end clock at 125m sam p l e s per second. adaptive equalizer imple m e nted with feed forward and decision feedback tech niques m eet the re quirem ent of ber l e ss than 10-12 for transm ission on cat5 t w isted pair cable ranging from 0 to 120 m e ters. 3.4.3 nrz i /nr z and serial/parallel decoder the recovered data is converted from nrzi to nrz. the data is not necessarily aligned to 4b/5b code group?s boundary. infineon-admtek co. ltd. 3-2
ADM6996L function description 3.4.4 data de-scrambling the de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or m o re bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scram b ling lfsr. upon achieving synchronization, the incom i ng data is xored by the deciphering lfsr and de-scram bled. in order to m a intain synchronization, the de-s cram bler continuously m o nitors the validity of the unscram bled data that it generates. to ensure this, a link state m onitor and a hold tim er are used to constantly m onitor the s ynchronization status. upon synchronization of the de-scrambler the hold tim er starts a 722 us countdown. upon detection of suffic i ent idle sym bols within the 7 22 us period , the hold tim er will res e t and begin a new countdown. this m onitoring operation will c ontinue indefinitely given a properly operating network connection with good signal integrity. if the link state monitor does not recognize sufficient unscram bled idle sym bols within 722 us period, the de-scrambler will be f o rce d out of the curren t sta t e of synchronization and r e set in o r der to re- acquir e synchronization. 3.4.5 symbol alignment the sym bol alignm ent circuit in the adm 6996l determ ines code word alignm ent by recognizing the /j/k delim iter pair. this ci rcuit operates on unaligned data from the de- scram b ler. once the /j/k sym bol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 3.4.6 symbol decoding the sym bol decoder functions as a look-up ta ble that translates incom i ng 5b sym bols into 4b nibbles as shown in table 1. the sy m bol decoder first detects the /j/k sym bol pair preceded by idle sy mbols and replaces the s y m bol with mac preamble. all subsequent 5b sym bols are converted to th e corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r symbol pair denoting the end of stream delim iter (esd). the trans l ated d a ta is p r esen ted on the internal rxd[3:0] signal lines with rxd[0] represents the least significant bit of the trans l ated n i bble. 3.4.7 valid data signal the valid data signal (rxdv) indicates that recovered a nd decoded nibbles are being presented on the internal rxd[3:0] s ync hronous to receive clock, rxclk. rxdv is asserted when the firs t n i bble of tran slated /j/k is ready for transfer over the interna l mii. it rem a ins active un til either th e /t/r delim iter is recognized, link test ind i cates failure, or no signal is detected. on any of th ese condition s , rxdv is de-asse rted. infineon-admtek co. ltd. 3-3
ADM6996L function description 3.4.8 receive errors the rxer s i gnal is used to communicate recei v e r error conditions. w h ile the receiver is in a state of holding rxdv asserted, the rxer will be asserted for each code word that does not m a p to a valid code-group. 3.4.9 100base-x link monitor the 100base-x link m o nitor functio n allows the receiv e r to ensure th at reliable data is being receiv ed. w ithout reliable data recepti on, the link m onitor will halt both tran sm i t and rece ive operations u n til su ch tim e that a v a lid link is d e tected. the adm6 996l perform s the link integrity te st as outlined in ieee 100base-x (clause 24) link m onitor s t ate diagram . the link stat us is m u ltiplexed with 10mbits/s link s t atus to form the reportable link status bit in seri al m a nagem e nt register 1h, and driven to the lnkact pi n. when persistent signal energy is detected on the network, the logic m oves into a link- ready state after approxim ately 500 us, and wait s for an enable from the auto negotiation module. w h en receive, the link-up state is entered, and the transm ission and recep tio n logic blocks becom e active. should auto negot iation be disabled, the link integrity logic moves immediately to the link-up state after entering th e lin k-ready s t ate. 3.4.10 carrier sen s e carrier sense (crs) for 100mbits/s operation is asserted upon th e detection of two noncontiguous zeros occurring within any 10-b it boundary of the received data stream . the carrier sense function is independent of symbol alignm ent. in switch m ode, crs is asserted during either packet transm ission or reception. for repeater m ode, crs is asserted only during packet reception. w h en th e idle sym bol pair is detected in the receiv e d data stream , crs is de-ass erted. in rep eater m ode, crs is only asserted due to receiv e activ ity. crs is intended to encapsulate rxdv. 3.4.11 bad ssd detection a bad start of stream de lim iter (bad ssd) is an error condition that occu rs in the 100base-x receiver if carrier is d e tected (crs asserted ) and a valid /j/k set of code- group (ssd) is not received. if this condition is detected, then th e ADM6996L will ass e rt rxer and present rxd[3:0] = 1110 to the internal mii for the cycles hat corr espond to received 5b code- groups until at least two idle code-groups are detected. once at least two idle code groups are detected, rxer and crs become de-ass erted. infineon-admtek co. ltd. 3-4
ADM6996L function description 3.4.12 far-end fault auto negotiation provides a m echanism for trans f erring inform ation from the local station to the link partner that a rem o te fault has occurred for 100base-tx. as auto negotiation is not currently specified for opera tion over fiber, the far end fault indication function (fefi) provides this capabi lity for 100base-fx applications. a rem o te f a ult is an er ro r in the link that one station can detect while the other cannot. an exam ple of this is a d i sc onnected wire at a sta tio n?s tr ansm itter. this s t ation will be receiv i ng va lid data and detect that the link is go od via the li nk integrity monitor, but will not be able to detect that its transm i ssion is not propagating to the other station. a 100base-fx station that detects s u ch a re m o te fault m a y modify its transm itted id le stream from all ones to a group of 84 ones fo llowed by a single 0. this is referred to as the fefi idle patte rn. 3.5 100base-tx transceiver ADM6996L im ple m ents a tp-pmd com p liant transceiver for 100base-t x operation. the differential transm it driver is shared by the 10base-t and 100base-tx subsystem s . this arrangem e nt results in one device that uses the sam e external m a gnetic for both the 10base-t and the 100base-tx transm ission w ith sim p le rc com ponent connections. the individually wave-shaped 10base-t and 100base-tx transm it signals are multiplexed in the trans m issi on output driver selection. 3.5.1 transmit d r ivers the ADM6996L 100base-tx transm ission driv er im ple m ents mlt-3 translation and wave-shaping functions. the rise /f all tim e of the output sign al is closely controlled to confor m to the target range specified in the ansi tp-pmd standard. 3.5.2 tw isted-pair receiver for 100base-tx operation, the incom i ng signal is detected by the on-chip twisted-pair receiv e r th at consists of a differential line r eceiv er, an adap tive equalizer and a base-line wander compensation circuits. the ADM6996L uses an adaptive equalizer th at changes filter frequency response in accordance with cable length. the cable leng th is estim ated based on the incom i ng signal strength. the equalizer tunes its elf a u tom a tically f o r any cable length to c o m p ensate f o r the am plitude and phase distorti ons incurred from the cable. 3.6 10base-t module infineon-admtek co. ltd. 3-5 the 10base-t transceiver module is ieee 802.3 com p liant. it includes the receiver, transm itter, collision, heartbea t, loop back, jabber, wave shap er, and link integrity
ADM6996L function description functions, as defined in the standard. figur e 3 provides an overview for the 10base-t module. the ADM6996L 10base-t m odule is com p rise d of the following functional blocks: ? ? ? ? ? ? ?
ADM6996L function description and tim ing m easure m en ts (as specified in the ieee 802.3 10base-t standard) to determ ine the validity of data on the twisted-pair inputs. the signal at the s t art of the packet is checked by the analog s quelch circuit and any pulses not exceeding th e squelch lev e l (either po sitiv e or neg a tive, dep e n d ing upon polarity) will be rejected. once this first s quelch level is overcom e correctly, the opposite squelch level m u st then be exceeded within 150n s. finally, th e signal m u st exceed the original squ e lch lev e l within an add i tional 150ns to ensure that the inpu t waveform will not be rejected. only after all these conditions have b een sa tisfied will a con t rol signal be generated to indicate to the rem a inder of the circ uitry that valid data is present. valid data is consider ed to be presen t until the squ e lch lev e l ha s not been g e nerated f o r a tim e longer than 200 ns, indicating end of p acket. once good data has been detected, the squelch levels are reduced to m i ni m i ze the effect of noise, causi ng prem ature end-of- packet detection. the receive squelch thresh old level can be lowered for use in longer cable applications. this is achieved by setting bit 10 of re gister address 11h. 3.7 carri er sense carrier sens e (crs) is asserted due to receiv e activity once v a lid data is d e tected via the sm art squelch function. for 10 mbits/s half duplex operation, crs is asserted during either packet tran sm ission or recep tio n. for 10 mbits/s full du plex and rep eater m ode operations, the crs is asserted only due to receive activity. 3.8 jabber function the jabber f unction m o nitors the ADM6996L out put and disables the tran sm itter if it attem p ts to transm it a lo nger than le gal siz e d packet. if txen is high for greater than 24m s , the 10base-t tra n sm itter will be disabled. once disabled by the ja bber f unctio n, the tr ansm itter stay s disa bled f o r the entir e tim e that the txen signal is a sserted. this signal has to be de-asserted for approxim atel y 256 m s (the un-jab tim e ) before the jabber function re-enables the transm it outputs. the jabber function can be disabled by programm i ng bit 4 of regi ster address 10h to high. 3.9 link test function a link pulse is used to check he integrity of the connection with the remote end. if valid link puls e s are not receiv e d, the link detect o r dis a bles the 10b ase-t twis ted-pair transm itter, receiv e r, an d collision d e tection functions. the link pulse generator produces pulses as defined in ieee 802.3 10base-t standard. each link pu lse is nom inally 100ns in durati on and is transmitted ev ery 1 6 m s , in the absence of transm it data. infineon-admtek co. ltd. 3-7
ADM6996L function description 3.10 automatic link polarity detection ADM6996L?s 10base-t transceiver module inco rporates an ?autom atic link polarity detection circuit?. the inverted po lar i ty is de term ined wh en seven consecutive link pulses of inverted polarity or three consecu tive packets are received with inverted end-of-packet pulses. if th e input polarity is reversed, the error condition will be autom a tically corrected and reported in bit 5 of register 10h. 3.11 clock synthesiz er the ADM6996L im ple m ents a clock synthesizer that generates all th e reference clocks needed from a single external frequency s ource. the clock source m u st be a ttl level signal at 25 mhz +/- 50ppm 3.12 auto negotiation the auto negotiation function provides a m echanism for exchanging con f iguration inform ation between two ends of a link segm ent and autom a tically selecting the highest perform a nce m ode of operation supported by both devices. f a st link pulse (flp) bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link seg m ent. for further d e tail regarding au to negotiatio n, refer to clause 28 of the ieee 802.3u specification. the ADM6996L supports four different ethernet protocols, so the inclusion of auto negotiati on ensures that the highest perform a nce protocol will be selected based on the ability of the link partner. highest pr io rity rela tive to the f o llow i ng lis t: ? ? ? ?
ADM6996L function description 3.14 sw itch functional description the ADM6996L uses a ?store & forward? sw itching approach for the following reason: store & forward switches allow switching be tween different speed m e dia (e.g. 10basex and 100basex). such switches require the large elastic buffer especially bridging between a server on a 100mbps netw or k and clients on a 10mbps segm e n t. store & forward switches im prove overall netw ork performance by acting as a ?network cache? store & forward switch e s preven t th e forwardin g of corrupted packets b y the fram e check sequence (f cs) before forwarding to the destination port. 3.15 basic operation the ADM6996L receiv e s incom i ng packets fro m one of its ports, search es in the ad dress table f o r th e destina tio n mac address and th en forwards the packet to the other port within sam e vlan group, if appropriate. if the destination address is not found in the address table, the ADM6996L treats the packet as a broadcast packet and forwards the packet to the other ports which in sam e vlan group. the ADM6996L automatically learns the port num b er of attached network devices by exam ining the source m a c address of all inco ming packets at wire sp eed. if the source address is not found in the address tabl e, the device adds it to the table. 3.15.1 address learning the ADM6996L uses a hash algorithm to lear n the mac address and can learn up to 2k mac addresses. address is stored in the address table. the ADM6996L searches for the source address (s a) of an incom i ng packet in the address table and acts as below: if the sa was not found in the address table (a new addre ss), the ADM6996L waits until the en d of the packet (non -error packet ) and updates the address table. if the sa was found in the address table, th en aging value of each correspond ing entry will be reset to 0. when the da is pause command, then the learn i ng process w ill be d i sabled autom a tically by ADM6996L. infineon-admtek co. ltd. 3-9
ADM6996L function description 3.15.2 address recognition and packet f o rw arding the ADM6996L forwards the inco m i ng packets between b r idged po rts accord ing to the destination address (da) as below. all th e packet f o rwar ding will ch eck vlan f i rst. forwarding port m u st sam e vlan with source port. 1) if the da i s an unicast address a nd the address was found in the address table, the a d m6996l will check the port number and acts as follows:
ADM6996L function description 3.15.6 illegal frames the ADM6996L will discard all i llegal fram es such as runt packet (less than 64 bytes), oversize packet (greater than 1518 or 1522 byt es) and bad crc. dribbling packing with good crc value will accep t by ADM6996L. in case of bypass m ode enabled, ADM6996L will support tag and untagged packets with size up to 1522 bytes. in cas e of non-bypass mode, ADM6996L will support ta g packets up to 1526 bytes, untagged packets up to 1522bytes. 3.15.7 half duplex flow control back pressure function is supported fo r half-duplex operation. w h en the ADM6996L cannot allo cate a receiv e buffer for an in com i ng packet (buffer full), the device will transm it a jam pattern on the po rt, thus forcing a collision. b ack pressure is enabled by the bpen set during reset asserting. an infineon-admtek co ltd proprietary algorithm is im ple m ented inside the ADM6996L to prevent back pressure function cause hub partitioned under heavy tr affic environm ent and reduce the packet lost rate to increase the whole system perfor m a nce. 3.15.8 full duplex flow control w h en full duplex port run out of its recei v e buffer, a pause packet co mmand will be issued by ADM6996L to notice the packet se nder to pause transm ission. this fra m e based flow control is totally com p liant to ieee 802.3x. ADM6996L can issue or receive pause packet. 3.15.9 broadcast storm filter if broadcast storm i ng filte r is enab le, the broa dcast pa ckets over the r i sing thresh old within 50 ms will be d i s carded by th e thresho l d s e tting. see eeprom reg.10h. broadcast s t orm mode after in itial: - tim e interv al : 50m s the m a x. packet num ber = 7490 in 100base, 749 in 10base 3.16 auto tp mdix function at norm a l applica tion w h ich switch connect to nic card is by one by one tp cable. if infineon-admtek co. ltd. 3-11 per port falling threshold 0 0 0 1 1 0 1 1 all 100tx disable 5% 10% 20% n o t a l l 100tx d i s a b l e 0 . 5 % 1 % 2 % per port rising threshold 0 0 0 1 1 0 1 1 all 100tx disable 10% 20% 40% n o t a l l 100tx d i s a b l e 1 % 2 % 4 %
ADM6996L function description switch connect other device such as another sw itch m u st by two way. first one is c r oss over tp cable. second way is u s e extra rj 45 which c r ossov e r in te rn al tx+- and rx +- signal. by second way custom er can use one by one cable to connect tw o switch devices. all these effort need extra cost and not good solution. ADM6996L provide auto mdix function which can adju st tx+- and rx+- at co rrect pin. us er can use one by one cable between ADM6996L and other device. this func tion can be enable/disable by hardware pin and eeprom configuration register 0x01h~0x09h bit 15. if hardware pin set all port at auto mdix m ode then eeprom setting is us eless. if hardware pin set all port at non auto mdix m ode then eeprom c a n set each port this function en able or disable. 3.17 port locking port locking function will provide custom er si mple way to lim it per port user num ber to one. if this f unction is turn on then ADM6996L will lock first mac address in learning table. af ter this mac address locking will never age out except reset signal. another mac address which not sam e as locking one will be dropped. ADM6996L provide one mac address per port. this function is per port setting. when turn on port locking function, recomm end custom er turn off ag ing function. see eepro m register 0x12h bit 0~8. 3.18 vlan setting & tag/ untag & port-base vlan ADM6996L supports bypass m ode and untagged port as default setting while the chip is power -on. thus, every packet with o r without tag will be forwardi ng to the destination port without any m odifi cation by ADM6996L. meanwhile port-base vlan could be enabled according to the pvid value ( user define 4bits to m a p 16 groups written at register 13 to register 22 ) of the configuration content of each port. ADM6996L also supports 16 802.1q vlan groups . in vlan four bytes tag include twelve vlan id. adm 6996l learn us er define four bits of vid. if user need to use this function, two eeprom registers are n eeded to be programm e d first : * port vid num b er at e e prom regist er 0x01h~ 0x09h bit 13~10, register 0x28h~0x2bh and register 0x2ch bit 7~0: ADM6996L will ch eck com i ng packet. if com i ng packet is non vlan packet then ADM6996L will us e pvid as vlan group reference. ADM6996L will use packet? s vlan value when receiv e tagg ed packet. * vlan group mapping register . eeprom re gister 013h~ 022h define vlan grouping value. user use these regi ster to define vlan group. user can define each port as t a g port or un tag port by configuration register bit 4. the operation of packet between t a g port and untag port can explain by follow exa m ple: example1: port r eceiv e s untag pa cket and send to untag port. infineon-admtek co. ltd. 3-12 ADM6996L will check the port u s er define f our bits of vlan id first then check vlan group resister . if destination port sam e vlan as receiving port then this packet will f o rward to des tina t ion port with out any ch a nge. if destination po rt not sam e vlan
ADM6996L function description as receiving port then this packet will be dropped. example2: port r eceiv e s untag packet and send to t ag port. ADM6996L will check the port user define four s bits of vlan id first then check vlan group resister . if destination port sam e vlan as receiving port than this packet will forward to d e stination port with four byte vlan t a g and new crc. if destination port not same vlan as receiv i ng po rt then this p acket will be dropped. example3: port r eceiv e s t ag packet and send to untag port. ADM6996L will check the packet vlan id first then check vlan group resis t er . if destin atio n port same vlan as rec e ivin g port than this p acket will f o rward to destination port after remove f our bytes with new crc error . if destination port not same vlan as receiving po rt then this packet will b e d r opped. example4: port r eceiv e s t ag packet and send to t ag port. ADM6996L will check the user define pack et vlan id first then ch eck vlan group resister . if destination port sam e vlan as receiving port than this packet will forward to destination port w ithout any change. if destinat ion port not sam e vlan as receiv i ng po rt then this p acket will be dropped. 3.19 priority setting it is a trend that data, v o ice and vid e o will be put on networking, switch not only deal data packet but also p r ovide serv ice of m u ltim edia data. ADM6996L provides two priority queues on each port with n:1 rate. see e e prom re g.0x10h. this priority function can set three w a ys as below : * by port base: set specifi c port at specific queue. ad m6996l only check the port priority and not check pack et? s content vlan and t o s. * by vlan first: ADM6996L chec k vlan three priority bit fi rst then ip t o s priority bits. * by ip t o s first: ADM6996L check ip t o s th ree priority bit firs t then vlan three prior ity bits. if port set at vlan/ t o s priority but receiving packet without vlan or t o s inf o rm ation then port b a se prio rity w ill be u s ed . 3.20 led display three led per port are provided by ADM6996L . link/act, duplex/c ol & speed are three led display of a d m6996l. dual co lor led m ode also supported by ADM6996L. for easy production pu rpose ADM6996L will send te s t sig n al to each led at power on reset stage. eeprom re gister 0x12h define led configuration table. infineon-admtek co. ltd. 3-13
ADM6996L function description ADM6996L led is active low signal. dupcol0 & dupcol1 will check external sign al at reset tim e . if externa l s i gnal add pu ll high th en led will ac tive low . if extern al s i g n al add pull down resister then led wi ll drive high. vc c d? led r? 5 1 0 d? led d? led r? 5 1 0 single color mode dual color mode l e d- hi g h speed li nk / a c t infineon-admtek co. ltd. 3-14
ADM6996L register description chapter 4 register description 4.1 eeprom content eeprom provides ADM6996L m a ny options s e tting such as: ? ? ? ? ? ?
ADM6996L register description register bit 15- 8 bit 7 - 0 default v a lue 0x1ah vlan 7 out bound port map vlan 7 out bound port map 0x ffff h 0x1bh vlan 8 out bound port map vlan 8 out bound port map 0x ffff h 0x1ch vlan 9 out bound port map vlan 9 out bound port map 0x ffff h 0x1dh vlan 10 outbound port map vlan 10 outbound port map 0x ffff h 0x1eh vlan 1 1 outbound port map vlan 1 1 outbound port map 0x ffff h 0x1fh vlan 12 outbound port map vlan 12 outbound port map 0x ffff h 0x20h vlan 13 outbound port map vlan 13 outbound port map 0x ffff h 0x21h vlan 14 outbound port map vlan 14 outbound port map 0x ffff h 0x22h vlan 15 outbound port map vlan 15 outbound port map 0x ffff h 0 x 2 3 h r e s e r v e d r e s e r v e d 0 x 0 0 0 0 h 0 x 2 4 h r e s e r v e d r e s e r v e d 0 x 0 0 0 0 h 0 x 2 5 h r e s e r v e d r e s e r v e d 0 x 0 0 0 0 h 0 x 2 6 h r e s e r v e d r e s e r v e d 0 x 0 0 0 0 h 0 x 2 7 h r e s e r v e d r e s e r v e d 0 x 0 0 0 0 h 0x28h reserved p0 pvid [1 1:4] 0x0000h 0x29h reserved p1 pvid [1 1:4] 0x0000h 0x2ah reserved p2 pvid [1 1:4] 0x0000h 0x2bh p4 pvid [1 1:4] p3 pvid [1 1:4] 0x0000h 0x2ch vlan group configuration p5 pvid [1 1:4] 0xd000h 0 x 2 d h r e s e r v e d 0 x 4 4 4 2 h 0 x 2 e h r e s e r v e d 0 x 0 0 0 0 h 0 x 2 f h p h y r e s t a r t 0 x 0 0 0 0 h 0x30h miscellaneous configuration 3 miscellaneous configuration 3 0x0987h 0x31h bandwidth control register 3,2 bandwidth control register 1,0 0x0000h 0x32h reserved bandwidth control register 5,4 0x0000h 0x33h bandwidth control enable bandwidth control enable 0x0000h 4.3 eeprom register 4.3.1 signatur e register , offset: 0x00h bits t ype description initial va lue 15:0 ro the value must be 4154h(a t) 0x4154h note: ADM6996L will check register 0 value before read all eeprom content. if this valu e not m a tch with 0x4154h then other v a lues in eep rom will be useles s. ADM6996L will use internal default valu e. user cann o t wr ite s i gnature register when programm ing ADM6996L internal register. infineon-admtek co. ltd. 4-2
ADM6996L register description 4.3.2 configuration registers, offset: 0x01h ~ 0x09h bits t ype description initial va lue 0 r/ w 802.3x flow control comm and ability . 1: enable. 0: disable. 0x1h 1 r/ w auto negotiation enable. 1: enable, 0: disable. 0x1h 2 r/ w speed. 1: 100m, 0: 10m. 0x1h 3 r/ w duplex. 1: full duplex, 0: half duplex. 0x1h 4 r/ w output packet t a gging. 1: t a g. 0:unt a g. 0x0h 5 r/ w port disable. 1: disabl e port. 0: enable port. 0x0h 6 r/ w t o s over vlan priority . 1: check t o s first, 0: check vlan. 0x0h 7 r/ w enable port-base priority . 1: port base priority . 0: vlan or t o s. if packet without vlan or t o s th en port priority turn on. note: if this bit turn on then ADM6996L will not ch eck t o s or vlan as priority reference. ADM6996L will check port base prio rity o n ly . ADM6996L default is bypass m ode which checks port base priority only . if user want check vlan tag priority then m u st set chip at t a g m ode. 0x0h 9:8 r/ w port-base priority . 0x0h 13:10 r/ w pvid. port vlan id. check register 0x28h~0x2ch for other pvid[1 1:4] 0x1h 14 r/ w select fx. 1: fx m ode. 0: tp m ode. note: port7 tx/fx can set by hardware r e set latch value p7fx. if hardware pin set por t 7 as fx then this bit is useless. if hardware pin set port7 as tx then this pin can se t port7 as fx or tx. 0x0h 15 r/ w crossover a u to mdix enable. 1: enable. 0: disable. note: hardware reset latch value eeck can set global auto mdix function. if hardware pin set all port at auto md ix then this bit is u s ele s s . if hardware pin set chip at non auto mdix then this bit can set each port at auto mdix. 0x0h 4.3.3 reserved register, offset: 0x0ah bits t ype description initial va lue 8 : 0 r o r e s e r v e d 0 x 1 0 2 h 9 r/ w replaced packet vid 0, 1 by pv id. 1: enable, 0 : disable. 0x0h 1 5 : 1 0 r o r e s e r v e d 0 x 1 6 h infineon-admtek co. ltd. 4-3
ADM6996L register description 4.3.4 configuration register, offset: 0x0bh bits t ype description initial va lue 5 : 0 r o r e s e r v e d 0 x 0 h 6 r/ w enable ipg leveling. 1/92 bit. 0/96 bit. note: when this bit is enab le a d m6996l w ill transm it packet out at 92 bit ipg to clean buf fer . if user d i sables this f unction th en ADM6996L will transm it pac k et at 96 b it. 0x0h 7 r/ w enable t r unk. 1: enable port3, 4 as t r unk port. 0: disable. 0x0h 1 4 : 8 r o r e s e r v e d 0 x 0 h 1 5 r / w disable far_end_fault detecti on. 1: disable. 0: enable. 0x1h 4.3.5 reserved register, offset: 0x0ch~0x0dh bits t ype description initial va lue 1 5 : 0 r o r e s e r v e d 0 x f a 5 h 4.3.6 vlan priority map r e gister, offset: 0x0eh bits t ype description initial va lue 1:0 r/ w mapped priority of tag value (vlan) 0. 0x0h 3:2 r/ w mapped priority of tag value (vlan) 1. 0x0h 5:4 r/ w mapped priority of tag value (vlan) 2. 0x1h 7:6 r/ w mapped priority of tag value (vlan) 3. 0x1h 9:8 r/ w mapped priority of tag value (vlan) 4. 0x2h 11:10 r/ w mapped priority of tag value (vlan) 5. 0x2h 13:12 r/ w mapped priority of tag value (vlan) 6. 0x3h 15:14 r/ w mapped priority of tag value (vlan) 7. 0x3h note: v a lue 3 ~ 0 are for priority queue q3~q0 respectively . the w e ight ratio is q3 : q2 : q1: q0 = 8 : 4 : 2 : 1. the default is port-base priority for un-tag packet and non_ip fra m e. 4.3.7 tos priority map register, offset: 0x0fh infineon-admtek co. ltd. 4-4 bits t ype description initial va lue 1:0 r/ w mapped priority of tag value (tos) 0. 0x0h 3:2 r/ w mapped priority of tag value (tos) 1. 0x0h 5:4 r/ w mapped priority of tag value (tos) 2. 0x1h 7:6 r/ w mapped priority of tag value (tos) 3. 0x1h 9:8 r/ w mapped priority of tag value (tos) 4. 0x2h 11:10 r/ w mapped priority of tag value (tos) 5. 0x2h
ADM6996L register description bits t ype description initial va lue 13:12 r/ w mapped priority of tag value (tos) 6. 0x3h 15:14 r/ w mapped priority of tag value (tos) 7. 0x3h note: v a lue 3 ~ 0 are for priority queue q3~q0 respectively . the w e ight ratio is q3 : q2 : q1: q0 = 8 : 4 : 2 : 1. the default is port-base priority for un-tag packet and non_ip fra m e. 4.3.8 packet w i th priority: normal packet content ethernet packet from la yer 2 pream b l e / s f d d e s t i n a t i o n ( 6 bytes) source (6 bytes) packet length (2 bytes) data (46-1500 bytes) crc (4 bytes) byte 0~5 byte 6~1 1 byte 12~13 byte 14~ 4.3.9 vlan pac k et ADM6996L will check packet byte 12 &13. if byte[12:13]=8100h then this packet is a vlan pack et byte 12~13 byte14~15 byte 16~17 byte 18 byte 14~15: t a g control inform ation tci bit[15:13]: user priority 7~0 bit 12: canonical form at indicator (c fi) bit[ 1 1 ~0] : vlan id. the ADM6996L will use bit[ 3:0] as vlan group. infineon-admtek co. ltd. 4-5 t a g protocol td 8100 t a g control inform ation tci len length routing inform ation
ADM6996L register description 4.3.10 tos ip packet ADM6996L check byte 12 &13 if this value is 0800h then ADM6996L knows this is a t o p priority packet. t ype 0800 ip header byte 12~13 byte 14~15 ip header define byte 14 bit[7:0]: ip protocol ve rsion num ber & header length. byte 15: service type bit[ 7~5] : ip priori ty (precedence ) from 7~0 bit 4: no delay (d) bit 3: high throughput bit 2: high reliability ( r ) bit[ 1:0] : reserved 4.3.11 miscellaneous configuration register, offset: 0x10h bits t ype description initial va lue 1:0 r/ w broadcast s t orm i ng thre shold[1:0]. see below table. 0x0h 2 r/ w broadcast s t orm i ng ena b le. 1/ enable, 0/disable. default 0. 0x0h 3 r/ w reserved. default 0. 0x0h 4 r/ w xcrc. 1/disable crc check, 0/enable crc che c k. default 0. 0x0h 5 r o r e s e r v e d 0 x 0 h 6 r o r e s e r v e d 0 x 1 h 7 r/ w aging disable. 1/disable ag ing, 0/enable aging. d e fault 0. 0x0h 9:8 r/ w discard m o de (drop schem e for q0) 0x0h 1 1 :10 r/ w discard m o de (drop schem e for q1) 0x0h 13:12 r/ w discard m o de (drop schem e for q2) 0x0h 15:14 r/ w discard m o de (drop schem e for q3) 0x0h note: bit[1:0]: broadcast s t orm i ng threshold. broadcast s t orm mode after in itial: - tim e interv al : 50m s the m a x. packet num ber = 7490 in 100base, 749 in 10base infineon-admtek co. ltd. 4-1
ADM6996L register description note (continued): - per port rising threshold 0 0 0 1 1 0 1 1 all 100tx d i s a b l e 1 0 % 2 0 % 4 0 % not all 100tx d i s a b l e 1 % 2 % 4 % - per port falling threshold 0 0 0 1 1 0 1 1 all 100tx d i s a b l e 5 % 1 0 % 2 0 % not all 100tx d i s a b l e 0 . 5 % 1 % 2 % bit 2: broadcast s t orm i ng enable. 0/disable. 1/e n able. bit 4: crc check disable. 1/ disable. 0/enable. bit 7: aging disable. 1/disable. 0/e n able. - drop scheme for each q u eue discard mode utiliz ation 0 0 0 1 1 0 1 1 t b d 0 % 0 % 2 5 % 5 0 % 4.3.12 vlan mode select register, offset: 0x11h bits t ype description initial va lue 3 : 0 r o r e s e r v e d 0 x 0 h 4 r/ w mac clone enable 0: norm al mode. learnin g with sa only . ADM6996L fill/s earch mac table by sa or da only . 1: mac clone m ode. le arning with sa, vid0. ADM6996L fill/search mac table by sa or da with vid0. th is bit c a n let ch ip learn two sa m e addresses with dif f erent vid0. 0x0h 5 r / w vlan mod e s e l e c t 0: by-pass m ode with port-base vlan. 1: 802.1q base vlan. 0x0h 7 : 6 r o r e s e r v e d 0 x 0 h 1 5 : 8 r o r e s e r v e d 0 x f f h note: infineon-admtek co. ltd. 4-2 below is bit4, 5 vlan t ag and mac application example.
ADM6996L register description below is router old architecture. the disadvantages of this are: 1. wan port only support 10m half-d uplex and non-mdix function. 2. need extra 1 0 m nic cost. 3. isa bus will becom e bot tleneck of whole system . below is new architecture by using adm 6996l serial chip vlan function. the advantages of below are: 1. wan port can upgrade to 100/10 full/half , auto mdix. 2. wan/lan port is programma ble and put on sam e switch. 3. no need extra nic and save lot of cost. 4. high bandwidth of mii port up to 200m speed. new router application works well on norm a l application. if user?s isp vendor( cable mode m ) lock registration card?s id then r outer cpu m u s t send this l o ck registration card?s id to w a n port. one condition happen is there ex ist two sam e mac id on this infineon-admtek co. ltd. 4-3 p ort 1 p ort 2 port5 mac mii port p ort 4 p ort 0 p ort 3 cpu with one mii mii 4 100/10 lan port 1 00/ 10 wa n p ort vlan & mac clone function po rt0 port4 mac mii port por t3 por t2 po rt1 cpu with one mii mii 10m half nic isa 1 0m ha lf non m dix w an por t 4 100/10 lan port
ADM6996L register description switch. one is orig inal card and an other one is cpu. this will m a ke switch lea r ning table trouble. ADM6996L provide mac clone function that allow two sam e m a c address with dif f e rent vlan id0 on learning table. this will solve lock r e gistration card?s id is sue. at8989p serial chip will put these two sam e mac addresses with different vlan id0 at different learning table entry. how to set ADM6996L on router. port0~3: lan port. port4: w an port. port5: m ii p o rt as cpu port. step1: set r e gister 0x11h bit4 and bit5 to 1. {coding: write register 0x11h as 0xff30h} step2: set p o rt0~3 as u n tag port and set pvid=1. {coding: write register 0x01h, 0x03h, 0x05h, 0x07h as 0x840f. port0~3 as untag, pvid=1, enable mdix} step3: set p o rt4 as untag port and set pvid=2. { coding:write register 0x08h as 0x880fh. port4 as untag, pvid=2, enable mdix.} step4: set p o rt5 mii port as tag port and set pvid=2. {coding:w r ite register 0x09h as 0x881fh. port5 mii port as tag, pvid=2.} step5: group port0, 1, 2, 3, 5 as vlan 1. {coding: w r ite register 0x14h as 0x0155h. vlan1 cover port0, 1, 2, 3, 5.} step6: group port4, 5 as vlan 2. {coding: write register 0x15h as 0x0180h. vlan2 cover port4, 5.} how mac clone operation: 1. lan to lan/cpu traffic. ADM6996L lan traffic to l an/cpu only. traffic to another lan port will be untag packet. traffic to cpu is tag p acket with vid=1. cpu can check vid to distinguish lan traffi c or wan traffic. 2. wan to cpu traffic. ADM6996L w a n traffic to cpu only. traffic to cpu is tag packet with vid=2. cpu can check vid to distingu is h lan traffic or wan traffic. 3. cpu to lan packet. ADM6996L cpu packet to lan port m u st add vid=1 in vlan field. ADM6996L check vid to distinguish lan traffi c or wan tr affic. lan output packet is untag. 4. cpu to wan packet. ADM6996L cpu packet to wan port m u st add vid=2 in vlan filed. ADM6996L check vid to distinguish lan traffi c or wan tr affic. wan output packet is untag. infineon-admtek co. ltd. 4-4 5. ADM6996L learning sequence
ADM6996L register description ADM6996L will check vlan mapping setting first then ch eck learning table. user does not worry lan/ w a n traffic m i x up. bit 10: half duplex back pressu re enable. 1/enable, 0/disable. 4.3.13 miscellaneous configuration register, offset: 0x12h bits t ype description initial va lue 0 r/ w port0 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 1 r / w r e s e r v e d 0 x 0 h 2 r/ w port1 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 3 r / w r e s e r v e d 0 x 0 h 4 r/ w port2 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 5 r / w r e s e r v e d 0 x 0 h 6 r/ w port3 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 7 r/ w port4 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 8 r/ w port5 mac lock. 1: lock first ma c source address, 0: disable. 0x0h 1 0 : 9 r / w r e s e r v e d 0 x 3 h 1 1 r / w r e s e r v e d 0 x 0 h 1 3 : 1 2 r / w r e s e r v e d 0 x 3 h 1 4 r / w r e s e r v e d 0 x 0 h 15 r/ w drop packet when exces sive col lision happen enable . 1: enable, 0: disable. 0x0h 4.3.14 vlan mapping table registers, offset: 0x22h ~ 0x13h bits t ype description initial va lue 8 : 0 r / w vlan mapping t a b l e . 0x1f f h 1 5 : 9 r o r e s e r v e d 0 x 7 f h note: 16 vlan group: see r e gister 0x2ch bit 1 1 =0 bit0: port0 bit2: port1 bit4: port2 bit6: port3 bit7: port4 bit8: port5. select the vlan group ports is to set the corresponding bits to 1. 4.3.15 reserved register, offset: 0x27h ~ 0x23h bits t ype description initial va lue 1 5 : 0 r / w r e s e r v e d 0 x 0 h infineon-admtek co. ltd. 4-5
ADM6996L register description 4.3.16 port0, 1 pvid bit 11 ~ 4 configuration register, offset: 0x28h bits t ype description initial va lue 7:0 r/ w port0 pvid bit 1 1 ~4. these 8 bits combine with register 0x01h bit [13~10] as full 12 bit vid. 0x0h 1 5 : 8 r o r e s e r v e d 0 x 0 h 4.3.17 port2, 3 pvid bit 11 ~ 4 configuration register, offset: 0x29h bits t ype description initial va lue 7:0 r/ w port1 pvid bit 1 1 ~4. these 8 bits combine with register 0x03h bit[13~10] as full 12 bit vid. 0x0h 1 5 : 8 r o r e s e r v e d 0 x 0 h 4.3.18 port4, 5 pvid bit 11~4 configuration register, offset: 0x2ah bits t ype description initial va lue 7:0 r/ w port2 pvid bit 1 1 ~4. these 8 bits combine with register 0x05h bit[13~10] as full 12 bit vid. 0x0h 1 5 : 8 r o r e s e r v e d 0 x 0 h 4.3.19 port6, 7 pvid bit 11~4 configuration register, offset: 0x2bh bits t ype description initial va lue 7:0 r/ w port3 pvid bit 1 1 ~4. these 8 bits combine with register 0x07h bit[13~10] as full 12 bit vid. 0x0h 15:8 ro port4 pvid bit 1 1 ~4. these 8 bits combine with register 0x08h bit[13~10] as full 12 bit vid. 0x0h 4.3.20 port8 pvid bit 11~4 & vlan group sh ift bits configuration register offset: 0x2ch infineon-admtek co. ltd. 4-1 bits t ype description initial va lue 7:0 r/ w port5 pvid bit 1 1 ~4. these 8 bits combine with register 0x09h bit[13~10] as full 12 bit vid. 0x0h 10:8 r/ w t a g shift for vlan grouping. default 000. 0: vid[3:0] 1: vid[ 4:1] 2: vid[5:2] 3: vid[6:3] 4: vid[ 7:4] 5: vid[8:5] 6: vid[9:6] 7: vid[10: 7] 0x0h 1 1 r / w r e s e r v e d 0 x 0 h 12 r/ w control reserved mac (0180c2000010-0180c20000ff) 1: forward, 0: discard. 0x1h 13 r/ w control reserved mac (0180c2000002- 0180c200000f) 1: forward, 0: discard. 0x1h
ADM6996L register description bits t ype description initial va lue 14 r/ w control reserved mac (0180c2000001) 1: forward, 0: discard. 0x0h 15 r/ w control reserved mac (0180c2000000) 1: forward, 0: discard. 0x1h note: bit[10:8]: vlan t a g shift regis t er . ADM6996L w ill select 4 bit from total 12 bit vid as vlan group reference. bit[15:12]: ieee 802.3 reserved da forward or drop police. 4.3.21 reserved register, offset: 0x2dh bits t ype description initial va lue 1 5 : 0 r / w r e s e r v e d 0 x 4 4 4 2 h 4.3.22 reserved register, offset: 0x2eh bits t ype initial va lue 1 5 : 0 r / w r e s e r v e d 0 x 0 0 0 0 h description 4.3.23 phy restart, offset: 0x2fh bits t ype description initial va lue 15:0 r/ w w r ite 0x0000h to this register will restart internal phys. 0x0000h 4.3.24 miscellaneous configuration register, offset: 0x30h infineon-admtek co. ltd. 4-2 bits t ype description initial va lue 0 r / w r e s e r v e d 0 x 1 h 1 r / w r e s e r v e d 0 x 1 h 2 r / w r e s e r v e d 0 x 1 h 4 : 3 r / w r e s e r v e d 0 x 0 h 5 r/ w mac clone enable bit[1]. 0x0h 6 r/ w mii speed double. 1: port 5 mii rxclk, txcl k maximum speed is 50mhz 0: port 5 mii rxclk, txcl k maximum speed is 25mhz 0x0h 7 r / w r e s e r v e d 0 x 1 h 8 r / w r e s e r v e d 0 x 1 h 9 r/ w dual speed hub col_led enable. 1: dual speed hub led display. port0 col led: 10m col led. port1 col led: 100m col led. 0: norm al led display. 0x0h 1 0 r / w r e s e r v e d 0 x 0 h
ADM6996L register description bits t ype description initial va lue 1 1 r / w r e s e r v e d 0 x 1 h 12 r/ w port 4 led mode. 1:link/act/speed 0:linkact/d upcol/speed 0x0h 1 5 : 1 3 r / w r e s e r v e d 0 x 0 h 4.3.25 bandw i dth contr o l register0~3, offset: 0x31h bits t ype description initial va lue 2:0 r/ w port 0 meter threshold control. reference tab l e below. 0 x 0 h 3 r/ w receive packet length counted on the source p o rt 0. 0 = the switch will add length to th e p0 counter. 0x0h 6:4 r/ w port 1 meter threshold control, default 000. reference tab l e below . 0 x 0 h 7 r/ w receive packet length counted on the source p o rt 1. 0 = the switch will add length to th e p1 counter. 0x0h 10:8 r/ w port 2 meter threshold control, default 000. reference tab l e below. 0 x 0 h 11 r/ w receive packet length counted on the source p o rt 2. 0 = the switch will add length to th e p2 counter. 0x0h 14:12 r/ w port 3 meter threshold control. reference tab l e below. 0 x 0 h 15 r/ w receive packet length counted on the source p o rt 3. 0 = the switch will add length to th e p3 counter. 0x0h note: reference t a ble 0 0 0 0 0 1 0 1 0 01 1 1 0 0 1 0 1 1 1 0 1 1 1 2 5 6 k 5 1 2 k 1 m 2 m 5 m 1 0 m 2 0 m 5 0 m 4.3.26 bandw i dth contr o l register 4~5, offset: 0x32h bits t ype description initial va lue 2:0 r/ w port 4 meter threshold control. reference tab l e below . 0 x 0 h 3 r/ w receive packet length counted on the source p o rt 4 0 = the switch will add length to th e p4 counter. 0x0h 6:4 r/ w port 5 meter threshold control 0x0h 7 r/ w receive packet length counted on the source p o rt 5 0 = the switch will add length to th e p5 counter. 0x0h 1 5 : 8 r o r e s e r v e d 0 x 0 h note: reference t a ble infineon-admtek co. ltd. 4-3 0 0 0 0 0 1 0 1 0 01 1 1 0 0 1 0 1 1 1 0 1 1 1 2 5 6 k 5 1 2 k 1 m 2 m 5 m 1 0 m 2 0 m 5 0 m
ADM6996L register description 4.3.27 bandw i dth contr o l enable register , offset: 0x33h bits t ype description initial va lue 0 r/ w bandwidth control enable for port 0. 1 = port 0 enables the bandwidth control. 0 = port 0 disables the bandwidth control. 0x0h 1 r / w r e s e r v e d 0 x 0 h 2 r/ w bandwidth control enable for port 1. 0x0h 3 r / w r e s e r v e d 0 x 0 h 4 r/ w bandwidth control enable for port 2. 0x0h 5 r / w r e s e r v e d 0 x 0 h 6 r/ w bandwidth control enable for port 3. 0x0h 7 r/ w bandwidth control enable for port 4. 0x0h 8 r/ w bandwidth control enable for port 5. 0x0h 1 5 : 9 r o r e s e r v e d 0 x 0 h 4.4 eeprom access custom er can select ADM6996L read eep ro m contents as chip setting or not. ADM6996L will check the signatu re of eeprom to decide read content of eeprom or not. resetl & eeprom c ontent relationship r e s e t l c s s k d i d o 0 high im pedance high im pedance high im pedance high im pedance rising edge 0
ADM6996L register description ADM6996L serial chip s will latch hardware-reset value as recomm end value. it in clud es eeprom interface: eecs: internal pull dow n 40k resister. eesk: tp p o rt auto-mdix select. internal pull down 40k resister as non auto-mdix mode. edi: dual color sele ct. intern al pull down 40k resister as s i ngle color mode. edo: eeprom enable. intern al pull up 40k resister as eeprom enable. below figure is ADM6996L serial chips eepro m pins operation at different stage. reset signal is control by cpu with at least 100ms low. point1 is reset rising edge. c p u must prepare proper value on eecs(0), eesk, edi, edo(1) before this rising edge. ADM6996L will read this value in to chip at poin t2. cpu must keep these values over point2. point2 is 200ns after reset rising edge. ADM6996L serial chip s will read eeprom c ontent at poin t4 which 800ns far away from the rising edge of reset. cpu must turn e e prom pins eecs, eesk, edi and edo to high-z or pull high before point4. if user want change state to high-z or pull high on eeprom pi ns, the order is cs-> d i - > do -> sk is better. a little bit d i f f e rent with the tim ing on writing ee prom. see below graph . must be carefully is when cs go down after write a com m a nd, sk must issu e at least one clock. this is a difference between ADM6996L with eeprom write tim ing. if system without eeprom then user m u st write ADM6996L inte rnal register by 93c66 tim ing. if use r uses eeprom then the writing tim ing is depend on eeprom type. infineon-admtek co. ltd. 4-5 200ns 800ns 200ns 100ms reset 12 3 4 5 cs sk write c ommand
ADM6996L register description 4.5 serial register map infineon-admtek co. ltd. 4-6 register bit 31- 0 mode default 0 x 0 0 h c h i p identif i e r r o 0x00071010h 0x01h port s t atus 0 ro 0x00000000h 0x02h port s t atus 1 ro 0x00000000h 0x03h cable broken s t atus ro 0x00000000h 0x04h port 0 receive packet c ount ro 0x00000000h 0 x 0 5 h r e s e r v e d r o 0x00000000h 0x06h port 1 receive packet c ount ro 0x00000000h 0 x 0 7 h r e s e r v e d r o 0x00000000h 0x08h port 2 receive packet c ount ro 0x00000000h 0 x 0 9 h r e s e r v e d r o 0x00000000h 0x0ah port 3 receive packet c ount ro 0x00000000h 0x0bh port 4 receive packet c ount ro 0x00000000h 0x0ch port 5 receive packet c ount ro 0x00000000h 0x0dh port 0 receive packet b y te count ro 0x00000000h 0 x 0 e h r e s e r v e d r o 0x00000000h 0x0fh port 1 receive packet b y te count ro 0x00000000h 0 x 1 0 h r e s e r v e d r o 0x00000000h 0x1 1h port 2 receive packet b y te count ro 0x00000000h 0 x 1 2 h r e s e r v e d r o 0x00000000h 0x13h port 3 receive packet b y te count ro 0x00000000h 0x14h port 4 receive packet b y te count ro 0x00000000h 0x15h port 5 receive packet b y te count ro 0x00000000h 0x16h port 0 t r ansm it packet count ro 0x00000000h 0 x 1 7 h r e s e r v e d r o 0x00000000h 0x18h port 1 t r ansm it packet count ro 0x00000000h 0 x 1 9 h r e s e r v e d r o 0x00000000h 0x1ah port 2 t r ansm it packet count ro 0x00000000h 0 x 1 b h r e s e r v e d r o 0x00000000h 0x1ch port 3 t r ansm it packet count ro 0x00000000h 0x1dh port 4 t r ansm it packet count ro 0x00000000h 0x1eh port 5 t r ansm it packet count ro 0x00000000h 0x1fh port 0 t r ansm it packet byte count ro 0x00000000h 0 x 2 0 h r e s e r v e d r o 0x00000000h 0x21h port 1 t r ansm it packet byte count ro 0x00000000h 0 x 2 2 h r e s e r v e d r o 0x00000000h 0x23h port 2 t r ansm it packet byte count ro 0x00000000h 0 x 2 4 h r e s e r v e d r o 0x00000000h 0x25h port 3 t r ansm it packet byte count ro 0x00000000h 0x26h port 4 t r ansm it packet byte count ro 0x00000000h 0x27h port 5 t r ansm it packet byte count ro 0x00000000h 0x28h port 0 collision count ro 0x00000000h 0 x 2 9 h r e s e r v e d r o 0x00000000h
ADM6996L register description register bit 31- 0 mode default 0x2ah port 1 collision count ro 0x00000000h 0 x 2 b h r e s e r v e d r o 0x00000000h 0x2ch port 2 collision count ro 0x00000000h 0 x 2 d h r e s e r v e d r o 0x00000000h 0x2eh port 3 collision count ro 0x00000000h 0x2fh port 4 collision count ro 0x00000000h 0x30h port 5 collision count ro 0x00000000h 0x31h port 0 error count ro 0x00000000h 0 x 3 2 h r e s e r v e d r o 0x00000000h 0x33h port 1 error count ro 0x00000000h 0 x 3 4 h r e s e r v e d r o 0x00000000h 0x35h port 2 error count ro 0x00000000h 0 x 3 6 h r e s e r v e d r o 0x00000000h 0x37h port 3 error count ro 0x00000000h 0x38h port 4 error count ro 0x00000000h 0x39h port 5 error count ro 0x00000000h 0x3ah over flow flag 0 lh/cor 0x00000000h 0x3bh over flow flag 1 lh/cor 0x00000000h 0x3ch over flow flag 2 lh/cor 0x00000000h 4.6 serial register description 4.6.1 chip identifier register, offset: 0x00h bits t ype description initial va lue 3:0 ro 0000 (v ersion num b er) 0x0h 3 1 : 4 r o 0 x 0 0 0 7 1 0 1 h 0 x 7 1 0 1 h 4.6.2 port status 0 register, offset: 0x01h infineon-admtek co. ltd. 4-7 bits t ype description initial va lue 0 ro port 0 linkup status: 1: link is established. 0: link is not established. 0x0h 1 ro port 0 speed status: 1: 100mb/s 0: 10 mb/s 0x0h 2 ro port 0 duplex status 1: full duplex. 0: half duplex. 0x0h 3 ro port 0 flow control enable 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 0x0h 4 r o r e s e r v e d 0 x 0 h
ADM6996L register description bits t ype description initial va lue infineon-admtek co. ltd. 4-8 5 r o r e s e r v e d 0 x 0 h 6 r o r e s e r v e d 0 x 0 h 7 r o r e s e r v e d 0 x 0 h 8 ro port 1 linkup status: 1: link is established. 0: link is not established. 0x0h 9 ro port 1 speed status: 1: 100mb/s 0: 10 mb/s 0x0h 10 ro port 1 duplex status 1: full duplex. 0: half duplex. 0x0h 11 ro port 1 flow control enable 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 0x0h 1 2 r o r e s e r v e d 0 x 0 h 1 3 r o r e s e r v e d 0 x 0 h 1 4 r o r e s e r v e d 0 x 0 h 1 5 r o r e s e r v e d 0 x 0 h 16 ro port 2 linkup status: 1: link is established. 0: link is not established. 0x0h 17 ro port 2 speed status: 1: 100mb/s 0: 10 mb/s 0x0h 18 ro port 2 duplex status 1: full duplex. 0: half duplex. 0x0h 19 ro port 2 flow control enable 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 0x0h 2 0 r o r e s e r v e d 0 x 0 h 2 1 r o r e s e r v e d 0 x 0 h 2 2 r o r e s e r v e d 0 x 0 h 2 3 r o r e s e r v e d 0 x 0 h 24 ro port 3 linkup status: 1: link is established. 0: link is not established. 0x0h 25 ro port 3 speed status: 1: 100mb/s 0: 10 mb/s 0x0h 26 ro port 3 duplex status 1: full duplex. 0: half duplex. 0x0h 27 ro port 3 flow control enable 0x0h
ADM6996L register description bits t ype description initial va lue 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 28 ro port 4 linkup status: 1: link is established. 0: link is not established. 0x0h 29 ro port 4 speed status: 1: 100mb/s 0: 10 mb/s 0x0h 30 ro port 4 duplex status 1: full duplex. 0: half duplex. 0x0h 31 ro port 4 flow control enable 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 0x0h 4.6.3 port status 1 register, offset: 0x02h bits t ype description initial va lue 0 ro port 5 linkup status: 1: link is established. 0: link is not established. 0x0h 2:1 ro port 5 speed status: two b its ind i ca te the opera tin g speed. bit[2] b it[1] speed 0 1 100mb/s 0 0 10mb/s 0x0h 3 ro port 5 duplex status 1: full duplex. 0: half duplex. 0x0h 4 ro port 5 flow control enable 1: 802.3x on for full duplex or back pressure on for half duplex. 0: flow control disable 0x0h 3 1 : 5 r o r e s e r v e d 0 x 0 h 4.6.4 cable broken status register, offset: 0x03h infineon-admtek co. ltd. 4-9 bits t ype description initial va lue 1:0 ro port 0 cable broken length 0x0h 2 ro port 0 cable broken 0x0h 4 : 3 r o r e s e r v e d 0 x 0 h 5 r o r e s e r v e d 0 x 0 h
ADM6996L register description bits t ype description initial va lue 7:6 ro port 1 cable broken length 0x0h 8 ro port 1 cable broken 0x0h 1 0 : 9 r o r e s e r v e d 0 x 0 h 1 1 r o r e s e r v e d 0 x 0 h 3:12 ro port 2 cable broken length 0x0h 14 ro port 2 cable broken 0x0h 1 6 : 1 5 r o r e s e r v e d 0 x 0 h 1 7 r o r e s e r v e d 0 x 0 h 19:18 ro port 3 cable broken length 0x0h 20 ro port 3 cable broken 0x0h 22:21 ro port 4 cable broken length 0x0h 23 ro port 4 cable broken 0x0h 3 1 : 2 4 r o r e s e r v e d 0 x 0 h 4.6.5 over flow flag 0 register, offset: 0x3ah bits t ype description initial va lue 0 ro overflow of port 0 receive packet c ount 0x0h 1 r o r e s e r v e d 0 x 0 h 2 ro overflow of port 1 receive packet c ount 0x0h 3 r o r e s e r v e d 0 x 0 h 4 ro overflow of port 2 receive packet c ount 0x0h 5 r o r e s e r v e d 0 x 0 h 6 ro overflow of port 3 receive packet c ount 0x0h 7 ro overflow of port 4 receive packet c ount 0x0h 8 ro overflow of port 5 receive packet c ount 0x0h 9 ro overflow of port 0 receive packet b y te count 0x0h 1 0 r o r e s e r v e d 0 x 0 h 11 ro overflow of port 1 receive packet b y te count 0x0h 1 2 r o r e s e r v e d 0 x 0 h 13 ro overflow of port 2 receive packet b y te count 0x0h 1 4 r o r e s e r v e d 0 x 0 h 15 ro overflow of port 3 receive packet b y te count 0x0h 16 ro overflow of port 4 receive packet b y te count 0x0h 17 ro overflow of port 5 receive packet b y te count 0x0h 3 1 : 1 8 r o reserved 0x0h 4.6.6 over flow flag 0: register 0x3bh infineon-admtek co. ltd. 4-10 bits t ype description initial va lue 0 ro overflow of port 0 transm it packet count 0x0h 1 r o r e s e r v e d 0 x 0 h 2 ro overflow of port 1 transm it packet count 0x0h
ADM6996L register description bits t ype description initial va lue 3 r o r e s e r v e d 0 x 0 h 4 ro overflow of port 2 transm it packet count 0x0h 5 r o r e s e r v e d 0 x 0 h 6 ro overflow of port 3 transm it packet count 0x0h 7 ro overflow of port 4 transm it packet count 0x0h 8 ro overflow of port 5 transm it packet count 0x0h 9 ro overflow of port 0 transm it packet byte count 0x0h 1 0 r o r e s e r v e d 0 x 0 h 11 ro overflow of port 1 transm it packet byte count 0x0h 1 2 r o r e s e r v e d 0 x 0 h 13 ro overflow of port 2 transm it packet byte count 0x0h 1 4 r o r e s e r v e d 0 x 0 h 15 ro overflow of port 3 transm it packet byte count 0x0h 16 ro overflow of port 4 transm it packet byte count 0x0h 17 ro overflow of port 5 transm it packet byte count 0x0h 3 1 : 1 8 r o reserved 0x0h 4.6.7 over flow flag 2 register, offset: 0x3ch bits t ype description initial va lue 0 ro overflow of port 0 collision count 0x0h 1 r o r e s e r v e d 0 x 0 h 2 ro overflow of port 1 collision count 0x0h 3 r o r e s e r v e d 0 x 0 h 4 ro overflow of port 2 collision count 0x0h 5 r o r e s e r v e d 0 x 0 h 6 ro overflow of port 3 collision count 0x0h 7 ro overflow of port 4 collision count 0x0h 8 ro overflow of port 5 collision count 0x0h 9 ro overflow of port 0 error count 0x0h 1 0 r o r e s e r v e d 0 x 0 h 11 ro overflow of port 1 error count 0x0h 1 2 r o r e s e r v e d 0 x 0 h 13 ro overflow of port 2 error count 0x0h 1 4 r o r e s e r v e d 0 x 0 h 15 ro overflow of port 3 error count 0x0h 16 ro overflow of port 4 error count 0x0h 17 ro overflow of port 5 error count 0x0h 3 1 : 1 8 r o reserved 0x0h infineon-admtek co. ltd. 4-11
ADM6996L register description 4.7 serial interface ti ming ADM6996L serial chip internal co unter or eeprom access timing. eesk: si m i lar as mdc signal. edi: sim ilar as mdio. ecs: must keep low. z 0 ta r e gi s t er da t a [ 3 1 : 0 ] i d l e prea m b le ta ble selec t ee ck ee d i (s t a ) z 01 0 0 0 0 0 0 0 0 z z ee di ( a t8 99 9) eeck ee di (s t a ) z id le re s e t typ e
ADM6996L register description pream ble: at least 32 continuous ?1?. start: 01(2 bits) opcode: 01 (2 bits, reset comm and) device address: chip physi cal address as phyas[1:0]. reset_type: reset counter by por t num b er or by counter index. 1: clear ded i cate po rt?s all coun ters. 0: clear dedicate counter. port_num be r or counter index: user define clear port or counter. idle: eeck must send at least one clock at idle tim e. infineon-admtek co. ltd. 4-2
ADM6996L electrical specification chapter 5 electrical specification 5.1 tx/fx interface 5.1.1 tp interface txp txn adm6995 rxp rxn 49.9 49.9 49.9 49.9 0.01u 0.01u 1:1 1:1 auto-mdix x'fmr 1 2 3 4 5 6 7 8 rj-45 vcca2 75 75 75 0.1u hi-pot cap r1 r2 c1 transform e r requirem e nt: . tx/rx rate 1:1 . tx/rx ce ntral tap connect together to vcca2. user can change tx/rx pin for easy la yout but do not change polarity. ADM6996L supports au to polarity on receiv i ng side. 5.1.2 fx interface txp txn adm6995 rxp rxn 69 1 gnd_rx 2 rd+ 3 rd- 4 sd 5 vcc_rx 6 vcc_tx 7 td- 8 td+ 9 gnd_tx 3.3v fiber transceiver 69 182 182 127 127 83 83 +3.3v +3.3v 83 127 +3.3v sd sd vcc(3.3) vcc(3.3) infineon-admtek co. ltd. 5-1
ADM6996L electrical specification 5.2 dc characteristics 5.2.1 absolute maximum rating symbol parameter rating units v v power supply -0.3 to 3.63 cc vcca2 tx line driv er 1.8 v v c c p l l p l l v o l t a g e 1 . 8 v vccik digital core voltage 1.8 v v in input voltage -0.3 to v + 0.3 cc v vout output voltage -0.3 to vcc + 0.3 v tstg storage temperature -55 to 155 ?
ADM6996L electrical specification 5.3 ac characteristics 5.3.1 pow er on reset parameter conditions min typical units trst rst low period 100 m s tconf start of idle pulse w i dth 100 ns symbol parameter min typical max units tesk eesk period ns teskl 2550 2570 teskh eesk high period 2570 ns e e d i t o e e s k r i s i n g s e t u p tim e 1 0 n s terdh e e d i t o e e s k r i s i n g h o l d tim e 1 0 ns tewdd eesk falling to eedo output delay tim e 2 0 n s 0m s 50m s 100m s rs t * a ll co nf i gu r at i o n p i n s tc o n f tr st tr st te r d h t e rds te w d d te s k te s k te s k l te s k l te s k h te s k h symbol max 5.3.2 eeprom i n terface timing 0us 10 u s 2 0us 30us ee c s ee sk ee d o ee d i conditions 5120 eesk low period ns 2550 terds infineon-admtek co. ltd. 5-3
ADM6996L electrical specification 5.3.3 10base-tx mii input timing 0ns 1000n s 2000n s m ii_r x clk m ii_r x dv m ii_r x d m ii_crs trx h trx s tck tckltckl tckh tck tckh ttx o d tc k tc kl tc kl tc kh tc k tc kh symbol conditions min typical units t c k m i i _ r x c l k peri o d 40 0 ns tckl m i i _ rxcl k lo w pe rio d 18 0 22 0 ns tckh parameter max mii_ rxclk high period 1 8 0 22 0 ns trx s mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g set up 1 0 ns trx h mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g hol d 1 0 ns symbol parameter conditions typical max units m i i _ txc l k peri o d 40 0 ns tckl m i i _ txcl k lo w pe rio d 18 0 22 0 ns tck h m i i _ txcl k hig h pe rio d 18 0 22 0 ns tt xo d m i i _ txc l k r i si ng out put del a y 0 25 ns 5.3.4 10base-tx mii output timing 0ns 500ns 1000ns 1500ns 2000ns 2500n s mi i _ t x c l k mi i _ t x e n mi i _ t x d min t c k m i i _ tx d, m i i_t x e n t o infineon-admtek co. ltd. 5-4
ADM6996L electrical specification 5.3.5 100base-tx mii input timing parameter conditions min typical units t c k m i i _ r x c l k peri o d ns tckl m i i _ rxcl k lo w pe rio d 0ns 100n s 200n s m ii_r x clk m ii_r x dv m ii_r x d m ii_crs trx h trx s tck tckltckl tckh tck tckh ttx o d tc k tc kl tc kl tc kh tc k tc kh symbol max 40 18 ns 22 tckh mii_ rxclk high period 22 ns mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g set up 1 0 ns trx h mii _ crs, m i i _ rx d v a n d mii_ rxd to mii_ rxclk risin g hol d 1 8 trx s ns 1 0 5.3.6 100base-tx mii output timing symbol parameter conditions typical max units t c k m i i _ txc l k peri o d 40 ns tckl m i i _ txcl k lo w pe rio d 18 22 ns 0ns 50ns 100ns 150ns 200ns 250ns mi i _ t x c l k mi i _ t x e n mi i _ t x d min infineon-admtek co. ltd. 5-5
ADM6996L electrical specification symbol parameter conditions typical max units tck h min m i i _ txcl k hig h pe rio d 18 22 ns m i i _ tx d, m i i_t x e n t o m i i _ txc l k r i si ng out put del a y 0 tt xo d ns 25 5.3.7 gpsi(7-w ire) input timing 0n s 250n s 50 0ns gp s i _ r x c l k gp s i _ r x d gp s i _ c rs / c ol tt x h tt x s tc k tc k l tc k l tc k h tc k tc k h to d tck tckltckl tckh tck tckh symbol parameter conditions min typical units tck gpsi_rxclk period 100 ns tckl gpsi_rxclk low per i od 40 60 ns tckh 40 60 ttxs gpsi_rxd, gpsi_crs/ c ol to gpsi_rxclk rising setup tim e 1 0 ns max gpsi_rxclk high pe riod ns 1 0 ttxh gpsi_rxd, gpsi_crs/ c ol to gpsi_rxclk rising hold tim e ns 5.3.8 gpsi(7-w ire) output t i ming 0ns 250n s 500n s g psi_tx c lk gpsi_tx d gpsi_tx e n infineon-admtek co. ltd. 5-6
ADM6996L electrical specification symbol parameter conditions typical max units gpsi_txclk period 100 ns tckl gpsi_txclk low per i od 40 60 ns tckh gpsi_txclk high pe riod 40 60 ns tod gpsi_txe n/gpsi_txd output delay 5 0 min tck ns gpsi_txc lk rising to 70 infineon-admtek co. ltd. 5-7
ADM6996L appendix chapter 6 packaging 6.1 128 pin pqfp outside dimension infineon-admtek co. ltd. 6-1 18.5 mm 20.0 + / - 0.1 mm 23.2 + / - 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm

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