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products and specifications discussed herein are subject to change by micron without notice. 09005aef808f8ccd dd9c16_32x72ag_b.fm - rev. b 2/03 en 1 ?2003 micron technology, inc. 128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm ddr sdram dimm mt9vddt1672a - 128mb MT9VDDT3272A - 256mb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? jedec-standard 184-pin dual in-line memory module (dimm) fast data transfer rates pc1600, pc2100, or pc2700 utilizes 200 mt/s, 266 mt/s, and 333mt/s ddr sdram components ecc-optimized pinout 128mb (16 meg x 72), 256mb (32 meg x 72) v dd = v dd q= +2.5v v ddspd = +2.3v to +3.6v +2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data?i.e., source-synchronous data capture differential clock inputs (ck and ck#) four internal device banks for concurrent operation programmable burst lengths: 2, 4, or 8 auto precharge option auto refresh and self refresh modes 15.6s (128mb), 7.8125s (256mb) maximum average periodic refresh interval serial presence-detect (spd) with eeprom programmable read cas latency figure 1: 184-pin dimm (mo-206) options marking package unbuffered a 184-pin dimm (gold) g 184-pin dimm (lead-free) y frequency/cas latency 6ns, 333 mt/s (167 mhz), cl = 2.5 -335 7.5ns, 266 mt/s (133 mhz ), cl = 2 -262 7.5ns, 266 mt/s (133 mhz ), cl = 2 -26a 7.5ns, 266 mt/s (133 mhz ), cl = 2.5 -265 10ns, 200 mt/s (100 mhz ), cl = 2 -202 self refresh standard none low power l table 1: address table 128mb 256mb refresh count 4k 8k row addressing 4k (a0?a11) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) device configuration 16 meg x 8 32 meg x 8 column addressing 1k (a0?a9) 1k (a0?a9) module rank addressing 1 (s0#) 1 (s0#)
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 2 ?2003 micron technology. inc. note: all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult fac- tory for current revision codes. example: MT9VDDT3272Ag-265a1 table 2: part numbers and timing parameters part number module density configuration module bandwidth memory clock/ data rate latency (cl - t rcd - t rp) mt9vddt1672a(l)g-335__ 128mb 16 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt9vddt1672a(l)y-335__ 128mb 16 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt9vddt1672a(l)g-262__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt9vddt1672a(l)y-262__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt9vddt1672a(l)g-26a__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt9vddt1672a(l)y-26a__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt9vddt1672a(l)g-265__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt9vddt1672a(l)y-265__ 128mb 16 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt9vddt1672a(l)g-202__ 128mb 16 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 mt9vddt1672a(l)y-202__ 128mb 16 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 MT9VDDT3272A(l)g-335__ 256mb 32 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 MT9VDDT3272A(l)y335__ 256mb 32 meg x 72 2.7 gb/s 6ns/333 mt/s 2.5-3-3 MT9VDDT3272A(l)g-262__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 MT9VDDT3272A(l)y-262__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-2-2 MT9VDDT3272A(l)g-26a__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 MT9VDDT3272A(l)y-26a__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 MT9VDDT3272A(l)g-265__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 MT9VDDT3272A(l)y-265__ 256mb 32 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 MT9VDDT3272A(l)g-202__ 256mb 32 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2 MT9VDDT3272A(l)y-202__ 256mb 32 meg x 72 1.6 gb/s 10ns/200 mt/s 2-2-2
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 3 ?2003 micron technology. inc. note: pin 115 is no connect (128mb), and a12 (256mb). figure 2: 184-pin dimm pinouts table 3: pin assignment (184-pin dimm front) pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dqs8 70 v dd 2dq0 25 dqs2 48 a0 71 nc 3v ss 26 v ss 49 cb2 72 dq48 4dq1 27 a9 50 v ss 73 dq49 5dqs0 28 dq18 51 cb3 74 v ss 6dq2 29 a7 52 ba1 75 ck2# 7v dd 30 v dd 53 dq32 76 ck2 8dq331dq19 54 v dd 77 v dd 9nc 32 a5 55 dq33 78 dqs6 10 nc 33 dq24 56 dqs4 79 dq50 11 v ss 34 v ss 57 dq34 80 dq51 12 dq8 35 dq25 58 v ss 81 v ss 13 dq9 36 dqs3 59 ba0 82 nc 14 dqs1 37 a4 60 dq35 83 dq56 15 v dd 38 v dd 61 dq40 84 dq57 16 ck1 39 dq26 62 v dd 85 v dd 17 ck1# 40 dq27 63 we# 86 dqs7 18 v ss 41 a2 64 dq41 87 dq58 19 dq10 42 v ss 65 cas# 88 dq59 20 dq11 43 a1 66 v ss 89 v ss 21 cke0 44 cb0 67 dqs5 90 nc 22 v dd 45 cb1 68 dq42 91 sda 23 dq16 46 v dd 69 dq43 92 scl table 4: pin assignment (184-pin dimm back) pin symbol pin symbol pin symbol pin symbol 93 v ss 116 v ss 139 v ss 162 dq47 94 dq4 117 dq21 140 dqs17 163 nc 95 dq5 118 a11 141 a10 164 v dd 96 v dd 119 dqs11 142 cb6 165 dq52 97 dqs9 120 v dd 143 v dd 166 dq53 98 dq6 121 dq22 144 cb7 167 nc 99 dq7 122 a8 145 v ss 168 v dd 100 v ss 123dq23146dq36 169 dqs15 101 nc 124 v ss 147dq37170dq54 102 nc 125 a6 148 v dd 171 dq55 103 nc 126 dq28 149 dqs13 172 v dd 104 v dd 127dq29150dq38 173 nc 105 dq12 128 v dd 151dq39174dq60 106 dq13 129 dqs12 152 v ss 175 dq61 107 dqs10 130 a3 153 dq44 176 v ss 108 v dd 131 dq30 154 ras# 177 dqs16 109 dq14 132 v ss 155dq45178dq62 110dq15133dq31 156 v dd 179 dq63 111 nc 134 cb4 157 s0# 180 v dd 112 v dd 135 cb5 158 nc 181 sa0 113 nc 136 v dd 159 dqs14 182 sa1 114 dq20 137 ck0 160 v ss 183 sa2 115 nc/ a12 138 ck0# 161 dq46 184 v ddspd pin 93 pin 144 pin 145 pin 184 pin 1 pin 52 pin 53 pin 92 back view front view indicates a v dd pin indicates a v ss pin no components this side u1 u2 u3 u4 u5 u6 u7 u8 u9 u10
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 4 ?2003 micron technology. inc. table 5: pin descriptions refer to pin assignment tables on page 3 for pin number and symbol information pin numbers symbol type description 1 vref input sstl_2 reference voltage. 63, 65, 154 we#, cas#, ras# input command inputs: we#, ras#, and cas# (along with s#) define the command being entered. 16, 17, 75, 76, 137, 138 ck0, ck0#, ck1, ck1#, ck2, ck2# input clocks: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 21 cke0 input clock enable: cke activates (high) and deactivates (low) internal clock signals, device input buffers, and output drivers. deactivating the clock provides precharge power-down and self refresh operation (all device banks idle), or active power-down (row active in any device bank). cke0 is synchronous for all functions except for disabling outputs, which is achieved asynchronously. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during powerdown. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied. 157 s0# input chip select: s# enables (registered low) and disable (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 52, 59 ba0, ba1 input bank addresses: ba0 and ba1 define to which device bank an active, read, write or precharge command is being applied. 27, 29, 32, 37, 41, 43, 48, 115 (256mb) , 118, 122, 125, 130, 141 a0-a11 (128mb) a0-a12 (256mb) input address inputs: sampled during the active command (row-address) and read/write command (column- address, with a10 defining auto precharge) to select one location out of the memory array in the respective device device bank. a10 is sampled during a precharge command to determine whether the precharge applies to one device bank (a10 low) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 181, 182, 183 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 91 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 44, 45, 49, 51, 134, 135, 142, 144 cb0-cb7 input/output data i/os: check bits. ecc, one-bit error detection and correction. 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 dqs0-dqs17 input/output data strobes: output with read data, input with write data. edge- aligned with read data, centered in write data. used to capture write data.
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 5 ?2003 micron technology. inc. 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 117, 121, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 dq0-dq63 input/output data i/os: data bus. 7, 15, 22, 30, 38, 46, 54, 62, 70, 77, 85, 96, 104, 108, 112, 120, 128, 136, 143, 148, 156, 164, 168, 172, 180 v dd supply power supply: +2.5v +0.2v. (please see note 50 on page 21.) 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss supply ground. 184 v ddspd supply serial eeprom positive power supply: +2.3v to +3.6v. this supply is isolated from the v dd /v dd q supply. 9, 10, 71, 82, 90, 101, 102, 103, 111, 113, 115 (128mb), 158, 163, 167, 173 nc ? no connects. table 5: pin descriptions (continued) refer to pin assignment tables on page 3 for pin number and symbol information
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 6 ?2003 micron technology. inc. figure 3: functional block diagram -26a, -265, -202 speed optimized a0 sa0 serial pd u10 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 (128mb) a0-a12 (256mb) ras# ba0, ba1: sdrams a0-a11: sdrams a0-a12: sdrams ras#: sdrams cas#: sdrams we#: sdrams cke0: sdrams cas# we# cke0 v ref v ss sdrams sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u9 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u5 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9 s0# u3 wp scl dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13 dqs4 dqs10 dqs1 dqs14 dqs5 dqs11 dqs2 dqs15 dqs6 dm cs# dqs u8 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12 dqs3 dqs16 dqs7 dqs17 dqs8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v ddq v dd sdrams sdrams sdram x 3 ck0 ck0# 120 sdram x 3 ck1 ck1# 120 sdram x 3 ck2 ck2# 120 v ddspd spd/eeprom dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 4.5pf 4.5pf 4.5pf note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide . u1 - u9 = mt46v16m8tg ddr sdrams 128mb module u1 - u9 = mt46v32m8tg ddr sdrams 256mb module
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 7 ?2003 micron technology. inc. figure 4: functional block diagram -335 speed optimized a0 sa0 serial pd u10 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 (128mb) a0-a12 (256mb) ras# ba0, ba1: sdrams a0-a11: sdrams a0-a12: sdrams ras#: sdrams cas#: sdrams we#: sdrams cke0: sdrams cas# we# cke0 v ref v ss sdrams sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u5 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u9 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9 s0# u3 wp scl dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13 dqs4 dqs10 dqs1 dqs14 dqs5 dqs11 dqs2 dqs15 dqs6 dm cs# dqs u7 dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs12 dqs3 dqs16 dqs7 dqs17 dqs8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v ddq v dd sdrams sdrams sdram x 3 ck0 ck0# 120 sdram x 3 ck1 ck1# 120 sdram x 3 ck2 ck2# 120 v ddspd spd/eeprom dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 3pf 3pf 3pf 5.1 5.1 5.1 5.1 5.1 5.1 note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide . u1 - u9 = mt46v16m8tg ddr sdrams 128mb module u1 - u9 = mt46v32m8tg ddr sdrams 256mb module
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 8 ?2003 micron technology. inc. general description the mt9vddt1672a and MT9VDDT3272A are high-speed cmos, dynamic random-access, 128mb and 256mb memory modules organized in a x72 (ecc) configuration. these modules use internally config- ured quad-bank ddr sdram devices. these ddr sdram modules use a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram mod- ule effectively consists of a single 2 n -bit wide, one- clock-cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock- cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. these ddr sdram modules operate from a differ- ential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and out- put data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram mod- ules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select device bank; a0?a11 select device row for the 128mb module, a0?a12 select device row for the 256mb module). the address bits registered coincident with the read or write com- mand are used to select the device bank and the start- ing device column location for the burst access. these ddr sdram modules provide for program- mable read or write burst lengths of 2, 4, or 8 loca- tions. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdram modules, the pipe- lined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a pow- ersaving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 128mb and 256mb ddr sdram component data sheet. serial presence-detect operation these ddr sdram modules incorporate serial presence-detect (spd). the spd function is imple- mented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/ write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which pro- vide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, perma- nently disabling hardware write protect. mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in fig- ure 5, mode register definition diagram, on page 9. the mode register is programmed via the mode reg- ister set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst length, a3 specifies the type of burst (sequential or inter- leaved), a4?a6 specify the cas latency, and a7?a11 (for the 128mb module) or a7?a12 (for the 256mb module) specify the operating mode.
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 9 ?2003 micron technology. inc. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being program- mable, as shown in figure 5, mode register definition diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a9 when the burst length is set to two, by a2?a9 when the burst length is set to four and by a3?a9 when the burst length is set to eight (where a9 is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 6, burst definition table, on page 10. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 2.5 clocks, as shown in figure 6, cas latency diagram, on page 10. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table 7, cas latency (cl) table, on page 10, indicates the operating frequencies at which each cas latency set- ting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 5: mode register definition diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a11 (128mb), or a7?a12 (256mb) each set to zero, and bits a0?a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9?a11 (128mb), or a7 and a9?a12 (256mb) each set to zero, bit a8 set to one, and bits a0?a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba0 and ba1) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11 burst length cas latency bt 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 operating mode a10 a11 ba0 ba1 10 11 12 13 * m13 and m12 (ba0 and ba1) must be ?0, 0? to select the base mode register (vs. the extended mode register). 128mb module 256mb module
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 10 ?2003 micron technology. inc. reset the dll, it should always be followed by a load mode register command to select normal operat- ing mode. all other combinations of values for a7?a11, or a7? a12 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. note: 1. for a burst length of two, a1 ? a i select the two- data-element block; a0 selects the first access within the block. 2. or a burst length of four, a2 ? a i select the four- data-element block; a0 ? a1 select the first access within the block. 3. for a burst length of eight, a3 ? a i select the eight- data-element block; a0 ? a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 11 for 128mb module, i = 12 for 256mb module figure 6: cas latency diagram extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and out- put drive strength. these functions are controlled via the bits shown in figure 7, extended mode register definition diagram, on pa ge 11. the extended mode register is programmed via the load mode regis- ter command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the table 6: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 7: cas latency (cl) table speed allowable operating frequency (mhz) cl = 2 cl = 2.5 -335 n/a 75 f 167 -26a 75 f 133 75 f 133 -265 75 f 100 75 f 133 -202 75 f 100 75 f 125 ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 11 ?2003 micron technology. inc. enabling of the dll should always be followed by a load mode register command to the mode regis- ter (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements could result in unspecified oper- ation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. figure 7: extende d mode register definition diagram note: 1. e13 and e12 (128mb module), or e14 and e13 (256mb module) (ba1 and ba0) must be ?0, 1? to select the extended mode register (vs. the base mode register). 2. the qfc# option is not supported. operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 2 1 0 e0 0 drive strength normal e1 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 2 1 0 operating mode a10 a11 ba1 ba0 10 11 12 13 ds 128mb module 256mb module 0 ? e2 2
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 12 ?2003 micron technology. inc. commands the truth tables below provides a general reference of available commands. for a more detailed descrip- tion of commands and operations, refer to the 128mb and 256mb ddr sdram component data sheets. note: 1. cke is high for all commands shown except self refresh. 2. deselect and nop are functionally interchangeable. 3. ba0?ba1 provide device bank address and a0?a11 (128 mb) or a0?a12 (256mb) provide device row address. 4. ba0?ba1 provide device bank address; a0?a9 provide devi ce column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 5. applies only to read bursts with auto precharge disabled ; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 6. a10 low: ba0?ba1 determine which device bank is prec harged. a10 high: all device banks are precharged and ba0?ba1 are ?don?t care.? 7. this command is auto refresh if cke is high, self refresh if cke is low. 8. internal refresh counter controls device row addressi ng; all inputs and i/os are ?don?t care? except for cke. 9. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other comb inations of ba0?ba1 are rese rved). a0?a11 (for 128mb module) or a0?a12 (for 256mb modul e) provide the op-code to be written to the selected mode register. table 8: truth table ? commands notes: 1 name (function) cs# ras# cas# we# addr notes deselect (nop) hxxx x 2 no operation (nop) l hhh x 2 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 burst terminate lhhl x 5 precharge (deactivate row in bank or banks) l l h l code 6 auto refresh or self refresh (enter self refresh mode) lllh x 7, 8 load mode register llllop-code 9 table 9: truth table ? dm operation used to mask write data; provided coincident with the corresponding data name (function) dm dqs write enable lvalid write inhibit hx
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 13 ?2003 micron technology. inc. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v dd q supply relative to vs ss . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v ref and inputs relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on i/o pins relative to v ss . . . . . . . . . . . . -0.5v to v dd q +0.5v operating temperature, t a (ambient) . . . . . . . . . . . . . . . . . . . . . .0c to +70c storage temperature (plastic) . . . . . . -55c to +150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9w short circuit output current. . . . . . . . . . . . . . . . 50ma table 10: dc electrical characteristics and operating conditions notes: 1?5, 14, 50; notes appear on pages 18?21; 0 c t a +70 c parameter/condition symbol min max units notes supply voltage v dd q 2.3 2.7 v 32, 36 i/o supply voltage v dd q 2.3 2.7 v 32, 36, 39 i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd q v 6, 39 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 39 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il (ac) -0.3 v ref - 0.15 v 25 input leakage current: any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) command/address, ras#, cas#, we#, cke, s# i l -18 18 a 49 ck, ck# i l -6 6 a 49 dm i l -2 2 a 49 output leakage current: (dqs are disabled; 0v v out v dd q) dq, dqs i oz -5 5 a 49 output levels: high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 36 i ol 16.8 ? ma 34 table 11: ac input operating conditions notes: 1?5, 12, 14, 50; notes appear on pages 18?21; 0 c t a +70 c; v dd = v dd q = +2.5v +0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih (ac) v ref + 0.310 ? v 25, 35 input low (logic 0) voltage v il (ac) ? v ref - 0.310 v 25, 35 i/o reference voltage v ref (ac) 0.49 x v dd q 0.51 x v dd q v 6
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 14 ?2003 micron technology. inc. ta bl e 1 2 : i dd specifications an d conditions (128mb) dram components only notes: 1?5, 8, 10, 12, 50; notes appear on pages 18?21; 0 c t a +70 c; v dd = v dd q = +2.5v +0.2v parameter/condition symbol max units notes -335 -262 -26a/ -265 -202 operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; i dd 0 tbd tbd 945 900 ma 20, 43 operating current: one device bank; active-read- precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 tbd tbd 1,080 990 ma 20, 43 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low; i dd 2 p tbd tbd 27 27 ma 21, 28, 45 idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f tbd tbd 405 315 ma 46 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3 p tbd tbd 180 180 ma 21, 28, 45 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3 n tbd tbd 405 315 ma 40 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4 r tbd tbd 1,125 945 ma 20, 43, 24, 45 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w tbd tbd 1,035 945 ma 20 auto refresh current t rc = t rfc (min) i dd 5 tbd tbd 1,890 1,845 ma 24, 45 t rc = 15.625s i dd 5a tbd tbd 45 45 ma 24, 45 self refresh current: cke 0.2v standard i dd 6 tbd tbd 18 18 ma 9 low power i dd 6a tbd tbd 9 9 ma operating current: four device bank interleaving reads (bl=4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active, read, or write commands. i dd 7 tbd tbd 2,925 2,475 ma 20, 44
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 15 ?2003 micron technology. inc. ta bl e 1 3 : i dd specifications an d conditions (256mb) dram components only notes: 1?5, 8, 10, 12, 50; notes appear on pages 18?21; 0 c t a +70 c; v dd = v dd q = +2.5v +0.2v parameter/condition symbol max unit s notes -335 -262 -26a/ -265 -202 operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; i dd 0 1,125 1,125 945 1,080 ma 20, 43 operating current: one device bank; active-read- precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 1,530 1,440 1,305 1,395 ma 20, 43 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low; i dd 2 p 36 36 36 36 ma 21, 28, 45 idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f 450 405 405 405 ma 46 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3 p 270 225 225 270 ma 21, 28, 45 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3 n 540 450 450 450 ma 42 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4 r 1,575 1,350 1,350 1,575 ma 20, 43, 24, 45 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w 1,395 1,215 1,215 1,710 ma 20 auto refresh current t rc = t rfc (min) i dd 5 2,295 2,115 2,115 2,205 ma 24, 45 t rc = 7.8125s i dd 6 54 54 54 54 ma 24, 45 self refresh current: cke 0.2v standard i dd 7 36 36 36 36 ma 9 low power i dd 7a 18 18 18 18 ma operating current: four device bank interleaving reads (bl=4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active, read, or write commands. i dd 8 3,645 3,150 3,285 3,285 ma 20, 44
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 16 ?2003 micron technology. inc. table 14: capacitance (all modules) note: 11; notes appear on pages 18?21 parameter symbol min max units input/output capacitance: dqs, dqss c io 4.0 5.0 pf input capacitance: command and address, s0# c i 1 2.0 3.0 pf input capacitance: ck0, ck0# (-26a, -265, -202) c i 2 12.0 15.0 pf input capacitance: ck0, ck0# (-335) c i 2 9 12.0 pf input capacitance: ck1, ck1#, ck2, ck2# (-26a, -265, -202) c i 2 10.5 13.5 pf input capacitance: cke c i 3 18.0 27.0 pf table 15: electrical characteristics and recommended ac operating conditions notes: 1?5, 8, 12?15, 29, 31, 50; notes appear on pages 18?21; 0 c t a +70 c; v dd = v dd q = +2.5v 0.2v ac characteristics -335 -26a/265 -202 units notes parameter symbol min max min max min max access window of dq from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 -0.8 +0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 2.5 t ck (2.5) 6 13 7.5 13 8 13 ns 40, 47, 48 cl = 2 t ck (2) 7.5 13 7.5 13 10 13 ns 40, 47 dq and dm input hold time relative to dqs t dh 0.45 0.5 0.6 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 0.6 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 2 ns 27 access window of dqs from ck/ck# t dqsck -0.60 +0.60 -0.75 +0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.45 0.5 0.6 ns 22, 25 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 +0.8 ns 16, 37 data-out low-impedance window from ck/ck# t lz -0.70 -0.75 -0.8 ns 16, 38 address and control input hold time (fast slew rate) t ih f 0.75 0.90 1.1 ns 12 address and control input setup time (fast slew rate) t is f 0.75 0.90 1.1 ns 12 address and control input hold time (slow slew rate) t ih s 0.80 1 1.1 ns 12 address and control input setup time (slow slew rate) t is s 0.80 1 1.1 ns 12 load mode register command cycle time t mrd 12 15 16 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp- t qhs ns 22, 23 data hold skew factor t qhs 0.55 0.75 1 ns
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 17 ?2003 micron technology. inc. active to precharge command t ras 42 70,000 40 120,000 40 120,000 ns 31 active to read with auto precharge command 128mb t rap t ras(min) - (burst length) * t ck/2) ns 40 active to read with auto precharge command 256mb t rap 18 t ras(min) - (burst length) * t ck/2) ns active to active/auto refresh command period t rc 60 65 70 ns auto refresh command period t rfc 72 75 80 ns 45 active to read or write delay t rcd 18 20 20 ns precharge command period t rp 18 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 000ns18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 111 t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval 128mb t refc 140.6 140.6 140.6 s 21 refresh to refresh command interval 256mb t refc 70.3 140.6 140.6 s 21 average periodic refresh interval 128mb t refi 15.6 15.6 15.6 s 21 average periodic refresh interval 256mb t refi 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 00 ns exit self refresh to non-read command t xsnr 75 75 ns exit self refresh to read command t xsrd 200 200 t ck table 15: electrical characteristics and recommended ac operating conditions (continued) ac characteristics -335 -26a/265 -202 units notes parameter symbol min max min max min max
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 18 ?2003 micron technology. inc. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci- fications are guaranteed for the specified ac input levels under normal use conditions. the mini- mum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmit- ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time at cl = 2 for -262, -26a, and -202, cl = 2.5 for -265 and -335 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v dd q/2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. command/address input slew rate = 0.5v/ns. for -335 and -262, -26a, and -265 with slew rates 1v/ ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 13. the ck/ck# input reference level (for timing ref- erenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabi- lizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low ) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. tras (max) for idd measurements is the largest multi- ple of t ck that meets the maximum absolute value for t ras. 21. the refresh period 64ms. this equates to an aver- age refresh rate of 15.625s (128mb module) 7.8125s (256mb module). however, an auto refresh command must be asserted at least output (v out ) reference point 50 ? v tt 30pf
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 19 ?2003 micron technology. inc. once every 140.6s (128mb module) or 70.3s (256mb module); burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications - t hp ( t ck/2), tdqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncer- tain when operating beyond a 45/55 ratio. figure 8, derating data valid window ( t qh - t dqsq), shows the derating curves for duty cycles ranging between 50/50 and 45/55. 23. each byte lane has a separate dqs, with dq0? dq7. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a)sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b)reach at least the target ac level. c)after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) . 26. ck and ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncer- tain. 28. v dd must not vary more than 4 percent if cke is not active while any device bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 30. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. figure 8: derating data valid window ( t qh - t dqsq) 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns -26a/-265 @ t ck = 10ns -202 @ t ck = 10ns -26a/-265 @ t ck = 7.5ns -202 @ t ck = 8ns -335 @ t ck = 6ns tbd
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 20 ?2003 micron technology. inc. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis- fied prior to the internal precharge command being issued. 32. any positive glitch must be less than 1/3 of the clock cycle and not more than +400mv or 2.9v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mv or 2.2v, whichever is more positive. the dc average cannot go below 2.3v minimum. 33. normal output drive curves: a)the full variation in driver pull-down current from minimum to maximum process, tempera- ture and voltage will lie within the outer bound- ing lines of the v-i curve of figure 9, pull-down characteristics. b)the variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-down characteristics. c)t he full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 10, pull-up characteristics. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 10, pull-up characteristics . e)the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0v, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1v to 1.0v. 34. the voltage levels used are derived from a mini- mum v dd level and the refernced test load. in practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. v ih overshoot: v ih (max) = v dd q+1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. v dd and v dd q must track each other. 37. this maximum value is derived from the refer- enced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hz (max) and the last dvw. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 38. for slew rates of greater than 1v/ns the (lz) tran- sition will start about 310ps earlier. 39. during initialzation, v dd q, v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0.0v, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. figure 9: pull-down characteristics figure 10: pull-up characteristics 160 140 i out (ma) v out (v) nominal low minimum nominal high maximum 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) 0 -20 i out (ma) nominal low minimum nominal high maximum -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 v dd q - v out (v)
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 21 ?2003 micron technology. inc. 40. the current micron part operates below the slow- est jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 41. t rap t rcd. 42. for -335, -262, -26a, and -265 speed grades, i dd 3n is specified to be 35ma x (# of ddr sdram devices) at 100 mhz. 43. random addressing changing and 50 percent of data changing at every transfer. 44. random addressing changing and 100 percent of data changing at every transfer. 45. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 46. i dd 2n specifies the dq, dqs and dm to be driven to a valid high or low logic level. idd2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although idd2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 47. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 48. min t ck value at cl=2.5 in the spd for and -26a speeds is 0.7ns, to facilitate proper system opera- tion. 49. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 50. the -335 module speed grade, using the -6r speed device, has v dd (min) = 2.4v.
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 22 ?2003 micron technology. inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 11, data validity, and figure 12, defi- nition of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 12, definition of start and stop). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 11: data validity figure 12: definition of start and stop figure 13: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 23 ?2003 micron technology. inc. figure 14: spd eeprom timing diagram table 16: eeprom device select code most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 17: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 24 ?2003 micron technology. inc. note: 1. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 18: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 33.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: iout = 3ma v ol ?0.4 v input leakage current: vin = gnd to vdd i li ?10a output leakage current: vout = gnd to vdd i lo ?10a standby current: scl = sda = vdd - 0.3v; all other inputs = v ss or v ref i sb ?30a power supply current: scl clock frequency = 100 khz i cc ?2ma table 19: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0s start condition hold time t hd:sta 4s clock high period t high 4s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r 1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 1
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 25 ?2003 micron technology. inc. table 20: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes at end of spd matrix byte description entry (version) mt9vddt1672a MT9VDDT3272A 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram ddr 07 07 3 number of row addresses 12 or 13 0c 0d 4 number of column addresses 10 0a 0a 5 number of ranks 10101 6 module data width 72 48 48 7 module data width (continued) 00000 8 module voltage interface levels sstl 2.5v 04 04 9 sdram cycle time, t ck, (cas latency = 2.5) (see note 1) 6ns (-335) 7ns (-262/-26a) 7.5ns (-265) 8ns (-202) 60 70 75 80 60 70 75 80 10 sdram access from clock, t ac (cas latency = 2.5) 0.7ns (-335) 0.75ns (-262/-265/-26a) 0.8ns (-202) 70 75 80 70 75 80 11 module configuration type ecc 02 02 12 refresh rate/type 15.6 or 7.81s/self 80 82 13 sdram width (primary sdram) 80808 14 error-checking sdram data width 80808 15 minimum clock delay, back -to- back 10101 random column access 16 burst lengths supported 2, 4, 80e0e 17 number of banks on sdram device 40404 18 cas latencies supported 2, 2.5 0c 0c 19 cs latency 00101 20 we latency 10202 21 sdram module attributes unbuffered, diff clk 20 20 22 sdram device attributes: general fast/concurrent auto precharge 00/c0 (see note 2) c0 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-335/-262/-26a) 10ns (-202/-265) 75 a0 75 a0 24 sdram cycle time, t ck (cas latency = 2) (see note 1) 0.7ns (-335) 0.75ns (-262/-265/-26a) 0.8ns (-202) 70 75 80 70 75 80 25 sdram cycle time, t ck (cas latency = 1) ?0000 26 sdram access from ck , (cas latency = 1) ?0000 27 minimum row precharge time, t rp 18ns (-335) 20ns (-262) 20ns (-202/-265/-26a) 48 3c 50 48 3c 50 28 minimum row active to row active, t rrd 12ns (-335) 15ns (-202/-265/-26a)/-262 30 3c 30 3c 29 minimum ras# to cas# delay, t rcd 18ns (-335) 20ns (-262) 20ns (-202/-265/-26a) 48 3c 50 48 3c 50
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 26 ?2003 micron technology. inc. 30 minimum ras# pulse width, t ras 42ns (-335) 45ns (-262/-265/-26a) 40ns (-202) 2a 2d 28 2a 2d 28 31 module rank density 128mb or 256mb 20 40 32 address and command setup time, t is (see note 3) 0.8ns (-335) 1.0ns (-262/-265/-26a) 1.1ns (-202) 80 a0 b0 80 a0 b0 33 address and command hold time, t ih (see note 3) 0.8ns (-335) 1.0ns (-262/-265/-26a) 1.1ns (-202) 80 a0 b0 80 a0 b0 34 data/data mask input setup time, t ds 0.45ns (-335 0.5ns (-262/-265/-26a) 0.6ns (-202) 45 50 60 45 50 60 35 data/data mask input hold time, t dh 0.45ns (-335 0.5ns (-262/-265/-26a) 0.6ns (-202) 45 50 60 45 50 60 36-40 reserved 00 00 41 minimum active/auto refresh time, ( t rc) 60ns (-335/-262) 65ns (-265/-26a) 70ns (-202) 3c 41 46 3c 41 46 42 minimum auto refresh to active/ auto refresh command period, ( t rfc) 72ns (-335) 75ns (-262/-265/-26a) 80ns (-202) 48 4b 50 48 4b 50 43 maximum cycle time, ( t ck (max)) 12ns (-335) 13ns (-202/-265/-26a/-262) 30 34 30 34 44 maximum dqs-dq skew time, ( t dqsq) 0.45ns (-335) 0.5ns (-262-265/-26a) 0.6ns (-202) 2d 32 3c 2d 32 3c 45 maximum read data hold skew factor, ( t qhs) 0.6ns (-335) 0.75ns (-262/-265/-26a) 1ns (-202) 60 75 a0 60 75 a0 46-61 reserved 00 00 62 spd revision release 0.0 00 00 63 checksum for bytes 0?62 -335 -262 -26a -265 -202 na /10 (see note 2) 94 05/c5 (see note 2) 35/f5 (see note 2) d0/90 (see note 2) 33 b7 e8 18 b3 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (continued) 00 00 72 manufacturing location 01?11 01?0b 01?0b 73-90 module part number (ascii) variable data variable data 91 pcb identification code 1?9 01?09 01?09 92 identification code (continued) 00000 93 year of manufacture in bcd variable data variable data table 20: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes at end of spd matrix byte description entry (version) mt9vddt1672a MT9VDDT3272A
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 27 ?2003 micron technology. inc. note: 1. the value of t ck for -26a modules is set at 7.0ns. component spec. value is 7.5ns. 2. supports fast/concurrent auto precharge. values are listed in the form ?without concurrent auto precharge? / ?with concurrent auto precharge.? contact factory for additonal information regarding this option. 3. the jedec spd specification allows fast or slow slew rate values for these bytes. the worst-case (slow slew rate) value is represented here. systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 94 week of manufacture in bcd variable data variable data 95-98 module serial number variable data variable data 99-127 manufacturer-specific data (rsvd) ?? table 20: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes at end of spd matrix byte description entry (version) mt9vddt1672a MT9VDDT3272A
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. 128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice.. dd9c16_32x72ag_b.fm - rev. b 2/03 en 28 ?2003 micron technology, inc figure 15: 184-pin dimm dimensions note: all dimensions in inches (millimeters) or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifica- tions are subject to change, as further product devel- opment and data characterization sometimes occur. 1.255 (31.88) 1.245 (31.62) pin 1 0.700 (17.78) typ. 0.098 (2.50) d (2x) 0.091 (2.30) typ. 0.250 (6.35) typ. 4.750 (120.65) 0.050 (1.27) typ. 0.091 (2.30) typ. 0.040 (1.02) typ. 0.079 (2.00) r (4x) 0.035 (0.90) r pin 92 front view back view no components this side 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 0.150 (3.80) 0.150 (3.80) typ. 0.394 (10.00) typ. 0.125 (3.18) max u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 max min
128mb, 256mb (x72, ecc) 184-pin ddr sdram dimm 09005aef808f8ccd micron technology, inc., reserves the right to change products or specifications without notice. dd9c16_32x72ag_b.fm - rev. b 2/03 en 29 ?2003 micron technology. inc. revision history rev. b, released, 2/03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/03 added low power option updated idd, capacitance, dc electrical values updated format added -335 and -262 speed grades added pf-free option rev. a, released, 01/02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 01/02 new data sheet

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