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four character 5.0 mm (0.20 inch) 5 x 7 alphanumeric displays hdsp-2301 hdsp-2302 HDSP-2303 technical data features ? integrated shift registers with constant current drivers ? compact ceramic package ? wide viewing angle ? end stackable four character package ? ttl compatible ? 5 x 7 led matrix displays full ascii set ? categorized for luminous intensity ? hdsp-2301/2303 categorized for color applications ? avionics ? business machines ? medical instruments ? portable data entry devices description the hdsp-2301/-2302/-2303 series of displays are 5.0 mm (0.20 inch) 5 x 7 led arrays for display of alpha- numeric information. these devices are available in yellow, high efficiency red, and high performance green. each four character cluster is contained in a 12 pin dual-in-line package. an devices yellow high efficiency red green hdsp-2301 hdsp-2302 HDSP-2303 on-board sipo (serial-in-parallel- out) 7-bit shift register associated with each digit controls constant current led row drivers. full character display is achieved by external column strobing.
2 absolute maximum ratings (hdsp-2301/-2302/-2303) supply voltage, v cc to ground ...................................... C0.5 v to 6.0 v inputs, data out and v b .................................................. C0.5 v to v cc column input voltage, v col ....................................... C0.5 v to +6.0 v free air operating temperature range, t a [1,2] .......... C20?c to +85?c storage temperature range, t s ................................ C55?c to +100?c maximum allowable package dissipation at t a = 25?c [1,2,3] hdsp-2301/-2302/-2303 .................................................. 1.46 watts maximum solder temperature 1.59 mm (0.63) below seating plane t < 5 sec ................................................. 260?c recommended operating conditions (hdsp-2301/-2302/-2303) parameter symbol min. nom. max. units fig. supply voltage v cc 4.75 5.0 5.25 v data out current, low state i ol 1.6 ma data out current, high state i oh C0.5 ma column input voltage, column on hdsp-2301/-2302/-2303 v col 2.75 3.5 v 4 setup time t setup 70 45 ns 1 hold time t hold 30 0 ns 1 width of clock t w(clock) 75 ns 1 clock frequency f clock 0 3 mhz 1 clock transition time t thl 200 ns 1 free air operating temperature range [1,2] t a C20 85 ?c 2 package dimensions 20.01 (0.790) max. 2.84 (0.112) ref. see note 3 see note 3 8.43 (0.335) 4.87 (0.192) ref. 5.00 ?0.13 (0.197 ?0.005) 123456 12 11 10 9 8 7 pin 1 marked by dot on back of package 5.08 (0.200) 2.54 (0.100) 1.27 ?0.13 (0.050 ?0.005) 6.85 (0.270) 2.54 ?0.13 (0.100 ?0.005) non accum. typ. 1.27 (0.050) typ. 0.54 ?0.08 (0.020 ?0.003) c l 6.35 ?0.25 (0.250 ?0.010) 0.25 ?0.05 (0.010 ?0.002) typ. pin function pin function 1 2 3 4 5 6 column 1 column 2 column 3 column 4 column 5 int. connect* 7 8 9 10 11 12 data out v b v cc clock ground data in *do not connect or use notes: 1. dimensions in millimeters (inches). 2. unless otherwise specified, the tolerance on all dimensions is ?0.38 mm (?0.015"). 3. characters are centered with respect to leads within ?0.13 mm (?0.005"). 12 34 max.
3 electrical characteristics over operating temperature range (unless otherwise specified) *all typical values specified at v cc = 5.0 v and t a = 25?c unless otherwise noted. **power dissipation per package with four characters illuminated. notes: 1. operation above 85?c ambient is possible provided the following conditions are met. the junction temperature should not exceed 125?c t j and the case temperature (as measured at pin 1 or the back of the display) should not exceed 100?c t c . 2. the hdsp-2301/-2302/-2303 should be derated linearly above 37?c at 16.7 mw/?c. this derating is based on a device mounted in a socket having a thermal resistance from case to ambient at 35?** c/w per device. see figure 2 for power deratings based on a lower thermal resistance. 3. maximum allowable dissipation is derived from v cc = 5.25 v, v b = 2.4 v, v col = 3.5 v 20 leds on per character, 20% df. supply current column current at any column input column current at any column input v b , clock or data input threshold high v b , clock or data input threshold low input current logical 1 input current logical 0 data out voltage power dissipation per package** thermal resistance ic junction-to-case v b = 0.4 v 45 60 ma v b = 2.4 v 73 95 ma v b = 0.4 v 500 m a v b = 2.4 v 380 520 ma 2.0 v 0.8 v 20 80 m a 10 40 m a C500 C800 m a C250 C400 m a 2.4 3.4 v 0.2 0.4 v 0.78 w 25 v cc = 5.25 v v clock = v data = 2.4 v all sr stages = logical 1 v cc = 5.25 v v col = 3.5 v all sr stages = logical 1 v cc = v col = 4.75 v v cc = 5.25 v, v ih = 2.4 v v cc = 5.25 v, v il = 0.4v v cc = 4.75 v, i oh = C0.5 ma, i col = 0 ma v cc = 4.75 v, i ol = 1.6 ma, i col = 0 ma v cc = 5.0 v, v col = 3.5 v, 17.5% df 15 leds on per character, v b = 2.4 v yellow hdsp-2301/high efficiency red hdsp-2302/ high performance green HDSP-2303 i cc i col i col v ih v il i ih i ih i il i il v oh v ol p d r q jCc description symbol test conditions min. typ.* max. units fig. v b , clock data in v b , clock data in ?c/w/ device 2 2 4
4 high performance green HDSP-2303 description symbol test conditions min. typ.* max. units fig. peak luminous intensity i vpeak v cc = 5.0 v, v col = 3.5 v 1280 2410 m cd 3 per led [4,8] t i = 25?c [6] , v b = 2.4 v (character average) peak wavelength l peak 568 nm dominant wavelength [5,7] l d 574 nm yellow hdsp-2301 description symbol test conditions min. typ.* max. units fig. peak luminous intensity i vpeak v cc = 5.0 v, v col = 3.5 v 650 1140 m cd 3 per led [4,8] t i = 25?c [6] , v b = 2.4 v (character average) peak wavelength l peak 583 nm dominant wavelength [5,7] l d 585 nm optical characteristics high efficiency red hdsp-2302 description symbol test conditions min. typ.* max. units fig. peak luminous intensity i vpeak v cc = 5.0 v, v col = 3.5 v 650 1430 m cd 3 per led [4,8] t i = 25?c [6] , v b = 2.4 v (character average) peak wavelength l peak 635 nm dominant wavelength [7] l d 626 nm *all typical values specified at v cc = 5.0 v and t a = 25?c unless otherwise noted. **power dissipation per package with four characters illuminated. notes: 4. the characters are categorized for luminous intensity with the intensity category designated by a letter code on the bottom of the package. 5. the hdsp-2301/-2303 are categorized for color with the color category designated by a number code on the bottom of the package. 6. t i refers to the initial case temperature of the device immediately prior to the light measurement. 7. dominant wavelength l d , is derived from the cie chromaticity diagram, and represents the single wavelength which defines the color of the device. 8. the luminous sterance of the led may be calculated using the following relationships: l v (cd/m 2 ) = l v (candela)/a (metre) 2 l v (footlamberts) = p i v (candela)/a (foot) 2 a = 5.3 x 10 C8 m 2 = 5.8 x 10 C7 (foot) 2
5 figure 1. switching characteristics hdsp-2301/-2302/-2303 (t a = C20?c to +85?c). figure 3. relative luminous intensity vs. temperature. figure 2. maximum allowable power dissipation vs. temperature. figure 4. peak column current vs. column voltage. p d max. ?maximum allowable power dissipation ?watts 0 0 t a ?ambient temperature ?? 90 20 70 80 100 2.0 1.8 1.6 1.4 1.0 0.8 0.4 0.2 60 50 40 30 10 r q ja = 60?/w r q ja = 50?/w r q ja = 40?/w 1.2 0.6 relative luminous intensity 0 t j ?junction temperature ?? 120 4.0 60 0 20 80 140 3.0 2.0 1.0 -20 40 100 hdsp-2302 hdsp-2301 HDSP-2303 i col ?peak column current ?ma 0 0 v col ?column voltage ?volts 5.0 3.0 500 400 300 200 1.0 2.0 4.0 100 hdsp-2301/-2302/-2303 t hold 1/f max. t w t thl t setup t setup t hold t phl t plh parameter condition min. typ. max. units f clock clock rate 3 mhz t plh , t phl propagation delay clock to data out c l = 15 pf r l = 2.4 k w 125 ns clock data in data out 1.5 v 1.5 v 90 % 10 % 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 2.4 v 0.4 v 2.4 v 0.4 v 2.4 v 0.4 v
6 electrical description the hdsp-230x series of four character alphanumeric displays have been designed to allow the user maximum flexibility in interface electronics design. each four character display module features data in and data out terminals arrayed for easy pc board interconnection. data out represents the output of the 7th bit of digit number 4 shift register. shift register clocking occurs on the high to low transition of the clock input. the like columns of each character in a display cluster are tied to a single pin. figure 5 is the block diagram for the displays. high true data in the shift register enables the output current mirror driver stage associated with each row of leds in the 5 x 7 diode array. the ttl compatible v b input may either be tied to v cc for maximum display intensity or pulse width modulated to achieve intensity control and reduction in power consumption. the normal mode of operation input data for digit 4, column 1, ambient lighting display color dim moderate bright hdsp-2301 (yellow) panelgraphic yellow 27 polaroid hncp37 chequers amber 107 3m light control film panelgraphic gray 10 hdsp-2302 (her) panelgraphic ruby red 60 chequers grey 105 polaroid hncp10 chequers red 112 HDSP-2303 (hp green) panelgraphic green 48 chequers green 107 figure 6. contrast enhancement filters. figure 5. block diagram of hdsp-2301/-2302/-2303. led matrix 1 serial decoded data input blanking control clock led matrix 2 led matrix 3 led matrix 4 5555 7777 7777 28 bit sipo shift register data locations 1 ?7 8 ?14 15 ?21 22 ?28 rows 1 ?7 constant current sinking led drivers rows 1 ?7 rows 1 ?7 rows 1 ?7 serial decoded data output 5 column drive inputs
7 mechanical and thermal considerations the hdsp-2301/-2302/-2303 are available in standard ceramic dual-in-line packages. they are designed for plugging into sockets or soldering into pc boards. the packages may be horizontally or vertically stacked for character arrays of any desired size. the hdsp-2301/- 2302/-2303 utilize a high output current ic to provide excellent readability in bright ambient lighting. full power operation (v cc = 5.25 v, v b = 2.4 v, v col = 3.5 v) with worst case thermal resistance from ic junction to ambient of 60?c/watt/device is possible up to ambient temperature of 37?c. for operation above 37?c, the maximum device dissipation should be derated linearly at 16.7 mw/?c (see figure 2). with an improved thermal design, operation at higher ambient temperatures without derating is possible. power derating for this family of displays can be achieved in several ways. the power supply voltage can be lowered to a minimum of 4.75 v. column input voltage, v col , can be decreased to the recommended minimum value of 2.75 v for the hdsp-2301/-2302/-2303. also, the average drive current can be decreased through pulse width modulation of v b . is loaded into the 7 on-board shift register locations 1 through 7. column 1 data for digits 3, 2, and 1 is similarly shifted into the display shift register locations. the column 1 input is now enabled for an appropriate period of time, t. a similar process is repeated for columns 2, 3, 4, and 5. if the time necessary to decode and load data into the shift register is t, then with five columns, each column of the display is operating at a duty factor of: d.f. = the time frame, t + t, allotted to each column of the display is generally chosen to provide the maximum duty factor consistent with the minimum refresh rate necessary to achieve a flicker free display. for most strobed display systems, each column of the display should be refreshed (turned on) at a minimum rate of 100 times per second. with columns to be addressed, this refresh rate then gives a value for the time t + t of: 1/[5 x (100)] = 2 msec if the device is operated at 3.0 mhz clock rate maximum, it is possible to maintain t << t. for short display strings, the duty factor will then approach 20%. for further applications information, refer to agilent application note 1016. t 5 (t + t) the hdsp-2301/-2302/-2303 displays have glass windows. a front panel contrast enhancement filter is desirable in most actual display applications. some suggested filter materials are provided in figure 6. additional information on filtering and contrast enhancement can be found in agilent application note 1015. for more information on soldering and post-solder cleaning, please see application note 1027, soldering led components.
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. obsoletes 5953-7749e 5966-2487e (11/99)
using the hdsp-2000 alphanumeric display family application note 1016 introduction first introduced in 1975, the hdsp-2000 alphanumeric display has been designed into a variety of applications. the hdsp-2000 display was originally designed for commercial, industrial, instru- mentation, and business equipment applications. however, the introduction of high efficiency red, yellow, and high performance green devices as well as several display sizes has opened up a mul- titude of new applications for the hdsp-2000 alphanumeric display family. the high efficiency red, yellow, and high performance green devices use gallium phos- phide (gap) leds. the gap displays are readable in direct sunlight with proper contrast en- hancement techniques. for this reason, the hdsp-2000 family dis- plays have been designed into a variety of avionic and process control applications. the hdsp-2000 family displays are available in three character sizes of 3.8 mm (0.15"), 4.9 mm (0.19"), and 6.9 mm (0.27") to allow the designer to optimize display com- pactness versus long distance readability. versions of the hdsp-2000 family alphanumeric displays are available with a true hermetic package and an operat- ing temperature range of C55 c to +85 c to allow designers to utilize the proven reliability of led dis- play technology in military and aerospace applications. this note is intended to serve as a design and application guide for users of the hdsp-2000 family of alphanumeric display devices. the information presented will cover: the theory of the device design and operation; consider- ations for specific circuit designs; thermal management, power de- rating and heat sinking; intensity modulation techniques. the hdsp-2000 family has been designed to provide a high resolu- tion information display subsystem. each character of the 4 character package consists of a 5 x 7 array of leds which can dis- play a full range of alphabetic and numeric characters plus punctua- tion, mathematical and other special symbols. the hdsp-2000 family is available in four colors: red, high efficiency red, yellow, and high performance green. the character height, character spacing, color and part number of each member of the hdsp-2000 family of displays is shown in table 1. the overall package size is designed to allow end stacking of multiple clusters to form char- acter strings of any desired length. electrical description the on-board electronics of the hdsp-2000 display family elimi- nates some of the classical difficulties associated with the use of alphanumeric displays. tra- ditionally, single digit led dot matrix displays have been orga- nized in an x-y addressable array requiring 12 interconnect pins per digit plus extensive row and col- umn drive support electronics. all members of the hdsp-2000 dis- play family provide on-board storage of decoded row data plus constant current sinking row driv- ers for each of the 28 rows in the 4 character display. this approach allows the user to address each display package through just 11 active interconnections vs. the 176 interconnections and 36 com- ponents required to effect a similar function using conven- tional led matrices. figure 1 is a block diagram of the internal circuitry of the hdsp-2000 display. the device consists of four led matrices and
2 table 1. the hdsp-2000 alphanumeric display family figure 1. block diagram led matrix 4 led matrix 3 led matrix 2 rows 1-7 constant current sinking led drivers 1234 rows blanking control, v b 567 123 column column drive inputs 45 rows 1-7 rows 1-7 rows 8-14 28-bit sipo shift register 1234 clock serial data input serial data output 5 6 7 rows 15-21 rows 22-28 xxxxxx.xx e c i v e dr o l o c r e t c a r a h c t h g i e h r e t c a r a h c g n i c a p s g n i t a r e p o e r u t a r e p m e t 0 0 0 2 - p s d h 1 0 0 2 - p s d h 2 0 0 2 - p s d h 3 0 0 2 - p s d h d e r w o l l e y d e r y c n e i c i f f e h g i h n e e r g e c n a m r o f r e p h g i h ) . n i 5 1 . 0 ( m m 8 . 3 ) . n i 5 1 . 0 ( m m 8 . 3 ) . n i 5 1 . 0 ( m m 8 . 3 ) . n i 5 1 . 0 ( m m 8 . 3 ) . n i 5 7 1 . 0 ( m m 5 . 4 ) . n i 5 7 1 . 0 ( m m 5 . 4 ) . n i 5 7 1 . 0 ( m m 5 . 4 ) . n i 5 7 1 . 0 ( m m 5 . 4 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 0 3 2 - p s d h 1 0 3 2 - p s d h 2 0 3 2 - p s d h 3 0 3 2 - p s d h d e r w o l l e y d e r y c n e i c i f f e h g i h n e e r g e c n a m r o f r e p h g i h ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 7 9 1 . 0 ( m m 0 . 5 ) . n i 7 9 1 . 0 ( m m 0 . 5 ) . n i 7 9 1 . 0 ( m m 0 . 5 ) . n i 7 9 1 . 0 ( m m 0 . 5 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 9 4 2 - p s d h 1 9 4 2 - p s d h 2 9 4 2 - p s d h 3 9 4 2 - p s d h d e r w o l l e y d e r y c n e i c i f f e h g i h n e e r g e c n a m r o f r e p h g i h ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 5 3 . 0 ( m m 9 . 8 ) . n i 5 3 . 0 ( m m 9 . 8 ) . n i 5 3 . 0 ( m m 9 . 8 ) . n i 5 3 . 0 ( m m 9 . 8 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 2 C 5 8 + o t c c 0 1 0 2 - p s d hd e r) . n i 5 1 . 0 ( m m 8 . 3) . n i 5 7 1 . 0 ( m m 5 . 40 4 C 5 8 + o t c c 0 1 3 2 - p s d h 1 1 3 2 - p s d h 2 1 3 2 - p s d h d e r w o l l e y d e r y c n e i c i f f e h g i h ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 2 9 1 . 0 ( m m 9 . 4 ) . n i 7 9 1 . 0 ( m m 0 . 5 ) . n i 7 9 1 . 0 ( m m 0 . 5 ) . n i 7 9 1 . 0 ( m m 0 . 5 5 5 C 5 8 + o t c c 5 5 C 5 8 + o t c c 5 5 C 5 8 + o t c c 0 5 4 2 - p s d h 1 5 4 2 - p s d h 2 5 4 2 - p s d h d e r w o l l e y d e r y c n e i c i f f e h g i h ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 7 2 . 0 ( m m 9 . 6 ) . n i 5 3 . 0 ( m m 9 . 8 ) . n i 5 3 . 0 ( m m 9 . 8 ) . n i 5 3 . 0 ( m m 9 . 8 5 5 C 5 8 + o t c c 5 5 C 5 8 + o t c c 5 5 C 5 8 + o t c c
3 two 14-bit serial-in-parallel-out shift registers. the led matrix for each character is a 5 x 7 diode ar- ray organized with the anodes of each column tied in common and the cathodes of each row tied in common. the 7 row cathode com- mons of each character are tied to the constant current sinking out- puts of 7 successive stages of the shift register. the like columns of the 4 characters are tied together and brought to a single address pin (i.e., column 1 of all 4 charac- ters is tied to pin 1, etc.). in this way, any diode in the four 5 x 7 matrices may be addressed by shifting data to the appropriate shift register location and apply- ing a voltage to the appropriate column. the serial-in-parallel-out (sipo) shift register has a constant cur- rent sinking output associated with each shift register stage. this constant current output drives each led at a nominal peak cur- rent of 12 to 14 ma peak. the output stage is a current mirror design with a nominal current gain of 10. a logical 1 loaded into each shift register bit will turn on the corresponding current source provided that a logical 1 is applied to the blanking input, v b . if v col is applied to the appropri- ate column input, the corresponding led diode will be turned on. since the row driv- ers have a constant current output, the led current will re- main constant as long as the column input voltage exceeds 2.4 v for red and 2.75 v for high effi- ciency red, yellow, and high performance green devices. data is loaded serially into the shift register on the high to low transition of the clock input. during the time that data is being loaded into the display, the col- umn current must be disabled to minimize the generation of cur- rent spikes between v cc , the columns, and ground. the result- ing power supply noise could induce noise on the clock and data inputs. the column current can be disabled either by switch- ing off the column drivers or by applying a logical 0 to the blank- ing input. the data output terminal is a ttl buffer interface to the 28th bit of the shift register (i.e., the 7th row of character 4 in each package) the data output is arranged to directly interconnect to the data input on a succeeding 4 digit hdsp-2000 display package. the data, clock and v b inputs are all buffered to allow direct interface to any ttl logic family. theory of operation dot matrix alphanumeric display systems generally have a logical organization which prescribes that any character be generated as a combination of several subsets of data. in a 5 x 7 matrix, this could be either 5 subsets of 7 bits each or 7 subsets of 5 bits each. this technique is utilized to re- duce from 35 to 5 or 7 the number of outputs required from the char- acter generator. in order to display a complete character, these subsets of data are then pre- sented sequentially to the appropriate locations of the dis- play matrix. if this process is repeated at a rate which insures that each of the appropriate ma- trix locations is reenergized a minimum of 100 times per second, the eye will perceive a continuous image of the entire character. the apparent intensity of each of the display elements will be equal to the intensity of that element dur- ing the on period multiplied by the ratio of on time to refresh period. this ratio is referred to as the display duty factor, and the technique is referred to as strobing. in the case of hdsp- 2000, each character is made up of 5 subsets of 7 bits. for a four character display, 28 bits repre- senting the first subset of each of the four characters are loaded se- rially into the on-board sipo shift register and the first column is then energized for a period of time, t. this process is then re- peated for columns 2 through 5. if the time required to load the 28 bits into the sipo shift register is t, then the duty factor is: df t tt .. ; () = + () 5 1 the term 5(t + t) is then the re- fresh period. for satisfactory display, the refresh period should be: 1 5 100 2 /() tt hz + () [] 3 or conversely 510 3 tt m + () sec, ( ) which gives tt m + () 24 sec. ( ) the time averaged luminous intensity of the display can be varied continuously over a range greater than 1000 to 1 by turning off or blanking the display before loading new data into the sipo shift register. if the time that the display is blanked is t b , then the duty factor of the display becomes:
4 df t ttt b .. () = ++ () 5 5 where ttt m a b ++ () 25 sec. ( ) drive circuit concepts a practical display system utiliz- ing the hdsp-2000 family of displays requires interfacing with a character generator, refresh memory and some timing cir- cuitry. a block diagram of such a display system is depicted in figure 2. this circuit provides for ascii data storage and decoding and properly refreshes the display at a 100 hz refresh rate. in this figure, the display length is shown as n characters with the leftmost display character labeled as char- acter 1 and the right most character of the display labeled as character n. the refreshing of the display is accomplished by a series of counters. the n counter sequentially ac- cesses n coded information symbols from the n x 7 ram. note that for the normal configu- ration of the hdsp-2000 displays, character 1 is the leftmost charac- ter, character 4 is the rightmost character and shift register cas- cades from left to right. thus, the symbol corresponding to charac- ter n is decoded first, then the symbol corresponding to charac- ter (n-1), and the symbol corresponding to character 1 is decoded last. each coded information symbol is read from the n x 7 ram and de- coded by a 5 x 7 decoder. the decoder can be selected to de- code ascii, ebdic, or any customized character font in this example, the ascii decoder is or- ganized as 128 x 7 words of 5 bits each. the ascii symbol and row select information is applied to the decoder and the decoder out- puts information for all 5 columns for the selected row and symbol. the 7 counter sequentially ac- cesses all seven rows of each ascii symbol. note that row 7 must be decoded first, then row 6, and row 1 is decoded last. the m counter is used to periodically load new serial data into the hdsp-2000 display. during one count, the display clock is en- abled and 7n bits of serial data are loaded into the display. during the remaining (m1) counts, this data is displayed. thus the duty factor for the cir- cuit in figure 2 is df m m m .. . () = - () =- ? ? ? - 1 5 20 1 6 1 the 5 counter sequentially re- freshes all 5 columns of the display. the outputs of the 5 counter are connected to a data multiplexer which selects one of the 5 outputs from the ascii de- coder and loads it into the data input of the hdsp-2000 display string. the 5 counter also en- ables one of the 5 column driver figure 2. ckt block diagram an1016.02 nx7 ram log 2 n 5 5 v cc v b 5 33 3 log 2 m row select ascii 5x7 decoder mux hdsp-2000 display n down counter m down counter 5 up counter 7 down counter clock in 1/5 decoder enable character i 7xnxmx5x100 hz column output high first count in m character n
5 transistors. note that the display is blanked via the v b input and also that the column driver tran- sistors are turned off during the time that new data is being loaded into the hdsp-2000 display string. this will eliminate any high cur- rent transients between the column inputs and ground during the data shifting operation. since data is loaded for all of the like columns in the display string and these columns are then en- abled simultaneously, only five column switch transistors are re- quired regardless of the number of characters in the string. the column switch transistors should be selected to handle 105 to 130 ma per character in the display string. the collector emitter satu- ration voltage characteristics and column voltage supply should be chosen to provide 2.4 v v col v cc for the standard red displays and 2.75 v v col v cc for the high efficiency red, yellow, and high performance green displays. to save on power supply costs and improve efficiency, this sup- ply may be a fullwave rectified unregulated dc voltage as long as the peak value does not ex- ceed the value of v cc and the minimum value does not drop be- low 2.4 v or 2.75 v depending on display color. figures 13 and 16 show practical implementations of the block dia- gram shown in figure 2. in those circuits, the display is mounted upside down, so that pin 1 is in the upper right hand corner. with this technique, data is loaded into display character n and data shifts from right to left as new data is loaded. the first bit loaded into the display would be row 1, character 1, then row 2, etc., and the last bit loaded would be row 7 of character n. this allows the 7, n and m counters to be imple- mented as up counters instead of down counters. since the display is upside down, column 5 of the display appears to be column 1 and column 4 of the display ap- pears to be column 2. thus, column 1 data for the display must be loaded into the display and column 5 must subsequently be enabled. this is accomplished by reversing the outputs of the 5 x 7 decoder. the d 0 , d 1 , d 2 , d 3 , and d 4 outputs of the mcm6674 de- coder output column 5, column 4, column 3, column 2, and column 1 information. interfacing the hdsp-2000 display to microprocessors because of the complexity of dealing with alphanumeric infor- mation, a microprocessor based system is typically used in con- junction with the hdsp-2000 family displays. depending upon overall systems configuration, mi- croprocessor time available to dedicate to display support, and the type of information to be dis- played, one may choose several different partitioning schemes to drive such a display. figure 3 shows four different techniques to interface the hdsp- 200 family displays to microprocessor systems: 1. the refresh controller interrupts the microprocessor at a 500 hz rate to request re- fresh data for the display. 2. the decoded data con- troller accepts 5 x 7 matrix data from the microprocessor and then automatically re- freshes the display with the same information until new data is supplied by the microprocessor. 3. the coded data control- ler accepts ascii data and interfaces like a ram to the microprocessor. 4. the display processor controller (hdsp-247x series) employs a dedicated single chip microprocessor as a data display/control/key- board interface which has many of the features of a complete terminal. the interface techniques depicted are specifically for the 8080a or 6800 microprocessor families. extension of these techniques to other processors should be a relatively simple software chore with little or no hardware changes required. the choice of a particular inter- face is an important consideration because it affects the design of the entire microprocessor system. the refresh controller provides the lowest cost interface because it uses the microproces- sor to provide ascii decoding and display strobing. because the ascii decoder is located within the microprocessor system, the designer has total control over the display font within the program. this feature is particularly impor- tant when the system will be used to display different languages and special graphic symbols. however, the refresh con- troller requires a significant amount of microprocessor time. furthermore, while the interrupt allows the refresh program to operate asynchronously from the main program, this technique
6 limits some of the software tech- niques that can be used in the main program. the decoded data control- ler requires microprocessor interaction only when the display message is changed. like the re- fresh controller, the ascii decoder is located within the mi- croprocessor program. however, the time required to decode the ascii string and store the result- ing 5 x 7 display data into the interface requires several millisec- onds of microprocessor time. the coded data control- ler also requires interaction from the microprocessor system only when the display message is changed. because the ascii de- coder is located within the display interface, the microprocessor re- quires much less time to load a new message into the display. the display processor con- troller, the hdsp-247x series, is the most powerful interface. the software within the display processor controller fur- ther reduces the host microprocessor interaction by providing more powerful left and right data entry modes compared to the ram entry mode of the de- coded data and coded data controllers. the display processor controller can also provide features such as a blinking cursor, editing com- mands, and a data out function. one version of the display pro- cessor controller allows the user to provide a custom ascii decoder for applications needing a special character font. figure 3. four different techniques to interface the hdsp-2000 alphanumeric display to a microprocessor system * program + ascii lookup table ** scratchpad ram** rom* piso display refresh controller data, clock 5 columns interrupt request system clock data bus address bus microprocessor latch 500 hz clock an1016.03 * program + ascii lookup table ** scratchpad with or without decoded ascii lookup table ram** rom* ram ascii decoder mux display ram controller data clock, 5 columns data bus address bus microprocessor counter * program ** scratchpad system clock ram** rom* ram mux display decoder data controller data clock, 5 columns data bus address bus microprocessor counter ram** rom* *** piso display display processor controller data, clock data bus address bus microprocessor slave microprocessor 1/5 decoder 5 columns * program ** scratchpad *** ascii decoder for custom font
7 figure 4. 6800 or 8080a microprocessor interface to the hdsp-2000 refresh controller 1q 2q 3q 4q 5q 12 9 812345 v cc d in 10 11 10 11 d o v br c 1 ck c 2 hdsp-2000 c 3 c 4 c 5 12 7 9 812345 v cc d in v br c 1 ck c 2 hdsp-2000 c 3 c 4 c 5 7 5 120 w (typ) 10 12 15 cl ck 74174 mje700 (typ) 74165 74ls293 q h c a b f 9 d e g h si ci s/l ck 6 1 1 k 2.7 k (typ) 13 4 11 14 1d 4d 2d 3d 5d 9 9 2 6 11 74ls20 74ls00 3 74ls00 110 8 74ls00 220 k v cc ne 555 timer 500 hz astable multivibrator to interrupt request 2 1 6 7 8 4 3 5 0.01 m f 0.01 m f 9 10 11 5 12 a b r 01 13 r 02 q a v cc q b 4 q c 8 1 13 12 2 4 5 6 74ls20 1 2 4 5 q d d 0 d 1 data bus d 2 d 3 d 4 d 5 d 6 4 35 15 1 v cc pr 2 j ck k 74ls112 cl q 11 4 1 510 6 2 g 3 a g 2 g 1 b 3 c a 0 a 1 a 2 v cc mc3459 to 6800 1 k 22 w v cc f 2 f 2 mc3459 to 6800 vma a 12 a 13 a 15 8 74ls20 8080a 6800 12 12 74ls04 13 13 10 4 9 6 3 5 74ls04 a 3 8080 6800 i/o write 8080a f 2 a 4 a 14 1 k 22 w v cc f 1 f 1 4 74ls138 5 13 11 12 4 14 3 5 6 10 15 1 2 an1016.04
8 refresh controller the refresh controller circuit depicted in figure 4 oper- ates by interrupting the microprocessor every two milli- seconds to request a new block of display data and column select data. display data is loaded from the data bus into the serial input of the hdsp-2000 via a 74165 par- allel in, serial out shift register. the 74ls293 counter and associ- ated gates insure that only seven clock pulses are delivered to the shift register and the hdsp-2000 for each word loaded. column select data is loaded into a 74174 latch which, in turn, drives the column switch transistors. the circuit timing relative to the mi- croprocessor clock and i/o is depicted in figure 5. the 6800 software necessary to support this interface is divided into two separate subroutines, rfrsh and load (figure 6). this approach is desirable to minimize microprocessor involve- ment during display refresh. the subroutine rfrsh loads a new set of decoded display data from the microprocessor scratchpad memory into the interface at each interrupt request. the subroutine load is utilized to decode a string of 32 ascii characters into 5 x 7 formatted display data and store this data in the scratchpad memory used by rfrsh. figures 7 and 8 depict two differ- ent software routines for interfacing the refresh con- troller to an 8080a microprocessor. the two subrou- tines shown in figure 7 are functional replacements for the 6800 program shown in figure 6. the programs shown in figures 6 and 7 require a 5n byte scratchpad memory where n is the display length. the routine in figure 8 eliminates this scratchpad memory by decoding and loading data each time a new interrupt request is received. because the microprocessor sys- tem is interrupted every 2 ms, proper software design is espe- cially important for the refresh controller. the use of the scratchpad memory significantly reduces the time required to re- fresh the display. the fastest program, shown in figure 6, uses in-line code to access data from the buffer and output it to the dis- play. this program requires 3.7% + .50n% of the available micropro- cessor time for a 1 mhz clock. the program shown in figure 7 is similar to the one shown in figure 6, except that it uses a program figure 5. refresh controller timing an1016.05 hdsp 2000 data hdsp 2000 clock s/l 74165 data bus address bus f 1 f 2 s/l 74165 data bus address bus f 2 f 1 data entry timing row 6 row 5 row 4 row 3 row 2 row 1 row 7 6800 microprocessor timing 8080a microprocessor timing
9 loop instead of the in-line code. this program uses 5.4% + .93n% of the microprocessor time for a 2 mhz clock. these programs uti- lize a subroutine load which is called whenever the display mes- sage is changed. this subroutine executes in 10.2 ms and 7.5 ms respectively for figure 6 and fig- ure 7. the program in figure 8 uses 7.6% + 1.35n% of the micro- processor time for a 2 mhz clock. a 50% reduction in the previously described microprocessor times can be achieved by using faster versions of the 6800 and 8080a microprocessors. the ascii to 5 x 7 dot matrix de- coder used by the programs in figures 6, 7, and 8 is located within the microprocessor pro- gram. this decoder requires 640 bytes of storage to decode the 128 character ascii set. the decoder used by these controllers is for- matted so that the first 128 bytes contain column 1 information; the next 128 bytes contain column 2 information, etc. each byte of this decoder is formatted such that d 6 through d 0 contain row 7 through row 1 display data respectively. the data is coded so that a high bit will turn the corresponding 5 x 7 display dot on. this decoder table is shown in figure 9. the resulting 5 x 7 dot matrix display font is shown in the hdsp-2471 data sheet. decoded data controller the decoded data control- ler circuit schematic for a 32 character display is depicted in figure 10. the circuit is specifi- cally designed for interface to an 8080a microprocessor. this cir- cuit is designed to accept and store in local memory all of the display data for a 32 character hdsp-2000 display (1120 bits). the microprocessor loads 160 bytes of display data into the two 1 k x 1 rams via the 74165 paral- lel in, serial out shift register. each byte of data represents one column of display data. the counter string automatically gen- erates the proper address location for each serial bit of data after ini- tialization by mem w, the character address, and the desired column. once the loading is com- plete, the counter sequentially loads and displays each column (224 bits) of data at a 90 hz rate (2 mhz input clock rate). the tim- ing for this circuit is shown in figure 11. the software required to decode a 32 character ascii string is shown in figure 12. this program decodes the 32 ascii characters into 160 bytes of dis- play data which are then stored in the controller. the program re- quires about 6.6 ms, for a 2 mhz clock, to decode and load the message into the decoded data controller. this pro- gram also uses the same decoder table as shown in figure 9. coded data controller the coded data control- ler (figure 13) is designed to accept ascii coded data for stor- age in a local 128 x 8 ram. after the microprocessor has loaded the ram, local scanning circuitry controls the decoding of the ascii, the display data loading, and the column select function. with minor modification, the cir- cuit can be utilized for up to 128 display characters. the ram used in this circuit is an mcm6810p with the address and data inputs isolated via 74ls367 tri-state buff- ers. this allows the ram to be accessed either by the micropro- cessor or by the local electronics. the protocol is arranged such that the microprocessor always takes precedence over the local scan- ning electronics. the write cycle timing for the coded data controller is depicted in figure 14. this circuit, as with the decoded data control- ler, requires no microprocessor time once the local ram has been loaded with the desired data. the circuit shown in figure 13 shows a coded data con- troller designed for a 32 character hdsp-2000 alphanu- meric display. the key waveforms shown in figure 15, labeled ? , - , and ? , are shown to simplify the analysis of this circuit. label ? is the 1 mhz clock. label - is the output of 7404 pin 2 which is the inverted q d output of the 74197. label ? is the output of the 7404 pin 6 which is the anded output of 2q b , 2q c , and 2q d of the 74393. the motorola 6810 ram stores 32 bytes of ascii data which is continuously read, de- coded, and displayed. the ascii data from the ram is decoded by the motorola 6674 128 character ascii decoder. the 6674 decoder has five column outputs which are gated to the data input of the dis- play via a 74151 multiplexer. strobing of the display is accom- plished via the 74197, 74393, and 7490 counter string. the 74197 is connected as a divide by 8 counter that sequentially selects the seven rows within the 6674. as shown by waveform - , the 74197 also enables seven clock cycles to be gated to the clock in- put of the display. the 74393 is a divide by 256 counter connected so that the five lowest order out- puts select each of the 32 ascii characters within the ram. the three highest order outputs deter- mine the relationship between load time and column on time. when 2q b = 2q c = 2q d = 1 of the
10 object loc code source statements * * bf 05 cdvr equ $bf05 bl 04 rdvr equ $bf04 06 00 decdr equ $0600 0000 point rmb 2 0002 colmn rmb 1 0003 count rmb 2 0005 00 ad ascii fdb data 0007 dispnt rmb 2 0009 dcrpnt rmb 2 000b colcnt rmb 1 000c digcnt rmb 1 000d buffr rmb 160 00ad data rmb 32 0400 org $0400 0400 86 ff rfrsh lda a i, $ff 0402 b7 bf 05 sta a e, cdvr 0405 de 00 ldx d, point 0407 a6 00 loophh lda a x, 0 0409 b7 bf 04 sta a e, rdvr 040c a6 01 lda a x, i 040e b7 bf 04 sta a e, rdvr ? ? ? 04a2 a6 1f lda a x, 31 04a4 b7 bf 04 sta a e, rdvr 04a7 96 02 lda a d, colmn 04a9 b7 bf 05 sta a e, cdvr 04ac 81 ef cmp a i, $ef 04ae 27 10 beq loopb 04b0 d6 00 lda b d, point +1 04b2 cb 20 add b i, 32 04b4 d7 00 sta b d, point +1 04b6 24 03 bcc loopa 04b8 7c 00 00 inc e, point 04bb od loopa sec 04bc 79 00 02 rol e, colmn 04bf 3b rti 04c0 ce 00 od loopb ldx i, buffer 04c3 df 00 stx d, point 04c5 de 03 ldx d, count 04c7 09 dex 04c8 df 03 stx d, count 04ca 86 fe lda a i, $fe 04cc 97 02 sta a d, colmn 04ce 3b rti 04cf 5f load clr b 04d0 ce 00 od ldx i, buffr 04d3 df 07 stx d, dispnt 04d5 86 06 lda a i, 11 rfrsh return return cdvr ff h turn off column drivers rdvr (point) store first byte decoded data in 74165 load b 0 initialize column offset = 0 rdvr (point + 31) store 32nd byte decoded data in 74165 cdvr colmn turn on appropriate column driver column 2 colmn + 1 update colmn for next refresh cycle just refreshed column 5? rdvr (point + 1) store second byte decoded data in 74165 point point + 32 update point with address of decoded data for next column to be refreshed yes no (loop b) point buffer update point with address of column 1 in decoded data ram count count ? optional 2 ms timer colmn fe h update colmn to turn on column 1 return digcnt = 0? no yes (loop 3) colcnt 5 digcnt 32 digcnt digcnt ? dispnt buffer load dispnt with address of decoded data ram dcrpnt decdr load dcrpnt with address of decoder rom dcrpnt (ascii) + b + decdr access byte of decoded data from decoder dispnt (dcrpnt) store byte of decoded data in decoded data ram b b + 80 h add offset for next column in decoder rom yes ascii ascii + 32 initialize ascii with address of rightmost ascii symbol plus one colcnt = 0? no (loop 1) colcnt colcnt ? ascii ascii ? update ascii with address of next symbol to left dispnt dispnt + 1 update dispnt with address of next byte in decoded data ram figure 6. 6800 microprocessor program utilizing a 160 byte ram buffer that interfaces to the refresh controller (cont.)
12 object loc code source statements 0004 rdvr equ 0004h 0005 cdvr equ 0005h e500 decdr equ 0e500h org 0e000h e000 05 e0 point dw buffr e002 fe colmn db 0feh e003 ff ff count dw 0ffffh e005 00 buffr ds 160 org 0e0a5h e0a5 a7 e0 ascii dw data e0a7 00 data ds 32 org 0e400h e400 f5 rfrsh push psw e401 c5 push b e402 e5 push h e403 2a 00 e0 lhld point e406 06 20 mvi b, 32 e408 3e ff mvi a, 0ffh e40a d3 05 out cdvr f40c 7e loop mov a, m e40d d3 04 out rdvr e40f 23 inx h e410 05 dcr b e411 c2 0c e4 jnz loop e414 3a 02 e0 lda colmn e417 d3 05 out cdvr e419 fe ef cpi 0efh e41b ca 28 e4 jz first e41e 22 00 e0 shld point e421 07 rlc e422 32 02 e0 sta colmn e425 c3 3a e4 jmp end e428 21 05 e0 first lxi h, buffr e42b 22 00 e0 shld point e42e 3e fe mvi a, 0feh e430 32 02 e0 sta colmn e433 2a 03 e0 lhld count e436 2b dcx h e437 22 03 e0 shld count e43a el end pop h e43b cl pop b e43c f1 pop psw e43d c9 ret e43e 11 24 e0 load lxi d, buffr+31 e441 0e 20 mvi c, 32 e443 2a a5 e0 loop1 lhld ascii e446 7e mov a, m e447 23 inx h e448 22 a5 e0 shld ascii e44b 26 e5 mvi h, decdr/256 e44d 6f mov l, a e44e 06 05 mvi b, 5 e450 7e loop2 mov a, m e451 12 stax d e452 7d mov a, l e453 c6 80 adi 80h e455 6f mov l, a e456 d2 5a e4 jnc loop3 e459 24 inr h e45a 7b loop3 mov a, e e45b c6 20 adi 32 e45d 5f mov e, a e45e 05 dcr b e45f c2 50 e4 jnz loop2 e462 7b mov a, e e463 c6 5f adi 5fh e465 5f mov e, a e466 0d dcr c e467 c2 43 e4 jnz loop1 e46a c9 ret figure 7. 8080a microprocessor program utilizing a 160 byte ram buffer that interfaces to the refresh controller mcm6674 must be replaced by a faster bipolar prom. if this prom is programmed with the code listed in figure 17, it will de- code a character font identical to the mcm6674. this same propaga- tion delay problem is present with the mcm6810 ram. following worst case design procedures, the mcm68a10 1.5 mhz ram should be used. to accommodate the ad- ditional address line made necessary by the display length expansion, the two 74ls367 tri-state buffers have been re- placed with the 74ls244 octal version. strobing of the display is accomplished using the 74197, 74393, and 7490 counter string. the 74197 is connected as a di- vide by 8 counter that sequentially selects the seven rows within the 82s2708. the 74393 is a divide by 256 counter connected so that the seven lowest outputs select each of the 128 ascii characters within the ram. the previously unused input a/output q a of the 7490 has been used as an additional divide by 2 counter. thus, when the highest output of the 74393, 2q d , and the q a output of the 7490 are nanded through 7437, the basic relationship between load time and column on time is estab- lished. however, the external gating that has been added does affect the duty factor slightly. al- though these additional gates increase the total package count by one, they perform the neces- sary function of ensuring that the column drivers are turned off be- fore the clock is gated to the display. this prevents noise from being generated on the clock of the display and eliminates errone- ous display data. the resultant duty factor is (23/32) (1/5) or 14.4%. since the hdsp-2000 is rated at i col(max) = 410 ma and
13 figure 7. 8080a microprocessor program utilizing a 160 byte ram buffer that interfaces to the refresh controller (cont.) rfrsh return store machine status on stack cdvr ff h turn off column drivers load de buffer + 31 load de with address for column 1 rightmost character in decoded data ram point point + 1 update point with address of next byte cdvr colmn turn on appropriate column driver column 2 colmn + 1 update colmn for next refresh cycle just refreshed column 5? rdvr (point) store byte of decoded data in 74165 yes no (first) (end) point buffer update point with address of column 1 in decoded data ram count count ? optional 2 ms timer restore machine status from stack colmn fe h update colmn to turn on column 1 return b = 0? no yes (loop 2) b b ? a (ascii) read ascii symbol into a yes b 32 c 32 b b ? b = 0? no yes (loop) c = 0? no (loop 1) c c ? ascii ascii + 1 update ascii with address of next symbol to right b 5 hl decdr load hl with address of decoder rom hl hl + 80 h update hl with address of next column in decoder de de + 32 update de with address of next column in decoded data ram de de ?161 update de with address for column 1 of character in decoded data rom immediately to left of preceeding char. (de) a store byte of decoded data in decoded data ram a (hl + a) read byte of decoded data from decoder
14 figure 8. 8080a microprocessor program that decodes a 32 character ascii string prior to loading into the refresh controller object loc code source statements 0004 rdvr equ 0004h 0005 cdvr equ 0005h e500 decdr equ 0e500h org 0e000h e000 07 e0 ascii dw data e002 fe colmn db 0feh e003 ff ff count dw 0ffffh e005 00 e5 base dw decdr e007 00 data ds 32 org 0e400h e400 f5 rfrsh push psw e401 c5 push b e402 d5 push d e403 e5 push h e404 2a 05 e0 lhld base e407 eb xchg e408 2a 00 e0 lhld ascii e40b 01 1f 00 lxi b, 31 e40e 09 dad b e40f 43 mov b, e e410 0e 20 mvi c, 32 e412 3e ff mvi a, 0ffh e414 d3 05 out cdvr e416 78 loop mov a, b e417 86 add m e418 5f mov e, a e419 1a ldax d e41a d3 04 out rdvr e41c 2b dcx h e41d 0d dcr c e41e c2 16 e4 jnz loop e421 eb xchg e422 3a 02 e0 lda colmn e425 d3 05 out cdvr e427 fe ef cpi 0efh e429 ca 3b e4 jz first e42c 07 rlc e42d 32 02 e0 sta colmn e430 68 mov l, b e431 01 80 00 lxi b, 0080h e434 09 dad b e435 22 05 e0 shld base e438 c3 4d e4 jmp end e43b 3e fe first mvi a, 0feh e43d 32 02 e0 sta colmn e440 21 00 e5 lxi h, decdr e443 22 05 e0 shld base e446 2a 03 e0 lhld count e449 2b dcx h e44a 22 03 e0 shld count e44d e1 end pop h e44e d1 pop d e44f c1 pop b e450 f1 pop psw e451 c9 ret rfrsh store machine status on stack just refreshed column 5? yes no (first) de base load de with address next column to be decoded in decoder rom hl ascii + 31 load hl with address of rightmost ascii symbol cdvr ff h turn off column drivers a (hl) read ascii symbol into a a (de + a) read byte of decoded data from decoder rdvr a store byte of decoded data in 74165 hl hl ?1 update hl with address of next symbol to left c 32 c c ?1 cdvr colmn turn on appropriate column driver c = 0? no yes (loop) return (end) count count ? optional 2 ms counter restore machine status on stack base decdr update base with address of column 1 data in decoder rom colmn fe h update colmn to turn on column 1 base base + 80 h update base with address of next column in decoder rom column 2 colmn + 1 update colmn for next refresh cycle
15 decoder decoder address address hdsp-2471 for fig. for rom 7,8,12 fig.6 address hexidecimal data e500 0600 080 08 30 45 7d 7d 38 7e 30 60 1e 3e 62 40 08 38 41 column 1 090 10 18 5e 78 38 78 38 3c 38 3c 38 08 20 12 48 01 0a0 00 00 00 14 24 23 36 00 00 00 08 08 00 08 00 20 0b0 3e 00 62 22 18 27 3c 01 36 06 00 00 00 14 41 06 0c0 3e 7e 7f 3e 7f 7f 7f 3e 7f 00 20 7f 7f 7f 7f 3e 0d0 7f 3e 7f 26 01 3f 07 7f 63 03 61 00 02 41 04 40 0e0 00 38 7f 38 38 38 08 08 7f 00 20 00 00 78 7c 38 0f0 7c 18 00 48 04 3c 1c 3c 44 04 44 00 00 00 08 2a e580 0680 100 1c 48 29 09 09 44 01 4a 50 04 49 14 3c 7c 44 63 column 2 110 08 24 61 14 44 15 45 43 45 41 42 08 7e 19 7e 12 120 00 5f 03 7f 2a 13 49 0b 00 41 2a 08 58 08 30 10 130 51 42 51 41 14 45 4a 71 49 49 36 5b 08 14 22 01 140 41 09 49 41 41 49 09 41 08 41 40 08 40 02 04 41 150 09 41 09 49 01 40 18 20 14 04 51 00 04 41 02 40 160 07 44 48 44 44 54 7e 14 08 44 40 7f 41 04 08 44 170 14 24 7c 54 3e 40 20 40 28 48 64 08 00 41 04 55 e600 0700 180 3e 45 11 11 05 44 29 4d 48 04 49 08 20 04 44 55 column 3 190 78 7e 01 15 45 14 44 42 44 40 40 2a 02 15 49 7c la0 00 00 00 14 7f 08 56 07 3e 3e 1c 3e 38 08 30 08 lb0 49 7f 49 49 12 45 49 09 49 49 36 3b 14 14 14 51 lc0 5d 09 49 41 41 49 09 41 08 7f 40 14 40 0c 08 41 ld0 09 51 19 49 7f 40 60 18 08 78 49 7f 08 7f 7f 40 le0 0b 44 44 44 44 54 09 54 04 7d 44 10 7f 18 04 44 lf0 24 14 08 54 44 40 40 30 10 30 54 36 77 36 08 2a e680 0780 200 7f 40 29 21 05 38 2e 49 50 38 49 10 20 7c 3c 49 column 4 210 08 24 61 14 3c 15 3d 43 45 41 42 1c 02 12 41 12 220 00 00 03 7f 2a 64 20 00 41 00 2a 08 00 08 00 04 230 45 40 49 49 7f 45 49 05 49 29 00 00 22 14 08 09 240 55 09 49 41 41 49 09 51 08 41 40 22 40 02 10 41 250 09 21 29 49 01 40 18 20 14 04 45 41 10 00 02 40 260 00 3c 44 44 48 54 02 54 04 40 3d 28 40 04 04 44 270 24 7c 04 54 20 20 20 40 28 08 4c 41 00 08 10 55 e700 0800 280 00 30 45 7d 79 44 10 30 60 40 3e 60 1c 02 04 41 column 5 290 04 18 5e 78 40 78 40 3c 38 3c 38 08 02 00 42 01 2a0 00 00 00 14 12 62 50 00 00 00 08 08 00 08 00 02 2b0 3e 00 46 36 10 39 30 03 36 1e 00 00 41 14 00 06 2c0 1e 7e 36 22 3e 41 01 72 7f 00 3f 41 40 7f 7f 3e 2d0 06 5e 46 32 01 3f 07 7f 63 03 43 41 20 00 04 40 2e0 00 40 38 20 7f 08 00 3c 78 00 00 44 00 78 78 38 2f0 18 40 04 20 00 7c 1c 3c 44 04 44 00 00 00 08 2a figure 9. 128 character ascii decoder table used by the 6800 refresh program in figure 6. 8080a refresh programs in figures 7, 8, and 12, and the hdsp-2471 display processor controller. decoded 5x7 display font is shown in the hdsp-247x data sheet there are 32 modules of four digits each, the transistors must source up to 32 times 410 ma or approxi- mately 13 a. darlington pnp power transistors (2n6285) with the proper resistors have been used to accomplish this task. display processor controller the previously mentioned inter- face techniques provide only for the display of ascii coded data. such important features as a blinking cursor, editing routines, and character addressing must be provided by other subroutines in the microprocessor software. the display processor con- troller is a system which utilizes a dedicated 8048 single chip microprocessor to provide these important features. this controller, as depicted in figure 18, is a series of printed circuit board subsystems available from
16 figure 10. 8080a microprocessor interface to the hdsp-2000 decoded data controller an1016.10 mje 700 (typ) 1 2 3 4 0 11 74ls00 13 12 2 c 1 c 2 c 3 c 4 hdsp-2000 display (32 char) * c 5 1 d in 12 2345 ck 10 3 d out 12 130 130 130 130 130 v cc 2.7 k (typ) 4 5 1 74ls145 intel 2102a-4 15 12 14 13 a d b c 11 3 13 d in r/w ce 16 15 14 a 7 1 a 6 2 a 5 7 a 4 6 a 3 5 a 2 4 a 1 8 a 0 12 13 74ls04 11 10 74ls04 2 81 4 3 6 74ls04 5 8 74ls04 74ls00 f 2 (ttl) memw a 12 a 13 a 14 a 15 74ls27 9 9 10 74ls04 74ls00 a 8 a 9 2 l 9 1 cl 6 d 5 c 4 b 3 11 10 14 15 s c v cc 12 13 11 7 9 j k q q 4 s c v cc v cc 74ls112 74ls165 2 3 6 74ls27 4 5 2 4 5 12 6 1 2 3 13 1 1 35 j k 1 q 2 9 s/l 15 ci 10 si 11 a v cc 12 b 13 c 14 d 3 e 4 f 5 g 6 h q h 12 13 14 a q d 74ls162 et ep q c q b q a 2 l 9 1 cl 6 d v cc v cc 5 c 4 b 3 11 14 a q d 74ls162 et ep q a 2 l 9 1 cl 6 d 5 c 4 b 3 11 15 12 13 14 a q d a 3 a 4 a 5 a 6 a 7 a 0 a 1 a 2 d 6 d 5 d 4 d 3 d 2 d 1 d 0 74ls163 et ep q c q b q a 2 9 10 74ls27 11 l 9 1 cl 6 d 8 5 c 4 b 3 11 15 12 13 14 10 7 10 7 10 7 10 7 a q d rco rco 15 rco 74ls163 et v cc v cc v cc ep q c q b q a d out 12 intel 2102a-4 11 3 13 d in r/w ce 16 15 14 a 7 1 a 6 2 a 5 7 a 4 6 a 3 5 a 2 4 a 1 8 a 0 a 8 a 9 data bus address bus note: address bus decoding a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 00000 rightmost character location 11111 leftmost character location 0 0 0 column 1 0 0 1 column 2 0 1 0 column 3 0 1 1 column 4 1 0 0 column 5
17 agilent technologies under the following part numbers: hdsp-2470 C controller with 64 character ascii to 5 x 7 decoder hdsp-2471 C controller with 128 character universal ascii to 5 x 7 decoder hdsp-2472 C controller with socket for user supplied custom coded rom/prom/ eprom. all of the controllers have the following features: ? choice of character string length: 4 to 48 characters in increments of four characters ? four modes of data entry left entry right entry ram entry ( 32 characters only) block entry ? flashing cursor C left entry only ? data out ( 32 characters only) edit functions clear display backspace cursor forward cursor insert delete right entry left entry these controllers have been de- signed to eliminate the burden of data handling between keyboard, display, and microprocessor. the product data sheet describes the technical function of the control- lers in detail. interfacing the controller to mi- croprocessor systems depends on the needs of the particular appli- cation. figure 19 depicts a latched interface from a master micropro- cessor to the hdsp-247x series of controllers. these interfaces are utilized to avoid having the master processor wait for the controller to accept data. in sophisticated systems, it may be desirable to have the hdsp-247x controller handle all of the keyboard/display interface while the microprocessor reads edited messages from the control- ler data out port. this function can be achieved through the use of peripheral interface adapters (pia) available from the micro- processor manufacturers. figure 20 depicts a 6800 based system in which data may enter the display from either a keyboard or a microprocessor. this interface uses a 6821 pia configured so that pb 7 controls whether the micro- processor or keyboard enters data into the controller. the 6800 pro- gram is shown in figure 21. subroutine load uses ca 1 and ca 2 to provide a data entry hand- shake that allows the 6800 to load data into the controller as fast as the controller can accept it. after the prompting message has been loaded, the microprocessor turns the control of data entry over to the keyboard. a signal from the keyboard (er in the example) sets a flag within the 6821. depending on how the 6821 is configured, the microprocessor figure 11. data entry timing for decoded data controller an1016.11 address bus decoding: a 2 a 1 a 0 a 7 a 6 a 5 a 4 a 3 000col1 00000 rightmost character 001col2 11111 leftmost character 0 1 0 col 3 0 1 1 col 4 1 0 0 col 5 ram write ram address 74165 clock data out 74165, ram data in memwr data bus address bus f 2 f 1 addr = a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 (001)(addr) (010)(addr) row 7 row 6 (011)(addr) row 5 (100)(addr) row 4 (101)(addr) row 3 (110)(addr) row 2 (111)(addr) row 1
18 figure 12. 8080a microprocessor program that decodes a 32 character ascii string prior to loading into the decoded data controller object loc code source statements b000 displ equ 0b000h e500 decdr equ 0e500h org 0e000h e000 02 e0 ascii dw data e002 00 data ds 32 org 0e400h e400 11 f8 b0 load lxi d, displ+00f8h e403 0e 20 mvi c, 32 e405 2a 00 e0 loop1 lhld ascii e408 7e mov a, m e409 23 inx h e40a 22 00 e0 shld ascii e40d 26 e5 mvi h, decdr/256 e40f 6f mov l, a e410 06 05 mvi b, 5 e412 7e loop2 mov a, m e413 12 stax d e414 13 inx d e415 7d mov a, l e416 c6 80 adi 80h e418 6f mov l, a e419 d2 1d e4 jnc l00p3 e41c 24 inr h e41d 05 l00p3 dcr b e41e c2 12 e4 jnz l00p2 e421 7b mov a, e e422 d6 0d sui 13 e424 5f mov e, a e425 0d dcr c e426 c2 05 e4 jnz loop1 e429 c9 ret load de disl + f8 h load de with address of display corresponding to column 1 leftmost character hl ascii load hl with address of leftmost ascii symbol a (hl) read byte of decoded data from decoder rom a (hl) read ascii symbol into a ascii ascii + 1 update ascii with address of next ascii symbol de de + 1 update de with address of next column in display hl hl + 80 h update hl with address of next column in decoder rom (de) a store byte of decoded data in display c 32 hl decdr + a load hl with address of decoder rom corresponding to column 1 of desired ascii symbol de de ?13 update de with address of display corresponding to column 1 next character to right b 5 b b ?1 b = 0? no yes (loop 2) c c ?1 c = 0? no yes (loop 1) return
19 figure 13. 8080a microprocessor interface to the 32 character hdsp-2000 coded data controller an1016.13 mje 210 (typ) 0 1 2 3 4 10 8 7410 11 9 1 12 7410 2 13 5 6 7410 4 3 1 c1 c2 c3 c4 hdsp-2000 display (32 char) * c5 1 di 12 2345 ck 10 2 39 w 39 w 39 w 39 w 39 w v cc mr750 10 k (typ) 3 4 5 1 2 3 5 6 7404 6 7 74145 15 12 14 13 a y 5 74151 4 d 0 3 d 1 2 d 2 1 d 3 15 d 4 7 12 13 14 15 16 st abc 11 10 9 d b c b r 0 r 0 r 9 r 9 7490 q b q c q d 9 8 11 11 13 12 9 8 j s s k q q 35 f (note 1) 2 1 410 j k q 74ls113 7 1 wr cs 2 3 74s32 8080a, 6800 interface: z 80 interface: a 0 6 a 1 5 a 2 4 a 3 3 a 4 2 a 5 1 2 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 12 11 1 4 3 7404 2 1 7404 15 a 6 11 rs 1 10 13 v cc 10 rs 2 8 rs 3 mcm6674 d 0 d 1 d 2 d 3 d 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 r/w 119753 12 10 6 4 2 5a 4a 3a 74ls367 2a 1a cs cs cs cs d 0 d 1 d 2 d 3 d 4 d 5 d 6 cs cs mcm6610 13 11 9 7 5 3 14 12 10 6 4 2 6a 5a 4a 3a 2a 1a 115 6y 5y 4y 3y 2y 1y 74ls367 3 4 5 6 11 10 9 1 2 13 12 1a cl 2a cl 1q a 1q b 1q c 1q d 2q a 2q b 2q c 8 2q d 74393 5 6 9 10 2 11 12 8 4 3 13 a a v cc 1 mhz clock input c clear q a b q b b q c d q d 1 c/l 74197 13 11 9 7 5 3 14 12 10 6 4 2 6a 5a 4a 3a 2a 1a d 6 d 5 d 4 d 3 d 2 d 1 d 0 115 6y 5y 4y 3y 2y 1y 74ls367 data bus a 0 a 1 a 2 a 3 a 4 a b c b a a b c address bus cs (note 2) note 1: f is microprocessor clock note 2: cs is iorq anded with the i/o address of the display * display is operated with pin 1 in the upper right hand corner
20 can either test the flag or allow the flag to automatically interrupt the microprocessor. subroutine read would then be used to read the data out outputs from the controller into the micropro- cessor system. the microprocessor uses the cb 1 input of the 6821 pia to determine when to read each of the 34 data output words into the system. a similar pia interface for the 8080a microprocessor is depicted in figures 22 and 23. the hdsp-247x series of control- lers are programmed to default to left entry mode for a 32 charac- ter string of displays. if some other entry mode or string length is desired, it is necessary to either load the appropriate control word from the microprocessor or to provide a control word during power on reset. the control- ler will read the data in lines during reset and interpret the contents as the control word. the circuit depicted in figure 24 can be utilized to load any desired preprogrammed word into the hdsp247x controller, during power on. figure 14. memory write timing for the 32 character hdsp-2000 coded data controller figure 15. timing information for the 32 character hdsp-2000 coded data controller an1016.14 f (z-80 interface only) wr (6800 or 8080a interface) data chip select address parameter symbol min. write cycle t wc 390 ns write delay t aw 65 ns chip enable to write t cw 65 ns data setup t dw 220 ns data hold t dh 20 ns write pulse t wp 310 ns write recovery t wr 10 ns chip enable hold t ch 20 ns t wc t cw t ch t dh t aw t dw t wp t wr an1016.15 display clock character 1 characters 2?2 224 clock cycles 224 clock cycles row 2 row 1 row 3 row 4 row 5 row6 row 7 row 1 row 2 row 3 row 4 row 6 row 7 columns on columns on 1 0 23456 0 columns off (load) columns off (load) columns off (load) 123 5 46 4 3 2 1
21 figure 16. 6800, 8080a, and z-80 interface to the 128 character hdsp-2000 coded data controller an1016.16 note 1: f is microprocessor clock note 2: cs is iorq anded with the i/o address of the display 2n6285 (typ) 0 1 2 3 4 11 7437 7490 4 6 7437 5 9 8 7437 10 9 10 3 7437 1 2 1 c1 c2 c3 c4 hdsp-2000 display (128 char) * c5 1 di 12 v b 8 2345 ck 10 2 36 w 36 w 36 w 36 w 36 w v cc 100 w (typ) 3 4 5 1 2 3 5 6 7404 6 7 74145 15 12 14 13 a y 5 74151 4 d 0 3 d 1 2 d 2 1 d 3 15 d 4 7 9 10 11 13 14 st 20 ce abc 11 10 9 d b c b 14 a r 0 r 0 r 9 r 9 10 v cc q b q c q d 9 q a 12 5 8 11 11 13 12 9 8 j s s k q q 35 f (note 1) 2 410 j k q 74ls113 8 1 wr cs 2 3 74s32 8080a, 6800 interface: z 80 interface: a 0 7 a 1 6 a 2 5 a 3 4 a 4 3 a 5 2 2 24 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 12 11 1 4 3 7404 2 1 7404 19 a 6 1 a 7 23 13 v cc 10 a 8 22 a 9 82s2708 d 0 d 1 d 2 d 3 d 4 a 0 a 1 a 2 a 3 a 4 a 5 a 6 r/w 18 3 16 5 14 2 17 4 15 6 1a1 2a4 1a2 74ls244 2a3 1a3 7 13 2a2 2y4 2y3 2y2 12 8 1a4 1y1 1y2 1y3 1y4 cs cs cs cs d 0 d 1 d 2 d 3 d 4 d 5 d 6 cs cs v cc mcm68a10 18 3 16 5 14 7 2 17 4 15 6 13 1a1 2a4 1a2 2a3 1a3 119 1y1 2y4 1y2 2y3 1y3 2a2 2y2 74ls244 3 4 5 6 11 10 9 1 2 13 12 1a cl 2a cl 1q a 1q b 1q c 1q d 2q a 2q b 2q c 8 2q d 74393 5 6 9 10 2 11 12 8 4 3 13 a a v cc 2 mhz clock input c clear q a b q b b q c d q d 1 c/l 74197 13 11 9 7 5 3 14 12 10 6 4 2 6a 5a 4a 3a 2a 1a d 6 d 5 d 4 d 3 d 2 d 1 d 0 115 6y 5y 4y 3y 2y 1y 74ls367 data bus a 0 a 1 a 2 a 3 a 4 12 8 1a4 1y4 a 5 9 11 2a1 2y1 a 6 a b c b a a b c address bus cs (note 2) * display is operated with pin 1 in the upper right hand corner 6 7440 1 2 4 5 8 7440 13 12 10 9
22 display power dissipation the hdsp-2000 combines a sig- nificant amount of logic and display capability in a very small package. as such, on-board power dissipation is relatively high and thermal design of the display mounting becomes an important consideration. the hdsp-2000 is designed to permit operation over a wide range of temperature and supply voltages. the design of a heat sink to maintain a junction temperature of less than 125 c for a multiple package system where every electrical input oper- ates at maximum voltage and current would be difficult at best. however, in virtually all applica- tions, the actual power dissipation is only a small fraction of the maximum power dissipation, since v col is less than 5.25 v, only a fraction of the 35 leds are on at any time, and the duty factor is never 20%. the calculation of power dissipation is important since the result is largely a func- tion of external circuit parameters. the minimization of power dissipation will reduce the amount of heat sinking required for the displays. furthermore, by the arrhenius model, the display reliability is increased by 40% for a 10 c reduction in junction tem- perature. thus, reduced power dissipation or better heat sinking can also increase the reliability of the display system. calculation of power dissipation in the hdsp-2000 display family can be made using the following formulas: p d = p(i cc ) + p(i ref ) + p(i col ) (7) where p(i cc ) = i cc1 v cc (8) 200 f1 f0 e4 e1 ef f5 f4 ff e9 ff ff f5 e4 ff f5 f5 row 4 210 ff f7 f7 f0 fd f5 ea ff e4 ee e8 ff fd fd f7 f7 220 e0 e4 e0 ea ee e4 e8 f0 e8 e2 ff ff ec ff e0 e4 prom 230 f5 e4 ee e6 f2 e1 fe e4 ee ef e0 ec f0 e0 e1 e2 address 240 ed f1 ee f0 e9 fc fc f3 ff e4 e1 f8 f0 f5 f3 f1 250 fe f1 fe ee e4 f1 ea f1 e4 e4 e4 e8 e4 e2 e0 e0 260 e2 e1 f9 f1 f3 f1 ee ed f9 e4 e1 f4 e4 f5 f9 f1 270 f9 f3 f9 f0 e4 f1 f1 f1 ea ef e2 e8 e0 e2 e0 f5 080 ff ff e4 e1 e8 ff e0 ee e4 e0 ff e0 e4 e0 ee ee row 1 280 f1 f0 e4 e1 e4 fb f8 ea e5 e2 e0 ee f5 e8 fb f1 row 5 090 ff ee ee ee ee e0 ee e1 ff e4 ee ee ff ff ff ff 290 f1 f1 f5 f5 f1 f8 ea e1 ea e4 e4 f1 f1 f5 f5 f1 0a0 e0 e4 ea ea e4 f8 e8 ec e2 e8 e4 e0 e0 e0 e0 e0 2a0 e0 e4 e0 ff e5 e8 f5 e0 e8 e2 ee e4 ec e0 e0 e8 0b0 ee e4 ee ee e2 ff e6 ff ee ee e0 ec e2 e0 e8 ee 2b0 f9 e4 f0 e1 ff e1 f1 e8 f1 e1 ec ec e8 ff e2 e4 0c0 ee e4 fe ee fe ff ff ef f1 ee e1 f1 f0 f1 f1 ee 2c0 f5 ff e9 f0 e9 f0 f0 f1 f1 e4 e1 f4 f0 f1 f1 f1 0d0 fe ee fe ee ff f1 f1 f1 f1 f1 ff ee e0 ee e4 e0 2d0 f0 f5 f4 e1 e4 f1 ea f5 ea e4 e8 e8 e2 e2 e0 e0 0e0 e6 e0 f0 e0 e1 e0 e2 ed f0 e4 e1 f0 ec e0 e0 e0 2e0 e0 ef f1 f0 f1 ff e4 e1 f1 e4 e1 f8 e4 f5 f1 f1 0f0 f6 ed e0 e0 e4 e0 e0 e0 e0 f1 e0 e2 e4 e8 e8 ea 2f0 f6 ed f0 ee e4 f1 f1 f5 e4 e1 e4 e4 e4 e4 e0 ea 100 f1 f0 e4 e1 e4 f1 e1 f1 e8 e4 e0 e4 f5 e4 f1 f1 row 2 300 f1 f0 e4 e1 e2 f1 f0 ea e1 e4 e0 e4 ee e4 f1 f1 row 6 110 f1 f5 f1 f1 f5 e5 ea e1 f1 e4 f1 f1 f5 f1 f1 f5 310 f1 f1 f5 f5 f1 f0 ea e1 f1 e4 e0 f1 f1 f5 f5 f1 120 e0 e4 ea ea ef f9 f4 ec e4 e4 f5 e4 e0 e0 e0 e1 320 e0 e0 e0 ea fe f3 f2 e0 e4 e4 f5 e4 e8 e0 ec f0 130 f1 ec f1 f1 e6 f0 e8 e1 f1 f1 ec ec e4 e0 e4 f1 330 f1 e4 f0 f1 e2 f1 f1 f0 f1 e2 ec e8 e4 e0 e4 e0 140 f1 ea e9 f1 e9 f0 f0 f0 f1 e4 e1 f2 f0 fb f9 f1 340 f5 f1 e9 f1 e9 f0 f0 f1 f1 e4 f1 f2 f0 f1 f1 f1 150 f1 f1 f1 f1 e4 f1 f1 f1 f f1 e1 e8 f0 e2 ea e0 350 f0 f2 f2 f1 e4 f1 e4 fb f1 e4 f0 e8 e1 e2 e0 e0 160 e6 e0 f0 e0 e1 e0 e5 f3 f0 e0 e0 f0 e4 e0 e0 e0 360 e0 f1 f9 f1 f3 f0 e4 f1 f1 e4 f1 f4 e4 f5 f1 f1 170 f9 f3 e0 e0 e4 e0 e0 e0 e0 f1 e0 e4 e4 e4 f5 f5 370 f0 e1 f0 e1 e5 f3 ea f5 ea f1 e8 e4 e4 e4 e0 f5 180 f1 f0 e4 e1 e2 fb e2 f1 fe e2 e0 e4 ee e8 fb f1 row 3 380 ff f0 ff ff e1 ff e0 fb e1 e0 ff e0 e4 e0 ee ee row 7 190 f1 f5 f1 f1 f5 e2 ea e1 ea ee f0 f1 f5 f1 f1 f5 390 ff ee ee ee ee e0 fb e1 ff e4 e4 ee ff ff ff ff 1a0 e0 e4 ea ff f4 e2 f4 e8 e8 e2 ee e4 e0 e0 e0 e2 3a0 e0 e4 e0 ea e4 e3 ed e0 e2 e8 e4 e0 f0 e0 ec e0 1b0 f3 e4 e1 e1 ea fe f0 e2 f1 f1 ec e0 e8 ff e2 e1 3b0 ee ee ff ee e2 ee ee f0 ee ec e0 f0 e2 e0 e8 e4 1c0 e1 f1 e9 f0 e9 f0 f0 f0 f1 e4 e1 f4 f0 f5 f5 f1 3c0 ee f1 fe ee fe ff f0 ef f1 ee ee f1 ff f1 f1 ee 1d0 f1 f1 f1 f0 e4 f1 f1 f1 ea ea e2 e8 e8 e2 f1 e0 3d0 f0 ed f1 ee e4 ee e4 f1 f1 e4 ff ee e0 ee e0 ff 1e0 e4 ee f6 ee ed ee e4 f3 f6 ec e1 f2 e4 fa f6 ee 3e0 e0 ef f6 ee ed ee e4 ee f1 ee ee f2 ee f5 f1 ee 1f0 f1 f1 f6 ef ff f1 f1 f1 f1 f1 ff e4 e4 e4 e2 ea 3f0 f0 e1 f0 fe e2 ed e4 ea f1 ee ff e2 e4 e8 e0 ea hexidecimal data figure 17. 82s2708 prom listing when v cc is applied continuously to the display p(i cc ) = i cc1 v cc (t + t)/ (t + t + t b ) (9) when v cc is turned off during the time t b where p(i ref ) = (i cc2 C i cc1 ) v cc (n/35) (10) when v b is connected to v cc and v cc is applied continuously to display p(i ref ) = 5 (i cc2 C i cc1 ) v cc (n/35) d.f. (11) when v b is logical 0 during times t and t b where p(i col ) = 5 i col v col (n/35) d.f. (12)
23 where n = average number of diodes illuminated per character d.f. = column on time from equation (1) or (5) i cc1 = i cc (v b = 0.4 v) i cc2 = i cc (v b = 2.4 v) p(i cc ) is the power which is dissi- pated in the logic within the shift register. p(i cc ) is constant regard- less of n, or d.f. as long as voltage is applied to the v cc pin. however, for low d.f., i cc can be switched off during the time the display is blanked. p(i ref ) is the power dissipated in the logic to drive the current mirror output. thus, if the output of the shift reg- ister and the v b input are both logical 1, p(i ref ) will be dissi- pated. p(i col ) is the power dissipated within the leds and the constant current outputs dur- ing the time that v col is applied and the leds are on. as can be seen from formulas (7) through (12) there are several techniques by which total power dissipation can be reduced: ? reduce n ? reduce v col ? reduce d. f. ? reduce v cc ? turn off v cc when display is blanked for most applications, n 20 dots. for example, the hdsp-2470 character generator has 3 charac- ters with 20 dots on (#, @, b), 1 character with 19 dots on (zero), and 6 characters with 18 dots on (a,d,e,m,r,w). with custom prom programming these 4 sym- bols (#, @, b, zero) can be modified to reduce the total num- ber of dots on to 18 or less. the average of all 36 alphabetic and numeric symbols is 14.7 dots on. the calculations assume that ev- ery character has the same number of illuminated dots. this assumption can overstate the maximum power dissipation if the application includes a fixed num- ber of spaces in the display. above 2.4 v v col for standard red devices and 2.75 v v col for gap devices, i col is nearly constant. while it is possible to operate the columns of the hdsp-2000 display using fullwave rectified unregu- lated dc, lower power dissipation can be achieved by using the regu- lated v cc supply. then, v col is equal to v cc minus the collector to emitter saturation voltage across the column switching tran- sistors. since the minimum recommended v col is 2.4 v or 2.75 v, pnp darlington transistors with a silicon diode in series with the emitter can be used to lower the power dissipation within the display. the time averaged luminous in- tensity for the display is equal to the peak luminous intensity on the data sheet times d.f. thus, reduction in d.f. will also reduce the time averaged luminous inten- sity as well as power dissipation. for most indoor applications, a d.f. of 10% for standard red and 5% for gap displays will provide satisfactory luminous intensity. for example, the 40 character hdsp-2470 system has a d.f. of 11.6%. however, a d.f. of 17% or higher is recommended for sun- light viewable applications for the gap displays. the hdsp-2000 family of alphanu- meric displays are specified for operation with a 5% tolerance 5 volt supply. a tighter tolerance supply will also reduce the power dissipation in the display. i cc can be switched off during the time the display is blanked. thus, power would be applied to the display; the shift register would be loaded with information; the columns would be turned on; and then the column current, v b , and v cc would be switched off until the next column refresh cycle. for low d.f., this can significantly reduce the power dissipation within the display. as d.f. in- creases, the display is blanked for a smaller portion of the refresh cycle and the power reduction is reduced. when the blanking time goes to zero, the power reduction also goes to zero. for example, the maximum power dissipation for a four char- acter hdsp-2000 display (n = 20, v col = 3.5 v, v b = 2.4 v, d.f. = 17.5%, v cc = 5.25 v) can be calcu- lated as shown below: p(i cc ) = (60 ma) (5.25 v) = 315 mw (13) p(i ref ) = 5 (95 ma C 60 ma) (5.25 v) (20/35) (0.175) = 92 mw (14) p(i col ) = 5 (410 ma) (3.5 v) (20/35) (0.175) = 718 mw (15) p d = p(i cc ) + p(i ref ) + p(i col ) = 1125 mw (16)
24 figure 18. hdsp-2470/-2471/-2472 display processor controller an1016.18 tip 105 (typ) 5 4 3 2 1 6 74ls37 74 ls37 4 1 2 3 5 11 74ls37 12 13 8 (22) 74ls37 9 10 6 5 (typ) 36 w v cc (h) (i) (f) (g) (d) (e) (b) (c) (j) column 4 (a) v b , display blank column 3 v cc column 2 column 1 column 5 (m) display data (l) clock (k) (o) (s) v cc v cc (n) (q) (t) g nd (r) (p) 100 w (typ) 4 3 2 74ls145 13 12 876543212322 9 10111314151618192120 gnd vcc a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 cs d 6 d 5 d 4 d 3 d 2 d 1 d 0 14 15 hdsp-2470 hdsp- 2471/2 hdsp-2471/2 hdsp-2470 hdsp- 2470 hdsp- 2471/2 mcm 68308 or equiv c 1 s/l b a 6 h 5 g 4 f 3 e 14 d 13 c 12 b 29 clk q h 15 ci 74ls165 data in ram address 0 1 1 k hdsp- 2470 hdsp- 2471/2 bus 6 18 26 40 bus 5 17 bus 4 16 bus 3 xtal 1 v dd v cc v cc xtal 2 6 mhz 1 k 1 m f 20 pf 20 pf 15 2 3 reset reset 4 (6) ea 7 + bus 2 14 bus 1 13 bus 0 12 p 27 38 p 26 37 p 25 36 wr 10 ale 11 bus 7 p 17 v ss intel 8048 19 20 34 irq chip select ready 6 (1) p 10 di 0 27 (11) (26) (24) (2) (20) (18) (16) (14) (12) (10) (8) p 11 di 1 28 (13) p 12 di 2 29 (15) p 13 di 3 30 (17) p 14 di 4 31 (19) p 15 di 5 32 (21) p 16 di 6 33 (23) t 0 di 7 data out data valid column on v b , display blank do 0 do 1 do 2 do 3 do 4 do 5 do 6 1 (7) p 20 21 (3) p 21 a 1 a 0 22 (5) p 22 a 2 23 (7) p 23 a 3 24 (9) p 24 a 4 35 (25) t 1 39 v cc
25 figure 19. latched interface to the hdsp-2470/-2471/-2472 display processor controller an1016.19 cs* vma 2 cs* 3 4 6 5 a 4 a 3 a 2 14 13 11 a 1 a 0 a 4 a 3 a 2 a 1 a 0 6 4 v cc 3 15 12 10 7 5 2 (25) (9) (7) (5) (3) ready hdsp 12470/1/2 (22) cs (1) 9 6d 5d 4d 3d 2d 1d 6q 74ls10 configuration a configuration b 74ls273 only required for ram mode left, right or block modes 5q 4q 3q 2q 1q cl 1 wr 8080a interface 74ls10 6800 interface 74ls10 1 2 12 13 74ls10 1 a b 2 12 13 74ls10 9 10 8 11 74ls10 address bus d 6 d 5 d 4 17 14 13 d 3 d 2 di 6 di 5 di 4 di 3 di 2 8 7 d 1 d 0 4 16 15 12 9 6 5 (23) (21) (19) (17) (15) di 1 di 0 (13) (11) 3 7d 6d 5d 4d 3d 2d 1d 7q d 7 18 di 7 19 (4) bd 8q v cc 1 cl 6q 5q 4q 3q 2q 2 1q cl 11 data bus *cs is a logical combination of high order address bits that distinguish the address of the hdsp-2470/1/2 from the rest of the microprocessor system.
26 figure 20. 6800 microprocessor interface utilizing a 6820 pia for an hdsp-2470/-2471/-2472 alphanumeric terminal an1016.20 5 2 13 di 7 di 6 di 5 di 4 10 6 3 12 9 7 4 4 data valid hdsp- 2470/71/72 display processor controller b column 1 c b a v b a c hdsp- 2416/24/32/40 display* 2 23 21 19 1 2a 11 1a 4b 3b 2b 1b sel st 3a 14 4a 74ls157 4y 3y 2y 1y 15 5 2 13 di 3 di 2 di 1 di 0 10 6 3 12 9 7 4 17 15 13 11 ready 22 cs 1 6 3 74ls132 4 1 2 5 1 2a 11 1a 4b 3b 2b 1b sel st 3a 14 4a 74ls157 4y 3y 2y 1y 15 3 v cc 4 1 6 13 11 7 2 b 1 b 2 a 1 a 2 cl 1000 pf 74ls122 motorola 6821 + v cc 1 k 20 m f 9 74ls132 10 er d 6 d 5 d 4 d 3 microswitch 61sw12-1 keyboard d 2 d 1 d 0 st 22 k q 5 1000 pf do 0 20 do 1 18 do 2 16 do 3 14 do 4 12 do 5 10 do 6 8 reset 6 *16, 24, 32 or 40 character hdsp-2000 display board designed to interface to the hdsp- 2470/71/72 display processor controller d column 2 e d e f column 3 g f g h column 4 i h i j column 5 k j l clock l k n v cc o n o p gnd q p q m display data m 16 pb 6 15 pb 5 14 pb 4 13 pb 3 12 pb 2 11 pb 1 10 26 d 7 27 d 6 28 d 5 29 d 4 d 3 30 d 2 31 d 1 32 d 0 33 cs 0 22 cs 1 24 cs 2 23 rs 0 36 rs 1 35 r/w 21 e f 2 25 reset 34 irq b 37 pb 0 18 cb 1 9 pa 7 8 pa 6 7 pa 5 6 pa 4 5 pa 3 4 pa 2 3 pa 1 2 pa 0 40 ca 1 39 ca 2 19 8 cb 2 17 pb 7 vma-a 15 a 3 a 13 a 0 a 1 r/w reset irq data bus
27 * port configuration: * 1. port a: pa0-pa7 outputs to data in of hdsp-247x * ca1 (input) mode 00 set flag neg edge of ready * ca2 (output) mode 100 cleared mpu read pra, set * neg edge of ready * 1. port b: * pb0-pb6 inputs data to 6800 from data out of hdsp-247x * cb1 (input) mode 00 sets flag neg edge of data valid * cb2 (input) mode 000 sets flag neg edge of er key * cb2 (input) mode 001 sets flag neg edge of er key causing irq * pb7 (output) low enables pa0-pa7 to mux * high enables keyboard to mux loc object code source statement 8008 pra equ $8008 8008 dra equ $8008 8009 cra equ $8009 800a prb equ $800a 800a drb equ $800a 800b crb equ $800b org $0000 0000 message rmb 2 org $0100 0100 status rmb 1 0101 cursor rmb 1 0102 data rmb 32 org $0400 0400 ce 0100 read ldx i, status 0403 b6 800a loop1 lda a e, prb clear cb1 and cb2 0406 5f clr b 0407 5c loop2 inc b 0408 b6 800b lda a e, crb 040b 2a fa bpl loop2 wait for data valid 040d c1 0a cmp b i, 10 040f 23 f2 hls loop1 0411 c6 21 lda b i, 33 0413 b6 800a loop3 lda a e, prb read and clear cb1 0416 84 7f and a i, $7f 0418 a7 00 sta a x, 0 store in ram 041a b6 800b loop4 lda a e, crb 041d 2a fb bpl loop4 wait for data valid 041f 08 inx 0420 5a dec b 0421 26 f0 bne loop3 read data 0423 b6 800a lda a e, prb 0426 84 7f and a i, $7f 0428 a7 00 sta a x, 0 042a 39 rts 042b de 00 load ldx d, messge 042d a6 00 loop10 lda a x, 0 042f 08 inx 0430 81 ff cmp a i, $ff last word in string 0432 27 0d beq endl jump when done 0434 b7 8008 sta a e, pra 0437 7d 8008 tst e, pra clear ca1 and ca2 043a b6 8009 loop11 lda a e, cra 043d 2a fb bpl loop11 wait 043f 20 ec bra loop10 0441 df 00 endl stx d, messge 0443 39 rts org $0500 0500 7f 8009 start clr e, cra 0503 7f 800b clr e, crb 0506 86 ff lda a i, $ff 0508 b7 8008 sta a e, dra 050b 86 24 lda a i, $24 050d b7 8009 sta a e, cra 0510 86 80 lda a i, $80 0512 b7 800a sta a e, drb 0515 86 04 lda a i, $04 0517 b7 800b sta a e, crb * procedure to load hdsp-247x system 051a oe cli 051b 7f 800a clr e, prb disable keybd from mux 051e bd 042b jsr e, load * procedure to read data out of hdsp-247x system 0521 7d 800a tst e, prb clear cb1, cb2 0524 86 80 lda a i, $80 0526 b7 800a sta a e, prb enable keybd to mux 0529 86 0c lda a i, $0c 042b b7 800b sta a e, crb enable irq, 052e 0f sei irq cause jsr to read figure 21. 6800 microprocessor program that interfaces to the circuit shown in figure 14. read return x address of status point to address of data destination load x message point to first ascii character message x store address of next character string a (x) read ascii character a 7 cb1 flag set on negative edge of data valid a 7 prb ?7f h read data out word a prb ?7f h read data out word (x) a store data out word b 0 b b + 1 force ca2 low; clear cb1 flag clear interrupt request from irqb a 7 ca1 flag set on negative edge of ready a 7 cb1 flag set on negative edge of data valid b = 33 cb1 flag cleared? yes wait for data valid wait for next display data output cycle no (loop 2) cb1 flag cleared? yes yes (endl) wait for data valid (loop 4) last character? denoted by ff h no no not done (loop 10) no x x + 1 no x x + 1 b b ?1 (x) a store data out word pra a output data word to display force ca2 low clear ca1 flag return b 10 yes (loop 1) read next data out word yes b = 0? no (loop 3) wait for ready ca1 flag cleared? yes (loop 11)
28 figure 22. 8080a microprocessor interface utilizing an 8255 pia for an hdsp-2470/-2471/-2472 alphanumeric terminal similarly, a typical power dissipa- tion for a four character hdsp-2000 display (n = 15, v col = 3.0 v, d.f. = 17.5%, v cc = 5.00 v) can be calculated as: p(i cc ) = (45 ma) (5.00 v) = 225 mw (17) p(i ref ) = 5 (73 ma C 45 ma) (5.00 v) (15/35) (0.175) = 52 mw (18) p(i col ) = 5 (335 ma) (3.0 v) (15/35) (0.175) = 377 mw (19) p d = p(i cc ) + p(i ref ) + p(i col ) = 654 mw (20) some typical power dissipations for other values of n, v col , d.f., v cc , are shown in figure 25. note that at a d.f. of 17.5%, which would be appropriate for a sun- light viewable application, the 5 2 13 di 7 di 6 di 5 di 4 10 6 3 12 9 7 4 4 hdsp- 2470/71/72 display processor controller b column 1 c b a v b a c hdsp- 2416/24/32/40 alphanumeric display* data valid 2 23 21 19 1 2a 11 1a 4b 3b 2b 1b sel st 3a 14 4a 74ls157 4y 3y 2y 1y 15 5 2 13 di 3 di 2 di 1 di 0 10 6 3 12 9 7 4 17 15 13 11 ready 22 cs 1 6 3 74ls132 74ls00 4 1 2 5 11 3 74ls00 74ls132 12 1 interrupt request 2 13 1 2a 11 1a 4b 3b 2b 1b sel st 3a 14 4a 74ls157 4y 3y 2y 1y 15 3 v cc 4 1 6 13 11 7 2 b 1 b 2 a 1 a 2 cl 1000 pf 74ls122 + v cc 1 k 20 m f 9 74ls132 intel 8255a 10 er d 6 d 5 d 4 d 3 microswitch 61sw12-1 keyboard d 2 d 1 d 0 st 22 k q 5 1000 pf do 0 20 do 1 18 do 2 16 do 3 14 do 4 12 do 5 10 do 6 8 reset 6 *16, 24, 32 or 40 character hdsp-2000 display board designed to interface to the hdsp- 2470/71/72 display processor controller d column 2 e d e f column 3 g f g h column 4 i h i j column 5 k j l clock l k n v cc o n o p gnd q p q m display data m 24 pb 6 23 pb 5 22 pb 4 21 pb 3 20 pb 2 19 pb 1 18 27 d 7 28 d 6 29 d 5 30 d 4 d 3 31 d 2 32 d 1 33 d 0 34 cs 6 a 1 8 a 0 9 rd 5 wr i/o wr 36 reset 35 pb 0 37 pa 7 38 pa 6 39 pa 5 40 pa 4 1 pa 3 2 pa 2 3 pa 1 4 pa 0 13 pc 4 10 (ack) pc 6 10 (obf) pc 7 16 (stb) 8 4 74ls132 5 6 pc 2 25 pb 7 a 4 a 1 a 0 i/o rd system reset data bus an1016.22
29 * port configuration: * 1. port a (mode 1 output): * pa0-pa7 outputs to data in of hdsp-247x * pc7 (obf) output; to chip select * pc6 (ack) input; to ready * flag pc7 (obf) cleared by output; set by ready * * 2. port b (mode 1 input): * pb0-pb6 inputs data from data out of hdsp-247x * pc2 (stb) input; loads data on neg edge of data valid * flag pco (intr) cleared by input; set by data valid * * 3. port c: * pc4 output; low enables pa0-pa7 to hdsp-247x * high enables keyboard to hdsp-247x loc object code source statements 000c pa equ 0ch 000d pb equ 0dh 000e pc equ 0eh 000f cntrl equ 0fh org 0e000h e000 02 e0 ascii dw text e002 00 text ds 32 org 0e100h e100 00 stat db 0 e101 00 addr db 0 e102 00 data ds 32 org 0e400h e400 f3 read di e401 f5 push psw e402 e5 push h e403 c5 push b e404 0e 20 mvi c, 32 e406 21 00 el lxi h, stat first word e409 db 0d in pb clear intr e40b 06 00 loop1 mvi b, 0 e40d db 0e loop2 in pc e40f 04 inr b e410 1f rar e411 d2 0d e4 jnc loop2 wait until intr is set e414 3e 0a mvi a, 10 e416 b8 cmp b e417 db 0d in pb e419 d2 0b e4 jnc loop1 wait until status word e41c 77 loop3 mov m, a store in ram e41d 23 inx h e41e db 0e loop4 in pc e420 1f rar e421 d2 1e e4 jnc loop4 wait until intr is set e424 db 0d in pb e426 0d dcr c e427 c2 1c e4 jnz loop3 e42a 77 mov m, a store last word e42b c1 pop b e42c e1 pop h e42d fl pop psw e42e fb el e42f c9 ret e430 2a 00 e0 load lhld ascii first word of message e433 7e loop5 mov a, m f434 fe ff cpi 0ffh check to see if done e436 ca 45 e4 jz endl e439 d3 0c out pa output to display e43b 23 inx h e43c db 0e loop6 in pc e43e 17 ral e43f d2 3c e4 jnc loop6 wait e442 c3 33 e4 jmp loop5 next word e445 23 endl inx h e446 22 00 e0 shld ascii e449 c9 ret e44a 3e a7 start mvi a, 0a7h pa output, pb input e44c d3 0f out cntrl e44e 3e 0c mvi a, 0ch clear inte a e450 d3 0f out cntrl e452 3e 05 mvi a, 05h e454 d3 0f out cntrl set inte b * procedure to load hdsp-247x system e456 3e 08 mvi a, 08h e458 d3 0f out cntrl enable a side of mux e45a cd 30 e4 call load * procedure to read data out of hdsp-247x system e45d 3e 09 mvi a, 09h e45f d3 0f out cntrl enable b side of mux e461 fb el int must call read figure 23. 8080a microprocessor program that interfaces to the circuit shown in figure 17. hl ascii point to first ascii character pa a output data word to display read return store machine status on stack load hl address of stat point to address of data destination hl a store last data out word a 0 intr flag set on negative edge of data valid c 32 b b + 1 hl hl + 1 hl hl + 1 c c ?1 b 0 a 0 intr flag set on negative edge of data valid wait for ready intr flag cleared? yes wait for data valid no (loop 2) intr flag cleared? yes wait for data valid (loop 4) obf flag cleared? yes (loop 6) (loop 5) no read pb clear intr flag (pc 0 ) a pb clear intr flag (pc 0 ) no a pb clear intr flag (pc 0 ) restore machine status from stack yes not done (endl) last character? denoted by ff h ascii hl hl hl + 1 return wait for next display data output cycle b 10 yes (loop 1) (hl) a store data out word a (hl) read ascii character no no read next data out word c = 0? no (loop 3) yes a 7 obf flag (pc7) set on negative edge of ready
30 figure 24. external circuitry to load a control word into the hdsp-2470/- 2471/-2472 alphanumeric system upon request maximum power dissipation can be reduced to under 1.0 w, while the typical power dissipation can be reduced to 0.60 w. in most in- door ambients, the d.f. can be reduced to 10% for standard red and 5% for gap displays. under these conditions the maximum power dissipation is 0.72 w or 0.52 w and the typical power dis- sipation is 0.43 w or 0.34 w. thus, in power sensitive applications, gap displays can be used to con- serve power. turning off v cc during the time the display is blanked can further reduce the power dissipation. in this manner the maximum power dissipation can be reduced .32 w and the typical power dissipation can be reduced to 0.20 w for the gap displays. heat sinking considerations for operation at the maximum temperature of 85 c, it is impor- tant that the following criteria be met: a. t pin 100 c where t pin = temperature of hottest pin b. t j 125 c the thermal resistance ic junc- tion to case, q jc , or ic junction to pin, q j-pin , is shown in table 2. using these factors, it is possible to determine the required heat sink power dissipation capability and associated power derating through the following equations: t* = q * a p d + t a (21) t j = t* + q j * p d (22) where * = pin or case table 2. device thermal resistance device q jc q j-pin hdsp-2000 series 20 c/w 25 c/w hdsp-2300 series 7.5 c/w 10 c/w hdsp-2490 series 7.5 c/w 13 c/w for example, given q pin-a of 35 c/w an ambient temperature of 60 c, and the operating condi- tions shown in equations (13), (14), and (16) the t pin and t j for the hdsp-2000 family can be calculated as shown below: t pin = (35 c/w) (1.12 w) + 60 c =99 c (23) t j =99 c + (25 c/w) (1.12 w) =99 c + 28 c = 127 c (24) heat sink design for the hdsp-2000 family of displays can be accomplished in a variety of ways. for single line applications, a maximum metalized printed cir- cuit board such as shown in figure 26 can be used. for ex- ample, the hdsp-2416/-2424/ -2432/-2440 display boards consist of 16, 24, 32 or 40 characters of hdsp-2000 displays mounted on a maximum metalized printed cir- cuit board. the hdsp-2432 printed circuit board is 2.3" x 6.4" and has a q pin-a of about 45 c/w per package for a 1/2 ounce cop- per clad printed circuit. these display boards are designed for free air operation of 55 c and operation to 70 c with forced air cooling of 150 fpm normal to the rear side of the board, for displays operating at a p d of 1.00 watt or less. heat sink design for operation above 70 c a free air operating temperature of 85 c can be achieved by heat sinking the display. figure 27 de- picts a two part heat sink which can be assembled using two differ- ent extruded parts. in this design, the vertical fins promote heat transfer due to naturally induced convection. care should be taken to insure a good thermal path be- tween the two portions of the heat sink. to optimize power handling capability, the heat transfer con- tact area between the printed circuit board metallization and the heat sink should be maximized. a thermally conductive silicon rubber sheet can be used to insu- late the printed circuit board. heat sink assemblies similar to an1016.24 desired mode, xx* desired length, yyyy* 14 4a 11 3a 5 2a 12 2 (4) 4y 1a di 7 9 13 (23) 3y 4b di 6 di 7 7 10 (21) 2y 74ls157 v cc hdsp- 2470/1/2 3b di 5 di 6 4 6 (19) 1y 2b di 4 di 5 3 1b di 4 1 sel 15 st 14 4a 11 3a 5 2a 12 2 (17) 4y 1a di 3 9 13 (15) 2y 4b di 2 di 3 7 10 (13) 3y 74ls157 3b di 1 di 2 4 6 (11) (1) (22) 1y 2b di 0 di 1 3 1b di 0 cs ready cs ready *see hdsp-2470/1/2 data sheet 1 sel 15 st
31 where x tt ttt b = + ++ ? ? ? ? figure 25. maximum and typical power dissipation for the hdsp-2000/1/2/3 and hdsp-2300 alphanumeric displays s n o i t p m u s s a n i d e s u n o i t a p i s s i d r e w o p m u m i x a m s n o i t i d n o c g n i t a r e p o ) d e i f i c e p s e s i w r e h t o s s e l n u ( r e w o p n o i t a p i s s i d n o i t a p i s s i d r e w o p m u m i x a m s n o i t i d n o c g n i t a r e p o ) d e i f i c e p s e s i w r e h t o s s e l n u ( r e w o p n o i t a p i s s i d v c c v 5 2 . 5 = v l o c v 5 . 3 = 0 2 = n 5 7 1 . = . f . d v b g n i r u d 0 l a c i g o l = t d n a ( t b ) t b 0 = w 2 1 . 1v c c v 0 0 . 5 = v l o c v 0 . 3 = 5 1 = n 5 7 1 . = . f . d v b g n i r u d 0 l a c i g o l = t d n a ( t b ) t b 0 = w 5 6 . n e c u d e r . 18 1 = nw 4 0 . 1 n e c u d e r . 2 . 2 v d n a l o c 8 1 = n v l o c v 0 . 3 = w 5 9 . v e c u d e r . 3 l o c v l o c v 0 . 3 =w 2 0 . 1v l o c v 4 . 2 =w 8 5 . v l o c v 5 7 . 2 =w 2 6 . . f . d e c u d e r . 40 1 . = . f . dw 8 7 .0 1 . = . f . dw 7 4 . 5 0 . = . f . dw 5 5 .5 0 . = . f . dw 5 3 . v e c u d e r . 5 l o c . 5 . f . d d n a v l o c v 0 . 3 = 0 1 . = . f . d w 2 7 . v l o c v 4 . 2 = 0 1 . = . f . d w 3 4 . v l o c v 0 . 3 = 5 0 . = . f . d w 2 5 . v l o c v 5 7 . 2 = 5 0 . = . f . d w 4 3 . e c u d e r . 6. f . d . 5 v f f o - n r u t c c . 6 t g n i r u d b 0 1 . = . f . d 5 2 6 . = x w 6 6 . 0 1 . = . f . d 5 2 6 . = x w 9 3 . 5 0 . = . f . d 5 7 3 . = x w 5 4 . 5 0 . = . f . d 5 7 3 . = x w 1 2 . v e c u d e r . 7 l o c , . 7 , . f . d e c u d e r . 7 v f f o - n r u t c c . 7 t g n i r u d b v l o c v 0 . 3 = 0 1 . = . f . d 5 2 6 . = x w 0 6 . v l o c v 4 . 2 = 0 1 . = . f . d 5 2 6 . = x w 4 3 . v l o c v 0 . 3 = 5 0 . = . f . d 5 7 3 . = x w 2 3 . v l o c v 5 7 . 2 = 5 0 . = . f . d 5 7 3 . = x w 0 2 .
32 hdsp-2000 display 25 mil insulating ?races?to separate metal conductors figure 26. maximum metalized printed circuit for the agilent hdsp-2000 thermal conducting compound thermal conductive silicone rubber sheet (electrically insulating) metal chassis display bezel and contrast enhancement filter hdsp-2000 display printed circuit board utilizing large metalization pattern two piece black anodized heat sink figure 27. two-part heat sink for the hdsp-2000 the one shown in figure 27 typi- cally exhibit a thermal resistance, q pin-a , of 14 c/w per package for a 32 character display. copper or aluminum bars mounted underneath the displays can also be used to heat sink the display assembly. heat generated within the displays is conducted through the ceramic substrate into the bar. the ends of the bar are mounted to a heat sink or to a metal front panel. the bar can be insulated from the pins of the dis- play and the printed circuit board with a thermally conductive sili- con rubber sheet. figure 28 shows a metal plate with slots milled in the plate for each row of displays such that each horizontal row of displays straddles a bar. a thermal resistance model for this heat sinking technique is shown in figure 29. this model assumes that all heat generated in the display is generated in the center of each display package and that the ends of the bar are connected to an ideal heat sink. then the temperature rise of the centermost display in the bar can be calculated as shown below: t c =4 ( q /2) p d + 3 q p d + 2 q p d + q p d + t a =8 q p d + t a (25) for display strings of an even number of n displays, the case temperature of the centermost displays can be calculated as t c =(n 2 /8) q p d + t a (26)
33 hdsp-2000 displays straddle copper bar mounting holes sip socket cross section view hdsp-2000 display copper bar w printed circuit board t l a = wt q = l ka milled slots heat conducted from ends of plate to heat sink or metal panel figure 28. multiline hdsp-2000 heat sink the effectiveness of this type of heatsink can be determined by calculating the thermal resistance of each section of bar under each display q= l ka () 27 where l = length of bar under each display, mm k = thermal conductivity of bar, w/mm c (0.3937 w/mm c for copper) a = cross sectional area of bar, mm 2 if the displays are mounted in a strip socket such as the robinson nugent sb-25-100-g socket, then the bar cross sectional area could figure 29. thermal resistance model for multiline hdsp-2000 heat sink be 6.35 mm (0.25") thick times the row-to-row pin spacing of the display minus 2.54 mm (.10"). thus, q can be calculated as shown below: an1016.29 q / 2 q jc q jc q jc q jc q jc q jc q jc q jc p d p d p d p d p d p d p d p d qqqqqqqq / 2 hdsp-2000 family q= = 17.8 mm 1.40 c/w (28) (. / )(. )(. ) 0 3937 6 35 5 08 w mm c mm mm hdsp-2300 family q= = 2mm 2.13 c/w (29) 03 0 3937 6 35 3 81 . (. / )(. )(. ) w mm c mm mm hdsp-2490 family q= = 35.6 mm 1.12 c/w (30) (. / )(. )( . ) 0 3937 6 35 12 7 w mm c mm mm the t c and t j can be calculated for a 32 character hdsp-2000 dis- play with a copper bar mounted under the row of displays for an ambient temperature of 85 c
34 and the operating conditions shown in equations (13), (14), (15), and (16): t c = 8 (1.40 c/w) (1.12 w) + 85 c =98 c (31) adding in the junction-to-case temperature rise as shown in equation (22), the t j can be calculated as: t j =98 c + (20 c/w) (1.12 w) =98 c + 22 c = 120 c (32) intensity control an important consideration re- garding display intensity is the control of the intensity with re- spect to the ambient lighting level. in dim ambients, a very bright dis- play will produce very rapid viewer fatigue. conversely, in bright ambient situations, a dim display will be difficult if not im- figure 30. intensity modulation control using a one shot multivibrator possible to read and will also pro- duce viewer fatigue and high error rates. for this reason, control of display intensity with respect to the environment ambient intensity is an important consideration. the hdsp-2000 family of displays is ideally suited for wide ranges of ambient lighting since the inten- sity of these displays can be varied over a very wide dynamic range. the propagation delay be- tween the v b input and the time that the leds turn on or off is un- der a microsecond, allowing dynamic variations of over 2000 to 1 in display luminous intensity at a 100 hz refresh rate. figure 30 depicts a scheme which will automatically control display intensity over a range of 10 to 1 as a function of ambient intensity. this circuit utilizes a resettable monostable multivibrator which is triggered by the column enable pulse. the duration of the multivibrator output is controlled by a photoconductor. at the end of a column enable pulse, the multivibrator is reset to insure that column current is off prior to the initiation of a new display shift register loading sequence. the output of this circuit is used to modulate either the v b inputs of the hdsp-2000 displays or the column enable input circuitry. for maximum reduction in dis- play power, both inputs should be modulated. in the circuit shown in figure 30, the photocell may be replaced by a 50 k w potentiometer to allow manual control of display intensity. figure 31 shows a manually ad- justable dimming circuit that provides a very wide range of dis- play intensity. with a 100 hz display refresh rate, a 4000 to 1 dynamic range of display intensity can be achieved. the intersil icm7555 timer is used as a retriggerable monostable multivibrator. the output of the timer is used to simultaneously pulse width modulate v b , the dis- play column current, and the display supply current. initially the 100 pf capacitor is held dis- charged by the timer. at the negative transition of the trigger input the timer would normally allow the capacitor to charge, however the 2n3906 transistor keeps the capacitor discharged until the trigger input goes high. as soon as the trigger input goes high, the capacitor is charged by a constant current source formed by the rca ca3084 transistor ar- ray. as soon as the voltage across the capacitor reaches 2/3 v cc the output of the timer goes low, and the timer discharges the capaci- tor. the 2n3906 transistor always discharges the capacitor when the trigger is low, therefore the out- put of the timer stays high if the voltage across the capacitor never reaches 2/3 v cc . for the values shown, t can be varied exponen- tially from .5 m s to about 1900 m s. since q1 and q2 are monolithic transistors, t is relatively indepen- dent of temperature. figure 31 also shows a circuit to switch v cc of the displays off dur- ing the time that the display is blanked. when the 2n2219a tran- sistor is off, the lm350 provides a regulated 3 a 5 v output. how- ever, when the 2n2219a transistor is turned on, the output of the lm350 regulator is reduced to 1.2 v. this reduces i cc to under 10 ma per display. capacitive loading of the regulator should be minimized as much as possible to maximize the switching speed. an1016.30 clr trigger 74122 a 1 to col. enable for decreasing ambient illumination 150 k v cc 15 m f clairex cl5 p5l or 500 k pot. a 2 q b 1 b 2 v cc q
35 figure 31. wide range intensity modulation control and power switching of display i cc to conserve power the intensity and color matching the luminous intensity and domi- nant wavelength of led displays can vary over a wide range. if there is too great a difference be- tween the luminous intensity or dominant wavelength of adjacent characters in the display string, the display will appear objection- able to the viewer. to solve the problem, all hdsp-2000 displays are categorized for luminous in- tensity. the category of each display package is indicated by a letter preceding the date code on the package. when assembling display strings, all packages in the string should have the same inten- sity category. this will insure satisfactory intensity matching of the characters. all hdsp-2000 family displays are categorized in overlapping intensity categories. all characters of all packages des- ignated to be within a given letter category will fall within an inten- sity ratio of less than 2:1. for dot matrix displays, a character-to- character intensity ratio of 2:1 is not generally discernible to the human eye. since the human eye is very sensi- tive to variations in dominant wavelength in the yellow and green region, all yellow and green hdsp-2000 family displays are also categorized for dominant wavelength. the dominant wave- length bin for each display package is indicated by a number code following the category letter code on the back of the package. the dominant wavelength bins are 3.5 nm wide for yellow and 4.0 nm wide for green. these domi- nant wavelength variations are generally not discernible by the human eye. an1016.31 0 out v + 8 v 5 v, 3 a v cc 1 to display v cc only in 120 360 2n2219a 0.01 m f 0.01 m f 74ls04 74ls00 2n3906 100 pf 1.5 k 9 3 2 6 1 ca3084 icm7555 v cc 10 11 8 7 to clock enable circuitry to column counter 1 k 1 k 1 2 3 4 1 2 v cc column 1 column 2 column 3 column 4 column 5 v b 3 4 5 74ls04 74145 lm350 adj 1 k 12 15 13 14 d a c b out 3 1 v c 48 rv + gnd 6 2 7 th tr dis load icm 7555 trigger input icm 7555 output display load display t t
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. 5953-7787 (11/99) y a l p s i d r o l o c g n i t h g i l t n e i b m a m i de t a r e d o mt h g i r b 0 x x 2 - p s d h d r a d n a t s d e r e t i l a m o h 0 5 6 1 - 0 0 1 h m l i f l e n a p m 3 0 1 5 6 r c i h p a r g l e n a p 3 6 d e r k r a d 0 6 d e r y b u r 8 1 1 d e r s r e u q e h c s a a h & m h o r 3 2 4 2 e t i l a m o h 6 6 2 1 - 0 0 1 h y a r g 0 5 2 1 - 0 0 1 h y a r g 0 3 2 1 - 0 0 1 h e z n o r b s a a h & m h o r y a r g 4 7 0 2 e z n o r b 0 7 3 2 1 x x 2 - p s d h ) w o l l e y ( e t i l a m o h 6 2 7 1 - 0 0 1 h 0 2 7 1 - 0 0 1 h m l i f l e n a p m 3 0 1 9 5 a c i h p a r g l e n a p 7 2 w o l l e y 3 2 r e b m a s r e u q e h c 7 0 1 r e b m a d i o r a l o p 7 3 p c n h t h g i l m 3 m l i f l o r t n o c 0 2 2 0 0 n c i h p a r g l e n a p 5 1 y a r g 0 1 y a r g s r e u q e h c 5 0 1 y a r g d i o r a l o p 0 1 - p c n h 2 x x 2 - p s d h ) r e h ( e t i l a m o h 0 7 6 1 - 0 0 1 h m l i f l e n a p m 3 0 1 3 6 r c i h p a r g l e n a p 5 6 d e r t e l r a c s 2 1 1 d e r s r e u q e h c 3 x x 2 - p s d h ) n e e r g p h ( e t i l a m o h 0 4 4 1 - 0 0 1 h 5 2 4 1 - 0 0 1 h c i h p a r g l e n a p 8 4 n e e r g s r e u q e h c 7 0 1 n e e r g figure 32. contrast enhancement filters contrast enhancement another important consideration for optimum display appearance and readability is the contrast be- tween the display on elements and the background. high con- trast can be achieved by placing a filter over the display. the filter, if properly chosen, will transmit the luminance of the light emitting elements while attenuating the luminance of the background. filter choice is dependent upon the led display package, ambient lighting conditions and the de- sired front panel appearance. for alphanumeric displays in indoor lighting ambients a plastic or glass wavelength filter can be used. in sunlight ambients a neutral den- sity circular polarizer sandwiched between two pieces of optically coated glass is recommended. figure 32 lists the filter materials recommended for each particular display color. for further informa- tion please see application note 1015 on contrast enhancement for led displays. (agilent green)

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