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july, 2007 v0.26p f71858 f71858 hardware kbc with acpi, temp. and fan control release date: july, 2007 version: v0.26p
july, 2007 v0.26p f71858 f71858 datasheet revision history version date page revision history 0.1p 2005/08/12 - preliminary version 0.11p 2005/09/05 5 updated hardware monitor functions of feature list 0.12p 2005/09/12 - updated pin type description. - added application circuit. 0.13p 2005/11/02 - added function/register description 0.14p 2005/11/20 - register modify 0.15p 2005/11/30 - register modify 0.16p 2006/01/05 - register modify and pin17/pin10 modify 0.17p 2006/01/13 - updated application circ uit and register description for laa version chip. 0.18p 2006/02/15 - modified typo. modified fan1~fan3 duty change rate select register (cr9bh) 0.19p 2006/03/15 - removed hw monitor register index 70h (hw_irq enable register) - added electrical characteristics description. - updated register description. 0.20p 2006/04/13 55 added fan4 d0h-d1h regi sters description. 0.21p 2006/05/03 35 modified acpi control register index f5h bit 7 32 modified select kb/mo wakeup register 27h bit 7 0.22p 2006/06/15 - modified name of vt1/vt2/vt3 which change to t1/t2/t0. t0 means local temperature. 0.23p 2006/09/06 - this version datasheet is for lac version chip use. - added fan control machine by internal clock when system boot up. modified typo. 0.24p 2006/11/10 - this version datasheet is for lad version chip use. 0.25p 2006/12/19 - modified typo. - updated application circuit. 0.26p 2007/7/6 - company readdress please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
july, 2007 v0.26p f71858 table of content 1. general de scripti on ........................................................................................................ 6 2. featur e li st................................................................................................................ ..... 6 3. key spec ification ........................................................................................................... .7 4. pin conf iguration ........................................................................................................... .8 5. pin de scription ............................................................................................................. .. 9 5.1 powe r pin.................................................................................................................. .. 9 5.2 lpc in terface .............................................................................................................. 9 5.3 keyboard c ontroller .................................................................................................. 10 5.4 ac pi....................................................................................................................... ... 10 5.5 h/w m onitor .............................................................................................................. 10 6. function de scription ..................................................................................................... 12 6.1 keyboard c ontroller .................................................................................................. 12 6.2 acpi f unction ............................................................................................................ 14 6.3 hardware monitor ...................................................................................................... 18 6.4 led f unction ............................................................................................................. 28 6.5 amdsi and intel sst peci func tion ........................................................................ 29 7. register de scription ..................................................................................................... 30 7.1 global control register s ........................................................................................... 30 7.2 kbc regi sters........................................................................................................... 32 7.3 acpi and pme registers.......................................................................................... 33 7.4 hardware monitor registers (ind ex port: 0x295; data port: 0x296) .......................... 36 7.4.1 logic device nu mber regi ster .......................................................................... 36 7.4.2 hardware monitor conf iguration regi sters ........................................................ 36 7.4.3 hardware monitor device regi sters .................................................................. 36 7.4.3.1 configur ation register ? index 01h.................................................................. 36 7.4.3.2 configur ation register ? index 02h................................................................... 36 7.4.3.3 peci sst amdsi interf ace configuration register ? index 0ah ...................... 37 7.4.3.4 amdsi version register ? index 0bh (meas_ type ==2?b10 ) ...................... 37 7.4.3.5 dual single co re select register ? index 0bh (meas_type ==2?b01) ......... 37 7.4.3.6 tcc activation temperature register ? index 0ch (meas_type == 2?b01) 37 7.4.3.7 amdsi node id register ? index 0ch (meas_ type ==2? b10)..................... 37 7.4.3.8 sst addr ess register ? index 0d h................................................................... 38 7.4.3.9 cpu temp. measure select register ? index 0e h............................................ 38 7.4.3.10 voltage reading and limit ? index 20h- 22h ...................................................... 38
july, 2007 v0.26p f71858 7.4.3.11 temperature pme# enable register ? index 60h ........................................... 38 7.4.3.12 temperature inte rrupt status register ? index 61h......................................... 39 7.4.3.13 temperature real time status register ? index 62h ...................................... 39 7.4.3.14 alert# output enable register 1 ? index 66h.............................................. 40 7.4.3.15 temperature pme# mode and tabl e select register -- index 69h .................. 40 7.4.3.16 local and temp1 limit hysteresis select register -- index 6ch ................. 41 7.4.3.17 temp2 and temp3 limit hysteresis select register -- index 6dh................. 41 7.4.3.18 diode open status register -- i ndex 6fh ..................................................... 41 7.4.3.19 temperature register ? index 70h- 8fh.......................................................... 41 7.4.3.20 temperature filter select register -- index 8eh .............................................. 42 7.4.3.21 fan pme# enable register ? index 90h ........................................................ 43 7.4.3.22 fan interrupt status register ? index 91h...................................................... 43 7.4.3.23 fan real time status register ? index 92h ................................................... 43 7.4.3.24 fan fault# enable register ? index 93h ..................................................... 43 7.4.3.25 fan type select r egister -- i ndex 94h ............................................................. 44 7.4.3.26 fan mode select re gister -- i ndex 96h ........................................................... 44 7.4.3.27 auto fan1 and fan2 bound ary hystersis select regi ster -- index 98h........... 45 7.4.3.28 auto fan3 boundary hystersis select register -- index 99h ........................... 45 7.4.3.29 fan1~fan3 duty change rate se lect register -- index 9b h .......................... 45 7.4.3.30 fan1 and fan2 start up duty-cycle/voltage ? index 9ch............... 46 7.4.3.31 fan3 start up duty-cycle/voltage ? index 9d h................................ 46 7.4.3.32 fan fault time regi ster -- index 9fh .............................................................. 46 7.4.3.33 t1 boundary 1 tem perature ? index a6h............................................. 47 7.4.3.34 t1 boundary 2 tem perature ? index a7h............................................. 47 7.4.3.35 t1 boundary 3 tem perature ? index a8h............................................. 47 7.4.3.36 t1 boundary 4 tem perature ? index a9h............................................. 47 7.4.3.37 fan1 segment 1 spee d count ? i ndex aah ......................................... 47 7.4.3.38 fan1 segment 2 spee d count ? i ndex abh ......................................... 48 7.4.3.39 fan1 segment 3 speed count ? i ndex ach....................................... 48 7.4.3.40 fan1 segment 4 speed count ? i ndex adh....................................... 48 7.4.3.41 fan1 segment 5 spee d count ? index aeh....................................... 48 7.4.3.42 fan1 temperature mapping select ? index afh......................................... 48 7.4.3.43 t2 boundary 1 tem perature ? index b6h............................................. 49 7.4.3.44 t2 boundary 2 tem perature ? index b7h............................................. 50 7.4.3.45 t2 boundary 3 tem perature ? index b8h............................................. 50 7.4.3.46 t2 boundary 4 tem perature ? index b9h............................................. 50 7.4.3.47 fan2 segment 1 spee d count ? i ndex bah ........................................ 50
july, 2007 v0.26p f71858 7.4.3.48 fan2 segment 2 spee d count ? i ndex bbh ........................................ 50 7.4.3.49 fan2 segment 3 speed count ? i ndex bch ...................................... 51 7.4.3.50 fan2 segment 4 speed count ? i ndex bdh ...................................... 51 7.4.3.51 fan2 segment 5 spee d count ? index beh....................................... 51 7.4.3.52 fan2 temperature mapping select ? index bfh ........................................ 51 7.4.3.53 t0 boundary 1 tem perature ? index c6h ............................................ 52 7.4.3.54 t0 boundary 2 tem perature ? index c7h ............................................ 52 7.4.3.55 t0 boundary 3 tem perature ? index c8h ............................................ 52 7.4.3.56 t0 boundary 4 tem perature ? index c9h ............................................ 53 7.4.3.57 fan3 segment 1 spee d count ? i ndex cah ........................................ 53 7.4.3.58 fan3 segment 2 spee d count ? i ndex cbh ........................................ 53 7.4.3.59 fan3 segment 3 spee d count ? index cch ...................................... 53 7.4.3.60 fan3 segment 4 spee d count ? index cdh ...................................... 53 7.4.3.61 fan3 segment 5 speed count ? i ndex ceh ...................................... 54 7.4.3.62 fan3 temperature mapping select ? index cfh ........................................ 54 8. pcb layout guide ........................................................................................................ 54 9. electrical char acteristic s .............................................................................................. 56 9.1 absolute maxi mum rati ngs ...................................................................................... 56 9.2 dc characte ristics .................................................................................................... 57 9.3 dc characterist ics conti nued ................................................................................... 57 9.4 ac characte ristics .................................................................................................... 58 10. ordering in formati on..................................................................................................... 62 11. package dimensions (48lqfp ) ................................................................................... 62 12. applicat ion cir cuit ........................................................................................................ .63
july, 2007 v.26p 6 f71858 1. general description the f71858 is hardware kbc integrating the acpi, temperature sensing and fan control functions specific for the legacy free mb application. the kbc functions include one keyboard and one ps/2 mouse, and can be used with ibm ? - compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer. the f71858 provides the acpi control signals as well such as s3 state, resume reset, pci reset outputs or power ok signals. the power led is programmable and compliant with pc2001. as to the environment sensing functions, f71858 provides 2 remote analog dual current temp. sensing inputs and one internal local temperature sensing. one alert signal will be issued while the temperature is over the programmable limit. 4 fan monitoring inputs and 3 fan controlling outputs provide fintek?s patented auto-fan controlling features. others, the f71858 supports amdsi and intel peci/sst interfaces for temperature use. for next generation cpu temp. sensing technology. f71858 is in lpc interface and powered by 3vcc, 3v standby, and battery. the package is in 48 pin lqfp green package. 2. feature list general functions ? comply with lpc spec. 1.0 ? hardware keyboard controller support one ps/2 keyboard and one ps/2 mouse ? fast gate a20 and hardware keyboard reset ? support dpm (device power management), acpi kbc ? lpc interface support serial interrupt channel 1, 12. ? two 16bit programmable address fully decoder, default 0x60 and 0x64. ? support two ps/2 interface, one for ps/2 mouse and the other for keyboard. ? keyboard?s scan code support set1, set2. ? programmable compatibility with the 8042. ? support both interrupt and polling modes. ? fast gate a20 and hardware keyboard reset.
july, 2007 v.26p 7 f71858 acpi functions ? 1 reset input and 5 pci reset output pins ? 2 programmable power led ? s3gate control ? resume reset ? power ok signal hardware monitor functions ? 2 current type accurate (3 j ) thermal inputs for cpu thermal diode/2n3906 transistors ? one internal local thermal sensor ? one alert pin (pin hw_irq#)(default limit 100c for cpu temp.) ? temperature sensing range from -40 j ~127 j ? 4 fan speed monitoring inputs ? 3 fan speed auto-control (support 3 wire and 4 wire fans) ? support pwm and dac mode control ? default pwm duty is 40% when system boot up promptly ? provide intel peci/sst interface for temperature sensing ? provide amdsi interface for temperature sensing ? support 3 channels voltage monitor ( vcc3v + vsb3v + vbat) ? voltage monitor resolution is 8mv per lsb package ? 48-pin lqfp 3. key specification supply voltage 3.0v to 3.6v operating supply current 5 ma typ.
july, 2007 v.26p 8 f71858 4. pin configuration
july, 2007 v.26p 9 f71858 5. pin description i/o 12t - ttl level bi-directional pin with 12 ma source-sink cap ability. i/ood 12t i/od 16t5v - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. - ttl level bi-directional pi n,open-drain output with 16 ma source-sink capability, 5v tolerance. od 16-u10-5v i/od 12ts5v o 8-u47-5v - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - open-drain pin with 8 ma source-sink capabilit y, pull-up 47k ohms, 5v tolerance. o 8 o 16 o 30 - output pin with 8 ma source-sink capability. - output pin with 16 ma source-sink capability. - output pin with 30 ma source-sink capability. aout - output pin(analog). od 12 od 12-5v od 24 - open-drain output pin with 12 ma sink capability. - open-drain output pin with 12 ma sink capability, 5v tolerance. - open-drain output pin with 24 ma sink capability. in t5v in ts - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in ts5v - ttl level input pin and schmitt trigger, 5v tolerance. ain - input pin(analog). p - power. 5.1 power pin pin no. pin name type description 9 vcc p 3v power 24 vcc3v p 3v power for analog (provide voltage monitor) 40 vsb3v p 3v stand by power (provide voltage monitor) 48 vbat p battery power (provide voltage monitor) 45 gnd p ground 21 gnd(d-) p ground for te mperature sensing use. 5.2 lpc interface pin no. pin name type pwr description 1 lreset# in ts5v vcc reset signal. it can connect to pcirst# signal on the host. 8 serirq i/o 12t vcc serial irq input/output. 2 lfram# in ts vcc indicates start of a new cycle or termination of a broken cycle. 3,4,5,6 lad[3:0] i/o 12t vcc these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. 7 pciclk in t vcc 33mhz pci clock input.
july, 2007 v.26p 10 f71858 5.3 keyboard controller pin no. pin name type pwr description 19 kbrst# od 12-u10 vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) 18 ga20 od 12-u10 vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) 42 kdata i/od 16ts,5v vsb keyboard data. 41 kclk i/od 16ts,5v vsb keyboard clock. 44 mdata i/od 16ts,5v vsb ps2 mouse data. 43 mclk i/od 16ts,5v vsb ps2 mouse clock. 5.4 acpi pin no. pin name type pwr description 31 led1 od 16,5v vsb power led for vsb. 32 led2 od 16,5v vsb power led for vsb. 25 rstin# in ts5v vsb reset buffer input signal. 26,30 pcirst1# pcirst5# od 16,5v vsb output buffer of rstin# and lreset# for ide reset. 27,28,29 pcirst[2:4]# o 16 vsb output buffer of rstin# and lreset#. 46 pwrok iod 12,5v vbat pwrok function, it is power good signal of vcc, which is delayed 400ms (default and programmable) as vcc arrives at 2.8v. 39 ps_in# in ts5v vsb main power switch button input. 38 ps_out# od 12 vsb panel switch output. this pin is low active and pulse output. it is power on request output#. 35 s3# in ts vsb s3# input is main power on-off switch input. 36 s4# in ts vsb s4# input is for s3/s4 (s5) state switch input. 33 s3gate od 12-5v vsb control dual voltage signal. 34 ps_on# od 12-5v vsb power supply on-off control output. connect to atx power supply ps_on# signal. 47 rsmrst# od 12 vbat resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.3v. 5.5 h/w monitor pin no. pin name type pwr description 14 fanin1 in ts5v vcc fan 1 tachometer input. 11 fan_ctl1 od 12-5v aout vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. default pwm duty is 40%. 15 fanin2 in ts54v vcc fan 2 tachometer input. 12 fan_ctl2 od 12-5v aout vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. default pwm duty is 40%. 16 fanin3 in ts5v vcc fan 3 speed input. default pwm duty is 40%.
july, 2007 v.26p 11 f71858 fan_ctl3/ od 12-5v aout fan 3 control output and 3pin fan is recommended to be controlled by this pin but not 4pin fan. this pin provides pwm duty-cycle output or a voltage output. 13 hpwm_dc vcc power on strapping : pull high: fan control method will be pwm mode nc: fan control method will be dac mode fanin4 in ts5v fan 4 speed input. sst i lv /o d8-s1 intel sst hardware monitor interface. 17 amdsi_clk od 12 vcc clock output for amd si interface. 23 d2+ aout ain vcc thermal diode/transistor temperature sensor input. 22 d1+(cpu) aout ain vcc thermal diode/transistor temperature sensor input. peci i lv /o d8-s1 intel peci hardware monitor interface. 10 amdsi_dat i lv /od 12 vcc amd si data interface. 20 hw_irq# od 12-5v vcc active low output. this pin will be logic low when the temperature exceeds its limit or fan fault event. 37 pme# od 12 vsb generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state.
july, 2007 v.26p 12 f71858 6. function description 6.1 keyboard controller the kbc circuit provides the functions included a keyboard and/or a ps/2 mouse, and can be used with ibm ? - compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer. output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the scan code rece ived from the keyboard and data bytes required by commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h, that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte
july, 2007 v.26p 13 f71858 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command function 20h read command byte 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test returns 055h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface
july, 2007 v.26p 14 f71858 aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bi ts of port1 into status register c2h continuously puts the upper four bi ts of port1 into status register d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh pulse only rc(the reset line) low for 6 s if command byte is even kbc command description ps2 wakeup function the kbc supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational key (1) ctrl +esc (2) ctrl+f1 (3) ctrl+space (4) any key (5) windows 98 wakeup up key, kbc will assert pme signal. mouse wakeup function has 2 kinds of conditions, when mouse (1) button click or (2) button click and movement, kbc will assert pme signal. those wakeup conditions are controlled by configuration register. 6.2 acpi function the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect different power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is
july, 2007 v.26p 15 f71858 necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v acpi default timing always off vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v acpi default timing always on
july, 2007 v.26p 16 f71858 pcirst and pwrok signals the f71858 supports 5 output buffers for 5 reset signals. the result of pcirst[1:5]# outcome will be affected by conditions as below. the pwrok signal is affected by rst_in#/lreset#/dvcc3vok.when rstcon_en set 1, powerok signal is affect by dvcc3vok and when rstcon_en set 0, powerok signal is affect by rst_in#/ lreset#/dvcc3vok, reference as below. pcirst# and pwrok rstcon_en 50ms rst_in# lreset# rst_dat rst_dis pcirst rstcon_en 1 0 0 1 rst_in# 50ms d_vcc3vok d_vcc3v o k pwrok 1ms
july, 2007 v.26p 17 f71858 s3 gate signals the s3 gate signal response s0/s3/s5 state and condition is as below. when system is in s3 state, s3_gate is asserted logic high; the other state is asserted logic low. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s5 s3 is illegal transition and s3_gate signal will be keep logic level. s3_gate diagram s3 / s4 s3/s4/d_vddok s3_gate = 0 idle s3 = 0&s4 = 0 s3_gate = 0 s3_gate = 1 s3 = 0&s4 = 1 s3 = 0&s4 = 0 s3 = 1 & s4 = 1& d_vdd3vok = 1
july, 2007 v.26p 18 f71858 6.3 hardware monitor for the 8-bit adc has the 8mv lsb, the maximum input voltage of the analog pin is 2.304v. therefore the voltage under 2.304v (ex:1.5v) can be directly connected to these analog inputs. the voltage higher than 2.304v should be reduced by a factor with external resistors so as to obtain the input range. vcc, vsb 3.3v and vbat 3v are the exception for it is main power of the f71858. therefore these powers can directly connect to this chip?s power pin and need no external resistors. there are two functions in these pins with 3.3v/3v. the first function is to supply internal logic power of the f71858 and the second function is that this voltage with 3.3v/3v is connected to internal serial resistors to monitor the vcc vsb 3.3v and vbat voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of 3.3v/3v. f71858 only support three power voltage monitor but without hardware high low limit protect. so it will not trigger pme event when voltage too high or too low. 8-bit adc with 8 mv lsb typical thermister connection voltage inputs (directly connect to the chip) 3vcc (directly connect to the chip) vin1 150k 150k 2n3906 typical bjt connection d+ gnd 3vsb 3vbat the f71858 monitors a local and 2 remote temperature sensor. both can be measured from -40c to 145c and there are four kinds of temperature to display. the temperature format is as the following table: table mode 0: display range is from 0c to 127c. the values in high byte registers are mean the temperature reading value and the unit is 1c. the value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125c. temperature digital output (high byte) digital output (low byte) 0.125c 0000 0000 001x xxxx 1c 0000 0001 000x xxxx 90c 0101 1010 000x xxxx
july, 2007 v.26p 19 f71858 127.875c 0111 1111 111x xxxx open 1011 1011 000x xxxx short 1100 1100 000x xxxx table mode 1: display range is from 0c to 145c. the values in high byte registers are mean the temperature reading value and the unit is 1c. the value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125c. temperature digital output (high byte) digital output (low byte) 0.250c 0000 0000 010x xxx 0 1c 0000 0001 000x xxx 0 100c 0110 0100 000x xxx 0 145.875c 1001 0001 111x xxx 0 open 1011 1011 000x xxxx short 1100 1100 000x xxxx table mode 2: (default) display range is from -40c to 127c. the values in high byte registers bit7 is sign bit and the values in high byte registers bit6~bit0 are mean the temperature reading value and the unit is 1c. the value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125c. temperature digital output (high byte) digital output (low byte) -40c 1101 1000 000x xxxx -1c 1111 1111 000x xxxx 0c 0000 0000 000x xxxx 100c 0110 0100 000x xxxx 127.875c 0111 1111 111x xxxx open 1011 1011 000x xxxx short 1100 1100 000x xxxx table mode 3: display range is from -40c to 145c. the values in high byte registers bit7~bit0 are mean the temperature reading value and the unit is 1c. the value in low bye register bit7~bit5 are temperature reading value and the unit is 0.125c. the sign bit is in low bye register bit0
july, 2007 v.26p 20 f71858 temperature digital output (high byte) digital output (low byte) -40c 1101 1000 000x xxx 1 -1c 1111 1111 111x xxx 1 0c 0000 0000 000x xxx 0 1c 0000 0001 000x xxx 0 90c 0101 1010 000x xxx 0 127c 0111 1111 111x xxx 0 145.875c 1001 0001 111x xxx 0 open 1011 1011 000x xxx x short 1100 1100 000x xxx x remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906 monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits provide thermal diode for temperature measurement, the f71858 is capable to these si tuations. the build-in reference table is for pnp 2n3906 transistor, and each different kind of thermal diode should be matched with specific margin and bjt gain. the transistor is directly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; therefore, careful pcb board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. high frequency emi is best filtered at d+ and d- with an external 2200pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sources tested cause the adc measurement to be higher than the actual temperature, depending on the frequency and amplitude. temperature hm_irq signal (hm_irq# and pme#) there are two mode of temperature hm_irq function: 1. hysteresis mode:
july, 2007 v.26p 21 f71858 over temperature event will trigger hm_irq# that shown as figure. in hysteresis mode, when monitored temperature exceeds the high te mperature threshold value, hm_irq# will be asserted until the temperature goes below the hysteresis temperature. t hyst t hm_irq# high 2. high low limit mode: (default): when in high low limit mode hm_irq# for temperature is shown as figure. when monitored temperature exceeds the over-tem perature threshold value, hm_irq# will be asserted until the temperature goes below the low limit temperature. t low hm_irq# t high temperature pme# there are two mode of temperature pme# function: 1. hysteresis mode: pme# interrupt for temperature is shown as figure. temperature exceeding high limit (low limit) or going below high hysteresis (low hy steresis) will cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register.
july, 2007 v.26p 22 f71858 *interrupt reset when interrupt status registers are written 1 pme# t low (pulse mode) * * t high t hhys t lhys * * 2. high low limit mode: (default): pme# interrupt for temperature is shown as figure. temperature exceeding high limit or going below low limit will cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register. *interrupt reset when interrupt status registers are written 1 pme# t low (pulse mode) * t high * fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer outputs are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification. the normal circuit and trimming circuits are shown as follows:
july, 2007 v.26p 23 f71858 fan out +12v gnd pull-up resister 4.7k ohms +12v fan input fanin 1 f71858 22k~30k 10k fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input f71858 > 1k fan with tach pull-up to +12v, or totem-pole putput and zener clamp 3.3v zener fan with tach pull-up to +12v, or totern-pole output and register attenuator fanin 1 fan out +5v gnd pull-up resister 4.7k ohms +5v fan input fanin1 f71858 1k~2.7k 10k fan connector fan out +5v gnd pull-up resister < 1k or totem-pole output +5v fan input fanin1 f71858 > 1k fan with tach pull-up to +5v, or totem-pole putput and zener clamp 3.3v zener fan with tach pull-up to +5v, or totern-pole output and register attenuator determine the fan counter according to: r pm count 6 10 5 . 1 = in other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachometer output per round. count rpm 6 10 5 . 1 = fan speed control the f71858 provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle dac fan control the range of dc output is 0~3.3v, controlled by 8-bit register. 1 lsb is about 0.013v. the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 255 value register 8bit programmed 3 . 3 (v) tage output_vol =
july, 2007 v.26p 24 f71858 and the suggested application circuit for dac fan control would be: dc output voltage r 3.9k r10k 12v pmos r27k 1 2 3 jp1 con3 r 10k d1 1n4148 r 4.7k c 47u fanin monitor c 0.1u 3 2 1 8 4 + - lm358 dc fan control with op pwm duty fan control the duty cycle of pwm can be programmed by a 8-bit register. the default duty cycle is set to 40%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g +5v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode, 3.linear auto mode. more detail, please refer the description of registers. manual mode: for manual mode, it generally acts as software fan speed control. stage auto mode: at this mode, the f71858 provides automatic fan speed control related to temperature variation of cpu/gpu or the system. the f71858 can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take figure as example. when temperature boundaries are set as 40, 50,
july, 2007 v.26p 25 f71858 60, and 70 c and there are five intervals (each interval is 10 c). the related desired pwm duty for each interval are 100%, 85%, 65%, 50%, 40%. when the temperature is within 50~60 c, the duty is 65% will be load into fan expect duty register. then, the f71858 will adjust pwmout duty-cycle to meet the expected value. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature variation. the f71858 will take charge of all the fan speed control and need no software support. desired duty (default 100%) (default 85%) (default 65%) (default 50%) (default 40%) boundtemp1 (default 70'c) boundtemp2 (default 60'c) boundtemp3 (default 50'c) boundtemp4 (default 40'c) there are two examples as below: a. stage auto mode (pwm duty) set temperature as 60 x c, 50 x c, 40 x c, 30 x c and duty as 100%, 90%, 80%, 70%, 60% 100% 90% 80% 70% 60% 60 degree c 50 degree c 40 degree c 30 degree c 0xff 0xe5 0xcc 0xb2 0x99 ab cd temp. fan speed pwm duty hysteresis 47 degree c a. once temp. is under 30 x c, the lowest fan speed keeps 60% pwm duty b. once temp. is over 30 x c,40 x c,50 x c, the fan speed will vary from 60% to 90% pwm duty and increase with temp. level. c. once temp. keeps in 55 x c, fan speed keeps in 90% pwm duty d. if set the hysteresis as 3 x c (default 4 x c), once temp reduces under 47 x c, fan speed reduces to 80% pwm duty and stays there. b. stage auto mode (rpm%)
july, 2007 v.26p 26 f71858 set temperature as 60 x c, 50 x c, 40 x c, 30 x c and assume the full speed is 6000rpm, set 90% of full speed rpm(5400rpm), 80%(4800rpm ), 70%(4200rpm), 60%(3600rpm) of full speed rpm 6000rpm 90%(5400rpm) 80%(4800rpm) 70%(4200rpm) 60%(3600rpm) 60 degree c 50 degree c 40 degree c 30 degree c ab cd temp. fan speed hysteresis 47 degree c a. once temp. is under 30 x c, the lowest fan speed keeps 60% of full speed (3600rpm). b. once temp. is over 30 x c,40 x c,50 x c, the fan speed will vary from 3600rpm to 5400rpm and increase with temp. level. c. once temp. keeps in 55 x c, fan speed keeps in 90% of full speed (5400rpm) d. if set the hysteresis as 3 x c (default 4 x c), once temp reduces under 47 x c, fan speed reduces to 4800rpm and stays there. linear auto mode: otherwise, f71858 supports linear auto mode. below has two examples to describe this mode. more detail, please refer the register description. a. linear auto mode (pwm duty) set temperature as 70 x c, 60 x c, 50 x c, 40 x c and duty as 100%, 70%, 60%, 50%, 40% 100% 70% 60% 50% 40% 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed pwm duty a. once temp. is under 40 x c, the lowest fan speed keeps 40% pwm duty b. once temp. is over 40 x c,50 x c,60 x c, the fan speed will vary from 40% to 70% pwm duty
july, 2007 v.26p 27 f71858 and linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 x c, fan speed will directly increase to 100% pwm duty (full speed) d. if set the hysteresis as 5 x c(default is 4 x c), once temp reduces under 65 x c (not 70 x c), fan speed reduces from 100% pwm duty and decrease linearly with temp.. b. linear auto mode (rpm%) set temperature as 70 x c, 60 x c, 50 x c, 40 x c and if full speed is 6000rpm, setting 100%, 70%, 60%, 50%, 40% of full speed. 6000rpm 70%(4200rpm) 60%(3600rpm) 50%(3000rpm) 40%(2400rpm) 70 degree c 60 degree c 50 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed a. once temp. is under 40 x c, the lowest fan speed keeps 40% of full speed (2400rpm) b. once temp. is over 40 x c,50 x c,60 x c, the fan speed will vary from 40% to 70% of full speed and almost linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 x c, fan speed will directly increase to full speed 6000rpm. d. if set the hysteresis as 5 x c, once temp reduces under 65 x c (not 70 x c), fan speed reduces from full speed and decrease linearly with temp.. pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rpm? modes, the f71858 adjust pwmout duty-cycle according to current fan count and ex pected fan count. it will operate as follows: (1). when expected count is 0xfff, pwmout duty-cycle will be set to 0x00 to turn off fan. (2). when expected count is 0x000, pwmout duty-cycle will be set to 0xff to turn on fan with full speed. (3). if both (1) and (2) are not true, when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h next, when f71858 up the fan speed will keep duty-cycle at start duty for
july, 2007 v.26p 28 f71858 1.2 seconds. after that, the f71858 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the f71858 will ignore it. start duty stop duty fan hm_irq signal (hm_irq# and pme#) fan fault will be asserted when the fan speed doesn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there are two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan speed count can?t reach the fan expected count in time. fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count still in 0xfff. 6.4 led function the f71858 provides two leds to indicate system state (s0, s3, and s5). every state has indicate 4 kinds of mode (1) always 0 (2) oscillate 1hz (3) oscillate 1/2 hz (4) always 1 and can be controlled by configuration register. when system is in s0 state, led1 defaults 0 and led2 defaults 1. when system is in s3 state, led1 and led2 oscillate 1hz. when system is in s5 state, led1 defaults 1 and led2 defaults 0.
july, 2007 v.26p 29 f71858 6.5 amdsi and intel sst peci function the f71858 provides intel sst/peci/amdsi interfaces for new generational cpu temperature sensing. in amdsi interface, there are sic and sid signals for temperature information reading from amd cpu. the sic signal is for clocking use, the other is for data transferring. more detail please refer register description. vddio sic sid 300 f71858 amd cpu sic sid 300 in intel sst and peci interfaces, the f71858 can connect to cpu/sst directly. the f71858 can read the temperature data from cpu, than the fan control machine of f71858 can implement the fan to cool down cpu temperature. as same as peci, chipset can get information from f71858 including cpu temperature, system temperature (f71858 prov ides d+/d- for system temperature sensing), fan speed status by sst. the application circuit is as below. more detail please refer the register description. sst f71858 ich8 sst intel peci f71858 cpu peci intel 100k
july, 2007 v.26p 30 f71858 7. register description 7.1 global control registers the configuration register is used to control the behavior of the corresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. to enable configuration, the entry key 0x87 must be written to the index port. to disable configuration, write exit key 0x78 twice or key 0xaa once to the index port. following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) 7.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the regi ster and device powered by vdd ( vcc ). 7.1.2 logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc dev ice configuration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 7.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 05h chip id 1 of f71858.
july, 2007 v.26p 31 f71858 7.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 07h chip id2 of f71858. 7.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1 of fintek devices. 7.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 7.1.7 port select register ? index 25h bit name r/w default description 7-5 reserved - - reserved. 4 port_4e_en r/w 1 the port could be changed by writing this register. 0: configuration register port is 2e/2f. 1: configuration register port is 4e/4f. (default) 3-0 reserved - - reserved. 7.1.8 select kb/mo wakeup register ? index 27h bit name r/w default description 7 dis_wake r/w 0 1: disable kb/mo wakeup function 0: enable kb/mo wakeup function. 6-4 reserved - 0 reserved. 2 mo_sel r/w 0 select mouse key to wakeup host 0: click mouse key 1: any mouse key 3,1-0 kb_sel r/w 000 select combination key to wakeup host 000: ctrl + esc 001: ctrl + f1 010: ctrl +space 011: any key 100:windows 98 wakeup up key
july, 2007 v.26p 32 f71858 7.2 kbc registers 7.2.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc dev ice configuration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor dev ice configuration registers. 7.2.2 kbc configur ation registers kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc base address. keyboard irq channe l enable register ? index 70h bit name r/w default description 7-6 reserved - - reserved. 0 enkbcirq r/w 1b enable the irq channel for keyboard. mouse irq channel enable register ? index 72h bit name r/w default description 7-6 reserved - - reserved. 0 enmocirq r/w 1b enable the irq channel for mouse.
july, 2007 v.26p 33 f71858 7.3 acpi and pme registers 7.3.1 logic device number register logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc dev ice configuration registers. 01h: select pme & acpi devic e configuration registers. 02h: select hardware monitor devic e configuration registers. 7.3.2 acpi and pme conf iguration registers device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable register ? index f0h bit name r/w default description 7 reserved - - reserved 6 ms_pme_en r/w 0 ps/2 mouse pme event enable. 0: disable ps/2 mouse pme event. 1: enable ps/2 mouse pme event. 5 kb_pme_en r/w 0 ps/2 keyboard pme event enable. 0: disable ps/2 keyboard pme event. 1: enable ps/2 keyboard pme event. 4-1 reserved - - reserved 0 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. pme event status register ? index f1h bit name r/w default description 7 reserved - - reserved 6 ms_pme_st r/w 0 ps/2 mouse pme event status. 0: ps/2 mouse has no pme event. 1: ps/2 mouse has a pme event to asser t. write 1 to clear to be ready for next pme event. 5 kb_pme_st r/w 0 ps/2 keyboard pme event status. 0: ps/2 keyboard has no pme event. 1: ps/2 keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 4-1 reserved - - reserved
july, 2007 v.26p 34 f71858 0 hm_pme_st r/w 0 hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register ? index f4h bit name r/w default description 7 ts3 r/w 0 set to 1 into s1 state. two wake up methods: 1. pme wake up event ? must write this bit to 0. 2. ps_out# wake up event ? auto clear this bit. 6-5 reserved - - reserved. 4 enkbwakeup r/w 0 0:disable keyb oard wakeup signal (ps_out#) 1:enable keyboard wakeup signal 3 enmowakeup r/w 0 0:disable mo use wakeup signal (ps_out#) 1:enable mouse wakeup signal 2-1 pwrctrl r/w 11 the acpi control the pson# to always on or always off or keep last state 00 : keep last state 10 : always on 01 : reserved (always on) 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it acpi control register ? index f5h bit name r/w default description 7 sel_s3 r/w 0 1:selected by ts3 ts3 0: chip decided into s3 state from s3 pin 1 : chip direct into s3 state 0: chip decided into s3 state from vdd (vcc) power detect ok., which chip detects voltage circuit 6 reserved - - reserved 5 by_pass_lrst r/w 1 bypass lreset# to pcireset[5:1] 4 rstcon_en r/w 0 pwrok and pcirst[5:1] are affect by rstcon bit. when rstcon set 0, pwrok output rst_in and vdd (vcc) voltage detect ok. rstcon set to 1, pwrok only output vdd (vcc) voltage detect ok. when rstcon set to 0, pcirst[5:1] output lreset# and confreg reset dat(0xf8) . rstcon set tp 1, pc irst[5:1] output rst_in, lreset# and confreg reset dat(0xf8). 3-2 delay r/w 11 the pwrok delay timing from vcc3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 1 bypass_db r/w 0 bypass the s3#/s4#/psin#/rstin# pins. 0 vindb_en r/w 1 enable the rstin# debounce. acpi soft reset register ? index f6h bit name r/w default description 7 soft_rst_acpi w 0 software reset to acpi set to 1 to reset acpi
july, 2007 v.26p 35 f71858 6-0 reserved - - reserved acpi reset enable register ? index f7h bit name r/w default description 7-5 reserved - - reserved 4-0 pci_rst_en r/w 5?h1f reset output enable acpi reset data register ? index f8h bit name r/w default description 7-5 reserved - - reserved 4-0 pci_rst_dat w 5?h0 write 1 to reset output low pulse 2ms. led s0 status register ? index f9h bit name r/w default description 7 phase r/w 0 when bit 7 is the same of the bi t 3, led2 oscillate phase is the same led1. 6 reserved - - reserved 5-4 led2_s0 r/w 2?b11 indicate led2 response when system in s0 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 3 phase r/w 0 when bit 7 is the same of the bi t 3, led2 oscillate phase is the same led1. 2 reserved - - reserved 1-0 led1_s0 w 2?b00 indicate led1 response when system in s0 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state led s3/s5 ststus register ? index fah bit name r/w default description 7-6 led2_s5 r/w 2?b00 indicate led2 response when system in s5 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 5-4 led2_s3 r/w 2?b01 indicate led2 response when system in s3 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state 3-2 led1_s5 r/w 2?b11 indicate led1 response when system in s5 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state. 1-0 led1_s3 w 2?b01 indicate led1 response when system in s3 state 00:led assert 0 01: oscillate 1hz 10: oscillate 1/2hz 11: tri-state
july, 2007 v.26p 36 f71858 7.4 hardware monitor registers (index port: 0x295; data port: 0x296) 7.4.1 logic device number register logic device number register ? index 07h logic device number register ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select kbc dev ice configuration registers. 01h: select pme & acpi device configuration registers. 02h: select hardware monitor device configuration registers. 7.4.2 hardware monitor configuration registers kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hm base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hm base address. 7.4.3 hardware moni tor device register 7.4.3.1 configuration register ? index 01h bit name r/w default description 7 reserved r 0 reserved 6 reserved r/w 0 reserved 5-4 reserved r 0 reserved 3 reserved r/w 0 reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 et one to enable startup of fan monito ring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. 7.4.3.2 configuration register ? index 02h bit name r/w default description
july, 2007 v.26p 37 f71858 7-6 reserved r 0 return 0. 5-4 alert_mode r/w 0 00: the alert# will be low active level mode. 01: the alert# will be low active pulse mode. (160us) 10: the alert # will indicate by 1hz led function. 11: the alert # will indicate by (400/800hz) beep output. 4-0 reserved r 0 -- 7.4.3.3 peci sst amdsi interface configuration register ? index 0ah bit name r/w default description 7-6 reserved r/w 0 reserved. 5 t1_iir_en r/w 0 set 1 to enable the iir for amdsi/peci reading. 4 sst_en r/w 0 enable sst interface. 3-2 peci_power_sel r/w 00 00: peci output high level will be 1.23v 01: peci output high level will be 1.13v 10: peci output high level will be 1.00v 11: peci output high level will be 1.00v 1-0 meas_type r/w 0 select the cpu temperature measure method 00: external thermal diode. 01: peci interface. 10: amdsi interface. 11: reserved. 7.4.3.4 amdsi version register ? index 0bh (meas_type ==2?b10) bit name r/w default description 7-0 amdsi_ver r - when amdsi interface enable, this will be amdsi version register. return the amdsi version. 7.4.3.5 dual single core select register ? index 0bh (meas_type ==2?b01) bit name r/w default description 7-2 reserved r - reserved 1 tempvalue_sel w 0 when dual core cpu selection. tem perature value measurement method will be select by this bit. 0: average dual cores? temperature. 1: select higher one temper ature of these two cores. 0 dual core_en r / w 0 when peci interface enable, this will be dual single core select register. 0: single core cpu selection 1: dual core cpu selection 7.4.3.6 tcc activation temperature register ? index 0ch (meas_type == 2?b01) bit name r/w default description 7-0 tcc_temp r/w 0 tcc activation temperature. the absolute value of cpu temperatur e is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is 0 ~ 255. 7.4.3.7 amdsi node id register ? index 0ch (meas_type ==2?b10) bit name r/w default description 7-0 node_id r - return the amdsi node id.
july, 2007 v.26p 38 f71858 7.4.3.8 sst address register ? index 0dh bit name r/w default description 7-0 sst_addr r/w 8?h4c address for sst interface. programmable. 7.4.3.9 cpu temp. measure select register ? index 0eh bit name r/w default description 7-4 reserved - 0 reserved. 3 add r/w 0 temperature scale selection. 1: temp. measure = reading value + reading value* 2 -scale[2:0] 0: temp. measure = reading value - reading value* 2 -scale[2:0] 2-0 scale[2:0] r/w 000 when add=1, the temp. measure is 000: 1 * reading value 001: 3/2 * reading value ??.. 110: 65/64 * reading value 111: 129/128 * reading value ------------------------------------------------------------------------- when add=0, the temp. measure is 000: 1 * reading value 001: 1/2 * reading value ??.. 110: 63/64 * reading value 111: 127/128 * reading value 7.4.3.10 voltage reading and limit ? index 20h- 22h address attribute default value description 20h ro -- vcc3v reading. the unit of reading is 8mv. 21h ro -- vsb3v reading. the unit of reading is 8mv. 22h ro -- vbat3v reading. the unit of reading is 8mv. 7.4.3.11 temperature pme# enable register ? index 60h bit name r/w default description 7 reserved r 0 reserved 6 en_t2_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit6) 5 en_t1_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit5) 4 en_l_high_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit4) 3 reserved r 0 reserved 2 en_ t2_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit2) 1 en_ t1_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit1) 0 en_l_low_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. (cr61 bit0)
july, 2007 v.26p 39 f71858 7.4.3.12 temperature interrupt status register ? index 61h bit name r/w default description 7 reserved r 0 reserved 6 t2_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the temp2(cr74) exceeds the high limit(cr84) or when temperature return from over high to under low limit(cr85). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2(cr74) exceeds the high limit(cr84) or when temperature return from over high to under ?high limit ?hysteresis (cr6d)?. write 1 to clear this bit, write 0 will be ignored. 5 t1_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the temp1(cr72) exceeds the high limit(cr82) or when temperature return from over high to under low limit(cr83). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1(cr72) exceeds the high limit(cr82) or when temperature return from over high to under ?high limit ?hysteresis (cr6c)?. write 1 to clear this bit, write 0 will be ignored. 4 local_high_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? set when the local temp (cr70) exceeds the high limit(cr80) or when temperature return from over high to under low limit(cr81). write 1 to clear this bit, write 0 will be ignored. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the high limit (cr80) or when temperature return from over high to under ?high limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. 3 reserved r 0 reserved 2 t2_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the low limit (cr85) or when temperature return from over high to under ?low limit ?hysteresis (cr6d)?.. write 1 to clear this bit, write 0 will be ignored. 1 t1_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the low lim it (cr83) or when temperature return from over high to under ?low limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. 0 local_low_sts r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) ?default? this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the low limit (cr81) or when temperature return from over high to under ?low limit ?hysteresis (cr6c)?.. write 1 to clear this bit, write 0 will be ignored. 7.4.3.13 temperature real time status register ? index 62h bit name r/w default description 7 reserved r 0 reserved
july, 2007 v.26p 40 f71858 6 t2_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the temp2 exceeds the high limit (cr84). clear when the temp2 is below the low limit (cr85) ?hysteresis (cr6d) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the high limit (cr84). clear when the temp2 is below the ?high limit (cr8 4) ?hysteresis (cr6d)? temperature. 5 t1_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the temp1 exceeds the high limit(cr82). clear when the temp1 is below the low limit (cr83) ?hysteresis (cr6c) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the high limit (cr82). clear when the temp1 is below the ?high limit (cr 82)?hysteresis (cr6c)? temperature. 4 local_high_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) set when the local temp exceeds the high limit (cr80). clear when the local temp is below the low limit (cr81) ?hysteresis (cr6c) temperature. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds the high limit (cr80). clear when the local temp is below the ?high limit(cr80)?hysteresis(cr6c)? temperature. 3 reserved r 0 reserved 2 t2_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp2 exceeds the low limit (cr85). clear when the temp2 is below the ?low limit(cr85) ?hysteresis (cr6d)? temperature. 1 t1_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the temp1 exceeds the low limit (cr83). clear when the temp1 is below the ?low limit(cr83) ?hysteresis (cr6c)? temperature. 0 local_low_exc r/w 0 h_l_limit_mode set to 1 (cr69 bit 4) this bit always return 0. h_l_limit_mode set to 0 (cr69 bit 4) set when the local temp exceeds t he low limit (cr81). clear when the local temp is below the ?low limit(cr81)?hysteresis (cr6c)? temperature. 7.4.3.14 alert# output enable register 1 ? index 66h bit name r/w default description 7-3 reserved r 0h -- 2 en_t2_alert r/w 0 when t2_high_exc(cr65 bit6) is active and this bit is enabled. then pin alert# will be active and user can select alert mode from (cr02). 1 en_t1_alert r/w 1 when t1_high_exc(cr65 bit5) is active and this bit is enabled. then pin alert# will be active and user can select alert mode from (cr02). 0 en_local_alert r/w 0 when local_high_exc(cr65 bit4) is active and this bit is enabled. then pin alert# will be active and user can select alert mode from (cr02). 7.4.3.15 temperature pme# mode and table select register -- index 69h bit name r/w default description 7-5 reserved r 0h --
july, 2007 v.26p 41 f71858 4 h_l_limit_mode r/w 1 if h_l_limit_mode set to 1 temp exceeds will be set when over high limit. and clear when the temp below the low limit ?hysteresis temperature. else if h_l_limit_mode set to 0 temp exceeds will be set when over high/low limit. and clear when the temp below the ?high/low limit?hysteresis? temperature. 3-2 reserved r 0h -- 1-0 temp_table_sel r/w 2h 00: temperature display range 0?c~127?c 01: temperature display range 0?c~145?c 10: temperature display rang e -40?c ~127?c (default) 11: temperature display range -40?c ~145?c 7.4.3.16 local and temp1 limit hyst eresis select register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 0h temp1 will exceeds when over limit until under then ?limit - temp1_hys (hysteresis)? 3-0 local_hys r/w 0h l temp will exceeds when over limit until under then ?limit ? l temp_hys (hysteresis)? 7.4.3.17 temp2 and temp3 limit hyst eresis select register -- index 6dh bit name r/w default description 7-4 reserved r 0h reserved 3-0 temp2_hys r/w 0h temp2 will exceeds when over limit until under then ?limit ? temp2_hys (hysteresis)? 7.4.3.18 diode open status register -- index 6fh bit name r/w default description 7-3 reserved ro 0h reserved 2 t2_diode_open ro 0h external diode 2 is open (1) or short (0) 1 t1_diode_open ro 0h external diode 1 is open (1) or short (0) 0 t0_diode_open ro 0h internal diode 0 is open (1) or short (0) 7.4.3.19 temperature register ? index 70h- 8fh address attribute default value description 70h ro -- when temp_table_sel=0x0 (cr69) local temperature[10:3] readi ng. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 127?c, minimum display is 0?c when temp_table_sel=0x1 (cr69) local temperature[10:3] readi ng. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 145?c, minimum display is 0?c when temp_table_sel=0x2 (cr69) ?default? local temperature[10:3] readi ng. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of the local temperature. maximum display is 127?c, minimum display is -40?c when temp_table_sel=0x3 (cr69) local temperature[10:3] readi ng. the unit of reading is 1 o c.at the moment of reading this register. cr71 bit0 is the si gn bit of the local temperature. maximum display is 145?c, minimum display is -40?c (when open this byte will return 0xbb, short this byte will return 0xcc) 71h ro -- cr71 bit7-bit5 are the local temperature reading value[2:0]. the unit of reading is 0.125 o c. when temp_table_sel=0x3 (cr69)
july, 2007 v.26p 42 f71858 cr71 bit 0 is the sign bit of the local temperature. 72h ro -- when temp_table_sel=0x0 (cr69) temperature 1 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 127?c, minimum display is 0?c when temp_table_sel=0x1 (cr69) temperature 1 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 145?c, minimum display is 0?c when temp_table_sel=0x2 (cr69) ?default? temperature 1 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of t he temperature 1. maximum display is 127?c, minimum display is -40?c when temp_table_sel=0x3 (cr69) temperature 1 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. cr73 bit0 is the sign bit of the temperature 1. maximum display is 145?c, minimum display is -40?c (when open this byte will return 0xbb, short this byte will return 0xcc) 73h ro -- cr73 bit7-bit5 are the temperature 1 readin g value[2:0]. the unit of reading is 0.125 o c. when temp_table_sel=0x3 (cr69) cr73 bit 0 is the sign bi t of the temperature 1. 74h ro -- when temp_table_sel=0x0 (cr69) temperature 2[10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 127?c, minimum display is 0?c when temp_table_sel=0x1 (cr69) temperature 2 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. maximum display is 145?c, minimum display is 0?c when temp_table_sel=0x2 (cr69) ?default? temperature 2 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. bit10 is the sign bit of t he temperature 2. maximum display is 127?c, minimum display is -40?c when temp_table_sel=0x3 (cr69) temperature 2 [10:3] reading. the unit of reading is 1 o c.at the moment of reading this register. cr75 bit0 is the sign bit of the temperature 2. maximum display is 145?c, minimum display is -40?c (when open this byte will return 0xbb, short this byte will return 0xcc) 75h ro -- cr75 bit7-bit5 are the temperature 2 readin g value[2:0]. the unit of reading is 0.125 o c. when temp_table_sel=0x3 (cr69) cr75 bit 0 is the sign bi t of the temperature 2. 76-7fh ro ffh reserved 80h r/w 46h local temperature sensor high limit. the unit is 1 o c. 81h r/w 3ch local temperature sensor low limit. the unit is 1 o c. 82h r/w 64h temperature sensor 1 high limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 low limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 high limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 low limit. the unit is 1 o c. 86~8dh ro ffh reserved 7.4.3.20 temperature filter select register -- index 8eh bit name r/w default description 7-6 reserved r 0h -- 5-4 iir-queur2 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times.
july, 2007 v.26p 43 f71858 3-2 iir-queur1 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 1-0 iir-queur-local r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 16 times. (default). 10: 24 times. 11: 32 times. 7.4.3.21 fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved ro 0h reserved 2 en_fan3_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit2) 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit1) 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. (cr91 bit0) 7.4.3.22 fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved ro 0 reserved 2 fan3_sts r/w -- this bit is set when the fan3 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w -- this bit is set when the fan2 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exce eds the count limit. write 1 to clear this bit, write 0 will be ignored. 7.4.3.23 fan real time status register ? index 92h bit name r/w default description 7-3 reserved -- 0 reserved 2 fan3_exc ro -- this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 1 fan2_exc ro -- this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 0 fan1_exc ro -- this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 7.4.3.24 fan fault# enable register ? index 93h bit name r/w default description 7 reserved ro 0h reserved 6 full_with_t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4 full_with_t0_en r/w 0 set one will enable fan to force full speed when t0 (local temperature) over high limit.
july, 2007 v.26p 44 f71858 3 reserved ro 0 reserved 2 en_fan3_alert r/w 0 when fan3_exc(cr92 bit2) is active and this bit is enabled. the pin alert# will be active and user can select alert mode from (cr02). 1 en_fan2_alert r/w 0 when fan2_exc(cr92 bit1) is active and this bit is enabled. the pin alert# will be active and user can select alert mode from (cr02). 0 en_fan1_alert r/w 0 when fan1_exc(cr92 bit0) is active and this bit is enabled. the pin alert# will be active and user can select alert mode from (cr02). 7.4.3.25 fan type select register -- index 94h bit name r/w default description 7-6 reserved ro 0h reserved for fan 4 5-4 fan3_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) 3-2 fan2_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal . 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) 1-0 fan1_type r/w 1sb 00: output pwm mode (push pull) to control fans. 01: use dac mode application circuit to control fan speed by fan?s power terminal . 10: output pwm mode (open drain) to control intel 4-wire fans. 11: use dac mode application circuit to control fan speed by fan?s power terminal. bit 0 default value is trapping by pin fan3_ctrl. if pull up 10k the bit0 default value is 0, else if without pull up resister bit0 default value will be 1(for dac mode) ?s? mean default by trapping. 7.4.3.26 fan mode select register -- index 96h bit name r/w default description 7-6 reserved ro 0h reserved for fan 4 5-4 fan3_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xc6-0xce. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that define in 0xc6-0xce. 10: manual mode fan control, user can write expect rpm count to 0xc2-0xc3, and f71858 will auto contro l duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 11: reserved
july, 2007 v.26p 45 f71858 3-2 fan2_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xb6-0xbe. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle (voltage) that define in 0xb6-0xbe. 10: manual mode fan control, user can write expect rpm count to 0xb2-0xb3, and f71858 will auto contro l duty cycle (pwm fan type) or voltage (dac mode type) to control fan speed. 11: reserved 1-0 fan1_mode r/w 1h 00: auto fan speed control, fan spee d will follow different temperature by different rpm that define in 0xa6-0xae. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that define in 0xa6-0xae. 10: manual mode fan control, user can write expect rpm count to 0xa2-0xa3, and f71858 will auto contro l duty cycle (pwm fan type) or voltage(dac mode type) to control fan speed. 11: reserved. 7.4.3.27 auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the (boundar y temperature? hysteresis ). 3-0 fan1_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the (boundar y temperature ? hysteresis ). 7.4.3.28 auto fan3 boundary hystersis select register -- index 99h bit name r/w default description 7-4 reserved ro 0h reserved for fan 4 3-0 fan3_hys r/w 2h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the (boundar y temperature? hysteresis ). 7.4.3.29 fan1~fan3 duty change rate select register -- index 9bh bit name r/w default description 7-6 reserved ro 0h reserved for fan 4 5-4 fan3_rate_sel r/w 1h fan3 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_rate_sel r/w 1h fan2 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_rate_sel r/w 1h fan1 duty update rate: 00: 2.5hz 01: 5hz (default) 10: 10hz 11: 20hz
july, 2007 v.26p 46 f71858 7.4.3.30 fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_min_duty r/w 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_min_duty r/w 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 7.4.3.31 fan3 start up duty-cycle/voltage ? index 9dh bit name r/w default description 7-4 reserved ro 0h reserved 3-0 fan3_min_duty r/w 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 7.4.3.32 fan fault time register -- index 9fh bit name r/w default description 7-4 reserved -- -- reservd 3-0 f_fault_time r/w ah this register determines the time of fan fault. the condition to cause fan fault event is: when pwm_duty reaches ffh, if the fan speed count can? t reach the fan expect count in time. the unit of this register is 1 second. the default value is 11 seconds. (set to 0 , means 1 seconds. ; set to 1, means 2 seconds. set to 2, means 3 seconds. ?. ) another condition to cause fan fault event is fan stop and the pwm duty is greater than the minimum duty programmed by the register index 97-98h. fan1 index a0h- afh address attribute default value description a0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h r/w 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count value (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w 8?h01 rpm mode(cr96 bit0=0): fan1 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode(cr96
july, 2007 v.26p 47 f71858 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). 7.4.3.33 t1 boundary 1 temperature ? index a6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1temp1 r/w 46h (70 o c) the 1 st boundary temperature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index aa)h. when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 2 register (index abh). 7.4.3.34 t1 boundary 2 temperature ? index a7h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound2temp1 r/w 3c (60 o c) the 2 st boundary temperature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 expect value will load from segment 2 register (index ab)h. when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 3 register (index ach). 7.4.3.35 t1 boundary 3 temperature ? index a8h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound3temp1 r/w 32h (50 o c) the 3 st boundary temperature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 expect value will load from segment 3 register (index ac)h. when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 4 register (index adh). 7.4.3.36 t1 boundary 4 temperature ? index a9h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound4temp1 r/w 28h (40 o c) the 4 st boundary temperature for t1 in temperature mode. when t1 temperature is exceed this boundary, fan1 expect value will load from segment 4 register (index adh). when t1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 5 register (index aeh). 7.4.3.37 fan1 segment 1 speed count ? index aah bit name r/w default description
july, 2007 v.26p 48 f71858 7 - 0 sec1speed1 r / w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: s peee d full value speed expect ? ? ? ? ? ? + = 32 32 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.38 fan1 segment 2 speed count ? index abh bit name r/w default description 7 - 0 sec2speed1 r / w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.39 fan1 segment 3 speed count ? index ach bit name r/w default description 7 - 0 sec3speed1 r / w a6h (65%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.40 fan1 segment 4 speed count ? index adh bit name r/w default description 7 - 0 sec4speed1 r / w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.41 fan1 segment 5 speed count ? index aeh bit name r/w default description 7 - 0 sec5speed1 r / w 66h (40%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.42 fan1 temperature ma pping select ? index afh bit name r/w default description 7 fan1_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan1_no_stop r/w 0 set 1 that fan1 will not stop but keep at fan1_min_duty x 4.
july, 2007 v.26p 49 f71858 5 fan1_up_t_en r / w 0 set 1 to force fan1 to the highest speed if any temperature over its high limit. 4 fan1_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan1_jump_high_en r / w 1 set 1 that fan1 speed will jump to fan1 segment 1 speed when temperature over t1 boundary 1. set 0 that fan1 speed will raise up to fan1 segment 1 speed by slop value( cr9b) when temperature over t1 boundary 1. 2 fan1_jump_low_en r / w 1 set 1 that fan1 speed will jump to fan1 segment 2 speed when temperature under fan1 boundary hystersis. set 0 that fan1 speed will decrease to fan1 segment 2 speed by slop value( cr9b) when temperature under fan1 boundary hystersis. 1-0 fan1_temp_sel r/w 1 0: fan1 follows local temperature 0. 1: fan1 follows temperature 1. 2: fan1 follows temperature 2. 3: fan1 doesn?t follow and temperature, that means the auto mode function will be disabled. fan2 index b0h- bfh address attribute default value description b0h ro 8?h0f fan2 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h r/w 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count value (msb), in auto fan mode(cr96 bit3 ? 0) this register is auto updated by hardware. duty mode(cr96 bit2=1): this byte is reserved byte. b3h r/w 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb). 7.4.3.43 t2 boundary 1 temperature ? index b6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1temp2 r/w 46h (70 o c) the 1 st boundary temperature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 expect value will load from segment 1 register (index ba)h. when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 2 register (index bah).
july, 2007 v.26p 50 f71858 7.4.3.44 t2 boundary 2 temperature ? index b7h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound2temp2 r/w 3c (60 o c) the 2 st boundary temperature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 expect value will load from segment 2 register (index bb)h. when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 3 register (index bbh). 7.4.3.45 t2 boundary 3 temperature ? index b8h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound3temp2 r/w 32h (50 o c) the 3 st boundary temperature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 expect value will load from segment 3 register (index bc)h. when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 4 register (index bch). 7.4.3.46 t2 boundary 4 temperature ? index b9h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound4temp2 r/w 28h (40 o c) the 4 st boundary temperature for t2 in temperature mode. when t2 temperature is exceed this boundary, fan2 expect value will load from segment 4 register (index bdh). when t2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 5 register (index bdh). 7.4.3.47 fan2 segment 1 speed count ? index bah bit name r/w default description 7 - 0 sec1speed2 r / w ffh (100%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. speeed full value speed expect ? ? ? ? ? ? + = 32 32 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.48 fan2 segment 2 speed count ? index bbh bit name r/w default description 7 - 0 sec2speed2 r / w d9h (85%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
july, 2007 v.26p 51 f71858 7.4.3.49 fan2 segment 3 speed count ? index bch bit name r/w default description 7 - 0 sec3speed2 r / w a6h (65%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.50 fan2 segment 4 speed count ? index bdh bit name r/w default description 7 - 0 sec4speed2 r / w 80h (50%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.51 fan2 segment 5 speed count ? index beh bit name r/w default description 7 - 0 sec5speed2 r / w 66h (40%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.52 fan2 temperature ma pping select ? index bfh bit name r/w default description 7 fan2_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan2_no_stop r/w 0 set 1 that fan2 will not stop but keep at fan2_min_duty x 4. 5 fan2_up_t_en r / w 0 set 1 to force fan2 to the highest speed if any temperature over its high limit. 4 fan2_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan2_jump_high_en r / w 1 set 1 that fan2 speed will jump to fan2 segment 1 speed when temperature over t2 boundary 1. set 0 that fan2 speed will raise up to fan2 segment 1 speed by slop value( cr9b) when temperature over t2 boundary 1. 2 fan2_jump_low_en r / w 1 set 1 that fan2 speed will jump to fan2 segment 2 speed when temperature under fan2 boundary hystersis. set 0 that fan2 speed will decrease to fan2 segment 2 speed by slop value( cr9b) when temperature under fan2 boundary hystersis. 1-0 fan2_temp_sel r/w 2 0: fan2 follows local temperature 0. 1: fan2 follows temperature 1. 2: fan2 follows temperature 2. 3: fan2 doesn?t follow and temperature, that means the auto mode function will be disabled. fan3 index c0h- cfh
july, 2007 v.26p 52 f71858 address attribute default value description c0h ro 8?h0f fan3 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h r/w 8?h00 rpm mode(cr96 bit4=0): fan3 expect speed count value (msb), in auto fan mode(cr96 bit5 ? 0) this register is auto updated by hardware. duty mode(cr96 bit4=1): this byte is reserved byte. c3h r/w 8?h01 rpm mode(cr96 bit4=0): fan3 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 8?hff fan3 full speed count reading (lsb). 7.4.3.53 t0 boundary 1 temperature ? index c6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1temp3 r/w 46h (70 o c) the 1 st boundary temperature for t0 in temperature mode. when t0 temperature is exceed this boundary, fan3 expect value will load from segment 1 register (index ca)h. when t0 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 2 register (index cah). 7.4.3.54 t0 boundary 2 temperature ? index c7h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound2temp3 r/w 3c (60 o c) the 2 st boundary temperature for t0 in temperature mode. when t0 temperature is exceed this boundary, fan3 expect value will load from segment 2 register (index cb)h. when t0 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 3 register (index cbh). 7.4.3.55 t0 boundary 3 temperature ? index c8h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound3temp3 r/w 32h (50 o c) the 3 st boundary temperature for t0 in temperature mode. when t0 temperature is exceed this boundary, fan3 expect value will load from segment 3 register (index cc)h. when t0 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 4 register (index cch).
july, 2007 v.26p 53 f71858 7.4.3.56 t0 boundary 4 temperature ? index c9h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound4temp3 r/w 28h (40 o c) the 4 st boundary temperature for t0 in temperature mode. when t0 temperature is exceed this boundary, fan3 expect value will load from segment 4 register (index cdh). when t0 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 5 register (index cdh). 7.4.3.57 fan3 segment 1 speed count ? index cah bit name r/w default description 7 - 0 sec1speed3 r / w ffh (100%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. speeed full value speed expect ? ? ? ? ? ? + = 32 32 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.58 fan3 segment 2 speed count ? index cbh bit name r/w default description 7 - 0 sec2speed3 r / w d9h (85%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.59 fan3 segment 3 speed count ? index cch bit name r/w default description 7 - 0 sec3speed3 r / w a6h (65%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.60 fan3 segment 4 speed count ? index cdh bit name r/w default description 7 - 0 sec4speed3 r / w 80h (50%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
july, 2007 v.26p 54 f71858 7.4.3.61 fan3 segment 5 speed count ? index ceh bit name r/w default description 7 - 0 sec5speed3 r / w 66h (40%) the meaning of this register is depending on the fan_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 7.4.3.62 fan3 temperature ma pping select ? index cfh bit name r/w default description 7 fan3_ld_before_en r / w 0 set 1 that fan speed will keep current temp. status before system re-boot up. 6 fan3_no_stop r/w 0 set 1 that fan3 will not stop but keep at fan3_min_duty x 4. 5 fan3_up_t_en r / w 0 set 1 to force fan3 to the highest speed if any temperature over its high limit. 4 fan3_interpolation_en r/w 0 set 1 will enable the interpolati on of the fan expect table. (auto linear mode) 3 fan3_jump_high_en r / w 1 set 1 that fan3 speed will jump to fan3 segment 1 speed when temperature over t0 boundary 1. set 0 that fan3 speed will raise up to fan3 segment 1 speed by slop value( cr9b) when temperature over t0 boundary 1. 2 fan3_jump_low_en r / w 1 set 1 that fan3 speed will jump to fan3 segment 2 speed when temperature under fan3 boundary hystersis. set 0 that fan3 speed will decrease to fan3 segment 2 speed by slop value( cr9b) when temperature under fan3 boundary hystersis. 1-0 fan3_temp_sel r/w 0 0: fan3 follows local temperature 0. 1: fan3 follows temperature 1. 2: fan3 follows temperature 2. 3: fan3 doesn?t follow and temperature, that means the auto mode function will be disabled. fan4 index d0h- d1h address attribute default value description d0h ro 8?h0f fan4 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. d1h ro 8?hff fan4 count reading (lsb). 8. pcb layout guide f71858 adopts current mode measure method to do temperature detected. the measure data will not be affected by different process of cpu due to use current mode technology. this ?? |?
july, 2007 v.26p 55 f71858 technology measures mini-voltage from the remo te sensor so a good pcb layout must be cared about noise minimizing. the noises often come from circuit trace which is a track from remote sensor (cpu side) to detect circuit input (f71858 side). the signal on this track will be inducted mini-noises when it passes through a high electromagnetic area. those effects will result in the mini-noises and show in the detected side. it will be reported a wrong data which you want to measure. please pay attention and follow up the check list below in order to get an actual and real temperature inside the chip. 1. the d1+/d2+ and agnd (d-) tracks must not pass through/by pwm power-mos. keep as far as possible from power mos. 2. place a 0.1f bypass capacitor close to the v cc pin. place an external 2200pf input filter capacitors across d+, d- and close to the f71858. near the pin agnd (d-) must be placed a through hole into the gnd plane before connect to the external 2200pf capacitor. 3. place the f71858 as close as practical to the remote sensor diode. in noisy environments, such as a computer main-board, the distance can be 4 to 8 inches. (typ). this length can be increased if the worst noise sources are avoided. noise sources generally include clock generators, crts, memory buses and pci/isa bus etc. 4. separated route the d1+, d2+ with agnd (d-) tracks close together and in parallel after adding external 2200pf capacitor. for more reliable, it had better with grounded guard tracks on each side. provide a ground plane under the tracks if possible. do not route d+ & d- lines next to the deflection coil of the crt. and also don?t route the trace across fast digital signals which can easily induce bigger error. gnd gnd thermda(dxp) 10mils 10mils minimum 10mils thermdc(dxn) 10mils vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc vcc 99 d1+ agnd(d-) 89 86 2200pf f71872f 0.1uf from thermal diode thermda thermdc f71858
july, 2007 v.26p 56 f71858 5. use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. 6. try to minimize the number of component/solder joints, called through hole, which can cause thermocouple effects. where through holes are used, make sure that they are in both the d+ and d- path and at the same temperature. thermocouple effects should not be a major problem as 1 j corresponds to about 200v. it means that a copper-solder thermocouple exhibits 3v/ j , and takes about 200v of the voltage error at d+ & d- to cause a 1 j measurement error. adding a few thermocouples causes a negligible error. 7. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. it will work up to around 6 to 12 feet. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance will affect the measurement accuracy. when using long cables, the filter capacitor should be reduced or removed. cable resistance can also induce errors. for example: 1 ? series resistance introduces about 0.5 j error. 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.0 v input voltage -0.5 to vcc+0.5 v
july, 2007 v.26p 57 f71858 operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life an d reliability of the device 9.2 dc characteristics (ta = 0 c to 70 c, vcc = 3.3v 10% , vss = 0v ) parameter rating operating voltage 3.0 to 3.6 vcc/vsb operating voltage 2.4 to 3.6 vbat 9.3 dc characteristics continued (ta = 0 c to 70 c, vcc = 3.3v 10%, vss = 0v) parameter sym. min typ max. unit conditions i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability(3.3v) input low voltage vil -0.5 0.8 v input high voltage vih 2.0 vcc+ 0.3 v output low current iol 12 ma 0.4v output high current ioh 12 ma 2.4v input high leakage ilih -1 1 a input low leakage ilil -1 1 a i/od 16t-5v - ttl level bi-directional pin with 16 ma source-sink capability(3.3v), 5 tolerance input low voltage vil -0.5 0.8 v input high voltage vih 2.0 vcc+ 0.3 v output low current iol 12 ma 0.4v input high leakage ilih -1 1 a input low leakage ilil -1 1 a od 12 ? open-drain output pin with 12ma source-sink capability(3.3v) output low current 12 ma 0.4v od 12_5v ? open-drain output pin with12ma sour ce-sink capability(3.3v), 5 tolerance output low current 12 ma 0.4v od 16-u10,5v ? open-drain output pin with12ma source-sink capability(3.3v), 5 tolerance, 10k pull high output low current 12 ma 0.4v in ts ? ttl level input pin and schmitt trigger input low threshold voltage 0.8 v input hign threshold voltage 2.0 v hysteresis 0.5 v input high leakage +1 a input low leakage -1 a in ts_5v ? ttl level input pin and schmitt trigger, 5 tolerance input low threshold voltage 0.8 v input hign threshold voltage 2.0 v hysteresis 0.5 v input high leakage +1 a
july, 2007 v.26p 58 f71858 input low leakage -1 a 9.4 ac characteristics 9.4.1 ps/2 interface no. description min. max. unit t1 duration of start of receive 5 25 s t2 data valid after falling edge of ps2clk 5 t8 - 5 s t3 ps2dat setup time to falling edge of ps2clk 1 s t4 ps2dat hold time from falling edge of ps2clk 5 95 s t5 duration of inhibit ps/2 device >0 s t6 duration of data frame 2 ms t7 duration of ps2clk inactive 30 50 s t8 duration of ps2clk active 30 50 s t9 duration of ps/2 device inhibit 100 300 s t10 duration of start of transmit 15 ms t11 data valid after falling edge of ps2clk 4 s t12 ps2dat setup time to rising edge of ps2clk 1 s t13 ps2dat hold time from rising edge of ps2clk 5 95 s ps/2 interface timing table data received from ps/2 device ps2clk ps2dat t1 b0 b1 b2 b3 b4 b5 b6 b7 p stop bit start bit t3 t4 t6 1 2 3 4 5 678 910 t7 11 t8 t5 t2 host received from ps/2 interface timing diagram data sent to ps/2 device
july, 2007 v.26p 59 f71858 ps2clk ps2dat t9 t12 b0 b1 b2 b3 b4 b5 b6 b7 p stop bit start bit t11 1 2 3 4 5 678 910 11 t10 t7 t8 t13 ack t6 host send to ps/2 device timing diagram 9.4.2 lpc interface no. description min. max. unit t1 lframe# drive low after rising edge of pciclk 2 12 ns t2 lframe# drive high after rising edge of pciclk 2 12 ns t3 lda[3:0] floating after rising edge of pciclk 28 ns t4 lda[3:0] setup time to rising edge of pciclk 7 ns t5 lda[3:0] hold time from rising edge of pciclk 0 ns t6 period of pciclk 27 33 ns t7 duration of pciclk low 12 ns t8 duration of pciclk high 12 ns lpc interface timing table typical timing for host read pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t1 t2 t4 t5 t3 0110 0 - i clocks 4 or 8 clocks 2 - 2k clocks 1 - j clocks host read timing diagram typical timing for host write
july, 2007 v.26p 60 f71858 pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync data data ptar hz t6 t7 t8 host write timing diagram timing for aboart mechanism pciclk lframe# lad[3:0] start dir addr addr addr addr htar hz sync 0110 0 - i clocks 4 or 8 clocks too many syncs causes timeout sync peripheral must stop driving host will drive high host abort timing diagram 9.4.3 serialized irq interface no. description min. max. unit t1 host drive serirq low after rising edge of pciclk 2 12 ns t2 host drive serirq high after rising edge of pciclk 2 12 ns t3 slave drive serirq low after rising edge of pciclk 2 12 ns t4 slave drive serirq high after rising edge of pciclk 2 12 ns t5 period of pciclk 27 33 ns t6 duration of pciclk low 12 ns t7 duration of pciclk high 12 ns sirq interface timing table start frame timing
july, 2007 v.26p 61 f71858 pciclk serirq drive source t1 t2 4 - 8 clocks start h sl or h r t start frame irq0 frame r t s irq1 frame r t s irq2 frame r t s irq1 host controller none irq1 none h : host control sl : slave control r : recovery t : turn-around s : sample t3 t4 sirq start frame timing diagram stop frame timing pciclk serirq drive source t1 t2 2 or 3 clocks stop hr t stop frame irq14 frame r t s irq15 frame r t s iochck# frame r t s host controller none irq15 h : host control sl : slave control r : recovery t : turn-around s : sample i : idle i next cycl e none 0 - n clocks t5 t6 t7 sirq stop frame timing diagram
july, 2007 v.26p 62 f71858 10. ordering information part number package type production flow F71858DG 48-lqfp (green package) commercial, 0 c to +70 c 11. package dimensions (48lqfp) 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- please note that all datasheet and specifications are subj ect to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037
july, 2007 v.26p 63 f71858 12. application circuit fanctl1 pled fanctl3 pme# vsb5v vcc5v sst/amdsi_clk ovt# fanin2 lad3 rsmrat# vbat kdata vcc3v ps_out# ovt# kclk vcc5v md ata pwok gnd(d-) lfram# rp3 4.7k 1 2 3 4 5 6 7 8 pcirst1# ps_on# iderst# ps_in# c1 0.1u ps_in# ga20 r3 330 rp2 4.7k 1 2 3 4 5 6 7 8 fanctl2 d2+ d1 diode ovt# rstin# rsmrst# pcirst3# s3# fanin1 u7 f71858d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 lreset# lfram# lad0 lad1 lad2 lad3 pciclk serirq vcc peci/amdsi_dat fanctl1 fanctl2 fan_ctl3/hpwm_dc fanin1 fanin2 fanin3 fanin4/sst/amdsi_clk ga20 kbrst# hw_irq# gnd(d-) d1+ d2+ vcc3v rstin# pcirst1# pcirst2# pcirst3# pcirst4# pcirst5# led1 led2 s3gate ps_on# s3# s4# pme# ps_out# ps_in# vsb3v kclk kdata mc lk md ata gnd pwok rsmrst# vbat c2 0.1u s4# s3gate pwok lad0 pme# vcc3v rp1 4.7k 1 2 3 4 5 6 7 8 mc lk vsb3v rstin# serirq vsb3v devicerst# sled sled d2 diode d1+ lad1 devicerst# r2 330 vsb5v kbrst# F71858DG 0.21 F71858DG a 13 tuesday , december 19, 2006 tit le size document number rev date: sheet of vcc3v devicerst# pcirst2# rstin# fanin3 kbrst# pwok lad2 pciclk iderst# rsmrst# iderst# ps_out# ps_out# ps_in# ga20 pme# ps_on# vcc3v pled lreset# peci/amdsi_dat
july, 2007 v.26p 64 f71858 peci/amdsi_dat d1+ q1 pnp 3906 si_dat peci/amdsi_dat d2+ 300 si_clk d- c3 3300p F71858DG 0.21 temperature a 23 tuesday , december 19, 2006 tit le size document number rev date: sheet of host sst peci 100k diode sensing circuit c4 3300p amd gnd(d-) 1.8v sst gnd(d-) d1+ from cpu amdsi sst/amdsi_clk d2+ for system sst/amdsi_clk d+ 300 peci client
july, 2007 v.26p 65 f71858 r45 330 jp17 header 3 1 2 3 fanin2 r32 3.9k r17 10k fan control for pwm or dc jp6 con3 1 2 3 dc fan control with op 1 r16 4.7k r28 4.7k r30 10k +12v q3 mosfet n 2n7002 d4 1n4148 c20 47u d6 1n4148 fanin1 r41 10k q6 mosfet n 2n7002 + c15 47u d8 1n4148 r42 10k q5 nds0605/sot jp12 4 header 1 2 3 4 fanctl1 + - u2a lm358 3 2 1 8 4 (4 pin fan control) r12 4.7k jp15 header 3 1 2 3 c14 0.1u r47 10k r17 4.7k r26 0 fanctl3 r39 27k r18 10k fanin3 pwm fan 2 speed control r19 3.9k r15 4.7k c21 0.1u fanin3 vcc5v r32 27k d6 1n4148 c12 47u r42 4.7k pwm fan 3 speed control r14 4.7k q8 pnp 12v c9 0.1u r16 27k r40 4.7k pwm fan 1 speed control + c11 47u r27 27k r25 4.7k jp4 con3 1 2 3 F71858DG 0.21 fan circuit b 33 tuesday , december 19, 2006 tit le size document number rev date: sheet of r27 4.7k + - u2b lm358 5 6 7 8 4 r29 4.7k q8 nds0605/sot c18 0.1u q3 nds0605/sot r26 0 +12v q9 mosfet n 2n7002 + c7 47u fanin2 12v fanctl2 fanctl3 c17 0.1u r34 330 fanctl1 r21 10k r31 4.7k r35 10k +12v jp2 con3 1 2 3 r20 330 r31 10k + - u3a lm358 3 2 1 8 4 r44 27k vcc5v c16 47u q2 pnp vcc5v r19 27k r36 4.7k dc fan control with op 2 c14 0.1u r39 4.7k q5 pnp d4 1n4148 fanctl2 12v d8 1n4148 fanin1 r43 3.9k dc fan control with op 3 r41 4.7k
july, 2007 v.26p 66 f71858 ps2 keyboard interface c5 100p l2 fb js2 m-d i n _6-r 1 2 3 4 5 6 ps2 mouse interface md at vcc5v f1 fuse l3 fb kdat r8 4.7k l4 fb j1 con3 1 2 3 f2 fuse r7 4.7k r6 4.7k c8 100p l1 fb F71858DG 0.21 kbc a 11 tuesday , december 19, 2006 tit le size document number rev date: sheet of js1 m-d i n _6-r 1 2 3 4 5 6 c7 0.1u c10 0.1u mc lk vsb5v kclk c9 100p r5 4.7k c6 100p

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