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1/41 STA323W january 2006 1features wide supply voltage range (10-36v) 3 power output configurations ? 2x10w + 1x20w ?2x20w ?1x40w power so-36 slug down package 2.1 channels of 24-bit ddx? 100db snr and dynamic range 32khz to 192khz input sample rates digital gain/attenuation +48db to -80db in 0.5db steps 4 x 28-bit user programmable biquads (eq) per channel i 2 c control 2-channel i 2 s input data interface individual channel and master gain/ attenuation individual channel and master soft and hard mute individual channel volume and eq bypass bass/treble tone control dual independent programmable limiters/ compressors automodes? ? 32 preset eq curves ? 15 preset crossover settings ? auto volume controlled loudness ? 3 preset volume curves ? 2 preset anti-clipping modes ? preset nighttime listening mode ?preset tv agc input and output channel mapping am noise reduction and pwm frequency shifting modes soft volume update and muting auto zero detect and invalid input detect muting selectable ddx? ternary or binary pwm output + variable pwm speeds selectable de-emphasis post-eq user programmable mix with default 2.1 bass management settings variable max power correction for lower full- power thd 4 output routing configurations selectable clock input ratio 96khz internal processing sample rate, 24 to 28-bit precision qxpander video application: 576 fs input mode suporting 2description the STA323W is an integrated solution of digital audio processing, digital amplifier control, and ddx-power output stage, thereby creating a high-power single-chip ddx? solution comprising of high-quality, high-efficiency, all digital amplifica- tion. the STA323W power section consists of four in- dependent half-bridges. these can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2x10w + 1x20w of power output. 2 channels can be provid- ed by two full-bridges, providing up to 2x20w of power. the ic can also be configured as a single paralelled full-bridge capable of high-current oper- ation and 1x40w output. also provided in the STA323W are a full assort- 2.1 high efficiency digital audio system rev. 2 fi gure 1. p ac k age table 1. order codes part number package STA323W powerso36 (slug down) STA323Wtr tape & reel powerso36 slug down .com .com .com 4 .com u datasheet
STA323W 2/41 ment of digital processing features. this includes up to 4 programmable 28-bit biquads (eq) per channel, and bass/treble tone control. automodes? enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. this includes auto volume loudness, preset volume curves, preset eq settings, etc. new advanced am radio inerference reduction modes. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. three channels of ddx? processing are provided. this high quality conversion from pcm audio to ddx's patented tri-state pwm switching waveform provides over 100db snr and dynamic range. 3 ordering information figure 2. block diagram figure 3. channel signal flow diagram through the digital core 3.1 eq processing two channels of input data (re-sampled if necessary) at 96 khz are provided to the eq processing block. in this block, upto 4 user-defined biquads can be appplied to each of the two channels. pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. the entire eq block can be bypassed for all channels simulatneously by setting the dspb bit to '1'. and the cxeqbp bits can be used to bypass the eq functionality on a per channel basis. figure below shows the internal signal flow through the eq block. serial data input, channel mapping & resampling ddx ? processing quad half-bridge power stage out1a out1b out2a out2b lrcki sdi_12 sda scl pll clk eapd bicki fault twarn power-down i 2 c system contro l audio eq, mix, crossver, volume, limiter processing system timing ddx-spirit serial data input, channel mapping & resampling ddx ? processing quad half-bridge power stage out1a out1b out2a out2b lrcki sdi_12 sda scl pll clk eapd bicki fault twarn power-down i 2 c system contro l audio eq, mix, crossver, volume, limiter processing system timing ddx-spirit channel mapping re-samp ling eq processing mix volume limiter 4x interp ddx ? i 2 s input ddx outp ut crossover filter .com .com .com .com 4 .com u datasheet
3/41 STA323W figure 4. channel signal flow through the eq block figure 5. 2-channel (full-bridge) power, ocfg(1?0) = 00 figure 6. - 2.1-channel power configuration ocfg(1?0) = 01 figure 7. 1-channel mono-parallel configuration, ocfg(1?0) = 11 pre scale high-p ass filter bq#1 bq#2 bass filter de- emphasis treble filt er re-sampled input to mix bq#4 bq#3 if hpb = 0 4 biquads user defined if ameq = 00 p reset eq if ameq = 01 auto loudness if ameq = 10 if demp = 1 if cxt cb = 0 bt c: bass boost /cut ttc: treble boost/cut if dspb = 0 & cxeqb = 0 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 .com .com .com .com 4 .com u datasheet
STA323W 4/41 figure 8. block diagrams (refer to stereo application circuit) figure 9. pin description l18 22 h l19 22 h c30 100nf c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf r63 20 r98 6 r100 6 c31 1 f c52 330pf r104 20 20pf 15 m3 vcc sign vl scl sda reset bicki sdi lrcki xti 3.3v 3.3v gnd reg config v ss v dd reg vdda gnda regulators protection & logic digital pwm modulator 19 35 36 18 20 21 17 24 23 m2 m5 m4 16 out1a v cc 1a 11 10 gnd1b out1b v cc 1b 12 l113 22 h l112 22 h c32 100nf +v cc c108 470nf c33 1 f 8 m17 m15 m16 m14 9 out2a v cc 2a 4 3 gnd2b d00au1541 out2b v cc 2b 6 32 22 30 26 31 27 33 1, 2, 5, 14, gndclean 34 28 29 c110 100nf c111 100nf r103 6 r102 6 vdd gnd n.c. 7250 550pf 25 res 7 13 gnd1a gnd2a 3.3v n.c. n.c. out2b v cc 2b gnd1a v cc 1a n.c. out1a gndclean vl config reset sda scl gnd v dd v ss v cc sign 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 gndreg v dd reg out1b gnd1b v cc 1b res xti pll filter 9 8 7 28 29 30 out2a gnda 10 27 n.c. v cc 2a gnd2a v dda bicki sdi 14 12 11 23 25 26 gnd2b lrcki 13 24 .com .com .com .com 4 .com u datasheet
5/41 STA323W table 2. pin description pin type name description 1 n.c. not connected 2 n.c. not connected 3 o out2b output half bridge 2b 4 i/o vcc2b positive supply 5 n.c. not connected 6 i/o gnd2b negative supply 7 i/o gnd2a negative supply 8 i/o vcc2a positive supply 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b 11 i/o vcc1b positive supply 12 i/o gnd1b negative supply 13 i/o. gnd1a negative supply 14 n.c. not connected 15 i/o vcc1a positive supply 16 o out1a output half bridge 1a 17 i/o gndclean logical ground 18 i/o gndreg substrate ground 19 i/o vdd digital logic supply 20 i/o vl logic supply 21 i config logic levels 22 i reset reset 23 i scl i2c serial clock 24 i/o sda i2c serial data 25 res reserved test pin to be externally connected to ground 26 i pll filter connection to pll filter 27 i xti pll input clock 28 i/o analog ground analog ground 29 i/o analog supply analog supply 3.3 30 i sdi_12 i2s serial data channels 1 & 2 31 i/o lrcki i2s left/right clock, 32 i bicki i2s serial clock 33 i/o digital ground digital ground 34 i/o digital supply digital supply 3.3v 35 i/o vss digital 5v regulator referred to +vcc 36 i/o vccdigital 5v regulator referred to ground .com .com .com .com 4 .com u datasheet
STA323W 6/41 table 3. absolute maximum ratings table 4. thermal data table 5. recommended dc operating conditions 4 electrical characteristcs (v dd3 = 3.3v 0.3v; t amb = 25c; unless otherwise specified) 4.1 general interface electrical characteristics note 1: the leakage currents are generally very small, < 1na. the values given here are maximum after an electrostatic stress o n the pin. note 2: human body model 4.2 dc electrical characteristics: 3.3v buffers symbol parameter value unit v dd_3.3 3.3v i/o power supply -0.5 to 4 v v i voltage on input pins -0.5 to (vdd+0.5) v v o voltage on output pins -0.5 to (vdd+0.5) v t stg storage temperature -40 to +150 c t amb ambient operating temperature -20 to +85 c v cc dc supply voltage 40 v v max maximum voltage on pins 20 5.5 v symbol parameter min typ max unit r thj-case thermal resistance junction to case (thermal pad) 2.5 c/w t j-sd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t h-sd thermal shut-down hysteresis 25 c symbol parameter value unit v dd_3.3 i/o power supply 3.0 to 3.6 v t j operating junction temperature -20 to +125 c symbol parameter test condition min. typ. max. unit note i il low level input no pull-up v i = 0v 1 a1 i ih high level input no pull-down v i = v dd3 2 a1 i oz tristate output leakage without pullup/down v i = v dd3 2 a1 v esd electrostatic protection leakage < 1 a 2000 v 2 symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v hyst schmitt trigger hysteresis 0.4 v v ol low level output ioi = 2ma 0.15 v v oh high level output ioh = -2ma vdd -0.15 v .com .com .com .com 4 .com u datasheet
7/41 STA323W 4.3 power electrical characteristcs (v l = 3.3v; vcc = 30v; t amb = 25c unless otherwise specified symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet rdson id=1a 200 270 m ? i dss power pchannel/nchannel leakage idss vcc=35v 50 a g n power pchannel rdson matching id=1a 95 % g p power nchannel rdson matching id=1a 95 % dt_s low current dead time (static) see test circuit no.1; see fig. 1 10 20 ns t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load 25 ns t f fall time resistive load; as fig. 1 25 ns v cc supply voltage operating voltage 10 36 v v l low logical state voltage vl v l = 3.3v 0.8 v v h high logical state voltage vh v l = 3.3v 1.7 v i vcc- pwrdn supply current from vcc in pwrdn pwrdn = 0 3 ma i vcc-hiz supply current from vcc in tri- state vcc=30v; tri-state 22 ma i vcc supply current from vcc in operation (both channel switching) input pulse width = 50% duty; switching frequency = 384khz; no lc filters; 80 ma i out-sh overcurrent protection threshold (short circuit current limit) 46 a v uv undervoltage protection threshold 7 v t pw-min output minimum pulse width no load 70 150 ns p o output power (refer to test circuit thd = 10% r l = 8 ? ; v s = 18v 20 w p o output power (refer to test circuit thd = 1% r l = 8 ? ; v s = 18v 16 w .com .com .com .com 4 .com u datasheet
STA323W 8/41 5 functional description 5.1 pin description 5.1.1 out1a, 1b, 2a & 2b (pins 16, 10, 9 & 3) output half bridge pwm outputs 1a, 1b, 2a & 2b provide the inputs signals to the speaker devices. 5.1.2 reset (pin 22) driving reset low sets all outputs low and returns all register settings to their defaults. the reset is asyn- chronous to the internal clock. 5.1.3 i 2 c signals (pins 23 & 24) the sda (i2c data) and scl (i2c clock) pins operate per the i2c specification. see section 4.0. fast- mode (400kb/sec) i2c communication is supported. 5.1.4 gnda & vdda: phase locked loop power (pins 28-29) the phase locked loop power is applied here. this +3.3v supply must be well bypassed and filtered for noise immunity. the audio performance of the device is critically dependent upon the pll circuit. 5.1.5 clk: master clock in (pin 27) this is the master clock in required for the operation of the digital core. the master clock must be an in- teger multiple of the lr clock frequency. typically, the master clock frequency is 12.288 mhz (256*fs) for a 48khz sample rate, which is the default at power-up. care must be taken to avoid over-clocking the device i.e provide the device with the nominally required system clock; otherwise, the device may not prop- erly operate or be able to communicate. 5.1.6 filter_pll: pll filter (pin 26) pll filter connects to external filter components for pll loop compensation. refer to the schematic dia- gram for the recommended circuit. 5.1.7 bicki: bit clock in (pin 32) the serial or bit clock input is for framing each data bit. the bit clock frequency is typically 64*fs, for ex- ample using i2s serial format. 5.1.8 sdi_12: serial data input (pin 30) pcm audio information enters the device here. six format choices are available including i2s, left- or right- justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. 5.1.9 lrcki: left/right clock in (pin 31) the left/right clock input is for data word framing. the clock frequency will be at the input sample rate fs. 5.2 audio performance tbd 5.3 pin connection (top view) 6 STA323W i 2 c bus specification the STA323W supports the i2c protocol. this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data trans- fer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA323W is always a slave device in all of its communications. .com .com .com .com 4 .com u datasheet
9/41 STA323W 6.1 communication protocol 6.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 6.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 6.1.3 stop condition stop is identified by a low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA323W and the bus master. 6.1.4 data input during the data input the STA323W samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 6.2 device addressing to start communication between the master and the STA323W, the master must initiate with a start con- dition. following this, the master sends 8-bits (msb first) onto the sda line corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i2c bus definition. in the STA323W the i2c interface uses a device addresse of 0x34 or 0011010x. the 8th bit (lsb) identifies read or write operation, rw. this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA323W identifies the device address on the bus. if a match is found, it acknowledges the identification on the sda bus during the 9th bit time. the byte following the device identification byte is the internal space address. 6.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA323W acknowledges this and then the master writes the internal address byte. after receiving the internal byte address the STA323W again responds with an acknowledgement. 6.3.1 byte write in the byte write mode the master sends one data byte. this is acknowledged by the STA323W. the master then terminates the transfer by generating a stop condition. 6.3.2 multi-byte write the multi-byte write modes can start from any internal address. sequential data byte writes will be written to sequential addresses within the STA323W. the master generating a stop condition terminates the transfer. 6.4 read operation 6.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA323W acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. .com .com .com .com 4 .com u datasheet
STA323W 10/41 6.4.1.1current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes will be read from sequential addresses within the STA323W. the master acknowledges each data byte read and then gen- erates a stop condition terminating the transfer. 6.4.2 random address byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA323W acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the STA323W again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA323W ac- knowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 6.4.2.1random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes will be read from sequential addresses within the STA323W. the master acknowledges each data byte read and then gen- erates a stop condition terminating the transfer. 6.5 write mode sequence figure 10. i 2 c write procedure 6.6 read mode sequence figure 11. i 2 c read procedure dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high .com .com .com .com 4 .com u datasheet
11/41 STA323W 7 register description table 6. register summary address name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc csz4 csz3 csz2 csz1 csz0 om1 om0 0x03 confd mme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame res mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 0x06 mmute mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0a c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0b auto1 amps amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x0c auto2 xo3 xo2 xo1 xo1 amam2 amam1 amam0 amame 0x0d auto3 peq4 peq3 peq2 peq1 peq0 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x1f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x1a b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x1b b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x1c b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x1d a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 0x1e a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x1f a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x20 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x21 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x22 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x23 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x24 b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x25 b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x26 cfud wa w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29resresresresresresresresres 0x2aresresresresresresresresres 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul fault twarn .com .com .com .com 4 .com u datasheet
STA323W 12/41 7.1 configuration register a (address 00h) 7.1.1 master clock select the STA323W will support sample rates of 32khz, 44.1khz, 48khz, 88.2khz, and 96khz. therefore the internal clock will be: 32.768mhz for 32khz 45.1584mhz for 44.1khz, 88.2khz, and 176.4khz 49.152mhz for 48khz, 96khz, and 192khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (fs). the correlation between the input clock and the input sample rate is determined by the status of the mcsx bits and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. table 7. ir and mcs settings for input sample rate and clock rate 7.1.2 interpolation ratio select the STA323W has variable interpolation (re-sampling) settings such that internal processing and ddx output rates remain consistent. the first processing block interpolates by either 2 times or 1 time (pass- through) or provides a down-sample by a factor of 2. the ir bits determine the re-sampling ratio of this interpolation. table 8. ir bit settings as a function of input sample rate d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 bit r/w rst name description 0 r/w 1 mcs0 master clock select: selects the ratio between the input i 2 s sample frequency and the input clock. 1r/w 1 mcs1 2r/w 0 mcs2 input sample rate fs (khz) ir mcs(2..0) 000 001 010 011 100 101 32, 44.1, 48 00 768fs 512fs 384fs 256fs 128fs 576fs 88.2, 96 01 384fs 256fs 192fs 128fs 64fs x 176.4, 192 1x 384fs 256fs 192fs 128fs 64fs x bit r/w rst name description 4...3 r/w 00 ir (1...0) interpolation ratio select: selects internal interpolation ratio based on input i 2 s sample frequency input sample rate fs (khz) ir (1,0) 1 st stage interpolation ratio 32 00 2 times over-sampling 44.1 00 2 times over-sampling 48 00 2 times over-sampling 88.2 01 pass-through 96 01 pass-through 176.4 10 down-sampling by 2 192 10 down-sampling by 2 .com .com .com .com 4 .com u datasheet
13/41 STA323W 7.1.3 thermal warning recovery bypass if the thermal warning adjustment is enabled (twab=0), then the thermal warning recovery will deter- mine if the adjustment is removed when thermal warning is negative. if twrb=0 and twab=0, then when a thermal warning disappears the gain adjustment determined by the thermal warning post- scale(default = -3db) will be removed and the gain will be added back to the system. if twrb=1 and twab=0, then when a thermal warning disappears the thermal warning post-scale gain adjustment will remain until twrb is changed to zero or the device is reset. 7.1.4 thermal warning adjustment bypass the on-chip STA323W power output block provides feedback to the digital controller using inputs to the power control block. the twarn input is used to indicate a thermal warning condition. when twarn is asserted (set to 0) for a period greater than 400ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. once the thermal warning volume adjustment is applied, whether the gain is reapplied when twarn is de-asserted is dependent on the twrb bit. 7.1.5 fault detect recovery bypass the ddx power block can provide feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either over-current or thermal). when fault is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the tri- state output (setting it to 0 which directs the power output block to begin recovery). it holds it at 0 for period of time in the range of .1ms to 1 second as defined by the fault-detect recovery constant register (fdrc registers 29-2ah), then toggle it back to 1. this sequence is repeated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. 7.2 configuration register b (address 01h) 7.2.1 serial audio input interface format bit r/w rst name description 5 r/w 1 twrb thermal-warning recovery bypass: 0 ? thermal warning recovery enabled 1 ? thermal warning recovery disabled bit r/w rst name description 6 r/w 1 twab thermal-warning adjustment bypass: 0 ? thermal warning adjustment enabled 1 ? thermal warning adjustment disabled bit r/w rst name description 7 r/w 0 fdrb fault detector recovery bypass: 0 ? fault detector recovery enabled 1 ? fault detector recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c1im c1im dscke saifb sai3 sai2 sai1 sai0 1 0 0 0 0000 bit r/w rst name description 3?0 r/w 0000 sai (3...0) serial audio input interface format: determines the interface format of the input serial digital audio interface. .com .com .com .com 4 .com u datasheet
STA323W 14/41 7.3 serial data interface the STA323W serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. the STA323W always acts as a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using 3 input pins: left/ right clock lrcki (pin 33), serial clock bicki (pin 31), and serial data 1 & 2 sdi12 (pin 32). the sai register (configuration register b - 01h, bits d3-d0) and the saifb register (configuration reg- ister b - 01h, bit d4) are used to specify the serial data format. the default serial data format is i2s, msb- first. available formats are shown in figure 11 and the tables that follow. figure 12. general serial input and output formats for example, sai=1110 and saifb=1 would specify right-justified 16-bit data, lsb-first. table 10 below lists the serial audio input formats supported by STA323W as related to bicki = 32/48/ 64fs, where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 khz. table 9. first bit selection table note: serial input and output formats are specified distinctly. saifb format 0 msb-first 1 lsb-first i 2 s left justified lrclk left right sclk sdata lsb msb lsb msb msb lrclk left right sclk sdata lsb msb lsb msb msb right justified lrclk left right sclk sdata lsb msb lsb msb msb .com .com .com .com 4 .com u datasheet
15/41 STA323W table 10. supported serial audio input formats table 11. serial input data timing characteristics (fs = 32 to 192khz) bicki sai (3...0) saifb interface format 32fs 1100 x i 2 s 15bit data 1110 x left/right-justified 16bit data 48fs 0100 x i 2 s 23bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0100 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 1110 x right-justified 16bit data 64fs 0000 x i 2 s 24bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0000 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 1110 x right-justified 16bit data bicki frequency (slave mode) 12.5mhz max. bicki pulse width low (t0) (slave mode) 40 ns min. bicki pulse width high (t1) (slave mode) 40 ns min. bicki active to lrcki edge delay (t2) 20 ns min. bicki active to lrcki edge delay (t3) 20 ns min. sdi valid to bicki active setup (t4) 20 ns min. bicki active to sdi hold time (t5) 20 ns min. .com .com .com .com 4 .com u datasheet
STA323W 16/41 figure 13. 7.3.1 delay serial clock enable 7.3.2 channel input mapping each channel received via i2s can be mapped to any internal processing channel via the channel input mapping registers. this allows for flexibility in processing. the default settings of these registers map each i2s input channel to its corresponding processing channel. 7.4 configuration register c (address 02h) 7.4.1 ddx ? power output mode the ddx? power output mode selects how the ddx? output timing is configured. different power de- vices can use different output modes. the ddx-2060/2100/2160 recommended use is om = 10. when om=11 the csz bits determine the size of the ddx? compensating pulse. bit r/w rst name description 5 r/w 0 dscke delay serial clock enable: 0 ? no serial clock delay 1 ? serial clock delay by 1 core clock cycle to tolerate anomalies in some i 2 s master devices bit r/w rst name description 6r/w 0 c1im 0 ? processing channel 1 receives left i 2 s input 1 ? processing channel 1 receives right i 2 s input 7r/w 1 c2im 0 ? processing channel 2 receives left i 2 s input 1 ? processing channel 2 receives right i 2 s input d7 d6 d5 d4 d3 d2 d1 d0 csz4 csz3 csz2 csz1 csz0 om1 om0 1000010 bit r/w rst name description 1...0 r/w 10 om (1...0) ddx power output mode: selects configuration of ddx ? output. bicki t 0 t1 lrcki t 2 t3 sdi t4 t5 .com .com .com .com 4 .com u datasheet
17/41 STA323W table 12. ddx? output modes 7.4.2 5.3.2ddx? variable compensating pulse size the ddx? variable compensating pulse size is intended to adapt to different power stage ics. contact apogee applications for support when deciding this function. table 13. ddx? compensating pulse 7.5 configuration register d (address 03h) 7.5.1 high-pass filter bypass the STA323W features an internal digital high-pass filter for the purpose of dc blocking. the purpose of this filter is to prevent dc signals from passing through a ddx? amplifier. dc signals can cause speaker damage. 7.5.2 de-emphasis by setting this bit to high, or one (1), de-emphasis will implemented on all channels. dspb (dsp bypass, bit d2, cfa) bit must be set to 0 for de-emphasis to function. om (1,0) output stage ? mode 00 not used 01 not used 10 ddx-2060/2100/2160 11 variable compensation csz (4?0) compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ?? 10000 16 clock period compensating pulse size ?? 11111 31 clock period compensating pulse size d7 d6 d5 d4 d3 d2 d1 d0 mme zde drc bql psl dspb demp hpb 00000 0 0 0 bit r/w rst name description 0 r/w 0 hpb high-pass filter bypass bit. 0 ? ac coupling high pass filter enabled 1 ? ac coupling high pass filter disabled bit r/w rst name description 1 r/w 0 demp de-emphasis: 0 ? no de-emphasis 1 ? de-emphasis .com .com .com .com 4 .com u datasheet
STA323W 18/41 7.5.3 dsp bypass setting the dspb bit bypasses all the eq and mixing functionality of the STA323W core. 7.5.4 post-scale link post-scale functionality is an attenuation placed after the volume control and directly before the conver- sion to pwm. post-scale can also be used to limit the maximum modulation index and therefore the peak current. a setting of 1 in the psl register will result in the use of the value stored in channel 1 post-scale for all three internal channels. 7.5.5 biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 7.5.6 dynamic range compression/anti-clipping bit both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dy- namic range compression mode the limiter threshold values vary with the volume settings allowing a night- time listening mode that provides a reduction in the dynamic range regardless of the volume level. 7.5.7 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. when zde=1, the zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this func- tion is enabled. 7.5.8 1.1.5miami modetm enable bit r/w rst name description 2 r/w 0 dspb dsp bypass bit: 0 ? normal operation 1 ? bypass of eq and mixing functionality bit r/w rst name description 3 r/w 0 psl post-scale link: 0 ? each channel uses individual post-scale value 1 ? each channel uses channel 1 post-scale value bit r/w rst name description 4 r/w 0 bql biquad link: 0 ? each channel uses coefficient values 1 ? each channel uses channel 1 coefficient values bit r/w rst name description 5 r/w 0 drc dynamic range compression/anti-clipping 0 ? limiters act in anti-clipping mode 1 ? limiters act in dynamic range compression mode bit r/w rst name description 6 r/w 1 zde zero-detect mute enable: setting of 1 enables the automatic zero- detect mute bit r/w rst name description 7 r/w 0 mme miami-mode enable: 0 ? sub mix into left/right disabled 1 ? sub mix into left/right enabled .com .com .com .com 4 .com u datasheet
19/41 STA323W 7.6 configuration register e (address 04h) 7.6.1 max power correction variable by enabling mpc and setting mpcv = 1, the max power correction becomes variable. by adjusting the mpcc registers (address 0x27-0x28) it becomes possible to adjust the thd at maximum unclipped power to a lower value for a particular application. 7.6.2 max power correction setting the mpc bit corrects the ddx-2060/2100/2160 power device at high power. this mode will lower the thd+n of a full ddx-2060 ddx ? system at maximum power output and slightly below. 7.6.3 am mode enable the STA323W features a ddx ? processing mode that minimizes the amount of noise generated in the frequency range of am radio. this mode is intended for use when ddx ? is operating in a device with an active am tuner. the snr of the ddx ? processing is reduced to ~83db in this mode, which is still greater than the snr of am radio. 7.6.4 pwm speed mode table 14. pwm output speed selections d7 d6 d5 d4 d3 d2 d1 d0 sve zce res pwms ame res mpc mpcv 000 0 0 0 0 0 bit r/w rst name description 0 r/w 0 mpcv max power correction variable: 0 ? use standard mpc coefficient 1 ? use mpcc bits for mpc coefficient bit r/w rst name description 7 r/w 1 mpc max power correction: 0 ? mpc disabled 1 ? mpc enabled bit r/w rst name description 3 r/w 0 ame am mode enable: 0 ? normal ddx ? operation. 1 ? am reduction mode ddx ? operation. bit r/w rst name description 4 r/w 0 pwms pwm speed selection: normal or odd pwms (1...0) pwm output speed 0 normal speed (384khz) all channels 1 odd speed (341.3khz) all channels .com .com .com .com 4 .com u datasheet
STA323W 20/41 7.6.5 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-cross- ings no clicks will be audible. 7.6.6 soft volume update enable the STA323W includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. by setting sve=0 this can be bypassed and volume changes will jump from old to new value directly. this feature is only available if individual channel volume bypass bit is set to ?0?. 7.7 configuration register f (address 05h) 7.7.1 output configuration selection table 15. output configuration selections 7.7.2 nvalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and clocking and will automati- cally mute all outputs if the signals are perceived as invalid. bit r/w rst name description 6 r/w 1 zce zero-crossing volume enable: 1 ? volume adjustments will only occur at digital zero-crossings 0 ? volume adjustments will occur immediately bit r/w rst name description 7 r/w 1 sve soft volume enable: 1 ? volume adjustments will use soft volume 0 ? volume adjustments will occur immediately d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle res bcle ide ocfg1 ocfg0 0 1 0111 1 0 bit r/w rst name description 1?0 r/w 00 ocfg (1?0) output configuration selection 00 ? 2-channel (full-bridge) power, 1-channel ddx is default ocfg (1...0) output power configuration 00 2 channel (full-bridge) power, 1 channel ddx: 1a/1b ? 1a/1b 2a/2b ? 2a/2b 01 2(half-bridge).1(full-bridge) on-board power: 1a ? 1a binary 2a ? 1b binary 3a/3b ? 2a/2b binary 10 reserved 11 1 channel mono-parallel: 3a ? 1a/1b 3b ? 2a/2b bit r/w rst name description 2 r/w 1 ide invalid input detect auto-mute enable: 0 ? disabled 1 ? enabled .com .com .com .com 4 .com u datasheet
21/41 STA323W 7.7.3 binary clock loss detection enable detects loss of input mclk in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. 7.7.4 auto-eapd on clock loss enable when ecle is active, it issues a power device power down signal (eapd) on clock loss detection. 7.7.5 external amplifier power down eapd is used to actively power down a connected ddx ? power device. this register has to be written to 1 at start-up to enable the ddx ? power device for normal operation. 7.8 volume control 7.8.1 master controls 7.8.1.1master mute register (address 06h) 7.8.1.2master volume register (address 07h) note : value of volume derived from mvol is dependent on amv automode volume settings. 7.8.2 channel controls 7.8.2.1channel 1 volume (address 08h) bit r/w rst name description 5 r/w 1 bcle binary output mode clock loss detection enable 0 ? disabled 1 ? enabled bit r/w rst name description 7 r/w 0 ecle auto eapd on clock loss 0 ? disabled 1 ? enabled bit r/w rst name description 7 r/w 0 eapd external amplifier power down: 0 ? external power stage power down active 1 ? normal operation d7 d6 d5 d4 d3 d2 d1 d0 mmute 0 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 .com .com .com .com 4 .com u datasheet
STA323W 22/41 7.8.2.2channel 2 volume (address 09h) 7.8.2.3channel 3 volume (address 0ah) 7.8.3 volume description the volume structure of the STA323W consists of individual volume registers for each of the three chan- nels and a master volume register, and individual channel volume trim registers. the channel volume set- tings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. these values are normally set at the initialization of the ic and not changed. the individual channel volumes are adjustable in 0.5db steps from +48db to -80 db. the master volume control is normally mapped to the master volume of the system. the values of these two settings are summed to find the actual gain/volume value for any given channel. when set to 1, the master mute will mute all channels, whereas the individual channel mutes (cxm) will mute only that channel. both the master mute and the channel mutes provide a ?soft mute? with the vol- ume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (~96khz). a ?hard mute? can be obtained by commanding a value of all 1?s (ffh) to any channel vol- ume register or the master volume register. when volume offsets are provided via the master volume reg- ister any channel whose total volume is less than ?100db will be muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register e) on a per chan- nel basis as this creates the smoothest possible volume transitions. when zce=0, volume updates will occur immediately. the STA323W also features a soft-volume update function that will ramp the volume between intermedi- ate values when the value is updated, when sve = 1 (configuration register e). this feature can be dis- abled by setting sve = 0. each channel also contains an individual channel volume bypass. if a particular channel has volume by- passed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. also, master soft-mute will not affect the channel if cxvbp = 1. each channel also contains a channel mute. if cxm = 1 a soft mute is performed on that channel table 16. master volume offset as a function of mv (7..0). d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 mv (7..0) volume offset from channel value 00000000 (00h) 0db 00000001 (01h) -0.5db 00000010 (02h) -1db ?? 01001100 (4ch) -38db ?? 11111110 (feh) -127db 11111111 (ffh) hard master mute .com .com .com .com 4 .com u datasheet
23/41 STA323W table 17. channel volume as a function of cxv (7..0) 7.9 automode registers 7.9.1 register ? automodes eq, volume, gc (address 0bh) table 18. automode eq by setting ameq to any setting other than 00 enables automode eq. when set, biquads 1-4 are not user programmable. any coefficient settings for these biquads will be ignored. also when automode eq is used the pre-scale value for channels 1-2 becomes hard-set to ?18db. table 19. automode volume cxv (7..0) volume 00000000 (00h) +48db 00000001 (01h) +47.5db 00000010 (02h) +47db ?? 01100001 (5fh) +0.5db 01100000 (60h) 0db 01011111 (61h) -0.5db ?? 11111110 (feh) -79.5 db 11111111 (ffh) hard channel mute d7 d6 d5 d4 d3 d2 d1 d0 amps amgc1 amgc0 amv1 amv0 ameq1 ameq0 1000000 ameq (1,0) mode (biquad 1-4) 00 user programmable 01 preset eq ? peq bits 10 auto volume controlled loudness curve 11 not used amv (1,0) mode (mvol) 00 mvol 0.5db 256 steps (standard) 01 mvol auto curve 30 steps 10 mvol auto curve 40 steps 11 mvol auto curve 50 steps .com .com .com .com 4 .com u datasheet
STA323W 24/41 table 20. automode gain compression/limiters 7.9.2 amps ? automode auto prescale 7.9.3 register ? automode am/pre-scale/bass management scale (address 0ch) 7.9.3.1automode am switching enable table 21. automode am switching frequency selection when ddx ? is used concurrently with an am radio tuner, it is advisable to use the amam bits to automat- ically adjust the output pwm switching rate dependent upon the specific radio frequency that the tuner is receiving. the values used in amam are also dependent upon the sample rate determined by the adc used. 7.9.3.2automode crossover setting amgc (1...0) mode 00 user programmable gc 01 ac no clipping 10 ac limited clipping (10%) 11 drc nighttime listening mode bit r/w rst name description 0 r/w 0 amps automode pre-scale 0 ? -18db used for pre-scale when ameq /= 00 1 ? user defined pre-scale when ameq /= 00 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000 bit r/w rst name description 0 r/w 0 amame automode am enable 0 ? switching frequency determined by pwms setting 1 ? switching frequency determined by amam settings 3?1 r/w 000 amam (2?0) am switching frequency setting default: 000 amam (2..0) 48khz/96khz input fs 44.1khz/88.2khz input fs 000 0.535mhz ? 0.720mhz 0.535mhz ? 0.670mhz 001 0.721mhz ? 0.900mhz 0.671mhz ? 0.800mhz 010 0.901mhz ? 1.100mhz 0.801mhz ? 1.000mhz 011 1.101mhz ? 1.300mhz 1.001mhz ? 1.180mhz 100 1.301mhz ? 1.480mhz 1.181mhz ? 1.340mhz 101 1.481mhz ? 1.600mhz 1.341mhz ? 1.500mhz 110 1.601mhz ? 1.700mhz 1.501mhz ? 1.700mhz bit r/w rst name description 7?4 r/w 0 xo (3?0) automode crossover frequency selection 000 ? user defined crossover coefficients are used otherwise ? preset coefficients for the crossover setting desired .com .com .com .com 4 .com u datasheet
25/41 STA323W table 22. crossover frequency selection 7.9.4 register - preset eq settings (address 0dh) table 23. preset eq selection xo (2..0) bass management - crossover frequency 0000 user 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz d7 d6 d5 d4 d3 d2 d1 d0 peq4 peq3 peq2 peq1 peq0 00000 peq (3..0) setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 (least boost) 10001 loudness 2 10010 loudness 3 10011 loudness 4 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 (most boost) .com .com .com .com 4 .com u datasheet
STA323W 26/41 7.10 channel configuration registers 7.10.1channel 1 configuration (address 0eh) 7.10.2channel 2 configuration (address 0fh) 7.10.3channel 3 configuration (address 10h) eq control can be bypassed on a per channel basis. if eq control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. cxeqbp: ? 0 perform eq on channel x ? normal operation ? 1 bypass eq on channel x tone control (bass/treble) can be bypassed on a per channel basis. if tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed. cxtcb: ? 0 perform tone control on channel x ? (default operation) ? 1 bypass tone control on channel x each channel can be configured to output either the patented ddx pwm data or standart binary pwm encoded data. by setting the cxbo bit to ?1?, each channel can be individually controlled to be in binary operation mode. also, there is the capability to map each channel independently onto any of the two limiters available within the STA323W or even not map it to any limiter at all (default mode). table 24. channel limiter mapping selection each pwm output channel can receive data from any channel output of the volume block. which channel a particular pwm output receives is dependent upon that channel?s cxom register bits. d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 000000 00 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp 000000 cxls (1,0) channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 .com .com .com .com 4 .com u datasheet
27/41 STA323W table 25. channel pwm output mapping 7.11 tone control (address 11h) table 26. tone control boost/cut selection 7.12 dynamics control 7.12.1limiter 1 attack/release threshold (address 12h) cxom (1...0) pwm output from 00 channel 1 01 channel 2 10 channel 3 11 not used d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 btc (3...0)/ttc (3...0) boost/cut 0000 -12db 0001 -12db ?? 0111 -4db 0110 -2db 0111 0db 1000 +2db 1001 +4db ?? 1101 +12db 1110 +12db 1111 +12db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 .com .com .com .com 4 .com u datasheet
STA323W 28/41 7.12.2limiter 1 attack/release threshold (address 13h) 7.12.3limiter 2 attack/release rate (address 14h) 7.12.4limiter 2 attack/release threshold (address 15h) 7.12.5dynamics control description the STA323W includes 2 independent limiter blocks. the purpose of the limiters is to automatically re- duce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for dvds.) the two modes are selected via the drc bit in configuration register d, bit 5 address 0x03. each channel can be mapped to limiter1, limiter2, or not mapped. if a channel is not mapped, that channel will clip normally when 0 db fs is exceeded. each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers. when the attack thesehold has been exceeded, the limiter, when active, will automatically start reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through an rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range. this is helpful as over-limiting can reduce the dynam- ic range to virtually zero and cause program material to sound ?lifeless?. in ac mode the attack and release thresholds are set relative to full-scale. in drc mode the attack thresh- old is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101 0 0 1 .com .com .com .com 4 .com u datasheet
29/41 STA323W figure 14. - basic limiter and volume flow diagram gain attenuation saturation rms limiter gain/volume input output table 27. limiter attack rate selection table 28. limiter release rate selection lxa (3...0) attack rate db/ms 0000 3.1584 fast 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 slow lxr (3...0) release rate db/ms 0000 0.5116 fast 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 slow .com .com .com .com 4 .com u datasheet
STA323W 30/41 7.12.6anti-clipping mode table 29. limiter attack threshold selection (ac-mode) table 30. limiter release threshold selection (ac-mode). 7.12.7dynamic range compression mode table 31. limiter attack threshold selection (drc-mode) . table 32. limiter release threshold selection (drc-mode).( lxat (3...0) ac (db relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 lxrt (3...0) ac (db relative to fs) 0000 - 0001 -29db 0010 -20db 0011 -16db 0100 -14db 0101 -12db 0110 -10db 0111 -8db 1000 -7db 1001 -6db 1010 -5db 1011 -4db 1100 -3db 1101 -2db 1110 -1db 1111 -0db lxat (3...0) drc (db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 lxrt (3...0) drc (db relative to volume + lxat) 0000 - 0001 -38db 0010 -36db 0011 -33db 0100 -31db 0101 -30db 0110 -28db 0111 -26db 1000 -24db 1001 -22db 1010 -20db 1011 -18db 1100 -15db 1101 -12db 1110 -9db 1111 -6db .com .com .com .com 4 .com u datasheet
31/41 STA323W 8 user programmable processing 8.1 eq - biquad equation the biquads use the equation that follows. this is diagrammed in figure 14 below. y[n] = 2(b0/2)x[n] + 2(b1/2)x[n-1] + b2x[n-2] - 2(a1/2)y[n-1] - a2y[n-2] = b0x[n] + b1x[n-1] + b2x[n-2] - a1y[n-1] - a2y[n-2] where y[n] represents the output and x[n] represents the input. multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 800000h (-1) to 7fffffh (0.9999998808). coefficients stored in the user defined coefficient ram are referenced in the following manner: ? cxhy0 = b1/2 ?cxhy1 = b2 ?cxhy2 = -a1/2 ?cxhy3 = -a2 ? cxhy4 = b0/2 the x represents the channel and the y the biquad number. for example c3h41 is the b0/2 coefficient in the fourth biquad for channel 3 figure 15. - biquad filter 8.2 pre-scale the pre-scale block which precedes the first biquad is used for attenuation when filters are designed that boost frequencies above 0dbfs. this is a single 28-bit signed multiplier, with 800000h = -1 and 7fffffh = 0.9999998808. by default, all pre-scale factors are set to 7fffffh. 8.3 post-scale the STA323W provides one additional multiplication after the last interpolation stage and before the dis- tortion compensation on each channel. this is a 24-bit signed fractional multiplier. the scale factor for this multiplier is loaded into ram using the same i2c registers as the biquad coefficients and the mix. all channels can use the same settings as channel 1 by setting the post-scale link bit. 8.4 mix/bass management the STA323W provides a post-eq mixing block per channel. each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. these coefficients are accessible via the user controlled coefficient ram described below. the mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (- 8388608) are used used to provide three channels of output from two channels of filtered input. + + + 2 2 -a 2 -a 1 /2 b 2 b 1 /2 b 0 /2 z -1 z -1 z -1 z -1 2 .com .com .com .com 4 .com u datasheet
STA323W 32/41 table 33. mix/bass management block diagram after a mix is achieved, STA323W also provides the capability to implement crossver filters on all channels corresponding to 2.1 bass management solution. channels 1-2 use a 1st order high-pass filter and chan- nel 3 uses a 2nd order low-pass filter corresponding to the setting of the xo bits of i2c register 0ch. if xo = 000, user specified crossover filters are used. by default these coefficients correspond to pass-through. however, the user can write these coefficients in a similar way as the eq biquads. when user-defined setting is selected, the user can only write 2nd order crossover filters. this output is then passed on to the volume/limiter block. 8.5 calculating 24-bit signed fractional numbers from a db value the pre-scale, mixing, and post-scale functions of the STA323W use 24-bit signed fractional multipliers to attenuate signals. these attenuations can also invert the phase and therefore range in value from -1 to +1. it is possible to calculate the coefficient to utilize for a given negative db value (attenuation) via the equations below. ? non-inverting phase numbers 0 to +1 : ? coefficient = round(8388607 * 10^(db/20)) ? inverting phase numbers 0 to -1 : ? coefficient = 16777216 - round(8388607 * 10^(db/20)) as can be seen by the preceding equations, the value for positive phase 0db is 0x7fffff and the value for negative phase 0db is 0x800000. c1mx1 c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 high-pass xo filter high-pass xo filter low -pass xo filter user-defined mix coefficients crossover frequency determined by xo setting. user-defined when xo = 000 channel #1 from eq channel #2 from eq channel#1 to gc/vol channel#2 to gc/vol channel#3 to gc/vol + + + .com .com .com .com 4 .com u datasheet
33/41 STA323W 8.6 user defined coefficient ram 8.6.1 coefficient address register 1 (address 16h) 8.6.2 coefficient b1data register bits 23...16 (address 17h) 8.6.3 coefficient b1data register bits 15...8 (address 18h) 8.6.4 coefficient b1data register bits 7...0 (address 19h) 8.6.5 coefficient b2 data register bits 23...16 (address 1ah) 8.6.6 coefficient b2 data register bits 15...8 (address 1bh) 8.6.7 coefficient b2 data register bits 7...0 (address 1ch) 8.6.8 coefficient a1 data register bits 23...16 (address 1dh) d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 .com .com .com .com 4 .com u datasheet
STA323W 34/41 8.6.9 1.1.9coefficient a1 data register bits 15...8 (address 1eh) 8.6.10coefficient a1 data register bits 7...0 (address 1fh) 8.6.11coefficient a2 data register bits 23...16 (address 20h) 8.6.12coefficient a2 data register bits 15...8 (address 21h) 8.6.13coefficient a2 data register bits 7...0 (address 22h) 8.6.14coefficient b0 data register bits 23...16 (address 23h) 8.6.15coefficient b0 data register bits 15...8 (address 24h) 8.6.16coefficient b0 data register bits 7...0 (address 25h) d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 .com .com .com .com 4 .com u datasheet
35/41 STA323W 8.6.17coefficient write control register (address 26h) coefficients for eq, mix and scaling are handled internally in the STA323W via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this func- tion. first register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to ram. the following are instructions for reading and writing coefficients. 8.7 reading a coefficient from ram write 8-bits of address to i 2 c register 16h write ?1? to bit r1 (d2) of i 2 c register 26h read top 8-bits of coefficient in i 2 c address 17h read middle 8-bits of coefficient in i 2 c address 18h read bottom 8-bits of coefficient in i 2 c address 19h 8.8 reading a set of coefficients from ram write 8-bits of address to i 2 c register 16h write ?1? to bit ra (d3) of i 2 c register 26h read top 8-bits of coefficient in i 2 c address 17h read middle 8-bits of coefficient in i 2 c address 18h read bottom 8-bits of coefficient in i 2 c address 19h read top 8-bits of coefficient b2 in i 2 c address 1ah read middle 8-bits of coefficient b2 in i 2 c address 1bh read bottom 8-bits of coefficient b2 in i 2 c address 1ch read top 8-bits of coefficient a1 in i 2 c address 1dh read middle 8-bits of coefficient a1 in i 2 c address 1eh read bottom 8-bits of coefficient a1 in i 2 c address 1fh read top 8-bits of coefficient a2 in i 2 c address 20h read middle 8-bits of coefficient a2 in i 2 c address 21h read bottom 8-bits of coefficient a2 in i 2 c address 22h read top 8-bits of coefficient b0 in i 2 c address 23h read middle 8-bits of coefficient b0 in i 2 c address 24h read bottom 8-bits of coefficient b0 in i 2 c address 25h 8.9 writing a single coefficient to ram write 8-bits of address to i 2 c register 16h write top 8-bits of coefficient in i 2 c address 17h write middle 8-bits of coefficient in i 2 c address 18h write bottom 8-bits of coefficient in i 2 c address 19h write 1 to w1 bit in i 2 c address 26h d7 d6 d5 d4 d3 d2 d1 d0 ra r1 wa w1 0000 .com .com .com .com 4 .com u datasheet
STA323W 36/41 8.10 writing a set of coefficients to ram write 8-bits of starting address to i 2 c register 16h write top 8-bits of coefficient b1 in i 2 c address 17h write middle 8-bits of coefficient b1 in i 2 c address 18h write bottom 8-bits of coefficient b1 in i 2 c address 19h write top 8-bits of coefficient b2 in i 2 c address 1ah write middle 8-bits of coefficient b2 in i 2 c address 1bh write bottom 8-bits of coefficient b2 in i 2 c address 1ch write top 8-bits of coefficient a1 in i 2 c address 1dh write middle 8-bits of coefficient a1 in i 2 c address 1eh write bottom 8-bits of coefficient a1 in i 2 c address 1fh write top 8-bits of coefficient a2 in i 2 c address 20h write middle 8-bits of coefficient a2 in i 2 c address 21h write bottom 8-bits of coefficient a2 in i 2 c address 22h write top 8-bits of coefficient b0 in i 2 c address 23h write middle 8-bits of coefficient b0 in i 2 c address 24h write bottom 8-bits of coefficient b0 in i 2 c address 25h write 1 to wa bit in i 2 c address 26h the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (e.g. 0, 5, 10, 15, ?, 45 decimal), and the STA323W will generate the ram addresses as offsets from this base value to write the complete set of coefficient data. .com .com .com .com 4 .com u datasheet
37/41 STA323W table 34. ram block for biquads, mixing, and scaling index (decimal) index (hex) coefficient default 0 00h channel 1 ? biquad 1 c1h10 (b1/2) 000000h 1 01h c1h11 (b2) 000000h 2 02h c1h12 (a1/2) 000000h 3 03h c1h13 (a2) 000000h 4 04h c1h14 (b0/2) 400000h 5 05h channel 1 ? biquad 2 c1h20 000000h ??? ?? 19 13h channel 1 ? biquad 4 c1h44 400000h 20 14h channel 2 ? biquad 1 c2h10 000000h 21 15h c2h11 000000h ??? ?? 39 27h channel 2 ? biquad 4 c2h44 400000h 40 28h high-pass 2 nd order filter for xo = 000 c12h0 (b1/2) 000000h 41 29h c12h1 (b2) 000000h 42 2ah c12h2 (a1/2) 000000h 43 2bh c12h3 (a2) 000000h 44 2ch c12h4 (b0/2) 400000h 45 2dh low-pass 2 nd order filter for xo = 000 c12l0 (b1/2) 000000h 46 2eh c12l1 (b2) 000000h 47 2fh c12l2 (a1/2) 000000h 48 30h c12l3 (a2) 000000h 49 31h c12l4 (b0/2) 400000h 50 32h channel 1 ? pre-scale c1pres 7fffffh 51 33h channel 2 ? pre-scale c2pres 7fffffh 52 34h channel 1 ? post-scale c1psts 7fffffh 53 35h channel 2 ? post-scale c2psts 7fffffh 54 36h channel 3 ? post-scale c3psts 7fffffh 55 37h thermal warning ? post scale twpsts 5a9df7h 56 38h channel 1 ? mix 1 c1mx1 7fffffh 57 39h channel 1 ? mix 2 c1mx2 000000h 58 3ah channel 2 ? mix 1 c2mx1 000000h 59 3bh channel 2 ? mix 2 c2mx2 7fffffh 60 3ch channel 3 ? mix 1 c3mx1 400000h 61 3dh channel 3 ? mix 2 c3mx2 400000h 62 3eh unused 63 3fh unused .com .com .com .com 4 .com u datasheet
STA323W 38/41 8.11 variable max power correction (address 27h-28h): mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. table 35. 8.12 fault detect recovery (address 2bh-2ch): fdrc bits specify the 16-bit fault detect recovery time delay. when fault is asserted, the tristate output will be immediately asserted low and held low for the time period specified by this constant. a con- stant value of 0001h in this register is ~.083ms. the default value of 000c specifies ~.1msec. table 36. figure 16. d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 frdc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 low current dead time = max(dtr,dtf) outy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% iny outy gnd +vcc m58 m57 r 8 ? + - v67 = vdc = vcc/2 d02au1448 .com .com .com .com 4 .com u datasheet
39/41 STA323W figure 17. powerso36 slug down mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0.0039 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 d 15.80 16.00 0.6220 0.6299 d1 9.40 9.80 0.3701 0.3858 e 13.90 14.5 0.5472 0.5709 e1 10.90 11.10 0.4291 0.4370 e2 2.90 0.1142 e3 5.80 6.20 0.2283 0.2441 e 0.65 0.0256 e3 11.05 0.4350 g 0 0.10 0.0039 h 15.50 15.90 0.6102 0.6260 h 1.10 0.0433 l 0.8 1.10 0.0315 0.0433 n 10? (max) s 8? (max) note: ? and e1?do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006? - critical dimensions are "a3", "e" and "g". powerso-36 0096119 c .com .com .com .com 4 .com u datasheet
STA323W 40/41 table 37. revision history date revision description of changes july 2005 1 first issue january 2006 2 modified in page 12/41 the table configuration register a (address 00h) .com .com .com .com 4 .com u datasheet
ininformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ddx is a trademark of apogee tecnology inc. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 41/41 STA323W .com .com .com 4 .com u datasheet

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