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? 1996,1997 mos integrated circuit m m m m PD464318L, 464336l 4m-bit bi-cmos synchronous fast static ram 256k-word by 18-bit / 128k-word by 36-bit h s tl interfa c e data sheet the mark ? ? ? ? shows major revised points. document no. m12000ej5v0ds00 (5th edition) date published september 1998 ns cp(k) printed in japan the information in this document is subject to change without notice. description the m PD464318L is a 262,144 words by 18 bits, and the m pd464336l is a 131,072 words by 36 bits synchronous static ram fabricated with advanced bi-cmos technology using n-channel memory cell. this technology and unique peripheral circuits make the m PD464318L and m pd464336l a high-speed device. the m PD464318L and m pd464336l are suitable for applications which require high-speed, low voltage, high-density memory and wide bit configuration, such as cache and buffer memory. these are packaged in a 119-pin plastic bga (ball grid array). features fully synchronous operation fast clock access time : 2.6 ns / 200 mhz, 3.0 ns / 167 mhz, 3.5 ns / 154 mhz single differential single clock, registered input / registered output asynchronous output enable control : /g byte write control : /sba (dqa1-9), /sbb (dqb1-9), /sbc (dqc1-9), /sbd (dqd1-9) common i/o using three-state outputs internally self-timed write cycle late write with 1 dead cycle between read-write user-configurable outputs : controlled impedance outputs or push-pull outputs boundary scan (jtag) ieee 1149.1 compatible 3.3 v (chip) / 1.5v (i/o) supply ordering information part number access time clock frequency package m PD464318Ls1-a5 2.6 ns 200 mhz 119-pin plastic bga m PD464318Ls1-a6 3.0 ns 167 mhz m PD464318Ls1-a65 3.5 ns 154 mhz m pd464336ls1-a5 2.6 ns 200 mhz m pd464336ls1-a6 3.0 ns 167 mhz m pd464336ls1-a65 3.5 ns 154 mhz
2 m m m m PD464318L, 464336l pin configurations /xxx indicates active low si gnal. 119-pin plastic bga (256k words by 18 bits pin assignment) [ m m m m PD464318Ls1 ] 7654321 pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. aa7v dd q a6 sa2 a5 sa6 a4 nc a3 sa9 a2 sa12 a1 v dd q b b7ncb6ncb5sa16b4ncb3sa17b2ncb1nc c c7 nc c6 sa3 c5 sa7 c4 v dd c3 sa10 c2 sa13 c1 nc dd7ncd6dqa9d5v ss d4 zq d3 v ss d2 nc d1 dqb1 ee7dqa8e6nce5v ss e4 /ss e3 v ss e2 dqb2 e1 nc ff7v dd qf6dqa7f5 v ss f4 /g f3 v ss f2 nc f1 v dd q gg7dqa6g6ncg5v ss g4 nc g3 /sbb g2 dqb3 g1 nc hh7nch6dqa5h5v ss h4 nc h3 v ss h2 nc h1 dqb4 jj7v dd qj6 v dd j5 v ref j4 v dd j3 v ref j2 v dd j1 v dd q kk7dqa4k6nck5v ss k4 k k3 v ss k2 dqb5 k1 nc l l7 nc l6dqa3l5/sbal4 /k l3 v ss l2 nc l1 dqb6 mm7v dd qm6 nc m5 v ss m4 /sw m3 v ss m2 dqb7 m1 v dd q nn7ncn6dqa2n5v ss n4 sa1 n3 v ss n2 nc n1 dqb8 pp7dqa1p6ncp5v ss p4 sa0 p3 v ss p2 dqb9 p1 nc r r7 nc r6 sa4 r5 v dd r4 v dd r3 v ss r2 sa14 r1 nc t t7 nc t6 sa5 t5 sa8 t4 nc t3 sa11 t2 sa15 t1 nc uu7v dd q u6 nc u5 tdo u4 tck u3 tdi u2 tms u1 v dd q 1 2 3 4 5 6 7 l n m r p t u d f e h g j k b c a 7 6 5 4 3 2 1 bottom view top view
3 m m m m PD464318L, 464336l pin name and functions pin name description function v dd core power supply supplies power for ram core v ss ground v dd q output power supply supplies power for output buffers v ref input reference k, /k main clock input sa0 to sa17 synchronous address input dqa1 to dqb9 synchronous data input / output /ss synchronous chip select logically selects sram /sw synchronous byte write enable /sba synchronous byte "a" write enable write dqa1 to dqa9 /sbb synchronous byte "b" write enable write dqb1 to dqb9 /g asynchronous output enable asynchronous input zq output impedance control nc no connection tms test mode select (jtag) tdi test data input (jtag) tck test clock input (jtag) tdo test data output (jtag)
4 m m m m PD464318L, 464336l 119-pin plastic bga (128k words by 36 bits pin assignment) [ m m m m pd464336ls1 ] 7654321 pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. aa7v dd q a6 sa2 a5 sa5 a4 nc a3 sa9 a2 sa12 a1 v dd q b b7ncb6ncb5sa15b4ncb3sa16b2ncb1nc c c7 nc c6 sa3 c5 sa6 c4 v dd c3 sa10 c2 sa13 c1 nc d d7dqb8d6dqb9d5 v ss d4 zq d3 v ss d2 dqc9 d1 dqc8 e e7dqb6e6dqb7e5 v ss e4 /ss e3 v ss e2 dqc7 e1 dqc6 ff7v dd qf6dqb5f5 v ss f4 /g f3 v ss f2 dqc5 f1 v dd q g g7 dqb3 g6 dqb4 g5 /sbb g4 nc g3 /sbc g2 dqc4 g1 dqc3 h h7dqb1h6dqb2h5 v ss h4 nc h3 v ss h2 dqc2 h1 dqc1 jj7v dd qj6 v dd j5 v ref j4 v dd j3 v ref j2 v dd j1 v dd q k k7dqa1k6dqa2k5 v ss k4 k k3 v ss k2 dqd2 k1 dqd1 l l7 dqa3 l6 dqa4 l5 /sba l4 /k l3 /sbd l2 dqd4 l1 dqd3 mm7v dd qm6dqa5m5 v ss m4 /sw m3 v ss m2 dqd5 m1 v dd q n n7dqa6n6dqa7n5 v ss n4 sa1 n3 v ss n2 dqd7 n1 dqd6 p p7dqa8p6dqa9p5 v ss p4 sa0 p3 v ss p2 dqd9 p1 dqd8 r r7 nc r6 sa4 r5 v dd r4 v dd r3 v ss r2 sa14 r1 nc t t7 nc t6 nc t5 sa7 t4 sa8 t3 sa11 t2 nc t1 nc uu7v dd q u6 nc u5 tdo u4 tck u3 tdi u2 tms u1 v dd q 1 2 3 4 5 6 7 l n m r p t u d f e h g j k b c a 7 6 5 4 3 2 1 bottom view top view
5 m m m m PD464318L, 464336l pin name and functions pin name description function v dd core power supply supplies power for ram core v ss ground v dd q output power supply supplies power for output buffers v ref input reference k, /k main clock sa0 to sa16 synchronous address input dqa1 to dqd9 synchronous data input / output /ss synchronous chip select logically selects sram /sw synchronous byte write enable /sba synchronous byte "a" write enable write dqa1 to dqa9 /sbb synchronous byte "b" write enable write dqb1 to dqb9 /sbc synchronous byte "c" write enable write dqc1 to dqc9 /sbd synchronous byte "d" write enable write dqd1 to dqd9 /g asynchronous output enable asynchronous input zq output impedance control nc no connection tms test mode select (jtag) tdi test data input (jtag) tck test clock input (jtag) tdo test data output (jtag)
6 m m m m PD464318L, 464336l late write block diagram k /sba k /k /ss /sw /sba /sbb /sbc /sbd data in register write control logic address register write address register read comp. memory array data in data out mux output register /sw /sbc /sbb dq /sbd /g /k /ss sa0 to sa17 mux h
7 m m m m PD464318L, 464336l synchronous truth table /ss /sw /sba /sbb /sbc /sbd mode dqa1 C 9dqb1 C 9dqc1 C 9dqd1 C 9 power h not selected hi-z hi-z hi-z hi-z active lh read dout dout dout dout active l l l l l l write din din din din active l l l h h h write din hi-z hi-z hi-z active l l h l l l write hi-z din din din active remark : dont care mode select (output buffer) zq mode notes izq rq controlled impedance push-pull output buffer mode 1 v dd push-pull output buffer mode 2 notes 1. see figure. 2. see figure. zq v dd zq rq (175 w rq 350 w)
8 m m m m PD464318L, 464336l electrical specifications absolute maximum ratings parameter symbol condition min. typ. max. unit note supply voltage v dd C0.5 +4 v 1 output supply voltage v dd q C0.5 +4 v 1 input voltage v in C0.5 v dd + 0.3 v 1 input / output voltage v i/o C0.5 v dd q + 0.3 v 1 operating temperature t j 20 110 c 2 storage temperature t stg C55 +125 c notes 1. C0.5 v min. (pulse width 10% tcyc) 2. t j = junction temperature caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t j = 20 to 110 c) parameter symbol conditions min. typ. max. unit core supply voltage v dd 3.15 3.3 3.45 v output buffer supply voltage v dd q 1.4 1.5 1.6 v input reference voltage v ref 0.60.951.3 v low level input voltage v il C0.3 note v ref C0.1 v high level input voltage v ih v ref +0.1 v dd q+0.3 v note C0.5 v min. (pulse width 10% tcyc) recommended ac operating conditions (t j = 20 to 110 c) note parameter symbol conditions min. typ. max. unit input reference voltage v ref (rms) C5% +5% v low level input voltage v il C0.3 v ref C0.2 v high level input voltage v ih v ref +0.2 v dd q+0.3 v note t j = 20 to 110c : m PD464318L-a6/ -a65, 464336l-a6/ -a65 t j = 20 to 100c : m PD464318L-a5, 464336l-a5 capacitance (t a = 25 c, f = 1 mhz) parameter note symbol test conditions max. unit input capacitance c in v in = 0 v 5 pf input / output capacitance c i/o v i/o = 0 v 7 pf clock pin (k, /k) input capacitance c clk v clk = 0 v 7 pf note these parameters are sampled and not 100% tested.
9 m m m m PD464318L, 464336l dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol conditions min. typ. max. unit input leakage current i li v in = 0 to v dd C5 +5 m a dq leakage current note i lo v i/o = 0 to v dd qC5+5 m a operating supply current i cc /ss = v il , idq = 0 ma m PD464318L 600 ma 200 mhz m pd464336l 700 note /ss = v ih or /g = v ih output voltage on controlled impedance push-pull output buffer mode (vzq = izq rq) parameter symbol conditions min. typ. max. unit low level output voltage v ol | i ol | 10 m a, i ol = 2.5v dd q / rq 10% v ss 0.1 v v ol = vddq / 2 (175 w < rq < 350 w ) high level output voltage v oh | i oh | 10 m a, i oh = 2.5v dd q / rq 10% v dd qC0.1 v dd qv v oh = vddq / 2 (175 w < rq < 350 w ) remark see figure. output voltage on push-pull output buffer mode (vzq = v dd ) parameter symbol conditions min. typ. max. unit low level output voltage v ol i ol = +4 ma C 0.3 v high level output voltage v oh i oh = C 4 ma v dd qC0.3 C v remark see figure (v tt = 0.75 v). dq (output) z0 = 50 w 10 pf dq (output) 5 pf dq (output) 5 pf 50 w v tt dq (output) z0 = 50 w 10 pf 50 w v tt zq v dd
10 m m m m PD464318L, 464336l ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions input waveform (rise and fall time = 0.5 ns (20 to 80%)) remark clock input differential voltage output waveform v tt or v dd q / 2 v tt or v dd q / 2 0 v v dd q h
11 m m m m PD464318L, 464336l output load (1) controlled impedance push-pull output buffer mode (2) push-pull output buffer mode (v tt =0.75 v) dq (output) z0 = 50 w 10 pf dq (output) 5 pf dq (output) 5 pf 50 w v tt dq (output) z0 = 50 w 10 pf 50 w v tt zq v dd zq rq (175 w rq 350 w)
12 m m m m PD464318L, 464336l single differential clock, registered input / registered output mode parameter symbol Ca5 (200 mhz) Ca6 (167 mhz) Ca65 (154 mhz) unit notes min. max. min. max. min. max. clock cycle time tkhkh 5.0 C 6.0 C 6.5 C ns clock phase time tkhkl / tklkh 2.4 C 2.5 C 3.0 C ns setup times address tavkh 0.5 C 0.5 C 0.5 C ns write data tdvkh write enable twvkh chip select tsvkh hold times address tkhax 1.0 C 1.0 C 1.0 C ns write data tkhdx write enable tkhwx chip select tkhsx clock access time tkhqv C 2.6 C 3.0 C 3.5 ns 1 k high to q change tkhqx 1.0 C 1.0 C 1.0 C ns 2 /g low to q valid tglqv C 2.5 C 3.0 C 3.5 ns 1 /g low to q change tglqx 1.0 C 1.0 C 1.0 C ns 2 /g high to q hi-z tghqz 1.0 2.5 1.0 3.0 1.0 3.5 ns 2 k high to q hi-z (/sw) tkhqz 1.0 3.5 1.0 3.5 1.0 4.0 ns 2 k high to q hi-z (/ss) tkhqz2 1.0 3.5 1.0 3.5 1.0 4.0 ns 2 k high to q lo-z tkhqx2 1.0 C 1.0 C 1.0 C ns /g high pulse width tghgl 5.0 C 6.0 C 6.5 C ns 3 /g high to k high tghkh 1.0 C 1.0 C 1.0 C ns 3 k high to /g low tkhgl 2.5 C 2.5 C 2.5 C ns 3 notes 1. see figure. 2. see figure. 3. controlled impedance push-pull output buffer mode only. dq (output) z0 = 50 w 10 pf dq (output) 5 pf dq (output) 5 pf 50 w v tt dq (output) z0 = 50 w 10 pf 50 w v tt
13 m m m m PD464318L, 464336l a qa qc qe qf qg bcde f gh i j k qi t khax t avkh t khkh t khkl t klkh t khsx t svkh t wvkh t khwx t ghqz t ghgl t glqx t glqv t khqz2 t khqv t khqx t khqx2 single differential clock, registered input / registered output mode (read operation) /k k address /ss /sw /g dq qb
14 m m m m PD464318L, 464336l l ql qo qp qq mnopq r s t uv t khax t avkh t khkh t khkl t klkh t khsx t svkh t wvkh t khwx t glqx t ghkh t glqv t khqz t khdx t dvkh t khqx2 single differential clock, registered input / registered output mode (write operation) /k k address /ss /sw /g dq dn qt ds t ghqz t khgl
15 m m m m PD464318L, 464336l jtag specifications the m PD464318L and m pd464336l support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name description pin assignments tck test clock input 4 u tms test mode select 2 u tdi test data input 3 u tdo test data output 5 u remark the device does not have trst (tap reset). the tap controller state is reset into test-logic-reset on the sram power-up. jtag dc characteristics (t j = 20 to 110 c) parameter symbol conditions min. typ. max. unit notes jtag input high voltage v ih 2.2 v dd +0.3 v jtag input low voltage v il C0.3 +0.8 v jtag output high voltage v oh 2.4 C v 1 jtag output low voltage v ol C0.4v2 notes 1. i oh = C8 ma 2. i ol = 8 ma jtag ac characteristics (t j = 20 to 110 c) parameter symbol conditions min. typ. max. unit note clock cycle time (tck) t thth 100 C ns clock phase time (tck) t thtl / t tlth 40 C ns setup time (tms / tdi) t mvth / t dvth 10 C ns hold time (tms / tdi) t thmx / t thdx 10 C ns tck low to tdo valid (tdo) t tlqv C20ns
16 m m m m PD464318L, 464336l jtag ac test conditions (t j = 20 to 110 c) input waveform (rise / fall time = 1 ns (20 to 50 %)) output waveform output load (v tt =1.5 v) tdo z0 = 50 w 50 w v tt test points 1.5 v 1.5 v 0 v 3.0 v test points 1.5 v 1.5 v 0 v 3.0 v
17 m m m m PD464318L, 464336l jtag timing diagram scan register definition register name 256k x 18 128k x 36 unit instruction register 3 3 bit bypass register 1 1 bit id register 32 32 bit boundary register 51 70 bit id register definition organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit 256k x 18 xxxx 0111001011 000000 00010010000 1 128k x 36 xxxx 0110101100 000000 00010010000 1 jtag instruction cording ir2 ir1 ir0 instruction note 0 0 0 extest 1 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note 1. tristate all data drivers and capture the pad values into a serial scan latch. t thth t tlqv t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo
18 m m m m PD464318L, 464336l scan exit order [ m m m m PD464318L (256k words by 18 bits) ] [ m m m m pd464336l (128k words by 36 bits) ] bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id bit no. signal name bump id 1 m2 5r 26 sa17 3b 1 m2 5r 36 sa16 3b 2 sa5 6t 27 nc 2b 37 nc 2b 3 sa0 4p 28 sa9 3a 2 sa0 4p 38 sa9 3a 29 sa10 3c 3 sa8 4t 39 sa10 3c 4 sa4 6r 30 sa13 2c 4 sa4 6r 40 sa13 2c 5 sa8 5t 31 sa12 2a 5 sa7 5t 41 sa12 2a 6 nc 7t 6 nc 7t 42 dqc9 2d 32 dqb1 1d 7 dqa9 6p 43 dqc8 1d 7 dqa1 7p 33 dqb2 2e 8 dqa8 7p 44 dqc7 2e 8 dqa2 6n 9 dqa7 6n 45 dqc6 1e 10 dqa6 7n 46 dqc5 2f 34 dqb3 2g 11 dqa5 6m 47 dqc4 2g 9 dqa3 6l 12 dqa4 6l 48 dqc3 1g 13 dqa3 7l 49 dqc2 2h 35 dqb4 1h 14 dqa2 6k 50 dqc1 1h 10 dqa4 7k 36 /sbb 3g 15 dqa1 7k 51 /sbc 3g 11 /sba 5l 37 zq 4d 16 /sba 5l 52 zq 4d 12 /k 4l 38 /ss 4e 17 /k 4l 53 /ss 4e 13 k 4k 39 nc 4g 18 k 4k 54 /c 4g 14 /g 4f 40 nc 4h 19 /g 4f 55 c 4h 41 /sw 4m 20 /sbb 5g 56 /sw 4m 21 dqb1 7h 57 /sbd 3l 15 dqa5 6h 22 dqb2 6h 58 dqd1 1k 16 dqa6 7g 42 dqb5 2k 23 dqb3 7g 59 dqd2 2k 43 dqb6 1l 24 dqb4 6g 60 dqd3 1l 17 dqa7 6f 25 dqb5 6f 61 dqd4 2l 18 dqa8 7e 44 dqb7 2m 26 dqb6 7e 62 dqd5 2m 45 dqb8 1n 27 dqb7 6e 63 dqd6 1n 28 dqb8 7d 64 dqd7 2n 19 dqa9 6d 29 dqb9 6d 65 dqd8 1p 20 sa2 6a 46 dqb9 2p 30 sa2 6a 66 dqd9 2p 21 sa3 6c 47 sa11 3t 31 sa3 6c 67 sa11 3t 22 sa7 5c 48 sa14 2r 32 sa6 5c 68 sa14 2r 23 sa6 5a 49 sa1 4n 33 sa5 5a 69 sa1 4n 24 nc 6b 50 sa15 2t 34 nc 6b 25 sa16 5b 51 m1 3r 35 sa15 5b 70 m1 3r
19 m m m m PD464318L, 464336l tap controller state diagram disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k resistor. tdo should be left unconnected. test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11
20 m m m m PD464318L, 464336l package drawing 119 pin plastic bga item millimeters inches p119s1-r4 a 22.00.2 0.8660.008 b 19.5 0.768 g 0.60.1 0.024 +0.004 C0.005 h 0.56 0.022 i 1.460.1 0.057 c 12.0 0.472 d 14.00.2 0.5510.008 e 0.84 0.033 f 1.27 (t.p.) 0.05 (t.p.) j 2.30 max. 0.091 k 0.15 0.006 l 0.780.1 0.031 p c0.7 c0.028 r25 25 s 1.25 0.049 t 1.0 0.039 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u c a b s t d j i h g e f k l r +0.005 C0.004 +0.004 C0.005 p
21 m m m m PD464318L, 464336l recommended soldering conditions please consult with our sales offices for soldering conditions of the m PD464318L and m pd464336l. type of surface mount device m PD464318Ls1: 119-pin plastic bga m pd464336ls1: 119-pin plastic bga
22 m m m m PD464318L, 464336l [memo]
23 m m m m PD464318L, 464336l 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme-diately after power-on for devices having reset function. notes for cmos devices
m m m m PD464318L, 464336l no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 [memo]

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