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| HT46R75D-3 dual slope a/d type 8-bit otp mcu with lcd rev. 1.00 1 july 19, 2011 features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v three system oscillators: external crystal oscillator -- hxt external rc oscillator -- erc internal high frequency rc oscillator -- hirc up to 22 bidirectional i/o lines one external interrupt input shard with an i/o lines one 8-bit and two 16-bit programmable timer/event counter with overflow interrupt and an 8-bit prescaler lcd driver with 24 8or28 4 segments lcd bias type: 1/3 bias r type or c type program memory: 8k 16 data memory: 192 8 single differential input channel dual slope analog to digital converter with operational amplifier watchdog timer with regulator power buzzer output internal 12khz rc oscillator external 32.768khz crystal oscillator power-down and wake-up features reduce power consumption voltage regulator (3.3v) and charge pump embedded voltage reference generator (1.5v) 8 subroutine nesting levels 16-bit table read instruction low voltage reset function one vibration sensor input four touch-key inputs bit manipulation instruction up to 0.5 s instruction cycle with 8mhz system clock 63 powerful instructions all instructions in 1 or 2 machine cycles 64-pin lqfp package general description the HT46R75D-3 is an 8-bit high performance, risc architecture microcontroller device specifically de- signed for a/d with lcd applications that interface di- rectly to analog signals, such as those from sensors. the advantages of low power consumption, i/o flexibil- ity, timer functions, oscillator options, dual slope a/d converter, lcd display, halt and wake-up functions, watchdog timer, as well as low cost, enhance the versa- tility of these devices to suit for a wide range of ad with lcd application possibilities such as sensor signal pro- cessing, scales, consumer products, subsystem con- trollers, etc. www.datasheet.co.kr datasheet pdf - http://www..net/
block diagram HT46R75D-3 rev. 1.00 2 july 19, 2011 osc2 osc1 res vdd mux pac pa port a wdt port b vss program rom program counter interrupt circuit stack intc data memory instruction register m u x instruction decoder status alu shifter timing generator acc wdt prescaler m u x mp pb pbc pb0/tk0 pb1/tk1 pb2/tk2 pb3/tk3 tmr0 tmr0 tmr0c prescaler lf m u x tmr1 m u x tmr1 tmr1c f sys /4 1-channel dual-slope converter with op lcd memory bp lcd driver com0~com3 seg0~seg15 charge pump regulator vochp voreg dopap dopan dopao dchop dsrr dsrc dscc th/lb prescaler m u x f sys lf m u x tmr2 m u x tmr2 tmr2c prescaler tckf m u x rtc osc osc4 osc3 pa0/vib pa1/bz pa2/bz/kref f sys /4 f sys /4 f wdt f rtc f rtc wdt osc touch key circuits amplifier vibration sensor input touch key inputs halt en/dis pa5/osc2 pa6/osc1 pa7/res pa3/osc4 pa4/osc3 pb4/int/seg0 pb5/tmr0/seg1 pb6/tmr1/seg2 pb7/tmr2/seg3 vmax vlcd vdd chpc1 chpc2 lvr circuits www.datasheet.co.kr datasheet pdf - http://www..net/ pin assignment HT46R75D-3 rev. 1.00 3 july 19, 2011 pb1/tk2 pb2/tk3 pb3/tk4 pb4/int pb5/tmr0 avdd ai th/lb vobgp chpc2 chpc1 vochp voreg avss dopap dopan dopao dchop dsrr dsrc dscc pa7/res c2 c1 vc vab com0 com1 com2 com3 com4/seg27 com5/seg26 com6/seg25 com7/seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 pc7/seg7 pc6/seg6 pc5/seg5 pc4/seg4 pc3/seg3 pc2/seg2 pc1/tmr2/seg1 pc0/tmr1/seg0 pa0/vib pa1/bz pa2/bz pa3/osc4 pa4/osc3 pa5/osc2 pa6/osc1 vdd vss pb0/tk1 HT46R75D-3 64 lqfp-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pb1/tk2 pb2/tk3 pb3/tk4 pb4/int pb5/tmr0 avdd th/lb vobgp chpc2 chpc1 vochp voreg avss dopap dopan dopao dchop dsrr dsrc dscc pa7/res com0 com1 com2 com3 com4/seg27 com5/seg26 com6/seg25 com7/seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 pc7/seg7 pc6/seg6 pc5/seg5 pc4/seg4 pc3/seg3 pc2/seg2 pc1/tmr2/seg1 pc0/tmr1/seg0 pa0/vib pa1/bz pa2/bz pa3/osc4 pa4/osc3 pa5/osc2 pa6/osc1 vdd vss pb0/tk1 HT46R75D-3 64 lqfp-b ai 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 www.datasheet.co.kr datasheet pdf - http://www..net/ pin description pin name i/o options description pa0/vib pa1/bz pa2/bz pa3/osc4 pa4/osc3 pa5/osc2 pa6/osc1 pa7/res i/o oscn or i/o res or i/o bidirectional 8-bit input/output port. each individual bit on this port can be configured to have a wake-up function using a register control bit. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. also the register control bits determine which pins on this port have pull-high resistors except for pa7. vib is the vibration sensor analog input which is pin-shared with pa0. bz and bz are buzzer outputs pin-shared with pa1 and pa2 and are to be used as buzzer outputs or normal i/o functions determined by a register control bit. osc1 and osc2 can be used as system oscillator pins which are pin-shared with pa6 and pa5. configuration options determine if these pins are used as i/o pins or system oscillator pins. osc3 and osc4 can be configured to be used as the 32.768khz oscilla - tor pins or as the normal i/o pins named pa4 and pa3 using a configura - tion option. res is pin-shared with pa7 determined by a configuration option. when pa7 is configured as an i/o pin, software instructions determine if this pin is open drain output or schmitt trigger input without pull-high resistor. pb0/tk1~ pb3/tk4 pb4/int pb5/tmr0 i/o bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. register control bits deter - mine which pins on this port have pull-high resistors. tk0~tk3 are touch sensor input pins which are pin-shared with pb0~pb3. pb4~pb5 are pin-shared with int and tmr0 respectively. pc0/tmr1/seg0 pc1/tmr2/seg1 pc2/seg2 pc3/seg3 pc4/seg4 pc5/seg5 pc6/seg6 pc7/seg7 i/o bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. register control bits deter- mine which pins on this port have pull-high resistors. pc0 and pc1 are pin-shared with tmr1 and tmr2 respectively. pc0~pc7 are also pin-shared with the lcd segments seg0~seg7 re- spectively which are selected by register control bits. once these pins are selected as segments, the i/o function including schmitt trigger input and pull-high function are disabled. however, these pins will default to an input mode with pull-high resistors after a reset. seg8~seg23 o lcd segment outputs com0~com3 o lcd common outputs com4/seg27 com5/seg26 com6/seg25 com7/seg24 o lcd common/segment outputs. the common or segment output function are determined by the register control bits. vab, vc, c1, c2 ai lcd voltage pump ai ai analog to digital converter input vobgp ao band gap voltage output pin (for internal use) voreg o regulator output 3.3v vochp o charge pump output -- a capacitor is required to be connected chpc1 charge pump capacitor (positive) chpc2 charge pump capacitor (negative) dopan, dopap, dopao, dchop ai/ao dual slope a/d converter pre-stage opa related pins. dopan is the opa negative input pin, dopap is the opa positive input pin, dopao is the opa output pin and dchop is the opa chopper pins. th/lb ai temperature sensor/low battery voltage input pin. HT46R75D-3 rev. 1.00 4 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ pin name i/o options description dsrr dsrc dscc ai/ao dual slope a/d converter main function rc circuit. dsrr is the input or reference signal, dsrc is the integrator negative input, and dscc is the comparator negative input. vdd pwr digital positive power supply vss pwr digital negative power supply, ground avdd pwr analog positive power supply avss pwr analog negative power supply, ground absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 20 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc, ext. rc osc, int. rc osc) 5v no load, f sys =8mhz, analog block off 48ma i dd2 operating current (crystal osc, ext. rc osc, int. rc osc) 3v no load, f sys =4mhz, adc block off 0.8 1.5 ma 5v 2.5 4 ma i dd3 operating current (crystal osc, ext. rc osc) 3v no load, f sys =2mhz, adc block off 0.5 1 ma 5v 1.5 3 ma i dd4 operating current (crystal osc, ext. rc osc) 5v v rego =3.3v, f sys =4mhz, adc on, adccclk= 125khz (all other analog de - vices off) 35ma i stb1 standby current (wdt disable) 3v no load, system halt, lcd off at halt 1 a 5v 2 a i stb2 standby current (wdt enable) 3v no load, system halt, lcd off at halt, adc off 2.5 5 a 5v 815 a i stb3 standby current (wdt disable in - ternal rc 12khz osc on) 3v no load, system halt, lcd off at halt, adc off 25 a 5v 610 a i stb4 standby current (wdt disable, lcd on and regulator on) 5v no load, system osc halt, internal rc 12khz osc on, adc block off, lcd on (1/3 bias, r type) at halt 380 500 a HT46R75D-3 rev. 1.00 5 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ symbol parameter test conditions min. typ. max. unit v dd conditions i stb5 standby current (internal rc 12khz osc off, rtc on) 3v no load, system halt rtc osc slowly start-up 5 a 5v 15 a i stb6 standby current (wdt disable, lcd on and regulator on) 5v no load, system osc off, rtc osc on, adc block off, lcd on (1/3 bias, r type) 390 510 a i stb7 standby current (wdt disable) 3v no load, only vibration sensor turn on & vib pin connected a 0.1 f cap to vss 24 a 5v 816 a v il1 input low voltage for i/o ports or input pins except res pin. 0 0.2v dd v 5v 0 1.5 v ih1 input high voltage for i/o ports or input pins except res pin. 0.8v dd v dd v 5v 3.5 5.0 v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lcd lcd highest voltage 0 v dd v v lvr low voltage reset configuration option: 2.1v 1.98 2.10 2.22 v configuration option: 3.15v 2.98 3.15 3.32 v configuration option: 4.2v 3.98 4.20 4.42 v v lvd low voltage detector 2.2 2.3 2.4 v i ol1 sink current for i/o ports except pa7 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh1 source current for i/o ports except pa7 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a i ol3 sink current for pa7 5v v ol =0.1v dd 23 ma r ph pull-high resistance of i/o ports 3v 20 60 100 k 5v 10 30 50 k v por vdd start voltage to ensure power-on reset 100 mv rr por vdd rise rate to ensure power-on reset 0.035 v/ms t por power-on reset low pulse width 1 ms v vibwk minimum voltage to wake mcu by the vibration sensor input 100hz~1khz sine wave (note) 250 mv HT46R75D-3 rev. 1.00 6 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ symbol parameter test conditions min. typ. max. unit v dd conditions charge pump and regulator v chpi input voltage charge pump on 2.2 3.6 v charge pump off 3.7 5.5 v v rego output voltage no load 3 3.3 3.6 v v regdp1 regulator output voltage drop (compare with no load) v dd =3.7v~5.5v charge pump off current 10ma 100 mv v regdp2 v dd =2.4v~3.6v charge pump on current 6ma 100 mv dual slope ad, amplifier and band gap v rfgtc reference generator temperature coefficient @3.3v 50 ppm/c v adoff input offset range 500 800 v v icmr common mode input range amplifier, no load 0.2 v rego 1.2 v integrator, no load 1.2 v rego 0.2 v note: 1. 2. test circuits for v vmbwk HT46R75D-3 rev. 1.00 7 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (external rc osc) 2.2v~ 5.5v 400 4000 khz system clock (crystal osc) 2.2v~ 5.5v 400 4000 khz 3.3v~ 5.5v 400 8000 khz 4.5v~ 5.5v 400 12000 khz f hirc internal rc osc 3v/5v ta=25c -2% 4/8 +2% mhz 5v ta=25c -2% 12 +2% mhz 3v/5v ta=0~70c -5% 4/8 +5% mhz 5v ta=0~70c -5% 12 +5% mhz 2.2v~ 3.6v ta=0~70c -8% 4 +8% mhz 3.0v~ 5.5v ta=0~70c -8% 4/8 +8% mhz 4.5v~ 5.5v ta=0~70c -8% 12 +8% mhz 2.2v~ 3.6v ta=-40~85c -12% 4 +12% mhz 3.0v~ 5.5v ta=-40~85c -12% 4/8 +12% mhz 4.5v~ 5.5v ta=-40~85c -12% 12 +12% mhz f erc external rc osc 5v ta=25 c, r=120k -2% 4 -2% mhz 5v ta=0~70 c, r=120k -5% 4 -5% mhz 5v ta=-40~85 c, r=120k -7% 4 -7% mhz 2.2v~ 5.5v ta=-40~85 c, r=120k -11% 4 -11% mhz f timer timer i/p frequency (tmr0/tmr1/tmr2) 2.2v~ 5.5v 0 4000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period (wake-up from halt) f sys =crystal oscillator 1024 t sys f sys =f erc or f hirc 1024 * t sys t int interrupt pulse width 1 ms t lvr low voltage width to reset 0.25 1.00 2.00 ms note: t sys = 1/f sys * when the system clock comes from the external rc or internal rc oscillator, the system start-up time period can be 2 or 1024 clock cycles determined by a configuration option. HT46R75D-3 rev. 1.00 8 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 9 july 19, 2011 functional description execution flow the system clock is derived from a crystal, an external rc or internal rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle con - sists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each in - struction to be effectively executed in a cycle. if an in - struction changes the value of the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) is 13 bits wide and it controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 4096 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by 1. the pc then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading a pcl register, a subroutine call, an ini - tial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed to the next instruction. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl performs a short jump. the destination is within 256 locations. ! " # $ % & ! " ' # ! " ( # $ % & ! " # ! " ( # $ % & ! " ( # ( ( ) * + , " + ) # execution flow mode program counter b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0000000000000 external interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 multi-function interrupt 0000000010000 adc interrupt 0000000010100 touch key interrupt 0000000011000 skip program counter+2 loading pcl pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *b12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 10 july 19, 2011 when a control transfer takes place, an additional dummy cycle is required. program memory the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192 16 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event coun- ter 1 interrupt service program. if a timer interrupt re- sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram begins execution at location 00ch. location 010h location 010h is reserved for the multi-function inter - rupt service program including the timer/event coun - ter 2 overflow, touch key module 16-bit and 10-bit counters interrupt. if an interrupt results from the touch key module or a timer/event counter 2 over - flow, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010h. location 014h location 014h is reserved for the adc interrupt ser - vice program. if an adc interrupt occurs, and if the in - terrupt is enabled and the stack is not full, the program begins execution at this location. location 018h location 018h is reserved for the touch key interrupt service program. if a touch key interrupt occurs, and if the interrupt is enabled and the stack is not full, the program begins execution at this location. table location any location in the rom can be used as a look-up ta - ble. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta - ble word are all transferred to the lower portion of tblh. the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the ta - ble location. before accessing the table, the location should be placed in tblp. all the table related instruc - tions require 2 cycles to complete the operation. these areas may function as a normal rom depend - ing upon the user s requirements. - . - / - ) 0 1 * 4 , ' & 5 1 + " 6 0 - 7 * # 4 , ' & 5 1 + " 6 0 - 7 * # + 8 - . - $ % - + - - & 5 & 1 - & 9 - - - - & 5 & 1 - & - 9 $ & - - - & 5 & 1 - & - 9 $ & - - - & 5 & 1 - & / & + ' 3 & - - & 5 & 1 - & & ) - - & 5 & 1 - & : : ; : : : : ; : : : $ : : : program memory instruction(s) table location b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 table location note: b12~b0: table location pc12~pc8: current program counter @7~@0: table of tblp www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 11 july 19, 2011 stack register stack the stack register is a special part of the memory used to save the contents of the program counter. the stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its activated level is indexed by a stack pointer (sp) and is neither readable nor writeable. at a commencement of a subroutine call or an interrupt ac - knowledgment, the content of the program counter is pushed onto the stack. at the end of the subroutine or in - terrupt routine, signaled by a return instruction (ret or reti), the contents of the program counter is restored to its previous value from the stack. after chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledgment is still inhibited. once the sp is decre - mented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the program - mer to use the structure easily. likewise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 8 return addresses are stored). data memory ram the data memory is divided into two functional groups, namely the special function registers and the general purpose data memory of 192 8 bit capacity. most of them are read/write, but some are read only. the unused space before 40h is reserved for future ex - panded usage and reading these locations will return the result 00h. the general purpose data memory, ad - dressed from 40h to ffh, is used for data and control information under instruction command. the areas in the ram can directly handle arithmetic, logic, incre - ment, decrement, and rotate operations. except some dedicated bits, each bit in the ram can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer register 0 (mp0; 01h) or the memory pointer register 1 (mp1; 03h). bank 1 contains the lcd data memory locations. after first setting up bp to the value of 01h to access bank 1 this bank must then be accessed indirectly using the memory pointer mp1. with bp set to a value of 01h, using mp1 to indirectly read or write to the data memory areas with addresses from 40h~5bh will result in oper - ations to bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of bp. 5 + & - 5 * / - ) < - + & - 5 * / - ) " = ) * # 2 & 5 + 7 > - 7 * ? ? : : : : : 6 : 0 : @ : ; : = : : : : : $ : : : : : : : 6 : 0 : @ : ; : = : : : : : $ : : : : : : : 6 : 0 : @ : ; : = : : : : : $ : : : : : : : 6 : 0 : @ : ; : = : : : : : $ : : : / / 4 4 4 : 4 a ! / / / : / 4 / ! : / : / 4 / : 4 4 a 4 $ < a a a 4 / / 0 : / 0 4 / / / / 4 / " ; ) * # 6 : @ : ram mapping - . - & - , 4 + , 4 + , 4 + , 4 + ; - . - / - ) 5 3 , , - 3 , www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 12 july 19, 2011 indirect addressing register iar0, iar1 location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write oper - ation of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1 (03h) respectively. reading loca - tion 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the memory pointer register, mp0 and mp1, are 8-bit registers. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. mp0 can only be applied to data memory, while mp1 can be applied to data memory and lcd display memory. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are pro - vided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct ad- dressing can only be used with bank 0 while all other banks must be addressed indirectly using mp1 and iar1. bank pointer bp depending upon which device is used, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, ex - cept for a wdt time-out reset in the power-down mode, in which case, the data memory bank remains unaf - fected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be ac - cessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing mode. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. accumulator acc the accumulator (acc) is related to the alu opera - tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc.) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except for the to and pdf flags, bits in the status regis - ter can be altered by instructions similar to other regis - ters. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clear - ing the watchdog timer and executing the halt in - struction. the z, ov, ac, and c flags reflect the status of the latest operations. bp register bit76543210 name dmbp0 r/w r/w por 0 bit 7~1 : unimplemented, read as 0 bit 0 dmbp0 : data memory bank point 0: bank 0 1: bank 1 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 13 july 19, 2011 bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register on entering the interrupt sequence or executing the subroutine call, the status register will not be automati - cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the device provides one external interrupts, three inter- nal timer/event counter interrupts, an adc interrupt and touch key interrupt. the interrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/ disable status and interrupt request flags. once an interrupt subroutine is serviced, other inter - rupts are all blocked, by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en - abled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becom - ing full. all interrupts will provide a wake-up function. as an inter - rupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the program memory. only the contents of the program counter is pushed onto the stack. if the contents of the register or of the status register is altered by the interrupt service program which corrupts the desired control se - quence, the contents should be saved in advance. an external interrupt is triggered by an edge transition on int pin (software control bits select the edge transition from high to low, low to high, both low to high and high to low), and the related interrupt request flag (eif; bit 4 of intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active, a sub - routine call to location 04h occurs. the interrupt request flag (eif) and emi bits are all cleared to disable other maskable interrupts. the internal timer/event counter 0 interrupt is initial- ized by setting the timer/event counter 0 interrupt re- quest flag (t0f; bit 5 of intc0), which is normally caused by a timer overflow. after the interrupt is en- abled, and the stack is not full, and the t0f bit is set, a subroutine call to location 08h occurs. the related inter- rupt request flag (t0f) is reset, and the emi bit is cleared to disable other maskable interrupts. the timer/event counter 1 is operated in the same manner but its related interrupt request flag is t1f (bit 6 of intc0) and its subroutine call location is 0ch. within this device there is one multi-function interrupt. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from the touch key module timer interrupt sources and timer/event counter 2 interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective in - terrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function inter - rupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 14 july 19, 2011 however, it must be noted that, although the multi-function interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts, namely the touch key module timer interrupts or the timer/event counter 2 interrupt, will not be automati - cally reset and must be manually reset by the applica - tion program. the a/d converter interrupt is initialized by setting the a/d converter interrupt request flag (adf; bit 5 of intc1), that is caused by an a/d conversion done sig - nal. after the interrupt is enabled, and the stack is not full, and the adf bit is set, a subroutine call to location 14h occurs. the related interrupt request flag (adf) is reset and the emi bit is cleared to disable further maskable interrupts. during the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the reti instruction is executed or the emi bit and the related interrupt control bit are set both to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti sets the emi bit and en - ables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch multi-function interrupt 4 10h a/d converter interrupt 5 14h touch key interrupt 6 18h once the interrupt request flags (tkf, adf, mff, t1f, t0f and eif) are all set, they remain in the intc1 or intc0 respectively until the interrupts are serviced or cleared by a software instruction. it is recommended that a program should not use the call subroutine within the interrupt subroutine. it sbe - cause interrupts often occur in an unpredictable manner or require to be serviced immediately in some applica - tions. during that period, if only one stack is left, and en - abling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. bit no. label function 0 emi controls the master (global) interrupt (1=enabled; 0=disabled) 1 eei controls the external interrupt (1=enabled; 0=disabled) 2 et0i controls the timer/event counter 0 interrupt (1=enabled; 0=disabled) 3 et1i controls the timer/event counter 1 interrupt (1=enabled; 0=disabled) 4 eif external interrupt request flag (1=active; 0=inactive) 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc0 register bit no. label function 0 emfi control multi-function interrupt (1=enabled; 0=disabled) 1 eadi control the adc interrupt (1=enabled; 0=disabled) 2 tke control touch key interrupt (1=enabled; 0=disabled) 3 unused bit, read as 0 4 mff multi-function interrupt request flag (1=active; 0=inactive) 5 adf adc request flag (1=active; 0=inactive) 6 tkf touch key interrupt (1=active; 0=inactive) 7 unused bit, read as 0 intc1 register www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 15 july 19, 2011 interrupts for touch key interrupt the touch key interrupt is initialised by setting the touch key interrupt request flag, tkf, bit 6 of intc1. this is caused by a signal completion of the touch key sensor. after the interrupt is enabled, and the stack is not full, and the tkf bit is set, a subroutine call to loca - tion 18h occurs. the related interrupt request flag, tkf, will be reset and the emi bit is cleared to disable further maskable interrupts. oscillator configuration the device provides three system oscillator circuits known as a crystal oscillator (hxt), an external rc os - cillator (erc) and an internal high speed rc oscillator (hirc) which are used for the system clock. there are also an internal 12khz rc (lirc) and a 32.768khz crystal oscillator (lxt) which can provide a source clock for the wdt clock named f s , the lcd driver clock named f sub and the timer/event counters low fre - quency clock named f l for various timing purposes. in the power down mode, the system oscillator, the in - ternal 12khz rc oscillator (lirc) or the external 32.768khz crystal oscillator (lxt) may be enabled or disabled depending upon the corresponding clock con - trol bit described in the relevant sections. the system can be woken-up from the power down mode by the oc- currence of an interrupt, a transition determined by con- figuration options on any of the port a pins, a wdt overflow or a timer overflow. external crystal/ ceramic oscillator hxt the external crystal/ceramic system oscillator is one of the system oscillator choices, which is selected via configuration options. for most crystal oscillator config - urations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, if a resonator instead of crystal is connected between osc1 and osc2, to ensure oscilla - tion, it may be necessary to add two small value capaci - tors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 24k and 1.5m , is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator config - uration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no influ - ence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compen - sation circuits are used to ensure that the influence of the power supply voltage, temperature and process varia - tions on the oscillation frequency are minimised. as a re - sistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 4mhz within a toler - ance of 2%. here only the osc1 pin is used, which is shared with i/o pin pa6, leaving pin pa5 free for use as a normal i/o pin. internal rc oscillator hirc the internal rc oscillator is a fully integrated system os - cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal fre- quency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 c degrees, the fixed os- cillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa5 and pa6 are free for use as normal i/o pins. ! 2 5 * - + + ) - b & - 7 + & . * c 9 5 * 5 - * 5 3 - & 7 @ 5 3 - + - & * 5 external crystal/ceramic oscillator @ 5 6 external rc oscillator erc www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 16 july 19, 2011 external 32.768khz crystal oscillator lxt the external 32.768khz crystal oscillator is one of the low frequency oscillator choices, which is selected via a configuration option. this clock source has a fixed fre - quency of 32.768khz and requires a 32.768khz crystal to be connected between pins osc3 and osc4. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscil - lation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manu - facturing tolerances. during power-up there is a time de - lay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the power down mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the power down mode. to do this, another clock, independent of the system clock, must be provided. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufac - turer s specification. the external parallel feedback re - sistor, rp, is required. lxt oscillator c1 and c2 values crystal frequency c1 c2 32768hz 8pf 10pf note: 1. c1 and c2 values are for guidance only. 2. r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the qosc bit in the ctrl0 register. qosc bit lxt mode 0 quick start 1 low-power after power on the qosc bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. how - ever, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the qosc bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the appli - cation program sets the qosc bit high about 2 seconds after power-on. it should be noted that, no matter what condition the qosc bit is set to, the lxt oscillator will always function normally; the only difference is that it will take more time to start up if in the low-power mode. internal 12khz oscillator lirc the internal 12khz rc oscillator is one of the low fre- quency oscillator choices, which is selected via configu- ration option. it is a fully integrated rc oscillator with a typical period of approximately 65 s at 5v, requiring no external components for its implementation. if the sys - tem enters the power down mode, the internal rc oscil - lator can still continue to run if its clock is necessary to be used to clock the functions for timing purpose such as the wdt function, lcd driver or timer/event coun - ters. the internal rc oscillator can be disabled only when it is not used as the clock source for all the periph - eral functions determined by the configuration options of the wdt function and the relevant control bits which de - termine the clock is enabled or disabled for related pe - ripheral functions. - + - & * 5 ! 2 2 c & 1 & + 7 ' 5 > 7 - - b & - 7 + & . * c 5 * 5 - * 5 3 - & 7 @ 5 @ 0 ; : 8 external 32.768khz oscillator lxt www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 17 july 19, 2011 watchdog timer wdt the wdt is implemented using an internal 12khz rc oscillator known as lirc, an external 32.768khz crystal oscillator or the instruction clock which is the system clock divided by 4. the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watch - dog timer can be disabled by a configuration option. if the watchdog timer is disabled, the wdt timer will have the same manner as in the enable-mode except that the timeout signal will not generate a chip reset. so in the watchdog timer disable mode, the wdt timer counter can be read out and can be cleared. this function is used for the application program to access the wdt fre - quency to get the temperature coefficient for analog component adjustment. the lirc oscillator can be dis - abled or enabled by the oscillator enable control bits wdtosc1 and wdtosc0 in the wdt control register wdtc for power saving reasons. there are 2 registers related to the wdt function named wdtc and wdtd. the wdtc register can control the wdt oscillator enable/disable and the wdt power source. the wdtd register is the wdt counter content register and this register is read only. the lirc oscillator power source selection bits named lircpwr1 and lircpwr0 can be used to choose the lirc oscillator power source, the lirc oscillator default power source is from vochp. the main purpose of the regulator is to be used for the wdt tempera- ture-coefficient adjustment. in this case, the application program should enable the regulator before switching to the regulator source. the lircen1 and lircen0 bits can be used to enable or disable the lirc oscillator (12 khz). if the application does not use the lirc oscillator, then it needs to disable it in order to save power. when the lirc oscillator is disabled, then it is actually turned off, regardless of the setting of the relevant control bits which select the lirc oscillator as its clock source. when the lirc oscillator is enabled, it can be used as the clock source in the power down mode defined by the corre - sponding control bits of the peripheral functions. once the internal 12khz rc oscillator lirc with period 65 s normally is selected, it is divided by max. 2 15 to get the time-out period of approximately 2.15s. this time-out period may vary with temperature, vdd and process variations. the wdt clock source may also come from the instruc - tion clock, in which case the wdt will operate in the same manner except that in the power down mode the wdt may stop counting and lose its protecting purpose. in this situation the device can only be restarted by ex - ternal logic. if the device operates in a noisy environ - ment, using the on-chip lirc oscillator is strongly recommended, since the halt instruction will stop the system clock. hxt system oscillator erc hirc lirc low speed oscillators f l f sys lxt f s configuration option f sys /4 f sub system oscillator configuration options timer/event counter 0, 1, 2 lfs fsubc lcd driver f s wdt (ctrl0) (ctrl0) rtcen lircen[1:0] (ctrl1) cpu (wdtc) halt halt, oscen www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 18 july 19, 2011 the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the power down mode, the overflow initializes a warm reset , and only the pc and sp are reset to zero. there are three methods to clear the contents of the wdt, an external reset (a low level on res ), a software instruction or a halt instruction. there are two types of software in - structions; the single clr wdt instruction, or the pair of instructions clr wdt1 and clr wdt2. of these two types of instruction, only one type of in - struction can be active at a time depending on the con - figuration option clr wdt times selection option. if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. if the clr wdt1 and clr wdt2 option is chosen (i.e., clr wdt times equal two), these two in - structions have to be executed to clear the wdt, other - wise the wdt may reset the chip due to a time-out. bit no. label function 0 1 lircpwr0~ lircpwr1 the lirc oscillator power source selection. 01: lirc power comes from vochp 10: lirc power comes from regulator 00/11: lirc power comes from vochp it is strongly recommend to use 01 for vochp to prevent the noise to let the lirc lose the power 2 3 lircen0~ lircen1 the lirc oscillator enable/disable control bits 01: lirc oscillator is disabled 10: lirc oscillator is enabled 00/11: lirc oscillator is enabled it is strongly recommended to use 10 for lirc osc enable 4 reserved 5 6 7 ws0 ws1 ws2 ws2~ws0: wdt prescaler rate select wdtc (1ch) register note: the initial value of the lircen1 and lircen0 bits will be set to 10 to enable the lirc oscillator if both the wdt function is enabled and the wdt clock is selected from the lirc oscillator determined by the configura - tion options. otherwise, the initial value of these two bits will be set to 01. the wdt clock (f s ) is further divided by an internal counter to give longer watchdog time-out period. in this de - vice, the division ratio can be varied by selecting different values of ws2~ws0bits to give 2 8 /f s to 2 15 /f s division ratio range. ws2 ws1 ws0 wdt rate 000 2 8 /f s 001 2 9 /f s 010 2 10 /f s 011 2 11 /f s 100 2 12 /f s 101 2 13 /f s 110 2 14 /f s 111 2 15 /f s bit no. label function 0~7 wdtd0~ wdtd7 the wdt counter value (bit4 ~ bit11) this register is read only and used for temperature adjusting. wdtd (1dh) register www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 19 july 19, 2011 buzzer output the buzzer function provides a means of producing a variable frequency output, suitable for applications such as piezo-buzzer driving or other external circuits that re - quire a precise frequency generator. the bz and bz pins form a complimentary pair, and are pin-shared with i/o pins, pa1 and pa2. the selection bits named bzs and bzs in the sfs register are used to select the buzzer options. note that the bz pin is the inverse of the bz pin which together generates a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the timer/event counter 0 or timer/event counter 1 overflow signal divided by 2 se - lected by the clock source selection bit named bzcs in the ctrl1 register. if the software selection bits have selected both pins pa1 and pa2 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits pac1 and pac2 of the pac port control reg - ister to zero. the pa1 data bit in the pa data register pac register pac1 pac register pac2 pa data register pa1 pa data register pa2 output function 00 0 x pa1= 0 , pa2=0 0 0 1 x pa1=bz, pa2=bz 01 0 x pa1= 0 , pa2=input line 0 1 1 x pa1=bz, pa2=input line 1 0 1 x pa1=input line, pa2=bz 10 0 x pa1=input line, pa2= 0 1 1 x x pa1=input line, pa2=input line x stands for don t care pa1/pa2 pin function control - - 3 + c & 8 8 - + , d & 5 & d & 5 & buzzer output pin control - + 4 . & - 3 . & - 5 4 + . 4 + . 9 * - & * 3 e 9 3 4 4 4 : $ < 4 $ 1 + 3 6 ' & - * f 4 ; 9 3 > = 9 3 > 9 3 > 9 3 > 9 3 > 9 3 > 9 3 > 6 9 3 1 f 1 $ ! 9 ' & & * 4 g 4 g $ 1 + 3 4 g watchdog timer www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 20 july 19, 2011 must also be set high to enable the buzzer outputs, if set low, both pins pa1 and pa2 will remain low. in this way the single bit pa1 of the pa data register can be used as an on/off control for both the bz and bz buzzer pin out - puts. note that the pa2 data bit in the pa data register has no control over the bz buzzer pin pa2. if software selection bits have selected that only the pa1 pin is to function as a bz buzzer pin, then the pa2 pin can be used as a normal i/o pin. for the pa1 pin to func - tion as a bz buzzer pin, pa1 must be setup as an output by setting bit pac1 of the pac port control register to zero. the pa1 data bit in the pa data register must also be set high to enable the buzzer output, if set low pin pa1 will remain low. in this way the pa1 bit can be used as an on/off control for the bz buzzer pin pa1. if the pac1 bit of the pac port control register is set high, then pin pa1 can still be used as an input even though the software selection bit has configured it as a bz buzzer output. note that no matter what the software selection bit is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will over - ride the software selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the software selection chosen; the ac- tual function of the pin can be changed dynamically by the application program by programming the appropri- ate port control register bit. note: the buzzer output pin control drawing shows the situation where both pins pa1 and pa2 are selected by software selection bits to be bz and bz buzzer pin out- puts. the port control register of both pins must have already been setup as outputs. the data setup on pin pa2 has no effect on the buzzer outputs. power down operation halt the power down mode is initialised by the halt in - struction and results in the following. the system oscillator stops running if the system os - cillator is selected to be turned off by clearing the oscon bit in the haltc register to zero. otherwise, the system oscillator will keep running if it is selected to be turned on in the power down mode. the contents of the on-chip data memory and of the registers remain unchanged. the wdt is cleared and starts recounting (if the wdt clock source is from the lirc or the lxt oscillator). all i/o ports maintain their original status. the pdf flag is set but the to flag is cleared. the lcd driver keeps running if the lcd clock f sub is enabled by setting the fsubc bit to 1 and the lcdon bit in the haltc register is set to 1 . the system leaves the power down mode by means of an external reset, an interrupt, an external transition sig - nal on port a, or a wdt overflow. an external reset causes device initialisation, and the wdt overflow per - forms a warm reset . after examining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. on the other hand, the to flag is set if wdt time-out occurs, and causes a wake-up that only re - sets the program counter and sp, and leaves the others in their original state. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each pin of port a can be independently selected to wake-up the device using the corresponding wake-up control bits. af- ter awakening from an i/o port stimulus, the program will resume execution at the next instruction. however, if awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is en- abled but the stack is full, the program will resume exe- cution at the next instruction. but if the interrupt is enabled, and the stack is not full, the regular interrupt re- sponse takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awakened using that interrupt. if a wake-up events occur, it takes 1024 t sys (system clock periods) or 2 t sys depending upon the sst config - uration option value, the oscon bit setting and the se - lected system oscillator type to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an inter - rupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, bit no. label function 0 lcdon lcd module state in power down mode 1: lcd module remains on (if f sub is active) regardless of the configuration option setting 0: lcd state is determined by the lcd_on configuration option 1~6 reserved, read as 0 7 oscon system oscillator state in power down mode 1: system oscillator keeps running in power down mode 0: system oscillator stops running in power down mode haltc register www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 21 july 19, 2011 if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. system oscillator sst configuration option oscon bit sst time hxt x 0 1024 t sys 12t sys erc 0 0 1024 t sys 012 t sys 1x2 t sys hirc 0 0 1024 t sys 012 t sys 1x2 t sys x: don t care system start-up time (sst) period reset there are several ways in which a reset may occur. res is reset during normal operation res is reset during halt low voltage reset wdt time-out is reset during normal operation the wdt time-out during power down mode differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and sp and leaves the other circuits at their original state. some registers remain unaffected during any other re- set conditions. most registers are reset to their initial conditions once the reset conditions are met. by exam - ining the pdf and to flags, the program can distinguish between different chip resets. to pdf reset conditions 0 0 res reset during power-up u u res or lvr reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 or 2 system clock pulses dependent upon the configuration option and software setting when the system awakes from the halt state or during power-up. awaking from the halt state or system power-up, the sst delay is added. an extra sst delay is added during the power-up pe - riod, and any wake-up from halt may enable only the sst delay. the functional unit chip reset status is shown below. program counter 000h interrupt disabled prescaler, divider cleared wdt cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack $ ' & 5 * reset timing chart $ , , $ , reset circuit note: most applications can use the basic reset cir - cuit as shown, however for applications with ex - tensive noise, it is recommended to use the hi-noise reset circuit. : 4 $ % - + $ + 7 * ) * * ' 1 5 5 + & - - * reset configuration www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 22 july 19, 2011 the register states are summarized below: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* iar0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuuuuuu uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ctrl0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctrl1 ---- --01 ---- --01 ---- --01 ---- --01 ---- --uu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pbc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu adcr -000 x000 -000 x000 -000 x000 -000 x000 -uuu xuuu adcd 0000 -111 0000 -111 0000 -111 0000 -111 uuuu -uuu wdtc 111- ss01 111- ss01 111- ss01 111- ss01 uuu- uuuu wdtd 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu chprc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr2h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu haltc 0--- ---0 0--- ---0 0--- ---0 0--- ---0 u--- ---u lcdout 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctrl1 00-- --01 00-- --01 00-- --01 00-- --01 uu-- --uu vibrc ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u regc ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pawk 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 23 july 19, 2011 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* papu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pbpu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu pcpu 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu sfs ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu lcdc -0-0 -000 -0-0 -000 -0-0 -000 -0-0 -000 -u-u -uuu mfic -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu tkm016dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: * stands for warm reset u stands for unchanged - not implement x stands for unknown s stands for depending upon the configuration options . refer to the wdt section for more details. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 24 july 19, 2011 timer/event counter three timer/event counters are implemented in the microcontroller. timer/event counter 0 contains an 8-bit programmable count-up counter whose clock may come from an external source or an internal clock source. an internal clock source comes from f sys or the internal low frequency clock known as f l . the clock f l is derived from the lirc or lxt oscillator and can be se - lected by the low frequency selection bit lfs bit in the ctrl0 register. timer/event counter 1 contains a 16-bit programmable count-up counter whose clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4 or the internal low frequency clock known as f l . the clock f l is derived from the lirc or lxt oscillator and can be selected by the low frequency selection bit lfs bit in the ctrl0 register. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. timer/event counter 2 contains a 16-bit programmable count-up counter whose clock may come from an exter - nal source or an internal clock source. an internal clock source comes from f sys /4 or the the internal low fre - quency clock known as f l . the external clock input al - lows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are two registers related to the timer/event counter 0; tmr0 and tmr0c. writing to tmr0 puts the starting value in the timer/event counter 0 register and reading tmr0 reads out the contents of timer/event counter 0. the tmr0c is a timer/event counter control register, which defines the overall operations. there are three registers related to the timer/event counter 1; tmr1h, tmr1l and tmr1c. writing to tmr1l will only put the written data into an internal lower-order byte buffer (8-bit) while writing to tmr1h will transfer the specified data and the contents of the lower-order byte buffer to both the tmr1h and tmr1l registers, respec - tively. the timer/event counter 1 preload register is changed when each time there is a write operation to tmr1h. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading tmr1l will read the contents of the lower-order byte buffer. tmr1c is the timer/event counter 1 control register, which defines the operating mode, counting enable or disable, the tmr1 active edge and the prescaler stage selections. also there are three registers related to the timer/event counter 2 named tmr2h, tmr2l and tmr2c. the operations of reading from and writing to the timer/event counter 2 registers named tmr2h and tmr2l are the same with timer/event counter 1 de- scribed above. + 7 - 3 + c - - & 5 / / / $ / / ! & + * 7 / * & - / 7 - + ; ' 1 - 9 $ & - - + 7 . * - ; ' 1 - 9 $ & - " / # & * ; ' * . - * + - ; ' / a g 3 ! f / a g 3 e 3 / a g 4 4 " , : 8 # 4 g " @ 0 ; , : 8 # 9 d 3 4 timer/event counter 0 / / / $ / / ! & + * 7 / * & - / 7 - + 3 ! & * + 7 - 3 + c - - & 5 4 c ) & 3 3 - : . ) 4 c ) 0 ' - 9 $ & - ; ' * . - * + - ; ' / a g f / a g 3 e 9 3 0 ' 1 - 9 $ & - - + 7 . * - / a g 4 4 " , : 8 # 4 g " @ 0 ; , : 8 # 9 d 3 4 timer/event counter 1 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 25 july 19, 2011 bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 to define the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int0 =f t0 001: f int0 =f t0 /2 010: f int0 =f t0 /4 011: f int0 =f t0 /8 100: f int0 =f t0 /16 101: f int0 =f t0 /32 110: f int0 =f t0 /64 111: f int0 =f t0 /128 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t0on enable/disable timer counting (0=disabled; 1=enabled) 5 t0s defines the tmr0 internal clock source 0: f sys 1: low frequency clock f l 6 7 t0m0 t0m1 defines the operating mode t0m1, t0m0= 01: event count mode (external clock) 10: timer mode (internal clock) 11: pulse width measurement mode (external clock) 00: unused tmr0c (0eh) register / / / $ / / ! & + * 7 / * & - / 7 - + 3 ! & * + 7 - 3 + c - - & 5 4 c ) & 3 3 - : . ) 4 c ) 0 ' - 9 $ & - ; ' * . - * + - ; ' / a g f / a g 3 e 9 3 0 ' 1 - 9 $ & - - + 7 . * - / a g 4 4 " , : 8 # 4 g " @ 0 ; , : 8 # 3 4 timer/event counter 2 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 26 july 19, 2011 bit no. label function 0 1 2 t1psc0 t1psc1 t1psc2 to define the prescaler stages, t1psc2, t1psc1, t1psc0= 000: f int1 =f t1 001: f int1 =f t1 /2 010: f int1 =f t1 /4 011: f int1 =f t1 /8 100: f int1 =f t1 /16 101: f int1 =f t1 /32 110: f int1 =f t1 /64 111: f int1 =f t1 /128 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1: count on falling edge; 0: count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t1on enable/disable timer counting (0=disabled; 1=enabled) 5 t1s defines the tmr1 internal clock source 0: f sys /4 1: low frequency clock f l 6 7 t1m0 t1m1 defines the operating mode t1m1, t1m0= 01: event count mode (external clock) 10: timer mode (internal clock) 11: pulse width measurement mode (external clock) 00: unused tmr1c (11h) register bit no. label function 0 1 2 t2psc0 t2psc1 t2psc2 to define the prescaler stages, t2psc2, t2psc1, t2psc0= 000: f int2 =f t2 001: f int2 =f t2 /2 010: f int2 =f t2 /4 011: f int2 =f t2 /8 100: f int2 =f t2 /16 101: f int2 =f t2 /32 110: f int2 =f t2 /64 111: f int2 =f t2 /128 3 t2e defines the tmr2 active edge of the timer/event counter: in event counter mode (t2m1,t2m0)=(0,1): 1: count on falling edge; 0: count on rising edge in pulse width measurement mode (t2m1,t2m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t2on enable/disable timer counting (0=disabled; 1=enabled) 5 t2s defines the tmr2 internal clock source 0: f sys /4 1: f l 6 7 t2m0 t2m1 defines the operating mode t2m1, t2m0= 01: event count mode (external clock) 10: timer mode (internal clock) 11: pulse width measurement mode (external clock) 00: unused tmr2c register www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 27 july 19, 2011 the txm0 and txm1 bits in tmrxc register where x may be equal to 0, 1 or 2 define the operation mode. the event count mode is used to count external events, which means that the clock source must come from the external (tmr0, tmr1 or tmr2) pin. the timer mode functions as a normal timer with the clock source com - ing from the internal selected clock source. finally, the pulse width measurement mode can be used to count a high or low level duration of an external signal on the tmr0, tmr1 or tmr2 pins with the timing based on the internally selected clock source. in the event count or timer mode, the timer/event coun - ter starts counting at the current contents in the timer/event counter and ends at ffh for -8-bit counter or ffffh for 16-bit counter. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag, t0f, t1f or t2f. in the pulse width measurement mode with the values of the timer enable control bit txon and the active edge control bit txe equal to 1 , after the tmrx pin has received a transient from low to high (or high to low if the txe bit is 0 ), it will start counting until the tmrx pin returns to the original level and resets the txon bit. the measured result remains in the timer/event counter even if the activated transient occurs again. therefore, only a 1-cycle measurement can be made until the txon bit is again set. the cycle measure- ment will re-function as long as it receives further transient pulses. in this operation mode, the timer/event counter be- gins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer enable bit known as txon in tmrxc where x indicates 0, 1 or 2 should be set to 1 . in the pulse width measurement mode, the txon is automatically cleared after the mea - surement cycle is completed. but in the other two modes, the txon bit can only be reset by instructions. the over - flow of the timer/event counters is one of the wake-up sources. no matter what the operation mode is, writing a 0 to the related timer/event counter interrupt enable control bit etxi disables the related interrupt service. in the case of a timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin - ues its operation until an overflow occurs. when the timer/event counter register tmrx or tmrxh/tmrxl is read, the clock is blocked to avoid er - rors, however as this may result in a counting error, it should be taken into account by the programmer. it is strongly recommended to load a desired value into the timer/event counter register tmrx or tmrxh/tmrxl first, before turning on the related timer/event counter, for proper operation since the initial value of tmrx or tmrxh/tmrxl is unknown. due to the timer/event counter scheme, the programmer should pay special attention to the instructions which enables then disables the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredict - able results. after this procedure, the timer/event func - tion can be operated normally. the bit0~bit2 of the timer/event counter control regis - ter tmrxc can be used to define the pre-scaling stages of the internal clock sources of timer/event counters. input/output ports there are up to 22 bidirectional input/output lines in the microcontroller, labeled as pa, pb and pc. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruc - tion mov a, [m] . for output operation, all the data is latched and remains unchanged until the output latch is re - written. each i/o line has its own control register, pac, pbc and pcc, to control the input/output configuration. with this control register, cmos outputs or schmitt trigger inputs with or without pull-high resistor structures can be re- configured dynamically under software control. to func- tion as an input, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1, the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the inter - nal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only con - figuration except pa7. these control registers are mapped to the ram memory locations respectively. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, and 15h. after a chip reset, these input/output lines remain at high levels or in a floating state, depending upon the pull-high configuration options. each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i, cpl [m], cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 28 july 19, 2011 / a g / a g $ ! f 0 / > / > / > ! ) * , ' & 5 " + ) # 7 . * - > - + & + + ' : . 5 & * - - + . * - 5 * 7 - + . * - - . * - 9 9 d 9 d 9 9 6 9 0 9 9 9 9 9 9 ! 6 9 / 9 / 9 $ < 9 / 9 $ < 9 $ < 9 $ < 9 $ < 6 9 $ < 6 0 9 $ < 0 @ 9 $ < @ d > d h h h h input/output ports @ / a g 7 . * - - + & * - - + . * - 5 * 7 - + . * - - . * - h h h h @ 9 $ ) * , ' & 5 " @ # $ 3 - @ + ) pa7 pin www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 29 july 19, 2011 each pin of these three i/o ports except pa7 pin has a pull-high resistor determined by a software option. once the pull-high software option is selected, the i/o pin has a pull-high resistor connected. take note that a non-pull-high i/o pin setup as an input will be in a float - ing condition. pa1 and pa2 are pin-shared with bz and bz signal, re - spectively. if the software selection bits are selected these pins as buzzer function, the output signals in the output mode of pa1/pa2 can be the buzzer signal. the input mode always retains its original function. once the software selection bits are selected as the bz/bz func - tion, the buzzer output signals are controlled by the pa1 data register. it is recommended that unused or not bonded out i/o lines should be set as output pins using software in - structions to avoid consuming power when in an input floating state. i/o register lists register name bit 76543210 sfs bzbs bzs pa pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pac pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 pawk pawk7 pawk6 pawk5 pawk4 pawk3 pawk2 pawk1 pawk0 papu papu6 papu5 papu4 papu3 papu2 papu1 papu0 pb pb5 pb4 pb3 pb2 pb1 pb0 pbc pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pcc pcc7 pcc6 pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 unimplemented, read as 0 pan, pbn, pcn : i/o line data bit. pacn, pbcn, pccn : i/o line control bit. papun, pbpun, pcpun : i/o line pull-high control. 0: disabled 1: enabled pawkn : port a wake-up control. 0: disabled 1: enabled sfs register bit76543210 name bzbs bzs r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1 bzbs : pa2 pin-shared function selection 0: i/o 1: bz bit 0 bzs : pa1 pin-shared function selection 0: i/o 1: bz www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 30 july 19, 2011 charge pump and voltage regulator there is one charge pump and one voltage regulator im - plement in this device. the charge pump can be enabled or disabled by the ap - plication program. the charge pump uses vdd as its in - put, and has the function of doubling the vdd voltage. the output voltage of the charge pump will be vddx2. the regulator can generate a stable voltage of 3.3v, for internal lirc oscillator, adc and also can provide an external bridge sensor excitation voltage or supply a ref - erence voltage for other applications. the user needs to guarantee the charge pump output voltage is greater than 3.6v to ensure that the regulator generates the re - quired 3.3v voltage output. the block diagram of this module is shown below. additionally, the device also includes a band gap voltage generator for the 1.5v low temperature sensitive refer- ence voltage. this reference voltage is used as the zero adjustment and for a single end type reference voltage. r fil is about 100k and the recommend c fil is 10 f. note: vobgp signal is only for chip internal used. don t connect to external component except the recommend c fil if the regcen bit is set to 0, the regulator will be dis - abled. when the regulator is disabled, the regulator out - put can be connected to a grounded resistor to allow its output to fall to zero rapidly. the regulator output can also be selected to be in a floating state. the vosw bit in the regc register is used to select the regulator out - put state when the regulator is disabled. chprc is the charge pump/regulator control register, which controls the charge pump on/off, regulator on/off functions as well as setting the clock divider value to generate the clock for the charge pump. the chpckd4~chpckd0 bits are use to set the clock divider to generate the desired clock frequency for proper charge pump operation. the actual frequency is determined by the following formula. actual charge pump clock= (f sys /16)/(chpckd +1). the suggested charge pump clock frequency is 20khz. the application needs to set the correct value to get the desired clock frequency. for a 4mhz application, the chpckd bits should be set to the value 11, and for a 2mhz application, the bits should be set to 5. the regcen bit in the chprc register is the regula - tor/ charge-pump module enable/disable control bit. if this bit is disabled, then the regulator will be disabled and the charge pump will be also be disabled to save power. when regcen = 0, the module will enter the power down mode ignoring the chpen setting. the adc and opa will also be disabled to reduce power. if regcen is set to 1 , the regulator will be enabled. if chpen is enabled, the charge pump will be active and will use vdd as its input to generate the double voltage output. this double voltage will be used as the input volt - age for the regulator. if chpen is set to 0 , the charge pump is disabled and the charge pump output will be equal to the charge pump input, vdd. it is necessary to take care of the v dd voltage. if the volt - age is less than 3.6v, then chpen should be set to 1 to enable the charge pump, otherwise chpen should be set to zero. if the charge pump is disabled and v dd is less than 3.6v then the output voltage of the regulator will not be guaranteed. % : 7 - 3 e : $ ! $ < $ ! $ < 4 : : : . & + - " # - . & 5 " + . & 1 + - # < 4 < h 1 2 3 3 " * - # 2 . & + - 7 < 5 $ $ 4 regc register bit76543210 name vosw r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 vosw : voltage regulator output selection 0: voreg is connected a resistor to ground 1: voreg is in a floating state. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 31 july 19, 2011 bit no. label function 0 regcen enable/disable regulator/charge-pump module. (1=enable; 0=disable) 1 chpen charge pump enable/disable setting. (1=enable; 0=disable) note: this bit will be ignore if the regcen is disable 2 bgpqst band gap quickly start-up function 0: r short, quickly start 1: r connected, normal rc filter mode every time when regcen change from 0 to 1 (regulator turn on) this bit should be set to 0 and then set to 1 to make sure the quickly stable. (the minimum 0 keeping time is about 2ms now ) 3~7 chpckd0~ chpckd4 the charge pump clock divider. this 5 bits can form the clock divide by 1~32. following the below equation: charge pump clock = (f sys /16) / (chpckd+1) chprc (1fh) register regcen chpen charge pump vochp pin regulator voreg pin opa adc description 0 x off v dd off hi-impedance disable the whole module is disable, opa/adc will lose the power 1 0 off v dd on 3.3v active use for v dd is greater than 3.6v (v dd >3.6v) 11on 2v dd on 3.3v active use for v dd is less than 3.6v (v dd =2.2v~3.6v) adc dual slope a dual slope a/d converter is implemented in this microcontroller. the dual slope module includes an op- erational amplifier, a programmable gain amplifier pga for the amplification of differential signals, an integrator and a comparator for the main dual slope ad converter. there are 2 special function registers related to this function known as adcr and adcd. the adcr regis - ter is the a/d control register, which controls the adc block power on/off, the chopper clock on/off, the charge/discharge control and is also used to read out the comparator output status. the adcd register is the a/d chopper clock divider register, which defines the chopper clock to the adc module. the adpwren bit, defined in adcr register, is used to control the adc module on/off function. the adccken bit defined in the adcr register is used to control the chopper clock on/off function. when adccken is set to 1 it will enable the chopper clock, with the clock fre - quency defined by the adcd register. the adc module includes the opa, pga, integrator and comparator. however, the bandgap voltage generator is independ - ent of this module. it will be automatically enabled when the regulator is enabled, and also be disabled when the regulator is disabled. the application program should enable the related power to permit them to function and disable them when entering the power down mode to conserve power. the charge/discharge control bits, addisch1 and addisch0, are used to control the dual slope circuit charging and discharging behavior. the adcmpo bit is read only for the comparator output, while the adintm bits can set the adcmpo trigger mode for interrupt generation. the adc pga input sig- nal can come from the dchop, th/lb or ai pin se- lected by the adis selection bit in adcd register. the pga gain can be either 2 or 4 determined by the pgag gain selection bit in the adcd register. the reference voltages of the adc integrator and comparator named vint and vcmp shown in the dual slope adc structure diagram can be selected by the adrr0 selection bit. dual slope adc operation the following descriptions are based on the fact that the adrr0 bit is set to 0. the amplifier and buffer combination, form a differential in - put pre-amplifier which amplifies the sensor input signal. ( ' / 9 0 9 0 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 32 july 19, 2011 bit no. label function 0 1 2 adcd0 adcd1 adcd2 define the chopper clock (adccken should be enable), the suggestion clock is around 10khz. the chopper clock define : 0: clock= (f sys /32)/1 1: clock= (f sys /32)/2 2: clock= (f sys /32)/4 3: clock= (f sys /32)/8 4: clock= (f sys /32)/16 5: clock= (f sys /32)/32 6: clock= (f sys /32)/64 7: clock= (f sys /32)/128 3 unimplemented, read as 0 4 adrr0 adc integrator and comparator reference voltage selection 0: (vint, vcmp) = (4/6 vdso, 1/6 vdso) 1: (vint, vcmp) = (4.4/6 vdso, 1/6 vdso) 5 6 adis0 adis1 ad pga input selection 00: from ai pin 01: from th/lb pin 10: from dchop pin 11: reserved 7 pgag adc pga gain selection 0: gain = 2 1: gain = 4 adcd (1ah) register ( ' 5 + 3 - ! 5 3 3 5 / a g < < : . - - ( ' 5 - - - + / $ ! $ < : : ! 3 3 / ( ' / a g 3 - : 9 4 3 - : : 9 4 < " < i > # " 5 & 3 - % - + - + 9 + c 1 - ) 7 - - & * . # 3 ! 2 ! > / * . + 3 - 7 3 3 - . - & 5 * c - * + 7 1 ) * 3 c - - . * - * dual slope adc structure www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 33 july 19, 2011 5 5 - 5 + 3 - ! : < @ , 5 3 3 5 ! 2 + + ? ? 7 ? ? + & * - - 3 - - 3 - + ) - 7 . * - $ < 6 , dual slope adc with bridge sensor input the combination of the integrator, the comparator, the resistor r ds , between dsrr and dsrc and the capaci - tor c ds , between dsrc and dscc form the main body of the dual slope adc. the integrator integrates the output voltage increase or decrease and is controlled by the switch circuit - refer to the block diagram. the integration and de-integration curves are illustrated by the following. the comparator will switch the state from high to low when v c , which is the dscc pin voltage,drops to less than 1/6 vdso. in general applications, the application program will switch the adc to the charging mode for a fixed time called ti, which is the integrating time. it will then switch to the dis-charging mode and wait for v c to drop to less than 1/6 vdso. at this point the comparator will change state and store the time taken, t c , which is the de-integrating time. the following formula 1 can then be used to calculate the input voltage v a . formula 1: v a = (1/3) vdso(2 tc/ti). (based on adrr0=0) in user applications, it is required to choose the correct value of r ds and c ds to determine the ti value, to allow the v c value to operate between 5/6 vdso and 1/6 vdso. v full cannot be greater than 5/6 vdso and v zero cannot be less than 1/6 vdso. " 8 - # " 3 & + + # ' . - . - 9 0 a 4 4 d $ www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 34 july 19, 2011 lcd driver lcd display memory the device provides an area of embedded data memory for the lcd display. this area is located at 40h to 5bh in bank 1 of the data memory. the bank pointer bp en- ables either the general purpose data memory or lcd memory to be chosen. when bp is set to 1 , any data written into location range 40h~5bh will affect the lcd display. when the bp is cleared to 0 , any data written into 40h~5bh will access the general purpose data memory. the lcd display memory can be read and writ - ten to only indirectly using mp1. when data is written into the display data area, it is automatically read by the lcd driver which then generates the corresponding lcd driving signals. to turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. the figure illustrates the mapping between the display memory and lcd pattern for the device. the lcd clock is driven by the f sub clock, which then passes through a divider, the division ratio of which is selected by the lcd clock selection bits lcdck1 and lcdck0 in the ctrl0 register to provide a lcd clock frequency of f sub /3, f sub /4 or f sub /8. the lcd clock source f sub can be derived from the lirc or lxt oscilla- tor selected by the selection bit named fsubs. note that the f sub clock can be enabled or disabled in the power down mode by the f sub clock control bit fsubc in the ctrl0 register. lcd driver output the output number of the lcd driver device can be con - figured as 24 8to28 4 using the corresponding soft - ware selection bits. the lcd driver bias type can be r type or c type determined by the rcs bit in the ldc register. the lcd driver has a fixed 1/3 bias value. if the c type bias is selected, a capacitor mounted between c1 and c2 pins is needed and two capacitors are needed to be connected to the ground for v ab and v c pins. all the capacitance of capacitors used for lcd bias generator is suggested to use the 0.1 f. bit no. label function 0 adpwren dual slope block (including input op) power on/off switching. 0: disable power 1: power source comes from the regulator. 1~2 addisch0~ addisch1 defines the adc discharge/charge. (addisch1:0) 00: reserved 01: charging (integrator input connect to buffer output) 10: discharging (integrator input connect to vdso) 11: reserved 3 adcmpo dual slope adc - last stage comparator output. read only bit, write data instructions will be ignored. during the discharging state, when the integrator output is less than the reference voltage, the adcmpo will change from high to low. 4~5 adintm0~ adintm1 adc integrator interrupt mode definition. these two bit define the adcmpo data interrupt trigger mode: (adintm1:0)= 00: no interrupt 01: rising edge 10: falling edge 11: both edge 6 adccken adc op chopper clock source on/off switching. 0: disable 1: enable (clock value is defined by adcd register) 7 unimplemented, read as 0 adcr (18h) register : / $ < / $ ! : : : 6 = : 6 : 6 : 6 0 @ display memory www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 35 july 19, 2011 lcdc register bit76543210 name vas rcs css2 css1 css0 r/w r/w r/w r/w r/w r/w por 0 0 000 bit 7 unimplemented, read as 0 bit 6 vas : vab pin voltage selection 0: v ab =v oreg 1: v ab = 1.5 v oreg this bit is only available when the lcd bias generator is selected to be c type. when the charge pump output voltage is equal to v dd and the c type bias generator is selected, the v ab voltage can only be selected as the v oreg voltage. if the charge pump output voltage is equal to 2 v dd , the v ab voltage can be selected as either the v oreg or 1.5 v oreg voltage. when rcs is set to 0 (r type), the user must write 1 to this bit. bit 5 unimplemented, read as 0 bit 4 rcs : lcd r type or c type bias selection 0: r type 1: c type bit 3 unimplemented, read as 0 bit 2~0 css2~css0 : lcd com/seg selection theses bits are used to configure the pin-shared com/seg function. depending upon the css bits settings, the lcd driver can be configured as 1/4 to 1/8 duty display. the configurations are shown in the following table. ccs2~0 duty pin-shared function maximum segcom com4/seg27 com5/seg26 com6/seg25 com7/seg24 000 1/4 seg27 seg26 seg25 seg24 284 001 1/5 com4 seg26 seg25 seg24 275 010 1/6 com4 com5 seg25 seg24 266 011 1/7 com4 com5 com6 seg24 257 1xx 1/8 com4 com5 com6 com7 248 lcdout register bit76543210 name lcds7 lcds6 lcds5 lcds4 lcds3 lcds2 lcds1 lcds0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~1 lcdsn : lcd seg or i/o function selection 0: i/o function -- pcn 1: seg function -- segn www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 36 july 19, 2011 / / / / 4 * . * ! / * 7 + . 7 $ % 5 + 2 9 7 & ) > 9 1 * > ) 5 > i > i 9 > i 9 lcd driver output (1/4 duty) www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 37 july 19, 2011 low voltage reset function there is a low voltage reset, lvr, circuit implemented in the microcontroller. the lvr functions can be enabled or disabled by the lvr function configuration option. the lvr has the same effect or function as the external res signal which performs a device reset. when in the power down mode, the lvr function is disabled. the microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as what might happen when changing a battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage, which is specified as 0.9v~v lvr , has to remain within this range for a period of time greater than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it will not perform a reset function. the lvr has an or function with the external res signal to perform a chip reset. 6 6 4 = * . + * j j ! - + 5 - * 4 + . low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. operation mode the device has two operational modes. the system clock may come from external rc (erc), external crystal (hxt) or internal rc (hirc) oscillator, and whose operational modes can be either normal mode or power down mode. when in the power down mode, the clocks in this device are all enabled or disabled using software. halt instruction mode system oscillator fsubc f sub clock rtcen rtc oscillator (osc3/osc4) not executed normal on x enable x on executed power down on (oscon=1) off (oscon=0) 0 disable 1 on power down on (oscon=1) off (oscon=0) 1 enable 1 on power down on (oscon=1) off (oscon=0) 0 disable 0 off power down on (oscon=1) off (oscon=0) 1 enable 0 off note: the lircen [1:0] and lircpwr [1:0] bits in the wdtc register should be properly configured to enable the lirc oscillator and select its power supply source. otherwise, the lirc osc will always be disabled. refer to the wdt section for the lirc oscillator setup details. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 38 july 19, 2011 bit no. label function 0 qosc 32.765khz crystal oscillator quick start-up control 0: quick start-up 1: low-power 1 fsubs f sub clock source selection 0: lirc oscillator 1: lxt oscillator 2 fsubc f sub power down mode clock control 0: disabled 1: enabled 3 4 lcdck0 lcdck1 to select the lcd driver clock: 00: lcd clock = f sub /3 01: lcd clock = f sub /4 1x: lcd clock = f sub /8 5 lfs low frequency clock source f l selection 0: lirc oscillator 1: lxt oscillator 6 7 reserved, should be kept as 00. ctrl0 register bit no. label function 0 rtcen 32.768khz oscillator (lxt) control in power down mode 0: disabled 1: enabled 1 bzcs buzzer clock source selection 0: from timer/event counter 0 1: from timer/event counter 1 2~5 unimplemented, read as 0 6 7 eintc1 eintc0 external interrupt trigger edge selection 00: disabled 01: falling edge 10: rising edge 11: double edges ctrl1 register vibration sensor amplifier the device contains a vibration sensor amplifier to am - plify the small electrical signals generated from vibration sensors. when the sensor is connected to the vibration input pin, vib, and a small signal resulting from a vibra - tion detection is generated on the vib pin, the internal amplifier will amplify the low amplitude signal which will then be used as a wake-up source when the device is in the power down mode. the vibration sensor amplifier can be enabled or disable by the control bit, vibren, in the vibrc register for power saving considerations. bit no. label function 0 vibren vibration sensor amplifier control 0: disabled 1: enabled 1~7 unimplemented, read as 0 vibrc register $ ! / a c , ' & 5 1 - * - 5 + 3 - - & * www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 39 july 19, 2011 touch key module the device provides four touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be imple - mented by the simple manipulation of internal registers. touch key structure the touch keys are pin-shared with the pb logic i/o pins, with the desired function chosen via register bits. these four keys are organised into a module and it con - tains its own control logic circuits and register set. touch key register definition the touch key module, which contains four touch key functions, has its own suite of six registers. the following table shows the register set for the touch key module. name description tkm016dh 16-bit c/f counter high byte tkm016dl 16-bit c/f counter low byte tkm0c0 control register 0 key select / x2 frequency / filter control / frequency select tkm0c1 control register 1 internal reference / touch pad reference tkm0c2 control register 2 counter on-off and clear control / reference clock control / tkst start bit tkm0c3 control register 3 counter overflow bits register description register name bit 76543 2 1 0 tkm016dh d7 d6 d5 d4 d3 d2 d1 d0 tkm016dl d7 d6 d5 d4 d3 d2 d1 d0 tkm0c0 m0mxs1 m0mxs0 d5 d4 d3 d2 d1 d0 tkm0c1 m0k4oen m0k3oen m0k2oen m0k1oen m0k4io m0k3io m0k2io m0k1io tkm0c2 m016cton d6 m0st m0roen m0rcclr m016ctclr d1 m0ros tkm0c3 d7 d6 m0rcov m016ctov d3 m0rovs2 m0rovs1 m0rovs0 register listing tkm016dh register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 touch key module 0 16-bit counter high byte contents tkm016dl register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 touch key module 0 16-bit counter low byte contents www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 40 july 19, 2011 tkm0c0 register b i t76543210 name m0mxs1 m0mxs0 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bits 7~6 m0mxs1, m0mxs0 : multiplexer key select 00: key 1 01: key 2 10: key 3 11: key 4 bit 5~0 d5~d0 : these bits must be set to the binary value 011000 tkm0c1 register b i t76543210 name m0k4oen m0k3oen m0k2oen m0k1oen m0k4io m0k3io m0k2io m0k1io r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~4 m0knoen : key selector control (n=1~4) 0: disable 1: enable bit 3~0 m0knio : touch key function select (n=1~4) 0: i/o pin 1: key n tkm0c2 register bit 7 6 5 4 3 2 1 0 name m016cton d6 m0st m0roen m0rcclr m016ctclr d1 m0ros r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 m016cton : 16-bit c/f counter control 0: disable 1: enable bit 6 d6 : this bit must be cleared to zero. bit 5 m0st : time slot counter start control 0: time slot counter stopped 0 1: enable time slot counter. when this bit changes from low to high, the time slot counter will be enabled and the touch sense procedure started. when the time slot counter has completed its counting, an interrupt will be generated. bit 4 m0roen : reference clock control 0: disable 1: enable bit 3 m0rcclr : time slot counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 2 m016ctclr : 16-bit c/f counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 1 d1 : this bit must be cleared to zero. bit 0 m0ros : time slot counter clock source 0: reference clock 1: key 4 sensor oscillator www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 41 july 19, 2011 tkm0c3 register bit 7 6 5 4 3 2 1 0 name d7 d6 m0rcov m016ctov d3 m0rovs2 m0rovs1 m0rovs0 r/w r r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7, d6 : read only bits -- unknown values bit 5 m0rcov : time slot counter overflow flag 0: no overflow 1: overflow bit 4 m016ctov : 16-bit c/f counter overflow flag 0: no overflow 1: overflow bit 3 d3 : this bit must be cleared to zero. bits 2~1 m0rovs2~m0rovs0 : time slot counter overflow time setup 000: 64 count 001: 128 count 010: 256 count 011: 512 count 100: 1024 count 101: 2048 count 110: 4096 count 111: 8192 count touch key operation when a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. by using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. using an internal programmable divider the reference clock is used to generate a fixed time period. by counting a number of generated clock cycles from the sense oscil - lator during this fixed time period touch key actions can be determined. the device contains four touch key inputs which are shared with logical i/o pins, with the desired function se - lected using register bits. the touch key module also has its own interrupt vectors and set of interrupts flags. during this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is mea - sured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fixed reference clock time interval, a touch key interrupt signal will be generated. touch key interrupt the touch key module, which consists of four touch keys, has the corresponding interrupts, one for each of the 16-bit c/f counter and time slot counter. the time slot counter interrupt has its own interrupt vec- tor while the 16-bit c/f counter interrupts are contained within the multi-function interrupts and therefore do not have their own vector. care must be taken during pro- gramming as the 16-bit c/f counter interrupt flags con- tained within the multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rather must be reset manually by the applica- tion program. more details regarding the touch key inter- rupts are located in the interrupt section of the datasheet. programming considerations after the relevant registers are setup, the touch key de - tection process is initiated the changing the m0st bit from low to high. this will enable and synchronise all rel - evant oscillators. the m0rcov flag, which is the time slot counter flag will go high and remain high until the counter overflows. when this happens an interrupt sig - nal will be generated. when the external touch key size and layout are de - fined, their related capacitances will then determine the sensor oscillator frequency. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 42 july 19, 2011 c/f & mux. mux. reference clock touch key (1 set = touch key*4) key0 key1 key2 key3 16-bit c/f counter 16-bit c/f counter overflow flag 16-bit c/f counter int flag time slot counter time slot counter overflow flag time slot counter int flag enable time slot counter clock select touch switch module block diagram & - & * 4 . 9 - & * / 1 / 1 / 1 / 1 $ % - + 9 - & ) & - & * 4 . 9 - & * $ % - + 9 - & ) & - & * 4 . 9 - & * $ % - + 9 - & ) & - & * 4 . 9 - & * $ % - + 9 - & ) touch key or i/o function select www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 43 july 19, 2011 configuration options the following table shows all kinds of options in the micro-controller. all of the options must be defined to ensure proper system functioning. no. options watchdog options 1 wdt function: enable or disable 2 clrwdt instruction(s): one or two clear wdt instruction(s) oscillator options 3 system oscillator selection -- f sys : high frequency internal rc oscillator (hirc) external rc oscillator (erc) external crystal oscillator (hxt) 4 high frequency internal rc oscillator (hirc) frequency selection -- 4mhz, 8mhz or 12mhz 5 system oscillator sst period selection -- 1024 clocks or 2 clocks 6f s internal clock source: f sys /4 or lirc or lxt lvd/lvr options 7 lvr low voltage reset function: enable or disabled 8 lvr voltage select: 2.1v, 3.15v or 4.2v lcd options 9 lcd function in power down mode: enabled or disabled 10 r type driving current: 50 aor100 a i/o pin options 11 i/o pin or res pin 12 i/o pin or lxt osc3/osc4 pin www.datasheet.co.kr datasheet pdf - http://www..net/ application circuits HT46R75D-3 rev. 1.00 44 july 19, 2011 HT46R75D-3 vdd pa7/res vss pa6/osc1 pa5/osc2 pa4/osc3 pa3/osc4 osc circuit osc circuit lcd panel com[7:0] pc[7:0]/seg[23:0] vab,vc c1,c2 vibration sensor pa0/vib pa1/bz pa2/bz pb0/tk1 pb1/tk2 pb2/tk3 pb3/tk4 touch key voreg vochp vobgp chpc1 chpc2 dscc dsrc dsrr dopap dopan dopao dchop weight or fat circuit 0.1uf 100ko 10ko 0.1uf 0.1uf 10uf 47uf 47uf 10uf 10uf 300ko th/lb vdd ai pb4/int pb5/tmr0 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 45 july 19, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 46 july 19, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 47 july 19, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/ instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT46R75D-3 rev. 1.00 48 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT46R75D-3 rev. 1.00 49 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT46R75D-3 rev. 1.00 50 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT46R75D-3 rev. 1.00 51 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). if an in- terrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT46R75D-3 rev. 1.00 52 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT46R75D-3 rev. 1.00 53 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT46R75D-3 rev. 1.00 54 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT46R75D-3 rev. 1.00 55 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT46R75D-3 rev. 1.00 56 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT46R75D-3 rev. 1.00 57 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) or the latest version of the package information. 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.016 f 0.005 0.009 g 0.053 0.057 h 0.063 i 0.002 0.006 j 0.018 0.030 k 0.004 0.008 07 HT46R75D-3 rev. 1.00 58 july 19, 2011 ; = 0 0 @ $ < : k www.datasheet.co.kr datasheet pdf - http://www..net/ symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 07 HT46R75D-3 rev. 1.00 59 july 19, 2011 www.datasheet.co.kr datasheet pdf - http://www..net/ HT46R75D-3 rev. 1.00 60 july 19, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. www.datasheet.co.kr datasheet pdf - http://www..net/ |
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