supertex inc. supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com AT9932 features constant output c urrent steps output voltage up or down very low susceptibility to input voltage transients frequency jitter externally programmable ?xed switching frequency temperature foldback with external ntc resistor internal 40v voltage regulator +/-1a mosfet gate driver short led protection open led protection input undervoltage protection enable & pwm dimming trimmed reference (3% accurate) aec-q100 compliant applications automobile ligh ting battery powered led lamps other low voltage ac/dc or dc/dc led drivers ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the AT9932 is an advanced ?xed frequency pwm controller ic designed to control an led lamp driver using a boost-buck topology that can step the input voltage up or down automatically. the ic provides fast output current transient response and very low susceptibility to input voltage transients, which allows the lamp driver to pass the rigorous electrical transient requirements of sae j1455 or iso 7637-2, making the AT9932 an ultimate solution for automobile lighting. capacitive isolation protects the led lamp from failure of the switching mosfet. the AT9932 features a unique feed-forward current control scheme, differential output current sensing, soft start, protection from short or open led load. switching frequency can be programmed with a single external resistor. the AT9932 includes a temperature fold-back of the output current using an external ntc resistor. this feature allows maximizing the light output of the led load over the entire operating temperature range. typical application circuit automotive boost-buck led lamp driver ic c in r in c vdd r inc r t c ss r ntc r 1 r 2 r s r ov r fb r 3 r drp r ref r fl t r n r p c jtr c c c o c d c 1 led(s) zd 1 d 1 r d l 1 m 1 vin ga te ffp ffn ref fl t fb drp comp t2 jtr div t1 ntc gnd pgnd ss rt uvlo av dd pvdd pwmd at 9932 l 2 c ref
2 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com electrical characteristics (speci?cations are at t a = 25 o c, v in = 12v, v pwmd = uvlo = avdd = pvdd, gate open, r t = 200k, c ref = 0.1f, c avdd = c pvdd = 1.0f, i t1 = i t2 = 100a unless otherwise noted.) sym parameter min typ max units conditions input v in input dc supply voltage range - 5.3 - 40 v --- i inen input supply current * - - 2.0 ma pwmd = gnd i indis input current, uvlo mode * - - 100 a uvlo = gnd, pwmd = gnd internal regulator v dd regulated output voltage * 4.65 5.00 5.35 v i dd = 0 - 20ma, v in = 6.0 - 40v, pwmd = gnd ?v dd,off hysteresis - - 250 - mv v dd falling v dd,on start voltage * 4.25 - 4.85 v v dd rising notes: * speci?cations apply over the full operating ambient temperature range of -40oc < t a < +125oc. guaranteed by design and characterization. ordering information device 24-lead tssop 7.80x4.40mm body 1.20mm height (max) 0.65mm pitch AT9932 AT9932ts-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value vin to gnd -0.5v to +45v pvdd, avdd to gnd voltage -0.3v to +6.0v gate to gnd voltage -0.3v to (pvdd+0.3v) all other pins to gnd voltage -0.3v to (avdd+0.3v) ffn, ffp current +2.0ma ref current +5.0ma continuous power dissipation (t a = +25c) 1000mw* junction temperature -40c to +150c storage temperature range -65c to +150c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speci?cations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. * r ja = 125 o c/w (max.) pin con?guration product marking 24-lead tssop (ts) 24-lead tssop (ts) (top view) 1 re f uvlo nc nc dr p fb comp ss pwmd fl t di v nt c vin av dd pvdd ga te pgnd gnd jtr rt ffn ffp t2 t1 24 yy = year sealed ww = week sealed l = lot number c = country of origin * a = assembler id = green packaging *may be part of ejector pi n top marking bottom marking y y w w a a a 9 9 3 2 t s l l l l l l l l ccccccccc package may or may not include the following marks: si or
3 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym description min typ max units conditions reference v ref reference output voltage * 1.210 1.250 1.290 v i ref = 0 v ref,dis reference output voltage, uvlo mode - - 0 - mv uvlo = gnd ?v ref load regulation - 0 - 2.0 mv i ref = 0 - 1.0ma gate output t r gate output rise time - - 20 35 ns c gate = 4.0nf, v in = avdd = pvdd = 5.0v t f gate output fall time - - 20 35 ns d max maximum duty cycle * 87 - 93 % --- feed-forward ramp generator t on(min) minimum gate on time * 250 - 400 ns i ffn = 500a, i ffp = 0, v comp = 3.5v t on(max) maximum gate on time * 6.0 - 13 s i ffn = 10a, i ffp = 0, v comp = 3.5v t on gate on time * 1.0 - 2.0 s i ffn = 110a, i ffp = 10a, v comp = 3.5v ?t on /t on ffn/ffp current balancing # -3.0 - 3.0 % i ffn = 100a, i ffp = 0, v comp = 3.5v transconductance operation ampli?er v fb , v drp input common-mode range # -0.3 - 3.0 v --- v os input offset voltage * -9.0 - 9.0 mv --- gm transconductance - - 0.95 - ma/v --- a v open loop voltage gain - 65 - - db comp open g b gain bandwidth product # 1.0 - - mhz c comp = 150pf i comp comp sink current # 0.2 - - ma v fb = 0.1v, comp = gnd comp source current # -0.2 - - ma v fb = -0.1v, comp = vdd i bias input bias current # - 0.5 1.0 na --- v comp output voltage range # 0.7 - v dd v --- hiccup threshold - - 700 - mv --- i leak output leakage current # - 0.5 1.0 na pwmd = gnd oscillator f osc1 output frequency * 90 105 120 khz r t = 1.0m f osc2 * 427 505 583 khz r t = 200k f osc output frequency range # 100 - 800 khz --- electrical characteristics (speci?cations are at t a = 25 o c, v in = 12v, v pwmd = uvlo = avdd = pvdd, gate open, r t = 200k, c ref = 0.1f, c avdd = c pvdd = 1.0f, i t1 = i t2 = 100a unless otherwise noted.) notes: * speci?cations apply over the full operating ambient temperature range of -40oc < t a < +125oc. guaranteed by design and characterization. # speci?cations guaranteed by design and not tested in production
4 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym description min typ max units conditions jitter f jtr jitter frequency - - 50 - hz c jtr = 0.1 f - - 500 - hz c jtr = 0.01 f f change in switching frequency - 4.5 - - khz --- temperature foldback circuit i ntc ntc current range # - - 1.0 ma --- n ntc ntc to drp current gain - - 0.13 - - i ntc = 0.5ma n t1 ntc to t1 current gain - - 3.0 - - i ntc = 0.5ma n t2 ntc to t2 current gain - - 6.0 - - i ntc = 0.5ma v t1, v t2 t1 and t2 reference voltage - - 3.5 - v --- soft start i ss,chg charging current - 10 - 25 a --- i ss,dis discharging current - 1.0 - - ma v ss = 5.0v v ss,rst reset voltage - - - 100 mv --- fault detect comparator v flt trip voltage - -20 - 20 mv --- i bias input bias current # - 0.5 1.0 na --- input under voltage lockout ?v uvlo under voltage threshold hysteresis - - 200 - mv uvlo falling v uvlo,on under voltage threshold * 1.15 1.25 1.40 v uvlo rising i bias input bias current # - 0.5 1.0 na --- pwm dimming v en , v pwm enable voltage level * 2.0 - - v --- disable voltage level * - - 0.8 v --- r pwmd pull-down resistor - 120 - 280 k --- electrical characteristics (speci?cations are at t a = 25 o c, v in = 12v, v pwmd = uvlo = avdd = pvdd, gate open, r t = 200k, c ref = 0.1f, c avdd = c pvdd = 1.0f, i t1 = i t2 = 100a unless otherwise noted.) notes: * speci?cations apply over the full operating ambient temperature range of -40oc < t a < +125oc. guaranteed by design and characterization. # speci?cations guaranteed by design and not tested in production
5 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com functional block diagram gm + - re se t i p i p i n - i p gn d dr p fb ss rt gate pwmd ff n ff p 0. 7v jt r re se t 1.25v/ 1.45 v rese t uvlo vi n avdd re f 4.25v/ 4.50 v fl t nt c di v t1 t2 i nt c i t1 4/30(i ntc - 3i t1 ) i t2 s/d: i nt c > 3i t1 + 6i t2 recovery: i ntc < 3i t1 pgnd pvdd 15 a comp 0. 7v + - s r q os c curren t mirror 1 - + jitter + - + - po r + - regulator current mirror 2 + - functional description power topology the AT9932 is optimized to drive a continuous conduction mode (ccm) boost-buck dc/dc converter topology com - monly referred to as ?uk converter. (see the circuit dia - gram on page 1.) this power converter topology offers nu - merous advantages useful for driving high-brightness light emitting diodes (hb leds). these advantages include step- up or step-down voltage conversion ratio and low input and output current ripple. the output load is decoupled from the input voltage with a capacitor, making the driver inherently failure-safe for the output load. the AT9932 features an optimal control method for use with a boost-buck led driver. this method achieves very low susceptibility to input voltage transients, which makes it in - dispensable for automotive led lighting applications. the AT9932 can maintain constant output current even under vigorous input transient conditions. its output current control loop is inherently stable and can be compensated using a single capacitor with the appropriate damping at the cou - pling capacitor. regulator (vin, avdd) and gate driver (gate, pvdd) the AT9932 can be powered directly from its vin pin that takes a voltage up to 40v. when v in voltage is applied, AT9932 seeks to maintain constant voltage at the avdd pin. when the under-voltage threshold is exceeded at avdd, the gate driver is enabled after a 100s power-on reset (por) delay. the output of the gate driver (gate) controls the gate of an external n-channel power mosfet. the maximum duty cycle of the gate signal is limited to 0.9(typ). the un - der voltage protection comparator disables it when the volt - age falls below the under voltage threshold. a separate pvdd input is provided to power the gate output to decouple the high switching currents of the gate driver from avdd. both pins (avdd, pvdd) must be wired together on the printed circuit board (pcb). avdd needs to be bypassed to gnd by a low esr capacitor (0.1f). pvdd needs to be bypassed to pgnd by a low esr capaci - tor (0.1f). the input current drawn from the external power supply (or vin pin) is a sum of the 2.0ma (max) current drawn by the all the internal circuitry and the current drawn by the gate driver (which in turn depends on the switching frequency and the gate charge of the external fet). i in = 2.0ma + q g ? f s
6 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com in the previous equation, f s is the switching frequency of the converter and q g is the gate charge of the external fet (which can be obtained from the fet datasheet). timing resistor (rt) the switching frequency f s is programmed by selecting an external sense resistor r t . the resistance value can be com - puted as: r t = 1 f s ? c t where c t = 9.5pf. jitter (jtr) clock frequency can be modulated by an externally pro - grammed saw-tooth wave shape to reduce conducted elec - tro-magnetic emission (emi) from the led driver. the devia - tion of the oscillator frequency is set internally to 5.0khz. the modulation frequency is programmed by connecting a capacitor at jtr. the value of the capacitor required for the jitter frequency is given by: c jtr = 5f f jtr (hz) note that the jitter frequency must be chosen to be signi? - cantly lower than the cross over frequency of the closed loop control. if not, the controller will not be able to reject the jitter frequency and the led current will have a current ripple at the jitter frequency. reference voltage (ref) the AT9932 provides a 1.25v reference voltage at the ref pin. this voltage is used to derive the various internal volt - ages required by the ic and is also used to set the led cur - rent externally. it should be bypassed with a low impedance capacitor (0.01 -0.1f). internal 1.0mhz transconductance ampli?er the AT9932 includes a 1.0mhz transconductance ampli?er, which can be used to close the led current feedback loop. the output state of the ampli?er is controlled by the signal applied to the pwmd pin. when pwmd is high, the output of the ampli?er is connected to the comp pin. when pwmd is low, comp is left open. this enables the integrating ca - pacitor at the comp pin to hold its charge when the pwmd signal has turned off the gate drive. when the ic is enabled, the voltage at comp will be positioned for the converter to return to its steady state condition. when the voltage at comp falls below 700mv, the gate output is disabled. this feature reduces power dissipation in the zener diode zd 1 during open circuit condition. soft start (ss) the soft start feature can determine the initial ramp-up of the error voltage at the comp pin. connecting a single ca - pacitor between ss to gnd can program the soft-start time. upon the ?rst applying voltage to the vdd pin, a current of 15a is supplied from the ss pin gradually charging the soft start capacitor. the comp voltage is tracking the voltage at the ss pin until regulation of the output current is reached. when v dd falls below the under-voltage threshold, the soft start capacitor is discharged rapidly. feed-forward ramp generator (ffp, ffn) and pwm comparator the heart of the AT9932 is the feed-forward circuit having two inputs: ffn and ffp. this circuit generates a voltage ramp proportional to the difference between the ffn and ffp currents. figure 1. feed-forward ramp generator as shown in fig. 1, the resistor r ffn is connected between ffn and the negative terminal of the coupling capacitor c1. a resistor of the same value (r ffp = r ffn ) is connected be - tween ffp and gnd. the on-time of the gate output can be computed as: t on = r ffn ? c eff ? (v comp - 0.7v) v c1 where c eff = 28pf40%, v comp is the comp voltage, and v c1 is the voltage across the coupling capacitor c 1 . the duty cycle of a continuous conduction mode boost-buck converter is given as: d = t on ? f s = v out = v out v c1 v out + v in l1 l 2 c 1 q 1 d 1 c d r d ff n ffp v re f + - v comp - 0.7v r ff p r ffn c ef f
7 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com where v in is the input supply voltage, and v out is the forward voltage of the led string. since the output voltage at comp is limited to v comp = v dd , the feed-forward resistors must be selected in accordance with: r ffn = r ffp v out c eff ? f s ? (v dd -0.7v) otherwise, the steady-state duty cycle d will not be reached, and the led driver will be unable to develop the desired current. the feed-forward loop provides instantaneous response to any transient at c 1 , and therefore achieves excellent rejec - tion of the input voltage transients along the supply line. it is inherently stable with proper selection of the damping net - work r d and c d . optimal selection of r d and c d is complex. however, the worst case design of the damping circuit can be performed under the assumption that v out(max) >> v in(min) for most automotive applications of the AT9932. the simpli - ?ed equations given below produce very good results under this assumption. c d = 9d max ? l 1 ? i o 2 (1 - d max ) v in(min) r d = v in(min) 3d max i o in the cases where the above assumption is not valid, the equations for r d and c d could still be used. however, they may produce somewhat too conservative results. power dis - sipation in the damping resistor r d can be computed as: p rd = ?v c1 2 12 ? r d where: ?v c1 = i out ? d f s ? c 1 is the peak-to-peak voltage ripple at the coupling capacitor c 1 . output over voltage protection the AT9932 led lamp driver supplies constant current to the load. therefore, an output circuit protection is needed to prevent dramatic failures when the output load fails open. a simple addition of a zener diode (zd 1 in the typical applica - tion circuit on page 1) will limit the output voltage when the output led connection is lost. programming led current and temperature foldback the AT9932 offers a temperature foldback feature that al - lows programming the output current in accordance with the temperature derating characteristics provided by the led manufacturers. a typical derating curve is shown in figure 2. figure 2. temperature derating curve of led current figure 3. output current feedback without temperature foldback when no temperature foldback is required, ntc and t1 should be connected to avdd, div and drp should be connected to gnd. t2 still requires a resistor to gnd (10~100k ). no pins should be left ?oating. the drp pin can be connected to gnd (figure 3). in this case, the output current of the AT9932 led driver is programmed using the following equation: i 1 = v ref ? r 6 r s r 5 where v ref is voltage at the ref pin (v ref = 1.25v). the same equation for calculating i 1 is used when tempera - ture fold-back is required, to calculate the current below t 1 . when an external ntc resistor is connected (figure 4), both temperatures t 1 and t 2 , as well as the current i 2 can be ac - curately programmed to maximize the light output of the led lamp. the ratio of the resistor divider r 2 /(r 1 + r 2 ) programs the voltage at the ntc pin. the voltage at t1 is approximately 3.5v. the currents sourced by ntc and t1 are mirrored into drp in accordance with the following equation: i 1 i 2 t 1 t 2 r s r 5 r 6 c re f 10k at 9932 re f fb di v t1 t2 ntc dr p avdd
8 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com i drp = i ntc C i t1 > 0 3 no current is sourced from drp when i ntc < 3 ? i t1 . temperature t 1 is programmed by selecting r 2 such that: r 2 = 3r ntc (t 1 ) where r ntc (t 1 ) is the resistance of the ntc resistor at the temperature t 1 . figure 4. output current feedback with temperature foldback further reduction of the ntc resistance r ntc will create a proportional offset of the current feedback reference at drp, and hence will cause decrease of the led current. to pro - gram the desired current i 2 at the temperature t 2 , the resistor r 4 at drp can be calculated as: where r ntc (t2) is resistance of the ntc resistor at the tem - perature t 2 , and v t1 is voltage at the t1 pin (v t1 3.5v). when the current from the ntc pin exceeds (3 ? i t1 + 6 ? i t2 ), over-temperature shutdown is triggered. the voltage at t2 is approximately equal to the voltage at t1. selecting re - sistance of r 3 at the t2 pin programs the desired shutdown temperature t 2 . r 3 = 6r ntc (t 2 ) ? (r 1 +r 2 ) r 2 - 3r ntc (t 2 ) the over-temperature recovery threshold is independent of the current in t2. the AT9932 recovers from thermal shut - down at the break temperature t 1 , where: i ntc < 3 ? i t1 input under voltage protection (uvlo) to protect the AT9932 against excessive input current at low input supply voltage, the under-voltage lockout (uvlo) pro - tection comparator input is provided. connecting a resistor divider between vin and gnd programs the uvlo thresh - olds as follows: v in(start) = (r in1 + r in2 ) ? 1.25v r in2 v in(stop) = 0.84 ? v in(start) the hysteresis is provided to prevent oscillation. the AT9932 becomes disabled and draws less than 100 a of current from vin or vdd when the uvlo pin voltage falls below the threshold. the 1.25v reference at the ref pin becomes 0v at this condition. hence, the uvlo input can be also used as a low stand-by power disable input. fault comparator (flt) figure 5. output short circuit protection the AT9932 also provides an internal protection compara - tor that can be used for protection against short and open led string conditions. when the voltage at the flt input falls below the gnd potential, the AT9932 shuts down. the soft-start capacitor at ss is discharged. switching resumes automatically after a por delay. con?guring the flt input to protect against a short led string is illustrated by figure 5. the short circuit current can be calculated as: i short = v ref ? r 6 + r 52 r s r 51 the same resistor divider can be used to protect the led driver from the open led condition, as shown in the sche - matic diagram on page 1. the addition of a zener diode zd 1 causes the flt comparator to trip when v out > v z . r s r 3 r 1 r 2 r 5 r 6 c re f r 4 r nt c AT9932 re f f b di v t 1 t 2 ntc dr p 4 30 r 5 + r 6 r 6 ? ? r 5 r 2 - 3r nt c (t 2 ) r nt c (t 2 )(r 1 + r 2 ) v t1 v re f r 4 = ? ? ? i 2 ? r s v ref r s r 51 r 52 r 6 c ref at 9932 ref flt fb
9 AT9932 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin description pin name description 1 vin this pin is the input of a 40v high voltage regulator. 2 avdd this is a power supply pin for all internal circuits. it must be bypassed with a low esr capacitor to gnd (at least 0.1f). 3 pvdd this is the power supply pin for the gate driver. it should be connected externally to avdd and bypassed with a low esr capacitor to pgnd (at least 0.1f). 4 gate this pin is the output gate driver for an external logic level n-channel power mosfet . 5 pgnd ground return for the gate drive circuitry. 6 gnd ground return for all the low power analog internal circuitry. this pin must be connected to the return path from the input. 7 jtr this pin controls the jitter of the clock programmed by a capacitor connected at this pin. 8 rt connecting an external resistor from this pin to gnd sets the frequency of the oscillator circuit. 9 ffn connecting a resistor between this pin and a negative terminal of the coupling capacitor in the boost-buck converter programs positive pwm ramp signal. the slew rate is proportional to the current sunk from this pin. when the ramp voltage exceeds the voltage at comp, the gate signal terminates. 10 ffp connecting a resistor between this pin and gnd cancels the ffn current error due to non-zero voltage at ffn. the ffn and ffp current mirrors are internally matched. 11 t2 connecting a resistor to this current output programs the over-temperature shutdown threshold tempera - ture detected by an external ntc resistor. 12 t1 connecting a resistor to this current input programs the temperature threshold beyond which the led current is reduced. 13 ntc connect an external ntc resistor to this pin for temperature foldback of the output current and over-tem - perature shutdown. 14 div this is the reference input that programs the voltage at the ntc pin. 15 flt this pin is an input of the fault comparator. this comparator is used for open and short led protection. the ic shuts down and restarts after a por delay when this comparator is triggered. 16 pwmd when this pin is pulled to gnd (or left open), the gate output is disabled. the comp pin becomes high- impedance and holds its voltage level. when this pin is logic-high, switching of ga te resumes. 17 ss connecting a capacitor from this pin to gnd programs the soft start time of the led driver . 18 comp this pin is the output of the error ampli?er. stable closed-loop control of the output led current can be achieved by connecting a compensation network between comp and gnd. this pin is pulled to gnd internally upon a start-up or detection of a fault condition. 19 fb this pin is the high impedance non-inverting input of the error ampli?er. the output current reference is programmed by connecting a resistor divider between ref and the negative terminal of the current sense resistor. 20 drp this is the output current reference input. connect this pin to gnd when no ntc derating is used. con - nect a resistor from this pin to gnd to program temperature droop of the led current. 21 nc no connection. 22 nc 23 uvlo this pin provides input under voltage protection. when voltage at this pin falls below its threshold, AT9932 halts switching, and the soft start capacitor is discharged rapidly. the voltage at the ref pin becomes 0v, and the entire ic consumes quiescent current less ofthan 100a. the switching resumes when the input voltage exceeds the start-up threshold. hysteresis is provided between the two thresholds. 24 ref this pin provides accurate reference voltage. it must be bypassed with a 0.01-0.1f capacitor to gnd.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2010 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 10 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) AT9932 doc.# dsfp-AT9932 a071610 24-lead tssop package outline (ts) 7.80x4.40mm body, 1.20mm height (max), 0.65mm pitch symbol a a1 a2 b d e e1 e l l1 l2 1 dimension (mm) min 0.85* 0.05 0.80 0.19 7.70 6.20* 4.30 0.65 bsc 0.45 1.00 ref 0.25 bsc 0 o 12 o ref nom - - 1.00 - 7.80 6.40 4.40 0.60 - max 1.20 0.15 1.15 ? 0.30 7.90 6.60* 4.50 0.75 8 o jedec registration ms-153, variation ad, issue f, may 2001. * this dimension is not speci?ed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings are not to scale. supertex doc. #: dspd-24tssopts, version b041309. d seating plane gauge plane l l1 l2 to p v iew side v iew vi ew a-a vi ew b vi ew b 1 e1 e a a2 a1 a a seating plane e b 24 1 note 1 (index area d/2 x e1/2) note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
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