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ht93lc66 4k 3-wire cmos serial eeprom block diagram 1 december 7, 2000 features operating voltage v cc C read: 2.0v~5.5v C write: 2.4v~5.5v low power consumption C operating: 5ma max. C standby: 10 a max. user selectable internal organization C 4k(ht93lc66): 512 8or256 16 3-wire serial interface write cycle time: 5ms max. automatic erase-before-write operation word/chip erase and write operation write operation with built-in timer software controlled write protection 10-year data retention after 100k rewrite cycles 10 6 rewrite cycles per word commercial temperature range (0 cto+70 c) 8-pin dip/sop package general description the ht93lc66 is a 4k-bit low voltage nonvola - tile, serial electrically erasable programmable read only memory device using the cmos float - ing gate process. its 4096 bits of memory are or - ganized into 256 words of 16 bits each when the org pin is connected to vcc or organized into 512 words of 8 bits each when it is tied to vss. the device is optimized for use in many indus - trial and commercial applications where low power and low voltage operation are essential. by popular microcontroller, the versatile serial in - terface including chip select (cs), serial clock (sk), data input (di) and data output (do) can be easily controlled.
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pin assignment pin description pin name i/o description cs i chip select input sk i serial clock input di i serial data input do o serial data output vss negative power supply, ground org i internal organization when org is connected to vdd or org is floated, the ( 16) memory organi - zation is selected. when org is tied to vss, the ( 8) memory organization is selected. there is an internal pull-up resistor on the org pin. (ht93lc66-a) nc no connection vcc positive power supply ht93lc66 2 december 7, 2000 * + $ , % $"" " " # % $ , % $"" " " # % * +
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absolute maximum ratings operation temperature (commercial)..................................................................................0 cto70 c applied v cc voltage with respect to vss......................................................................... 0.3v to 6.0v applied voltage on any pin with respect to vss ............................................................ v ss 0.3v to v cc +0.3v supply read voltage.............................................................................................................. 2v to 5.5v note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and pro - longed exposure to extreme conditions may affect device reliability. d.c. characteristics symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage read 2.0 5.5 v write 2.4 5.5 v i cc1 operating current (ttl) 5v do unload, sk=1mhz 5ma i cc2 operating current (cmos) 5v do unload, sk=1mhz 5ma 2~5.5v do unload, sk=250khz 5ma i stb standby current (cmos) 5v cs=sk=di=0v 10 a i li input leakage current 5v v in =v ss ~v cc 0 1 a i lo output leakage current 5v v out =v ss ~v cc cs=0v 0 1 a v il input low voltage 5v 0 0.8 v 2~5.5v 0 0.1v cc v v ih input high voltage 5v 2 v cc v 2~5.5v 0.9v cc v cc v v ol output low voltage 5v i ol =2.1ma 0.4 v 2~5.5v i ol =10 a 0.2 v v oh output high voltage 5v i oh = 400 a 2.4 v 2~5.5v i oh = 10 av cc 0.2 v c in input capacitance v in =0v, f=250khz 5pf c out output capacitance v out =0v, f=250khz 5pf ht93lc66 3 june 4, 1999
a.c. characteristics symbol parameter vcc=5v 10% vcc=3v 10% vcc=2v* unit min. max. min. max. min. max. f sk clock frequency 0 2000 0 500 0 250 khz t skh sk high time 250 1000 2000 ns t skl sk low time 250 1000 2000 ns t css cs setup time 50 200 200 ns t csh cs hold time 0 0 0 ns t cds cs deselect time 250 250 1000 ns t dis di setup time 100 200 400 ns t dih di hold time 100 200 400 ns t pd1 do delay to 1 250 1000 2000 ns t pd0 do delay to 0 250 1000 2000 ns t sv status valid time 250 250 ns t hv do disable time 100 400 400 ns t pr write cycle time 5 5 ms * for read operating only a.c. test conditions input rise and fall time: 5ns (1v to 2v) input and output timing reference levels: 1.5v output load: see figure right ht93lc66 4 december 7, 2000 % -- --'./ $ 012$ / &!'3 output load circuit
timing diagrams ht93lc66 5 december 7, 2000 functional description the ht93lc66 is accessed via a three-wire serial communication interface. the device is arranged into 256 words by 16 bits or 512 words by 8 bits depending whether the org pin is connected to vcc or vss. the ht93lc66 contains seven in - structions: read, erase, write, ewen, ewds, eral and wral. when the user selectable internal organization is arranged into 256 16 (512 8), these instructions are all made up of 11(12) bits data: 1 start bit, 2 op code bits and 8(9) address bits. by using the control signal cs, sk and data in- put signal di, these instructions can be given to the ht93lc66. these serial instruction data presented at the di input will be written into the device at the rising edge of sk. during the read cycle, do pin acts as the data output and during the write or erase cycle, do pin in- dicates the busy/ready status. when the do pin is active for read data or as a busy/ready indicator the cs pin must be high; otherwise do pin will be in a high-impedance state. for successful instruc - tions, cs must be low once after the instruction is sent. after power on, the device is by default in the ewds state. and, an ewen instruction must be performed before any erase or write instruction can be executed. the fol - lowing are the functional descriptions and tim - ing diagrams of all seven instructions. read the read instruction will stream out data at a specified address on the do pin. the data on do pin changes during the low-to-high edge of sk signal. the 8 bits or 16 bits data stream is preceded by a logical 0 dummy bit. irrespec - tive of the condition of the ewen or ewds in - struction, the read command is always valid and independent of these two instructions. af - ter the data word has been read the internal ad- dress will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data. the address will wrap around with cs high un- til cs returns to low. ewen/ewds the ewen/ewds instruction will enable or disable the programming capabilities. at both the power on and power off state the device auto - matically entered the disable mode. before a write, erase, wral or eral instruction is given, the programming enable instruction ewen must be issued, otherwise the erase/write instruction is invalid. after the ewen instruction is issued, the programming enable condition remains until power is turned off or a ewds instruction is given. no data can be written into the device in the programming disabled state. by so doing, the internal memory data can be protected. " " % # " "" "4 " " 4 #" #4 5 5- 467 $ $
ht93lc66 6 december 7, 2000 erase the erase instruction erases data at the spec - ified addresses in the programming enable mode. after the erase op-code and the speci - fied address have been issued, the data erase is activated by the falling edge of cs. since the in - ternal auto-timing generator provides all tim - ing signals for the internal erase, so the sk clock is not required. during the internal erase, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and further instructions can be executed. write the write instruction writes data into the de - vice at the specified addresses in the program - ming enable mode. after the write op-code and the specified address and data have been issued, the data writing is activated by the fall - ing edge of cs. since the internal auto-timing generator provides all timing signal for the in - ternal writing, so the sk clock is not required. the auto-timing write cycle includes an auto - matic erase-before-write capability. so, it is not necessary to erase data before the write in- struction. during the internal writing, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and fur- ther instructions can be executed. eral the eral instruction erases the entire 256 16 or 512 8 memory cells to logical 1 state in the programming enable mode. after the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of cs. since the internal auto-timing generator pro - vides all timing signal for the erase-all opera - tion, so the sk clock is not required. during the internal erase-all operation, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and further instruc - tion can be executed. wral the wral instruction writes data into the en - tire 256 16 or 512 8 memory cells in the pro - gramming enable mode. after the write-all instruction set has been issued, the data writ - ing is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signals for the write-all operation, so the sk clock is not required. during the internal write-all operation, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over the do pin will return to high and further instruc- tion can be executed.
timing diagrams read ewen/ewds write ht93lc66 7 december 7, 2000 " " " 8 # - - "8 09 : 9 , --09 : " " " % 4 ;67 4 ; 7 - # "8 47 " / /
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instruction set summary ht93lc66 instruction comments start bit op code address org=0 org=1 x8 x16 data org=0 org=1 x8 x16 read read data 1 10 a8~a0 a7~a0 d7~d0 d15~d0 erase erase data 1 11 a8~a0 a7~a0 write write data 1 01 a8~a0 a7~a0 d7~d0 d15~d0 ewen erase/write enable 1 00 11xxxxxxx 11xxxxxx ewds erase/write disable 1 00 00xxxxxxx 00xxxxxx eral erase all 1 00 10xxxxxxx 10xxxxxx wral write all 1 00 01xxxxxxx 01xxxxxx d7~d0 d15~d0 note: x stands for don t care ht93lc66 9 december 7, 2000
ht93lc66 10 december 7, 2000 copyright
2000 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate technology corp. 48531 warm spring boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885

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