View ADC08034-1_3042256.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters 555 august 31, 1994 853-0034 13721 description the adc0803 family is a series of three cmos 8-bit successive approximation a/d converters using a resistive ladder and capacitive array together with an auto-zero comparator . these converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry . the 3-state output data lines can be connected directly to the data bus. the dif ferential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. additionally , the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution. features ? compatible with most microprocessors ? differential inputs ? 3-state outputs ? logic levels ttl and mos compatible ? can be used with internal or external clock ? analog input range 0v to v cc ? single 5v supply ? guaranteed specification with 1mhz clock pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 15 d 1 , n packages cs rd wr intr clk in v in (+) v in () a gnd v ref /2 d gnd v cc clk r d0 d1 d2 d3 d4 d5 d6 d7 top view note: sol e released in large so package only. applications ? transducer-to-microprocessor interface ? digital thermometer ? digitally-controlled thermostat ? microprocessor-based monitoring and control systems ordering information description temperature range order code dwg # 20-pin plastic dual in-line package (dip) -40 to +85 c adc0803/04-1 lcn 0408b 20-pin plastic dual in-line package (dip) 0 to 70 c adc0803/04-1 cn 0408b 20-pin plastic small outline (so) package 0 to 70 c adc0803/04-1 cd 1021b 20-pin plastic small outline (so) package -40 to 85 c adc0803/04-1 lcd 1021b absolute maximum ratings symbol parameter rating unit v cc supply voltage 6.5 v logic control input voltages -0.3 to +16 v all other input voltages -0.3 to (v cc +0.3) v t a operating temperature range adc0803/04-1 lcd -40 to +85 c adc0803/04-1 lcn -40 to +85 c adc0803/04-1 cd 0 to +70 c adc0803/04-1 cn 0 to +70 c t stg storage temperature -65 to +150 c t sold lead soldering temperature (10 seconds) 300 c p d maximum power dissipation t a =25 c (still air) 1 n package 1690 mw d package 1390 mw notes: 1. derate above 25 c, at the following rates: n package at 13.5mw/ c; d package at 11.1mw/ c
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 556 block diagram m v in (+) v in () 7 6 + ladder and decoder + auto zero comparator v ref /2 a gnd 9 8 v cc 20 10 d gnd wr cs rd 3 1 2 sar 8bit shift register intr ff clock output latches le oe d7 (msb) (11) d6 (12) d5 (13) d4 (14) d3 (15) d2 (16) d1 (17) d0 (lsb) (18) intr clk in clk r s r q 5 4 19
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 557 dc electrical characteristics v cc = 5.0v, f clk = 1mhz, t min t a t max , unless otherwise specified. symbol parameter test conditions adc0803/4 unit symbol parameter test conditions min typ max unit adc0803 relative accuracy error (adjusted) full-scale adjusted 0.50 lsb adc0804 relative accuracy error (unadjusted) v ref /2 = 2.500v dc 1 lsb r in v ref /2 input resistance 3 v cc = 0v 2 400 680 w analog input voltage range 3 0.05 v cc +0.05 v dc common-mode error over analog input voltage range 1/16 1/8 lsb power supply sensitivity v cc = 5v 10% 1 1/16 lsb control inputs v ih logical a1o input voltage v cc = 5.25v dc 2.0 15 v dc v il logical a0o input voltage v cc = 4.75v dc 0.8 v dc i ih logical a1o input current v in = 5v dc 0.005 1 m a dc i il logical a0o input current v in = 0v dc 1 0.005 m a dc clock in and clock r v t + clock in positive-going threshold voltage 2.7 3.1 3.5 v dc v t clock in negative-going threshold voltage 1.5 1.8 2.1 v dc v h clock in hysteresis (v t +)(v t ) 0.6 1.3 2.0 v dc v ol logical a0o clock r output voltage i ol = 360 m a, v cc = 4.75v dc 0.4 v dc v oh logical a1o clock r output voltage i oh = 360 m a, v cc = 4.75v dc 2.4 v dc data output and intr v ol logical a0o output voltage data outputs i ol = 1.6ma, v cc = 4.75v dc 0.4 v dc intr outputs i ol = 1.0ma, v cc = 4.75v dc 0.4 v dc v oh logical a1o output voltage i oh = 360 m a, v cc = 4.75v dc 2.4 v dc v oh logical a1o output voltage i oh = 10 m a, v cc = 4.75v dc 4.5 v dc i ozl 3-state output leakage v out = 0v dc , cs = logical a1o 3 m a dc i ozh 3-state output leakage v out = 5v dc , cs = logical a1o 3 m a dc i sc +output short-circuit current v out = 0v, t a = 25 c 4.5 12 ma dc i sc output short-circuit current v out = v cc , t a = 25 c 9.0 30 ma dc i cc power supply current f clk = 1mhz, v ref /2 = open, cs = logical a1o, t a = 25 c 3.0 3.5 ma notes: 1. analog inputs must remain within the range: 0.05 v in v cc + 0.05v. 2. see typical performance characteristics for input resistance at v cc = 5v. 3. v ref /2 and v in must be applied after the v cc has been turned on to prevent the possibility of latching.
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 558 ac electrical characteristics symbol parameter to from test conditions adc0803/4 unit symbol parameter to from test conditions min typ max unit conversion time f clk =1mhz 1 66 73 m s f clk clock frequency 1 0.1 1.0 3.0 mhz clock duty cycle 1 40 60 % cr free-running conversion rate cs =0, f clk =1mhz intr tied to wr 13690 conv/s t w( wr )l start pulse width cs =0 30 ns t acc access time output rd cs =0, c l =100pf 75 100 ns t 1h , t 0h 3-state control output rd cl=10pf, r l =10k w see 3-state test circuit 70 100 ns t w1 , t r1 intr delay intr wd or rd 100 150 ns c in logic input=capacitance 5 7.5 pf c out 3-state output capacitance 5 7.5 pf notes: 1. accuracy is guaranteed at f clk =1mhz. accuracy may degrade at higher clock frequencies. functional description these devices operate on the successive approximation principle. analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [ v in (+)-v in (-) ] matches the voltage from the decoder . after all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. conversion begins with the arrival of a pulse at the wr input if the cs input is low. on the high-to-low transition of the signal at the wr or the cs input, the sar is initialized, the shift register is reset, and the intr output is set high. the a/d will remain in the reset state as long as the cs and wr inputs remain low . conversion will start from one to eight clock periods after one or both of these inputs makes a low-to-high transition. after the conversion is complete, the intr pin will make a high-to-low transition. this can be used to interrupt a processor , or otherwise signal the availability of a new conversion result. a read (rd ) operation (with cs low) will clear the intr line and enable the output latches. the device may be run in the free-running mode as described later . a conversion in progress can be interrupted by issuing another start command. digital control inputs the digital control inputs (cs, wr, rd ) are compatible with standard ttl logic voltage levels. the required signals at these inputs correspond to chip select, start conversion, and output enable control signals, respectively. they are active-low for easy interface to microprocessor and microcontroller control buses. for applications not using microprocessors, the cs input (pin 1) can be grounded and the a/d start function is achieved by a negative-going pulse to the wr input (pin 3). the output enable function is achieved by a logic low signal at the rd input (pin 2), which may be grounded to constantly have the latest conversion present at the output. analog operation analog input current the analog comparisons are performed by a capacitive charge summing circuit. the input capacitor is switched between v in(+) 4 and v in(-) , while reference capacitors are switched between taps on the reference voltage divider string. the net charge corresponds to the weighted dif ference between the input and the most recent total value set by the successive approximation register. the internal switching action causes displacement currents to flow at the analog inputs. the voltage on the on-chip capacitance is switched through the analog dif ferential input voltage, resulting in proportional currents entering the v in(+) input and leaving the v in(-) input. these transient currents occur at the leading edge of the internal clock pulses. they decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period. input bypass capacitors and source resistance bypass capacitors at the input will average the charges mentioned above, causing a dc and an ac current to flow through the output resistance of the analog signal sources. this charge pumping action is worse for continuous conversions with the v in(+) input at full scale. this current can be a few microamps, so bypass capacitors should not be used at the analog inputs of the v ref /2 input for high resistance sources (> 1k w ). if input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental ef fects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. this is possible because the magnitude of the input current is a precise linear function of the dif ferential voltage.
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 559 large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time. if a low pass filter is required in the system, use a low valued series resistor (< 1k w ) for a passive rc section or add an op amp active filter (low pass). for applications with source resistances at or below 1k w , a 0.1 m f bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire. a 100 w series resistor can be used to isolate this capacitor (both the resistor and capacitor should be placed out of the feedback loop) from the output of the op amp, if used. analog differential voltage inputs and common- mode rejection these a/d converters have additional flexibility due to the analog dif ferential voltage input. the v in(-) input (pin 7) can be used to subtract a fixed voltage from the input reading (tare correction). this is also useful in a 4/20ma current loop conversion. common-mode noise can also be reduced by the use of the dif ferential input. the time interval between sampling v in(+) and v in(-) is 4.5 clock periods. the maximum error due to this time dif ference is given by: v(max)=(v p ) (2f cm ) (4.5/f clk ), where: v=error voltage due to sampling delay v p =peak value of common-mode voltage f cm =common mode frequency for example, with a 60hz common-mode frequency , f cm , and a 1mhz a/d clock, f clk , keeping this error to 1/4 lsb (about 5mv) would allow a common-mode voltage, v p , which is given by: v p [v(max) (f clk ) (2f cm )(4.5) or v p (5 x 10 3 ) (10 4 ) (6.28) (60) (4.5) 2.95v the allowed range of analog input voltages usually places more severe restrictions on input common-mode voltage levels than this, however. an analog input span less than the full 5v capability of the device, together with a relatively large zero of fset, can be easily handled by use of the dif ferential input. (see reference v oltage span adjust). noise and stray pickup the leads of the analog inputs (pins 6 and 7) should be kept as short as possible to minimize input noise coupling and stray signal pick-up. both emi and undesired digital signal coupling to these inputs can cause system errors. the source resistance for these inputs should generally be below 5k w to help avoid undesired noise pickup. input bypass capacitors at the analog inputs can create errors as described previously . full scale adjustment with any input bypass capacitors in place will eliminate these errors. reference voltage for application flexibility , these a/d converters have been designed to accommodate fixed reference voltages of 5v to pin 20 or 2.5v to pin 9, or an adjusted reference voltage at pin 9. the reference can be set by forcing it at v ref /2 input, or can be determined by the supply voltage (pin 20). figure 1 indicates how this is accomplished. reference voltage span adjust note that the pin 9 (v ref /2) voltage is either 1/2 the voltage applied to the v cc supply pin, or is equal to the voltage which is externally forced at the v ref /2 pin. in addition to allowing for flexible references and full span voltages, this also allows for a ratiometric voltage reference. the internal gain of the v ref /2 input is 2, making the full-scale dif ferential input voltage twice the voltage at pin 9. for example, a dynamic voltage range of the analog input voltage that extends from 0 to 4v gives a span of 4v (4-0), so the v ref /2 voltage can be made equal to 2v (half of the 4v span) and full scale output would correspond to 4v at the input. on the other hand, if the dynamic input voltage had a range of 0.5 to 3.5v , the span or dynamic input range is 3v (3.5-0.5). t o encode this 3v span with 0.5v yielding a code of zero, the minimum expected input (0.5v, in this case) is applied to the v in (-) pin to account for the offset, and the v ref /2 pin is set to 1/2 the 3v span, or 1.5v . the a/d converter will now encode the v in (+) signal between 0.5 and 3.5v with 0.5v at the input corresponding to a code of zero and 3.5v at the input producing a full scale output code. the full 8 bits of resolution are thus applied over this reduced input voltage range. the required connections are shown in figure 2. operating mode these converters can be operated in two modes: 1) absolute mode 2) ratiometric mode in absolute mode applications, both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion. for v ref /2 voltages of 2.5v, initial errors of 10mv will cause conversion errors of 1 lsb due to the gain of 2 at the v ref /2 input. in reduced span applications, the initial value and stability of the v ref /2 input voltage become even more important as the same error is a larger percentage of the v ref /2 nominal value. see figure 3. in ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the a/d converter , and, therefore, cancels out in the final digital code. see figure 4. generally , the reference voltage will require an initial adjustment. errors due to an improper reference voltage value appear as full-scale errors in the a/d transfer function. errors and input span adjustments there are many sources of error in any data converter , some of which can be adjusted out. inherent errors, such as relative accuracy , cannot be eliminated, but such errors as full-scale and zero scale of fset errors can be eliminated quite easily . see figure 2. zero scale error zero scale error of an a/d is the dif ference of potential between the ideal 1/2 lsb value (9.8mv for v ref /2=2.500v) and that input voltage which just causes an output transition from code 0000 0000 to a code of 0000 0001. if the minimum input value is not ground potential, a zero of fset can be made. the converter can be made to output a digital code of 0000 0000 for the minimum expected input voltage by biasing the v in (-) input to that minimum value expected at the v in (-) input to that minimum value expected at the v in (+) input. this uses the
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 560 differential mode of the converter. any offset adjustment should be done prior to full scale adjustment. full scale adjustment full scale gain is adjusted by applying any desired of fset voltage to v in (-), then applying the v in (+) a voltage that is 1-1/2 lsb less than the desired analog full-scale voltage range and then adjusting the magnitude of v ref /2 input voltage (or the v cc supply if there is no v ref /2 input connection) for a digital output code which just changes from 1111 1110 to 1111 1111. the ideal v in (+) voltage for this full-scale adjustment is given by: v in ( ) v in ( ) 1.5 x v max v min 255 where: v max =high end of analog input range (ground referenced) v min =low end (zero of fset) of analog input (ground referenced) clocking option the clock signal for these a/ds can be derived from external sources, such as a system clock, or self-clocking can be accomplished by adding an external resistor and capacitor , as shown in figure 6. heavy capacitive or dc loading of the clk r pin should be avoided as this will disturb normal converter operation. loads less than 50pf are allowed. this permits driving up to seven a/d converter clk in pins of this family from a single clk r pin of one converter . for larger loading of the clock line, a cmos or low power ttl buf fer or pnp input logic should be used to minimize the loading on the clk r pin. restart during a conversion a conversion in process can be halted and a new conversion began by bringing the cs and wr inputs low and allowing at least one of them to go high again. the output data latch is not updated if the conversion in progress is not completed; the data from the previously completed conversion will remain in the output data latches until a subsequent conversion is completed. continuous conversion to provide continuous conversion of input data, the cs and rd inputs are grounded and intr output is tied to the wr input. this intr /wr connection should be momentarily forced to a logic low upon power-up to insure circuit operation. see figure 5 for one way to accomplish this. driving the data bus this cmos a/d converter, like mos microprocessors and memories, will require a bus driver when the total capacitance of the data bus gets large. other circuitry tied to the data bus will add to the total capacitive loading, even in the high impedance mode. there are alternatives in handling this problem. the capacitive loading of the data bus slows down the response time, although dc specifications are still met. for systems with a relatively low cpu clock frequency , more time is available in which to establish proper logic levels on the bus, allowing higher capacitive loads to be driven (see typical performance characteristics). at higher cpu clock frequencies, time can be extended for i/o reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035). finally , if time is critical and capacitive loading is high, external bus drivers must be used. these can be 3-state buf fers (low power schottky is recommended, such as the n74ls240 series) or special higher current drive products designed as bus drivers. high current bipolar bus drivers with pnp inputs are recommended as the pnp input of fers low loading of the a/d output, allowing better response time. power supplies noise spikes on the v cc line can cause conversion errors as the internal comparator will respond to them. a low inductance filter capacitor should be used close to the converter v cc pin and values of 1 m f or greater are recommended. a separate 5v regulator for the converter (and other 5v linear circuitry) will greatly reduce digital noise on the v cc supply and the attendant problems. wiring and layout precautions digital wire-wrap sockets and connections are not satisfactory for breadboarding this (or any) a/d converter . sockets on pc boards can be used. all logic signal wires and leads should be grouped or kept as far as possible from the analog signal leads. single wire analog input leads may pick up undesired hum and noise, requiring the use of shielded leads to the analog inputs in many applications. a single-point analog ground separate from the logic or digital ground points should be used. the power supply bypass capacitor and the self-clocking capacitor , if used, should be returned to digital ground. any v ref /2 bypass capacitor, analog input filter capacitors, and any input shielding should be returned to the analog ground point. proper grounding will minimize zero-scale errors which are present in every code. zero-scale errors can usually be traced to improper board layout and wiring. applications microprocessor interfacing this family of a/d converters was designed for easy microprocessor interfacing. these converters can be memory mapped with appropriate memory address decoding for cs (read) input. the active-low write pulse from the processor is then connected to the wr input of the a/d converter, while the processor active-low read pulse is fed to the converter rd input to read the converted data. if the clock signal is derived from the microprocessor system clock, the designer/programmer should be sure that there is no attempt to read the converter until 74 converter clock pulses after the start pulse goes high. alternatively, the intr pin may be used to interrupt the processor to cause reading of the converted data. of course, the converter can be connected and addressed as a peripheral (in i/o space), as shown in figure 7. a bus driver should be used as a buf fer to the a/d output in large microprocessor systems where the data leaves the pc board and/or must drive capacitive loads in excess of 100pf. see figure 9. interfacing the scn8048 microcomputer family is pretty simple, as shown in figure 8. since the scn8048 family has 24 i/o lines, one of these (shown here as bit 0 or port 1) can be used as the chip select signal to the converter , eliminating the need for an address
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 561 decoder. the rd and wr signals are generated by reading from and writing to a dummy address. digitizing a transducer interface output circuit description figure 10 shows an example of digitizing transducer interface output voltage. in this case, the transducer interface is the ne5521, an lvdt (linear variable differential transformer) signal conditioner. the diode at the a/d input is used to insure that the input to the a/d does not go excessively beyond the supply voltage of the a/d. see the ne5521 data sheet for a complete description of the operation of that part. circuit adjustment t o adjust the full scale and zero scale of the a/d, determine the range of voltages that the transducer interface output will take on. set the l vdt core for null and set the zero scale scale adjust potentiometer for a digital output from the a/d of 1000 000. set the l vdt core for maximum voltage from the interface and set the full scale adjust potentiometer so the a/d output is just barely 1 111 1111. a digital thermostat circuit description the schematic of a digital thermostat is shown in figure 1 1. the a/d digitizes the output of the lm35, a temperature transducer ic with an output of 10mv per c. with v ref /2 set for 2.56v, this 10mv corresponds to 1/2 lsb and the circuit resolution is 2 c. reducing v ref /2 to 1.28 yields a resolution of 1 c. of course, the lower v ref /2 is, the more sensitive the a/d will be to noise. the desired temperature is set by holding either of the set buttons closed. the scc80c451 programming could cause the desired (set) temperature to be displayed while either button is depressed and for a short time after it is released. at other times the ambient temperature could be displayed. the set temperature is stored in an scn8051 internal register . the a/d conversion is started by writing anything at all to the a/d with port pin p10 set high. the desired temperature is compared with the digitized actual temperature, and the heater is turned on or of f by clearing setting port pin p12. if desired, another port pin could be used to turn on or off an air conditioner. the display drivers are ne587s if common anode led displays are used. of course, it is possible to interface to lcd displays as well.
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 562 typical performance characteristics f clk = 1mhz cs = h 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 50 25 0 25 50 75 100 125 ambient temperature (c o ) power suppl y current (ma) 10.0 8.0 6.0 4.0 2.0 1.0 0.8 0.6 0.4 0.2 0.1 10 20 40 60 80100 200 400 600 1000 clock cap (pf) clock frq (mhz) max. typ. min. v cc = 5.0v t a = 25 o c 5 4 3 2 1 0 1 2 3 4 5 0 1 2 3 4 5 f (ma) ref/2 applied v ref/2 (v) 1.70 1.60 1.50 1.40 1.30 4.50 4.75 5.00 5.25 5.50 55 o c +25 o c +125 o c logic input (v) v cc supply voltage (v) 55 o c < t a 125 o c v t+ v t 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 4.50 4.75 5.00 5.25 5.50 clkin threshold vol tage (v) v cc supply voltage (v) 18 16 14 12 10 8 6 50 25 0 25 50 75 100 125 ambient temperature ( o c) output current (ma) v cc = 5.0v v o = 2.5v v o = 0.4v v cc = 5.0v v ref/2 = 2.5v 4 3 2 1 0 0 20 40 60 80 100 120 conversion time ( m s) error (lsb) v cc = 5.0v t a = 25 o c 350 300 250 200 150 100 50 0 0 200 400 600 800 1000 load capacitance (pf) dealy (ns) power supply current vs temperature clock frequency vs clock capacitor input current vs applied voltage at v ref/2 pin logic input threshold voltage vs supply voltage clkin threshold voltage vs supply voltage output current vs temperature full scale error vs conversion time delay from rd falling edge to data valid vs load capacitance 5.5v 5.0v 4.5v
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 563 3-state test circuits and waveforms (adc0801-1) t r 90% 50% 10% t 0h 10% v cc gnd v oh gnd rd data output c l v cc data output 10k c l cs rd t r 90% 50% 10% t 1h 90% v cc gnd v oh gnd rd data output v cc 10k cs rd data output v cc 20ns 10pf t oh t 1h 10pf timing diagrams (all timing is measured from the 50% voltage points) start conversion cs wr t wi t w(wr )l actual internal status of the converter (last data was read) (last data was not read) intr intr cs rd data outputs intr reset t ri t acc t 1h, t 0h threestate 1 to 8 x 1/f clk onot busyo obusyo internal t c data is valid in output latches int asserted 1/2 t clk note note: read strobe must occur 8 clock periods (8/f clk ) after assertion of interrupt to guarantee reset of intr . output enable and reset intr
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 564 note: the v ref /2 voltage is either 1/2 the v cc voltage or is that which is forced at pin 9. figure 1. internal reference design v ref /2 v cc 20 v ref r r digital circuits analog circuits 8 10 9 figure 2. offsetting the zero scale and adjusting the input range (span) (5v) v ref fs offset adjust zs offset adjust 330 0.1 m f to v ref /2 to v in () + voltage reference v ref /2 a. fixed reference b. fixed reference derived from v cc c. optional full scale adjustment v in (+) v in () v cc +5v + v ref /2 10 m f a/d a/d v in (+) v in () v cc v ref /2 + 10 m f +5v 2k 2k +5v 2k 2k 100 figure 3. absolute mode of operation a/d v in (+) v in () v cc v ref /2 + 10 m f 2k 2k 100 full scale optional transducer v cc figure 4. ratiometric mode of operation with optional full scale adjustment
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 565 clk in a gnd v ref /2 v in () a/d +5v 10k 2.7k 10k 47 m f to 100 m f 56pf 10k cs 1 2 3 4 5 6 7 8 9 10 rd intr wr v in (+) d gnd 20 clk r 18 17 16 15 14 13 12 11 v cc d0 db0 d1 d2 d3 d4 d5 d6 d7 db1 db2 db3 db4 db5 db6 db7 +5v 19 figure 5. connection for continuous conversion r clk in 4 c clk a/d f clk = 1/1.7 r c r = 10k clk r 19 figure 6. self-clocking the converter d gnd v ref /2 clk in a gnd v in () a/d 10k cs 1 2 3 4 5 6 7 8 9 10 rd intr wr v in (+) 20 clk r 18 17 16 15 14 13 12 11 v cc d0 db0 d1 d2 d3 d4 d5 d6 d7 db1 db2 db3 db4 db5 db6 db7 +5v 19 address decode logic int i/o wr i/o rd analog inputs 56pf figure 7. interfacing to 8080a microprocessor 20 v cc d gnd v ref /2 a gnd a/d cs 1 2 3 4 5 6 7 8 17 rd into wr v in (+) v cc d0 d1 d2 d3 d4 d5 d6 d7 +5v 40 16 12 39 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 scn8051 or scn80c51 18 17 16 15 14 13 12 11 2 3 5 1 rd intr wr 19 clk r 10k 4 clk in 6 7 analog inputs 12 11 figure 8. scn8051 interfacing 56pf 18 17 16 15 14 13 12 11 d0 d1 d2 d3 d4 d5 d6 d7 a/d oe data bus 8bit buffer n74ls241 n74ls244 n74ls541 figure 9. buffering the a/d output to drive high capacitance loads and for driving off-board loads
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 566 a/d 4.7k 1.5k 1 m f 4.7k 0.47 m f 22k 470 c t 18k +5v ne5521 lvdt in4148 v in () 3.3k 2k v cc v in (+) 2k +5v 100 2k full scale adjust 820 v ref /2 figure 10. digitizing a transducer interface output
philips semiconductors linear products product specification adc0803/4-1 cmos 8-bit a/d converters august 31, 1994 567 scc80c51 a/d cs 18 17 16 15 14 13 12 11 8 rd int wr d0 d1 d2 d3 d4 d5 d6 d7 10 6 27 db0 db1 db2 db3 db4 db5 db6 db7 p10 18 17 16 15 14 13 12 11 2 3 5 1 rd intr wr lower p15 raise p16 13 14 1/4 hef4071 20 gnd 29 p12 +v 2n3906 1n4148 to heater 1/4 hef4071 6 2 1 7 3 6 2 1 7 3 rbi 5 ne587 ne587 rbo 4 rbi 5 7 8 10k 7 8 10k 20 19 +5v v cc clk r 10k clk in 56pf 4 + 10 m f v in () v in (+) 7 d gnd 10 8 a gnd lm35 6 figure 11. digital thermostat

▲Up To Search▲

Price & Availability of ADC08034-1

	To Download ADC08034-1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .