View STGIPS20K60_3005549.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. august 2009 doc id 16098 rev 1 1/19 19 STGIPS20K60 igbt intelligent power module (ipm) 17 a - 600 v - sdip-25l molded features 17 a, 600 v 3-phase igbt inverter bridge including control ics for gate driving and free- wheeling diodes 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull down / pull up resistors internal bootstrap diode dead time and interlocking function v ce(sat) negative temperature coefficient short-circuit rugged igbts undervoltage lockout smart shutdown function comparator for fault protection against over temperature and overcurrent dbc fully isolated package isolation rating of 2500 vrms/min applications 3-phase inverters for motor drives home appliances, such as washing machines, refrigerators, air conditioners description the new intelligent power module developed by stmicroelectronics provides a compact, high performance ac motor drive for a simple and rugged design. it mainly targets low power inverters for applications such as home appliances and air conditioners. it combines st proprietary control ics with the most advanced short-circuit rugged igbt system technology. please refer to dedicated technical note tn0107 for mounting instructions. sdip-25l molded table 1. device summary order code marking package packaging STGIPS20K60 gips20k60 sdip-25l molded tube www.st.com
contents STGIPS20K60 2/19 doc id 16098 rev 1 contents 1 internal block diagram and pi n configuration . . . . . . . . . . . . . . . . . . . . 3 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STGIPS20K60 internal block diagram and pin configuration doc id 16098 rev 1 3/19 1 internal block diagram and pin configuration figure 1. internal block diagram am05002v1 w nw p vboot u vboot w out v vboot v out u out w lin s d/ od vcc gnd dt out hvg v b oot hin lvg cp+ lin s d/ od vcc gnd dt out hvg v b oot hin lvg cp+ pin 16 pin 1 p p pin 17 pin 25 gnd lin-u hin-v lin-v hin-w hin-u lin-w cin vcc nu nv u v lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ s d/od
internal block diagram and pin configuration STGIPS20K60 4/19 doc id 16098 rev 1 table 2. pin description pin n symbol description 1out u high-side reference output for u phase 2v bootu bootstrap voltage for u phase 3lin u low-side logic input for u phase 4hin u high-side logic input for u phase 5v cc low voltage power supply 6out v high-side reference output for v phase 7v boot v bootstrap voltage for v phase 8 gnd ground 9lin v low-side logic input for v phase 10 hin v high-side logic input for v phase 11 out w high-side reference output for w phase 12 v boot w bootstrap voltage for w phase 13 lin w low-side logic input for w phase 14 hin w high-side logic input for w phase 15 sd / od shutdown logic input (active lo w) / open-drain (comparator output) 16 cin comparator input 17 n w negative dc input for w phase 18 w w phase output 19 p positive dc input 20 n v negative dc input for v phase 21 v v phase output 22 p positive dc input 23 n u negative dc input for u phase 24 u u phase output 25 p positive dc input
STGIPS20K60 internal block diagram and pin configuration doc id 16098 rev 1 5/19 figure 2. pin layout (bottom view)
absolute maximum ratings STGIPS20K60 6/19 doc id 16098 rev 1 2 absolute maximum ratings table 3. inverter part symbol parameter value unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and gnd for i = u, v, w 600 v i c (2) 2. calculated according to the iterative formula: each igbt continuous collector current at t c = 25c 17 a i cp (3) 3. pulse width limited by max junction temperature each igbt pulsed collector current 40 a p tot each igbt total dissipation at t c = 25c 42 w t scw short circuit withstand time, v ce = 0.5 v (br)ces t j = 125 c, v cc = v boot = 15 v, v in (1) = 0 5 v 5s table 4. control part symbol parameter value unit v out output voltage applied between out u, out v, out w - gnd v boot - 21 to v boot + 0.3 v v cc low voltage power supply -0.3 to +21 v v cin comparator input voltage -0.3 to v cc +0.3 v v boot bootstrap voltage applied between v boot i - out i for i = u, v, w -0.3 to 620 v v i logic input voltage -0.3 to 15 v v od open-drain voltage -0.3 to 15 v dv out /dt allowed output slew rate 50 v/ns table 5. total system symbol parameter value unit v out output voltage applied between u, v, w - gnd 450 v v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 2500 v t j operating junction temperature -40 to 125 c i c t c () t jmax () t c ? r thj c ? v ce sat () max () t jmax () i c t c () , () ---------------------------------------------------------------------------------------------------------- =
STGIPS20K60 absolute maximum ratings doc id 16098 rev 1 7/19 table 6. thermal data symbol parameter value unit r thjc thermal resistance junction-case single igbt 2.4 c/w thermal resistance junction-case single diode 5 c/w
electrical characteristics STGIPS20K60 8/19 doc id 16098 rev 1 3 electrical characteristics (t j = 25 c unless otherwise specified) note: t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. table 7. inverter part symbol parameter test conditions value unit min. typ. max. v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 12 a - 2.2 2.75 v v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 12 a, t j = 125 c -1.8 i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 600 v, v cc = v boot = 15 v - 100 a v f diode forward voltage v in (1) = 0 ?logic state?, i c = 12 a - 1.9 v high-side inductive load t on turn-on time v pn = 300 v, v cc = v boot = 15 v, v in (1) = 0 ? 5 v, i c = 12 a (see figure 3 ) -tbd - ns t c(on) crossover time (on) - tbd - t off turn-off time - tbd - t c(off) crossover time (off) - tbd - t rr reverse recovery time - tbd - e on turn-on switching losses - tbd - j e off turn-off switching losses - tbd - low-side in ductive load t on turn-on time v pn = 300 v, v cc = v boot = 15 v, v in (1) = 0 ? 5 v, i c = 12 a (see figure 3 ) -tbd - ns t c(on) crossover time (on) - tbd - t off turn-off time - tbd - t c(off) crossover time (off) - tbd - t rr reverse recovery time - tbd - e on turn-on switching losses - tbd - j e off turn-off switching losses - tbd - 1. applied between hin i , lin i and gnd for i = u, v, w
STGIPS20K60 electrical characteristics doc id 16098 rev 1 9/19 3.1 control part table 8. low voltage power supply symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 v v cc_thon v cc uv turn on threshold 11.5 12.0 v v cc_thoff v cc uv turn off threshold 10 10.5 v i qccu undervoltage quiescent supply current v cc = 10 v sd = 5 v; lin = 5 v; and hin = gnd; cp+ = gnd 350 450 a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; and hin = gnd; cp+ = gnd 23.5ma v ref internal reference voltage 0.5 0.54 0.58 mv table 9. bootstrapped voltage symbol parameter test cond itions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 v v bs_thon v bs uv turn on threshold 10.6 11.5 v v bs_thoff v bs uv turn off threshold 9.0 10.0 v i qbsu undervoltage v bs quiescent current v bs = 10 v sd = 5 v; lin and hin = 5 v; cp+ = gnd 70 110 a i qbs v bs quiescent current v bs = 15 v sd = 5 v; lin and hin = 5 v; cp+ = gnd 150 210 a r ds(on) (1) bootstrap driver on resistance lvg on 120 ? 1. r ds(on) is tested in the following way:
electrical characteristics STGIPS20K60 10/19 doc id 16098 rev 1 note: x: don?t care table 10. logic inputs symbol parameter test cond itions min. typ. max. unit v il low logic level voltage 0.8 v v ih high logic level voltage 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl lin logic ?0? input bias current lin = 0 v 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a i sdh sd logic ?1? input bias current sd = 15 v 120 300 a i sdl sd logic ?0? input bias current sd = 0 v 3 a dt dead time see figure 4 600 ns table 11. sense comparator characteristics (v cc = 15 v) symbol parameter test cond itions min. typ. max. unit i io input bias current v cp+ = 1 v - 3 a v ol open-drain low-level output voltage i od = - 3 ma - 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k ? resistor - 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k ? - 60 v/sec table 12. truth table input output sd lin hin lvg hvg l x x l l h h l l l h l h l l h l l h l h h h l h
STGIPS20K60 electrical characteristics doc id 16098 rev 1 11/19 3.2 waveforms definitions figure 3. switching time definition
electrical characteristics STGIPS20K60 12/19 doc id 16098 rev 1 figure 4. dead time and inte rlocking waveforms definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
STGIPS20K60 applications information doc id 16098 rev 1 13/19 4 applications information figure 5. typical application circuit am05001v1 cvcc w nw lin s d/od vcc gnd dt out hvg v b oot hin lvg cp+ vboot v p out u vboot u out v vboot w out w rg lin s d/od vcc gnd dt out hvg v b oot hin lvg cp+ lin s d/od vcc gnd dt out hvg v b oot hin lvg cp+ rg rdt rg cdt rg rg rg controller cvcc rdt cdt cvcc r c r s d vdc m c s d + 3 . 3 v/5v line c bu c b v c b w vcc r s h u nt gnd hin-u lin-u s d/od hin-w lin-v hin-v lin-w cin vcc n u nv t1 t2 t 3 t4 t5 rdt t6 v u cdt d1 d2 d 3 d4 d5 d6
applications information STGIPS20K60 14/19 doc id 16098 rev 1 4.1 recommendations to prevent the input signals oscillation, the wiring of each input should be as short as possible. by integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto-coupler is possible. each capacitor should be located as nearby the pins of ipm as possible. low inductance shunt resistors should be used for phase leg current sensing. electrolytic bus capacitors should be mounte d as close to the module bus terminals as possible. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. the sd signal should be pulled up to 5 v / 3.3 v with an external resistor (see section 5: smart shutdown function for detailed info).
STGIPS20K60 smart shutdown function doc id 16098 rev 1 15/19 5 smart shutdown function the stgips14k60 integrates a comparator for fault sensing purposes. the comparator non-inverting input (cin) can be connected to an external shunt resistor in order to implement a simple over-current protection function. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low- level leading the half- bridge in tri-state. in the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a rc network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. the time delay between the fault and the outputs turn-off is no more dependent on the rc values of the external network connected to the shutdown pin. at the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external rc network. figure 6. smart shutdown timing waveforms hin/lin hvg/lvg sd/od open drain gate (internal) upper threshold lower threshold comp vref cp+ protection fast shut down: the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold real disable time 2 1 1 2 = (r on_od // r sd ) c sd = r sd c sd sd/od from/to controller v bias smart sd logic c sd r sd r on_od shut down circuit time constants
package mechanical data STGIPS20K60 16/19 doc id 16098 rev 1 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. please refer to dedicated technical note tn0107 for mounting instructions. table 13. sdip-25l molded package mechanical data dim. (mm.) min. typ. max. a44 -44.8 a1 0.95 - 1.75 a2 1.2 - 2 a3 39 - 39.8 b 21.6 - 22.4 b1 11.45 - 12.25 b2 24.83 - 25.63 c5 -5.8 c1 6.4 - 7.4 c2 11.1 - 12.1 e 1.95 - 2.75 e1 3.2 - 4 e2 4.3 - 5.1 e3 6.1 - 6.9 f0.8 - 1.2 f1 0.3 - 0.7 r3 - 4 t0.4 - 0.7
STGIPS20K60 package mechanical data doc id 16098 rev 1 17/19 figure 7. sdip-25l molded package mechanical data 8154676revc
revision history STGIPS20K60 18/19 doc id 16098 rev 1 7 revision history table 14. document revision history date revision changes 10-aug-2009 1 initial release
STGIPS20K60 doc id 16098 rev 1 19/19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STGIPS20K60

	To Download STGIPS20K60 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .