? semiconductor components industries, llc, 2003 october, 2003 ? rev. 0 1 publication order number: nths4101p/d nths4101p 20 v, p-channel power mosfet chipfet single package features ? offers an ultra low r ds(on) solution in the chipfet package ? miniature chipfet package 40% smaller footprint than tsop?6 making it an ideal device for applications where board space is at a premium ? low profile (<1.1 mm) allows it to fit easily into extremely thin environments such as portable electronics ? designed to provide low r ds(on) at gate voltage as low as 1.8 v, the operating voltage used in many logic ics in portable electronics ? simplifies circuit design since additional boost circuits for gate voltages are not required ? operated at standard logic level gate drive, facilitating future migration to lower levels using the same basic topology applications ? optimized for battery and load management applications in portable equipment such as mp3 players, cell phones, digital cameras, personal digital assistant and other portable applications ? charge control in battery chargers ? buck and boost converters maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss ?20 v dc gate?to?source voltage ? continuous v gs 8.0 v dc drain current ? continuous ? 5 seconds i d i d ?4.8 ?6.7 a total power dissipation continuous @ t a = 25 c (5 sec) @ t a = 25 c continuous @ 85 c (5 sec) @ 85 c p d 1.3 2.5 0.7 1.3 w continuous source current is ?4.8 a thermal resistance (note 1) junction?to?ambient, 5 sec junction?to?ambient, continuous r ja r ja 50 95 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to a 1 x 1 fr4 board. g s d p?channel mosfet s d g d d d d d 1 2 3 4 5 6 7 8 device package shipping 2 ordering information nths4101pt1 chipfet 3000 tape / reel pin connections chipfet case 1206a style 1 marking diagram c6 c6 = specific device code 1 2 3 4 8 7 6 5 http://onsemi.com ?20 v 30 m @ ?2.5 v 21 m @ ?4.5 v r ds(on) typ ?4.8 a i d max v (br)dss 42 m @ ?1.8 v nths4101pt1g chipfet (pb?free) 3000 tape / reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
nths4101p http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit off characteristics drain?to?source breakdown voltage (note 2) temperature coefficient (positive) v (br)dss v gs = 0 v dc , i d = ?250 a dc ?20 ? ? v dc gate?body leakage current zero i gss v ds = 0 v dc , v gs = 8.0 v dc ? ? 100 na dc zero gate voltage drain current i dss v ds = ?16 v dc , v gs = 0 v dc v ds = ?16 v dc , v gs = 0 v dc , t j = 85 c ? ? ? ? ?1.0 ?5.0 a dc on characteristics (note 2) gate threshold voltage v gs(th) v ds = v gs , i d = ?250 a dc ?0.45 ? ?1.5 v dc static drain?to?source on?resistance r ds(on) v gs = ?4.5 v dc , i d = ?4.8 a dc v gs = ?2.5 v dc , i d = ?4.2 a dc v gs = ?1.8 v dc , i d = ?1.0 a dc ? ? ? 21 30 42 34 40 52 m forward transconductance g fs v ds = ?5.0 v dc , i d = ?4.8 a dc ? 15 ? s diode forward voltage v sd i s = ?4.8 a dc , v gs = 0 v dc ? ?0.8 ?1.2 v dynamic characteristics input capacitance c iss v ds = ?16 v dc v v ? 2100 ? pf output capacitance c oss v gs = 0 v f=10mhz ? 290 ? transfer capacitance c rss f = 1 . 0 mh z ? 200 ? switching characteristics (note 3) turn?on delay time t d(on) v dd = ?16 v dc ? 8.0 ? ns rise time t r v gs = ?4.5 v dc ? 28 ? turn?off delay time t d(off) i d = ?4.5 a dc ? 75 ? fall time t f r g = 2.5 ? 60 ? gate charge q g v gs = ?4.5 v dc ? 25 35 nc q gs i d = ?4.5 a dc ? 4.0 ? q gd v ds = ?16 v dc (note 3) ? 7.0 ? 2. pulse test: pulse width = 250 s, duty cycle = 2%. 3. switching characteristics are independent of operating junction temperatures.
nths4101p http://onsemi.com 3 typical performance curves (t j = 25 c unless otherwise noted) 125 c 0 10 5 8 6 3 2 ?v ds , drain?to?source voltage (volts) ?i d, drain current (amps) 6 2 0 1 figure 1. on?region characteristics 0 10 1.5 12 6 4 2 0.5 0 2.5 figure 2. transfer characteristics ?v gs , gate?to?source voltage (volts) 0.02 810 0.04 0 figure 3. on?resistance vs. drain current and gate voltage ?i d, drain current (amps) r ds(on), drain?to?source resistance ( ) ?i d, drain current (amps) figure 4. on?resistance variation with temperature t j , junction temperature ( c) figure 5. drain?to?source leakage current vs. voltage t j = 25 c 0.1 24 t j = ?55 c t j = 25 c v gs = ?4.5 v 4 25 c ?1.2 v 16 ?1.4 v ?1.6 v ?1.8 v 78 0.06 v gs = ?10 v to ?2.4 v 08 10 ?v ds, drain?to?source voltage (volts) 10000 0.1 ?i dss , leakage (na) v gs = ?4.5 v 1000 1 100 v gs = ?2.5 v 46 4 8 0.08 6 t j = 100 c t j = 125 c 2 9 7 5 1 3 3 9 5 3 1 7 14 12 v gs = ?1.8 v ?50 0 ?25 25 1.3 1.1 0.9 0.7 0.5 50 125 100 75 150 r ds(on), drain?to?source resistance (normalized) 1.5 v gs = 0 v
nths4101p http://onsemi.com 4 typical performance curves (t j = 25 c unless otherwise noted) v ds = 0 v v gs = 0 v 0 10 4 3000 2000 1000 0 8 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) 09 6 4 1 0 q g , total gate charge (nc) ?v gs, gate?to?source voltage (volts) t j = 25 c c oss c iss c rss i d = ?4.5 a t j = 25 c 5000 18 15 2 3 q2 q1 10 1 10 1 100 r g , gate resistance (ohms) t, time (ns) v dd = ?16 v i d = ?4.5 a v gs = ?4.5 v 1000 ?6 ?2 4000 5 t d(off) t d(on) t f t r ?v gs ?v ds 6 12 327 0.9 0 ?v sd , source?to?drain voltage (volts) ?i s , source current (amps) v gs = 0 v t j = 25 c 1.0 0.5 0.4 1 5 figure 6. capacitance variation figure 7. gate?to?source and drain?to?source voltage vs. total gate charge figure 8. resistive switching time variation vs. gate resistance figure 9. diode forward voltage vs. current figure 10. maximum rated forward biased safe operating area 0.1 1 100 ?v ds , drain?to?source voltage (volts) 0.01 100 ?i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs = 8 v single pulse t c = 25 c 1 ms 100 s dc 10 s 2 ?4 3500 2500 1500 500 4500 24 21 qt 100 0.6 0.8 0.7 0.1 1 12 14 16 18 20 2 3 4
nths4101p http://onsemi.com 5 package dimensions chipfet case 1206a?03 issue e b s c d g l a 1234 8765 m j k 1 2 3 4 8 7 6 5 dim min max min max inches millimeters a 2.95 3.10 0.116 0.122 b 1.55 1.70 0.061 0.067 c 1.00 1.10 0.039 0.043 d 0.25 0.35 0.010 0.014 g 0.65 bsc 0.025 bsc j 0.10 0.20 0.004 0.008 k 0.28 0.42 0.011 0.017 l 0.55 bsc 0.022 bsc m 5 nom s 1.80 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 7. 1206a-01 and 1206a-02 obsolete. new standard is 1206a-03. 0.05 (0.002) 5 nom 2.00 0.072 0.080 style 1: pin 1. drain 2. drain 3. drain 4. gate 5. source 6. drain 7. drain 8. drain figure 11. basic figure 12. style 1 0.457 0.018 2.032 0.08 0.635 0.025 0.66 0.026 0.711 0.028 0.178 0.007 2.032 0.08 1.727 0.068 0.66 0.026 0.711 0.028 mm inches scale 20:1 0.457 0.018 solder footprint* *for information on soldering specifications, please refer to our soldering reference manual, solderrm/d.
nths4101p http://onsemi.com 6 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 nths4101p/d chipfet is a trademark of vishay siliconix literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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