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em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 1 1 . general description em78p447s is an 8 - bit microprocessor with low - power and high - speed cmos technology. it is equipped with 4k*13 - bits electrical one time programmable read only memory (otp - rom). it provides a protection bit to prevent user?s code in th e otp memory from being intruded. seven option bits are also available to meet user?s requirements. with its otp - rom feature, the em78p447s is able to offer a convenient way of developing and verifying user?s programs. moreover, user can take advantage of emc writer to easily program his development code.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 2 2 . feature s ? operating voltage range: 2.3v~5.5v. ? operating temperature range: 0 c~70 c. ? operating frequency rang( base on 2 clocks) * crystal mode: dc~20mhz at 5v, dc~8mhz at 3v, dc~4mhz at 2.3v. * rc mode: dc~4mhz at 5v, dc~4mhz at 3v, dc~4mhz at 2,3v. ? low power consumption: * less then 2.2 ma at 5v/4mhz * typically 30 m a, at 3v/32khz * typically 1 m a, during sleep mode ? 4k 13 bits on chip rom ? one security register to prevent intrusion of ot p memory codes ? one configuration register to accommodate user?s requirements ? 148 8 bits on chip registers(sram, general purpose register) ? 3 bi - directional i/o ports ? 5 level stacks for subroutine nesting ? 8 - bit real time clock/counter (tcc) with selective signal sources, trigger edges, and overflow interrupt ? two clocks per instruction cycle ? power down (sleep) mode ? two available interruptions * tcc overflow interrupt * external interrupt ? programmable free running watchdog timer ? 10 program mable pull - high pins ? 2 programmable open - drain pins ? 2 programmable r - option pins ? package types: * 28 pin dip 600mil : em78p447sap * 28 pin sop(soic) 300mil : em78p447sam * 28 pin ssop 209mil : em78p447sas * 32 pin dip 300mil : em78p447sbp
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 3 * 32 p in sop(soic) 450mil : em78p447sbwm ? 99.9% single instruction cycle commands ? the transient point of system frequency between hxt and lxt is around 400khz
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 4 3. p in assignment 1 2 3 4 5 6 7 8 tcc nc vss /int p50 p51 9 10 11 12 13 14 /r eset osci osco p77 p76 p75 p52 p53 p60 p61 p62 vdd p63 p64 p74 p73 p72 p71 p70 p67 p66 p65 dip sop soic 18 17 16 15 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 vss vdd /int vss p50 p51 9 10 11 12 13 14 /reset osci osco p77 p76 p75 p52 p53 p60 p61 p62 tcc p63 p64 p74 p73 p72 p71 p70 p67 p66 p65 ssop 18 17 16 15 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 tcc nc vss /int p50 p 51 9 10 11 12 13 14 /reset osci osco p77 p76 p75 p52 p53 p60 p61 p62 vdd p63 p64 p74 p73 p72 p71 p70 p67 p66 p65 dip sop soic 22 21 20 19 32 31 30 29 28 27 26 25 24 23 15 16 p55 p54 p56 p57 18 17 em78p447sap em78p447sam em78p447sbp em78p447sbwm em78p447sas fig. 1 pin assignment table 1 em78p447sap and em78p447sam pin description symbol pin no. type function vdd 2 - * power supply. osci 27 i * xtal type: crystal input terminal or external clock input pin. * rc type: rc oscillator input pin. osco 26 i/o * xtal t ype: output terminal for crystal oscillator or external clock input pin. * rc type: instruction clock output. * external clock signal input. tcc 1 i * the real time clock/counter (with schmitt trigger input pin) must be tied to vdd or vss if not in use. /reset 28 i * input pin with schmitt trigger. if this pin remains at logic low, the controller will also remain in reset condition. p50~p53 6~9 i/o * p50~p53 are bi - directional i/o pins. p60~p67 10~17 i/o * p60~p67 are bi - directional i/o pins. these can be pulled - high internally by software control. p70~p77 18~25 i/o * p70~p77 are bi - directional i/o pins. * p74~p75 can be pulled - high internally by software control. * p76~p77 can have open - drain output by software control. * p70 and p71 can also be define d as the r - option pins. /int 5 i * external interrupt pin triggered by falling edge.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 5 vss 4 - * ground. nc 3 - * no connection. table 2 em78p447sas pin description symbol pin no. type function vdd 3 - * power supply. osci 27 i * xtal type: crystal input terminal or external clock input pin. * rc type: rc oscillator input pin. osco 26 i/o * xtal type: output terminal for crystal oscillator or external clock input pin. * rc type: instruction clock output. * external clock signal input. tcc 2 i * the real time clock/counter (with schmitt trigger input pin) must be tied to vdd or vss if not in use. /reset 28 i * input pin with schmitt trigger. if this pin remains at logic low, the controller will also remain in reset condition. p50~p53 5~8 i/o * p50~p53 are bi - directional i/o pins. p60~p67 9~13, 15~17 i/o * p60~p67 are bi - directional i/o pins. these can be pulled - high internally by software control. p70~p77 18~25 i/o * p70~p77 are bi - directional i/o pins. * p74~p75 can be pull ed - high internally by software control. * p76~p77 can have open - drain output by software control. * p70 and p71 can also be defined as the r - option pins. /int 4 i * external interrupt pin triggered by falling edge. vss 1,14 - * ground. table 3 em78p447sbp and em78p447sbwm pin description symbol pin no. type function vdd 4 - * power supply. osci 29 i * xtal type: crystal input terminal or external clock input pin. * rc type: rc oscillator input pin. osco 28 i/o * xtal type: ou tput terminal for crystal oscillator or external clock input pin. * rc type: instruction clock output. * external clock signal input. tcc 3 i * the real time clock/counter (with schmitt trigger input pin), must be tied to vdd or vss if not in use. /reset 30 i * input pin with schmitt trigger. if this pin remains at logic low, the controller will keep in reset condition. p50~p57 8~11,2~1, 32~31 i/o * p50~p57 are bi - directional i/o pins. p60~p67 12~19 i/o * p60~p67 are bi - directional i/o pins. these can b e pulled - high internally by software control. p70~p77 20~27 i/o * p70~p77 are bi - directional i/o pins. * p74~p75 can be pulled - high internally by software control. * p76~p77 can have open - drain output by software control. * p70 and p71 can also be define d as the r - option pins. /int 7 i * external interrupt pin triggered by falling edge. vss 6 - * ground. nc 5 - * no connection.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 6 4. f unction description ioc5 r5 p 5 0 p 5 1 p 5 2 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 ioc6 r 6 ioc7 r7 acc r3 stack 1 stack 2 stack 3 stack 4 stack 5 p c rom instruction register instruction decoder alu interrupt control r4 ram wdt timer prescale r oscillator/timing control wdt time - out r1(tcc) sleep & wake control data & control bus /int tcc osci osco /reset p 6 0 p 6 1 p 6 2 p 6 3 p 6 4 p 6 5 p 6 6 p 6 7 p 7 0 p 7 1 p 7 2 p 7 3 p 7 4 p 7 5 p 7 6 p 7 7 fig. 2 functional block diagram 4 .1 operational re gisters 1. r0 (indirect addressing register) r0 is not a physically implemented register. its major function is to act as an indirect addressing pointer. any instruction using r0 as a pointer actually accesses data pointed by the ram select register (r4). 2. r1 (time clock /counter) ? increased by an external signal edge, which is defined by te bit (cont - 4) through the tcc pin, or by the instruction cycle clock. ? writable and readable as any other registers. ? defined by resetting pab (cont - 3).
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 7 ? the presc aler is assigned to tcc, if the pab bit (cont - 3) is reset. ? the contents of the prescaler counter will be cleared only when tcc register is written a value. 3. r2 (program counter) & stack ? depending on the device type, r2 and hardware stack are 10 - bit wide. the structure is depicted in fig.3. ? generating 1024 13 bits on - chip otp rom addresses to the relative programming instruction codes. one program page is 1024 words long. ? r2 is set as all "0"s when under reset condition. ? "jmp" instruction allows direct loading of the lower 10 program counter bits. thus, "jmp" allows pc to go to any location within a page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be locat ed anywhere within a page. ? "ret" ("retl k", "reti") instruction loads the program counter with the contents of the top - level stack. ? "add r2,a" allows the contents of ?a? to be added to the current pc, and the ninth and tenth bits of the pc are cleared. ? "mov r2,a" allows to load an address from the "a" register to the lower 8 bits of the pc, and the ninth and tenth bits of the pc are cleared. ? any instruction that writes to r2 (e.g. "add r2,a", "mov r2,a", "bc r2,6", ) will cause the ninth and ten th bits (a8~ a9 ) of the pc to be cleared. thus, the computed jump is limited to the first 256 locations of a page. ? all instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of r2. such instru ction will need one more instruction cycle. pc a11a10 a9a8 a7 ~ a0 call ret retl reti stack 1 stack 2 stack 3 stack 4 stack 5 000 3ff page 0 00 400 7ff page 1 800 bff page 2 c00 fff page 3 01 10 11 001:hareware in terrupt location 002:software interrupt (int instruction) location fff:reset location fig. 3 program counter organization
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 8 4. r3 (status register) 7 6 5 4 3 2 1 0 gp ps1 ps0 t p z dc c ? bit 0 (c) carry flag ? bit 1 (dc) auxiliary carry flag ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. ? bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. ? bit 4 (t) time - out bit. set to 1 with the "slep" and " wdtc" commands, or during power up, and reset to 0 with the wdt time - out. ? bits 5 (ps0) ~ 6 (ps1) page select bits. ps0~ps1 are used to pre - select a program memory page. when executing a "jmp", "call", or other instructions which causes the program counte r to change (e.g. mov r2, a), ps0~ps1 are loaded into the 11th and 12th bits of the program counter and select one of the available program memory pages. note that ret (retl, reti) instruction does not change the ps0~ps1 bits. that is, the return will alwa ys be to the page from where the subroutine was called, regardless of the ps0~ps1 bits current setting. ps1 ps0 program memory page [address] 0 0 page 0 [000 - 3ff] 0 1 page 1 [400 - 7ff] 1 0 page 2 [800 - bff] 1 1 page 3 [c00 - fff] ? bit 7 ( gp) general read /write bit. 5. r4 (ram select register) ? bits 0~5 are used to select the registers (address: 00~3f) in the indirect addressing mode. ? bits 6~7 determine which bank is activated among the 4 banks. ? if no indirect addressing is used, the rsr can be used a s an 8 - bit general - purpose read/writer register. ? see the configuration of the data memory in fig. 4. 6. r5~r7 (port 5 ~ port7) ? r5, r6 and r7 are i/o registers 7. r8~r1f and r20~r3e (general purpose register) ? r8~r1f, and r20~r3e (including banks 0~3) are general - purpose registers.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 9 8. r3f (interrupt status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - exif - - tcif ? bit 0 (tcif) the tcc overflow interrupt flag. set as tcc overflows; flag cleared by software. ? bit 3 (exif) extern al interrupt flag. set by falling edge on /int pin, flag cleared by software ? bits 1, 2, 4~7 are not used and read are as ?0?. ? "1" means interrupt request, "0" means non - interrupt. ? r3f can be cleared by instruction, but cannot be set by instruction. ? iocf is the interrupt mask register. ? note that reading r3f will obtain the result of the r3f "logic and" and iocf. 00 r 0 r1(tcc) r2(pc) r3(status) r4(rsr) r5(port5) r6(port6) r7(port7) r8 r9 ra rb rc rd re rf 16x8 common register 31x8 bank register (bank 0) r3f 31x8 bank register (bank 3) 31x8 bank register (bank 2) 31x8 bank register (bank 1) ioc5 ioc6 ioc7 ioce iocf stack (5 level) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 : : 1f 20 : : 3e 3f 00 01 10 11 iocb fig. 4 data memory configuration
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 10 9. r20~r3e (general - purpose register) ? ra~r1f, and r20~r 3e (including banks 0~3) are general - purpose registers. 10. r3f (interrupt status register) 7 6 5 4 3 2 1 0 - - - - exif - tcif ?1? means interrupt request, and ?0? means no interrupt occurs. ? bit 0 (tcif) tcc overflow interrupt flag. set when tcc over flows, reset by software. ? bit 3 (exif) external interrupt flag. set by falling edge on /int pin, reset by software. ? bits 1, 2 and 3 ~ 7 not used. ? r3f can be cleared by instruction but cannot be set by it. ? iocf is the interrupt mask register. ? note that reading r3f will obtain the result of the r3f "logic and" and iocf. 4 .2 special purpose registers 1. a (accumulator) ? internal data transfer, or instruction operand holding. ? it cannot be addressed. 2. cont (control register) 7 6 5 4 3 2 1 0 /phen /int ts te pab psr2 psr1 psr0 ? bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 ? bi t 3 (pab) prescaler assignment bit. 0: tcc 1: wdt ? bit 4 (te) tcc signal edge 0: increment if the transition from low to high takes place on tcc pin 1: increment if the transition from high to low takes place on tcc pin
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 11 ? bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: transition on tcc pin ? bit 6 (/int) interrupt enable flag 0: masked by disi or hardware interrupt 1: enabled by eni/reti instructions ? bit 7 (/phen) control bit used to enable the pull - high of p60~p67, p74 and p 75 pins 0: enable internal pull - high. 1: disable internal pull - high. ? cont register is both readable and writable. 3. ioc5 ~ ioc7 (i/o port control register) ? "1" put the relative i/o pin into high impedance, while "0" defines the relative i/o pin as out put. ? ioc5 and ioc7 registers are both readable and writable. 4. iocb (wake - up control register for port6) 7 6 5 4 3 2 1 0 /wue7 /wue6 /wue5 /wue4 /wue3 /wue2 /wue1 /wue0 ? bit 0 (/wue0) control bit is used to enable the wake - up function of p60 pin. 0: enable internal wake - up. 1: disable internal wake - up. ? bit 1 (/wue1) control bit is used to enable the wake - up function of p61 pin. ? bit 2 (/wue2) control bit is used to enable the wake - up function of p62 pin. ? bit 3 (/wue3) control bit is used to ena ble the wake - up function of p63 pin. ? bit 4 (/wue4) control bit is used to enable the wake - up function of p64 pin. ? bit 5 (/wue5) control bit is used to enable the wake - up function of p65 pin. ? bit 6 (/wue6) control bit is used to enable the wake - up fun ction of p66 pin. ? bit 7 (/wue7) control bit is used to enable the wake - up function of p67 pin. ? iocb register is both readable and writable. 5 . ioce (wdt control register) 7 6 5 4 3 2 1 0 - ode wdte slpc roc - - /wue ? bit 0 (/wue) control bit is used to enable the wake - up function of p74 and p75. 0: enable the wake - up function. 1: disable the wake - up function. the /wue bit can be read and written.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 12 ? bit 3 (roc) roc is used for the r - option. setting roc to "1" will enable the status of r - option pins (p 70, p71) for the controller to read. clearing roc will disable the r - option function. otherwise, the r - option function is introduced. users must connect the p71 pin or/and p70 pin to vss with a 560k w external resistor (rex). if rex is connected/disconnect ed with vdd, the status of p70 (p71) will be read as "0"/"1" (refer to fig. 7(b)). the roc bit can be read and written. ? bit 4 (slpc) this bit is set by hardware at the falling edge of wake - up signal and is cleared by software. slpc is used to control the oscillator operation. the oscillator is disabled (oscillator is stopped, and the controller enters into sleep2 mode) on the high - to - low transition and is enabled (controller is awakened from sleep2 mode) on low - to - high transition. in order to ensure the s table output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18 ms (oscillator start - up timer, ost) before the next instruction of the program is executed. the ost is always activated by a wake - up event from slee p mode regardless of the code option bit enwdt status is "0" or otherwise. after waking up, the wdt is enabled if the code option enwdt is "1". the block diagram of sleep2 mode and wake - up invoked by an input trigger is depicted in fig. 5. the slpc bit can be read and written. ? bit 5 (wdte) control bit used to enable watchdog timer. the wdte bit is useful only when enwdt, the code option bit, is "0". it is only when the enwdt bit is "0" that wdte bit. is able to disabled/enabled the wdt. 0: disable wdt. 1: enable wdt. the wdte bit is not used if enwdt, the code option bit enwdt, is "1". that is, if the enwdt bit is "1", wdt is always disabled no matter what the wdte bit status is. the wdte bit can be read and written. ? bit 6 (ode) control bit is used to en able the open - drain of p76 and p77 pins 0: disable open - drain output. 1: enable open - drain output. the ode bit can be read and written. ? bits 1~2, and 7 not used. 6 . iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - exie - - tcie ? bit 0 (tcie) tci f interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt ? bit 3 (exie) exif interrupt enable bit.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 13 0: disable exif interrupt 1: enable exif interrupt ? bits 1, 2 and 4~7 not used. ? individual interrupt is enabled by setting its associate d control bit in the iocf to "1". ? global interrupt is enabled by the eni instruction and is disabled by the disi instruction (refer to fig. 9). ? iocf register is both readable and writable. oscillator enable d isable reset q d q clk p r c l clear from s/w set 2 /wue 0 /wue1 /wue7 vcc p60~p67 vcc /wue p74~p75 /phen 8 fig. 5 sleep m ode and wake - up circuits on i/o ports block diagram
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 14 4 .3 tcc/wdt & prescaler an 8 - bit counter is available as prescaler for the tcc or wdt. the prescaler is available for either the tcc or wdt only at any given time, and the pab bit of the cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the ratio. the prescaler is cleared each time the instruction is written to tcc under tcc mode. the wdt and prescaler, when assigned to wdt mode, are cleared by the ?wdtc? or ?slep? instructions. fig. 6 depicts the circuit diagram of tcc/wdt. ? r1 (tcc) is an 8 - bit timer/counter. the clock source of tcc can be internal or external clock input (edge selectable from tcc pin). if tcc signal source is from internal clock, tcc will increas e by 1 at every instruction cycle (without prescaler). referring to fig. 6, clk=fosc/2 or clk=fosc/4 selection is determined by the code option bit clk status. clk=fosc/2 is used if clk bit is "0", and clk=fosc/4 is used if clk bit is "1". if tcc signal so urce comes from external clock input, tcc is increased by 1 at every falling edge or rising edge of tcc pin. ? the watchdog timer is a free running on - chip rc oscillator. the wdt will keep on running even after the oscillator driver has been turned off (i. e. in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the device to reset. the wdt can be enabled or disabled any time during normal mode by software programming. refer to wdte bit of ioce register. without presca ler, the wdt time - out period is approximately 18 ms 1 (default). wdt te tcc 8 - bit counter 2 cycles tcc(r1) sync pin m x u m x u m x u 8 - to - 1 mux mux ts 0 psr0~psr2 wdt timeuot pab tcc overflow interrupt clk(=fosc/2) pab (in ioce) wdte data bus pab 1 0 1 0 1 0 1 fig. 6 tcc and wdt block diagram 1 : vdd = 5v, set up time period = 16.5ms 5% vdd = 3v, set up time period = 18ms 5%
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 15 4 .4 i/o ports the i/o registers, port 5, port 6, and port 7, are bi - directional tri - state i/o ports. the funct ions of pull - high, r - option, and open - drain can be performed internally by cont and ioce respectively. there is input status change wake - up function on port 6, p74, and p75. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc7). the i/o registers and i/o control registers are both readable and writable. the i/o interface circuits for port 5, port 6, and port 7 are shown in figures. 7(a) and (b) respectively. pdrd q q clk d p r c l pcwr pdwr q q clk d p r c l port 0 1 m u x iod pcrd fig. 7 ( a) the i/o port and i/o control register circuit pdrd q q clk d p r c l pcwr pdwr q q clk d p r c l 0 1 m u x iod roc vcc weakly pull - up port rex* *the rex is 560k ohm external resistor pcrd fig.7(b) the i/o port with r - option (p70, p71) circuit
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 16 4 .5 reset and wake - up 1 . reset a reset is initiated by one of the following events - (1) power on reset, or (2) /reset pin in put ?low?, or (3) wdt timeout. (if enabled) the device is kept in a reset condition for a period of approx. 18ms 1 (one oscillator start - up timer period) after the reset is detected. once the reset occurs, the following functions are performed (refer to fig .8). ? the oscillator starts or is running ? the program counter (r2) is set to all "1". ? when power is switched on, bits 5~6 of r3 and the upper 2 bits of r4 are cleared. ? all i/o port pins are configured as input mode (high - impedance state). ? the watchdog timer and prescaler are cleared. ? upon power on, the bits 5~6 of r3 are cleared. ? upon power on, the upper 2 bits of r4 are cleared. ? the bits of cont register are set to all "1" except bit 6 (int flag). ? iocb register is set to ?1? (disa ble p60 ~ p67 wake - up function). ? bits 3 and 6 of ioce register are cleared, and bits 0, 4, and 5 are set to "1". ? bits 0 and 3 of r3f register and bits 0 and 3 of iocf registers are cleared. the sleep (power down) mode is asserted by executing the ?sl ep? instruction. while entering sleep mode, wdt (if enabled) is cleared but keeps on running. the controller can be awakened by - (1) external reset input on /reset pin; (2) wdt time - out (if enabled) the above two cases will cause the controller em78p447s t o reset. the t and p flags of r3 can be used to determine the source of the reset (wake - up). in addition to the basic sleep1 mode, em78p447s has another sleep mode (designated as sleep2 mode and is invoked by clearing the ioce register ?slpc? bit). in the sleep2 mode, the 1 note: vdd = 5v, set up time period = 16.2ms 5% vdd = 3v, set up time period = 19.6ms 5%
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 17 controller can be awakened by - (a) any of the wake - up pins is ?0? as illustrated in figure. 5. upon waking, the controller will continue to execute the succeeding address. under this case, before entering sleep2 mode, the wake - up function of the trigger sources (p60~p67 and p74~p75) should be selected (e.g., input pin) and enabled (e.g., pull - high, wake - up control). it should be noted that after waking up, the wdt is enabled if the code option bit enwdt is ?0?. the wdt operation (to be ena bled or disabled) should be appropriately controlled by software after waking up. (b) wdt time - out (if enabled) or external reset input on /reset pin will trigger a controller reset. table 4 the summary of the initialized values fo r registers address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name c57 c56 c55 c54 c53 c52 c51 c50 type a b a b a b a b - - - - n/a ioc5 power - on 0 1 0 1 0 1 0 1 1 1 1 1 /reset and wdt 0 1 0 1 0 1 0 1 1 1 1 1 wake - up from pin change 0 p 0 p 0 p 0 p p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 n/a ioc6 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name c77 c76 c75 c74 c73 c72 c71 c70 n/a ioc7 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name /phen /int ts te pab psr2 psr1 psr0 n/a cont power - on 1 0 1 1 1 1 1 1 /reset and wdt 1 p 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x00 r0(iar) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x01 r1(tcc) power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x02 r2(pc) power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change **0/p **0/p **0/p **0/p **0/p **0/p **0/p **0/p bit name gp ps1 ps0 t p z dc c 0x03 r3(sr) po wer - on 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p wake - up from pin change p p p t t p p p bit name rsr.1 rsr.0 - - - - - - 0x04 r4(rsr) power - on 0 0 u u u u u u /reset and wdt 0 0 p p p p p p wake - up from pin change p p p p p p p p b it name p57 p56 p55 p54 p53 p52 p51 p50 0x05 r5(p5) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 0x06 r6(p6) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p77 p76 p75 p74 p73 p72 p71 p70 0x07 r7(p7) power - on u u u u u u u u /reset and wdt p p p p p p p p
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 18 wake - up from pin change p p p p p p p p bit name - - - - exif - - tcif 0x3f r3f(isr) power - on u u u u 0 u u 0 /reset and wdt u u u u 0 u u 0 wake - up from pin change u u u u p u u p bit name /wue7 /wue6 /wue5 /wue4 /wue3 /wue2 /wue1 /wue0 0x0b iocb power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up fro m pin change p p p p p p p p bit name - ode wte slpc roc - - /wue 0x0e ioce power - on u 0 1 1 0 u u 1 /reset and wdt u 0 1 1 0 u u 1 wake - up from pin change u p 1 1 p u u p bit name - - - - exie - - tcie 0x0f iocf power - on u u u u 0 u u 0 / reset and wdt u u u u 0 u u 0 wake - up from pin change u u u u p u u p bit name - - - - - - - - 0x08 r8 power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x09~0x3e r9~r3 e power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p ** to execute next instruction after the ?slpc? bit status of ioce register being on high - to - low transition. x: not used. u: unknown or don?t care. p: previous value before reset. t: check table 5 2 . the status of rst, t, and p of status register a reset condition is initiated by one of the following events: 1. a power - on condition, 2. a high - low - high pulse on /reset pin, and 3. watchdog timer tim e - out. the values of t and p (listed in table 5 below) are used to verify the event that triggered the processor to wake up. table 6 shows the events that may affect the status of t and p. table 5 the values of rst, t and p after r eset reset type t p power on 1 1 /reset during operating mode *p *p /reset wake - up during sleep1 mode 1 0 /reset wake - up during sleep2 mode *p *p wdt during operating mode 0 *p wdt wake - up during sleep1 mode 0 0 wdt wake - up during sleep2 mode 0 *p wake - up on pin change during sleep2 mode *p *p *p: previous status before reset
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 19 table 6 the events that may affect the t and p status event t p power on 1 1 wdtc instruction 1 1 wdt time - out 0 *p slep instruction 1 0 wake - up on pin change during sleep2 mode *p *p *p: previous value before reset voltage detector power-on reset wdte setup time vdd d q clk clr clk reset wdt timeout wdt /reset oscillator fig. 8 controller reset block diagram 4 .6 interrupt the em78p447s has two interrupts listed below: (1) tcc overflow interrupt (2) ext ernal interrupt (/int pin). r3f is the interrupt status register that records the interrupt requests in the relative flags/bits. iocf is the interrupt mask register. the global interrupt is enabled by the eni instruction and is disabled by the disi instruc tion. when one of the interrupts (enabled) occurs, the next instruction will be fetched from address 001h. once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in r3f. the interrupt flag bit must be c leared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 20 the flag (except icif bit) in the interrupt status register (r3f) is set regardless of the status of its mask bit or the ex ecution of eni. note that the outcome of r3f are the logic and of r3f and iocf (refer to fig. 9). the reti instruction ends the interrupt routine and enables the global interrupt (the execution of eni). when an interrupt is generated by the int instruction (enabled), the next instruction will be fetched from address 002h. q q clk d p r c l q q clk d p r c l /irqn r3f reset iocf rfwr iocf rd iocfwr rfrd irqn irqm iod eni/disi interrupt fig. 9 interrupt input circuit 4 .7 oscillator 1 . oscillator modes the em78p447s can operate in three different oscillator modes, i.e., hig h xtal (hxt) oscillator mode, low xtal (lxt) oscillator mode, and external rc oscillator mode (erc) oscillator mode. user can select one of them by programming ms, hlf and hlp in the code option register. table 7 depicts how these three modes are defined. the maximum limit for operational frequencies of crystal/resonator under different vdds is listed in table 8. table 7 oscillator modes defined by ms and hlp mode ms hlf hlp erc(external rc oscillator mode) 0 *x *x hxt(high xtal os cillator mode) 1 1 *x
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 21 lxt(low xtal oscillator mode) 1 0 0 1. x, don?t care 2. the transient point of system frequency between hxt and lxy is around 400 khz. table 8 the summary of maximum operating speeds conditions vdd fx t max.(mhz) 2.3 4.0 3.0 8.0 two cycles with two clocks 5.0 20.0 2 . crystal oscillator/ceramic resonators(xtal) em78p447s can be driven by an external clock signal through the osci pin as shown in fig. 10 below. in most applications, pin osci and pin osco can be connected with a crystal or ceramic resonator to generate oscillation. fig. 12 depicts such circuit. the same thing applies whether it is in the hxt mode or in the lxt mode. table 9 provides the recommended values of c1 and c2. since each reson ator has its own attribute, user should refer to its specification for appropriate values of c1 and c2. rs. a serial resistor may be necessary for at strip cut crystal or low frequency mode. osci osco em78p447s ext. clock fig. 10 crystal /resonator circuit osci osco em78p447s c1 c2 xtal rs fig. 11 crystal/resonator circuit
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 22 table 9 capacitor selection guide for crystal oscillator or ceramic resonator oscillator type frequency mode frequency c1(pf) c2(pf) 455 khz 100~150 100~150 2.0 mhz 20~40 20~40 ceramic resonators hxt 4.0 mhz 10~30 10~30 32.768khz 25 15 100khz 25 25 lxt 200khz 25 25 455khz 20~40 20~150 1.0mhz 15~30 15~30 2.0mhz 15 15 crystal oscillator hxt 4.0mhz 15 15 osci em78p447s c 7404 330 330 xtal 7404 7404 fig. 12 crystal/resonator - series mode circuit osci em78p447s 7404 4.7k 10k xtal 7404 c1 vdd 10k c2 fig. 13 crystal/resonator - parallel mode circuit 3 . external rc oscillator mode for some applications that do not need a very precise timing calculation, the rc oscillator (fig. 15) offers a lot of cost savings. nevertheless, it should be noted that the frequency of the rc oscillator is influenced by the supply voltage, the values of the resistor (rext), the capacito r (cext), and even by the operation temperature. moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 23 in order to maintain a stable system frequency, the values of the cext should not be less th an 20pf, and that the value of rext should not be greater than 1 m ohm. if they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. the smaller the rext in the rc oscillator, the faster its frequency will be. on the contrary, for very low rext values, for instance, 1 k w , the oscillator becomes unstable because the nmos cannot discharge the current of the capacitance correctly. based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the rc oscillator, the package types, the way the pcb is layout, will affect the system frequency. osci em78p447s vcc rext cext fig. 14 external rc oscillator mode circuit table 10 rc oscillator frequencies cext rext average fosc 5v,25 c average fosc 3v,25 c 3.3k 4.32 mhz 3.56 mhz 5.1k 2.83 mhz 2.8 mhz 10k 1.62mhz 1.57 mhz 20 pf 100k 184 khz 187 khz 3.3k 1.39 mhz 1.35 mhz 5.1k 950 khz 930 khz 10k 500 k hz 490 khz 100 pf 100k 54khz 55 khz 3.3k 580 khz 550 khz 5.1k 390 khz 380 khz 10k 200 khz 200 khz 300 pf 100k 21 khz 21 khz 1. measured on dip packages. 2. for design reference only.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 24 4 .8 code option register the em78p447s has one code option w ord that is not a part of the normal program memory. the option bits cannot be accessed during normal program execution. bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ms /enwdt clk cs hlp hlp type - - - - - - ? bit 12 (ms ):oscillato r type selection. 0: rc type 1: xtal type(xtal1 and xtal2) ? bit 11 (/enwdt) : watchdog timer enable bit. 0: enable 1: disable ? bit 10 (clk) : instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. refer to the section on instruction set. ? bit 9 (cs) : code security bit 0: security on 1: security off ? bit 8 (hlf) : xtal frequency selection 0: xtal2 type (low frequency, 32.768khz) 1: xtal1 type (high frequency) this bit will affect system oscillation only when bit12(m s) is ?1?. when ms is?0?, hlf must be ?0?. : the transient point of system frequency between hxt and lxy is around 400 khz. ? bit 7 (hlp) : power selection. 0: low power 1: high power ? bit 6(type) : type selection for em78p447sa or b. 0: em78p447sb 1: em78p447sa ? bit 5 and bit4 : reserved. the bit5 set to ?1? all the time. the bit4 set to ?0? all the time. ? bit 3~0 : customer?s id code
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 25 4 .9 power on considerations any microcontroller is not guaranteed to start and operate properly before the pow er supply stays at its steady state. em78p447s is equipped with power on voltage detector(povd) with a detecting level is 2.0v. it will work well if vdd rises fast enough (10 ms or less). in many critical applications, however, extra devices are still requ ired to assist in solving power - up problems. 4 .10 external power on reset circuit the circuit shown in fig.16 implements an external rc to produce the reset pulse. the pulse width (time constant) should be kept long enough for vdd to reached minimum operat ion voltage. this circuit is used when the power supply has slow rise time. because the current leakage from the /reset pin is about 5 m a, it is recommended that r should not be greater than 40 k. in this way, the /reset pin voltage is held below 0.2v. the diode (d) acts as a short circuit at the moment of power down. the capacitor c will discharge rapidly and fully. rin, the current - limited resistor, will prevent high current or esd (electrostatic discharge) from flowing to pin /reset. em78p447s /reset vdd d r rin c fig. 15 external power - up reset circuit 4 .11 residue - voltage protection when battery is replaced, device power (vdd) is taken off but residue - voltage remains. the residue - voltage may trips below vdd minimum, but not to zero. th is condition may cause a poor power on reset. fig.16 and fig.17 show how to build the residue - voltage protection circuit. em78p447s /reset vdd 40k q1 1n4684 10k 33k vdd fig. 16 the residue voltage protection circuit 1
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 26 em78p447s /reset vdd q1 vdd 40k r2 r1 fig. 17 the residue voltage protection circuit 2 4 .12 instruction set each instruction in the instruction set is a 13 - bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instr uction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "mov r2,a", "add r2,a", or by instructions of arithmetic or logic operation on r2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ). in this case, the execution takes two instruction cycles. if for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (a) change one instruction cycle to consist of 4 oscillat or periods. (b) executed within two instruction cycles, "jmp", "call", "ret", "retl", "reti", or the conditional skip ("jbs", "jbc", "jz", "jza", "djz", "djza") instructions which were tested to be true. also execute within two instruction cycles, the inst ructions that are written to the program counter. case (a) is selected by the code option bit, called clk. one instruction cycle consists of two oscillator clocks if clk is low, and four oscillator clocks if clk is high. note that once the 4 oscillator per iods within one instruction cycle is selected as in case (a), the internal clock source to tcc should be clk=fosc/4, not fosc/ 2 as indicated in fig. 5. in addition, the instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operate on i/o register. the symbol "r" represents a register designator that specifies which one of the registers (including operation al registers and general purpose registers) is to be utilized by the instruction. "b" represents
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 27 a bit field designator that selects the value for the bit which is located in the register "r", and affects operation. "k" represents an 8 or 10 - bit constant or literal value. instruction binary hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? w dt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 re t [top of stack] ? pc none 0 0000 0001 0011 0013 reti [top of stack] ? pc, enable interrupt none 0 0000 0001 0100 0014 contr cont ? a none 0 0000 0001 rrrr 001r ior r iocr ? a none 0 0000 0010 0000 0020 tbl r2+a ? r2, bits 8~9 of r 2 unchanged z,c,dc 0 0000 01rr rrrr 00rr mov r,a a ? r none 0 0000 1000 0000 0080 clra 0 ? a z 0 0000 11rr rrrr 00rr clr r 0 ? r z 0 0001 00rr rrrr 01rr sub a,r r - a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r - a ? r z,c,dc 0 0001 1 0rr rrrr 01rr deca r r - 1 ? a z 0 0001 11rr rrrr 01rr dec r r - 1 ? r z 0 0010 00rr rrrr 02rr or a,r a r ? a z 0 0010 01rr rrrr 02rr or r,a a r ? r z 0 0010 10rr rrrr 02rr and a,r a & r ? a z 0 0010 11rr rrrr 02rr and r,a a & r ? r z 0 0011 00rr rrrr 03rr xor a,r a ? r ? a z 0 0011 01rr rrrr 03rr xor r,a a ? r ? r z 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? a z 0 0100 01rr rrrr 04rr mov r,r r ? r z 0 0100 10rr rrrr 04rr coma r /r ? a z 0 0100 11rr rrrr 04rr com r /r ? r z 0 0101 00rr rrrr 05rr inca r r+1 ? a z 0 0101 01rr rrrr 05rr inc r r+1 ? r z 0 0101 10rr rrrr 05rr djza r r - 1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r - 1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n - 1), r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n - 1), r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1 ), r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1), r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0 - 3) ? a(4 - 7), r(4 - 7) ? a(0 - 3) none 0 0111 01rr rrrr 07rr swap r r(0 - 3) ? r(4 - 7) none 0 0111 10rr rrrr 07rr jza r r+ 1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 ? [sp], (page, k) ? pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) ? pc none 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1001 kkkk kkkk 19kk or a,k a k ? a z 1 1010 kkkk kkkk 1akk and a,k a & k ? a z 1 1011 kkkk kkkk 1bkk xor a,k a ? k ? a z 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 28 instruction binary hex mnemonic operation status affected 1 1101 kkkk kkkk 1dkk sub a,k k - a ? a z,c,dc 1 1110 0000 0010 1e02 int pc+1 ? [sp], 0 02h ? pc none 1 1111 kkkk kkkk 1fkk add a,k k+a ? a z,c,dc this instruction is applicable to ioc5 ~ ioc7, iocb, ioce, iocf only. this instruction is not recommended for r3f operation. this instruction cannot operate under r3f.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 29 4 .13 timing diagram reset timing (clk="0") clk /reset nop instruction 1 executed tdrh tcc input timing (clks="0") clk tcc ttcc tins ac testing : input is driven at 2.4v for logic "1",and 0.4v for logic "0".timing measurements are made at 2.0v for logic "1",and 0.8v for logic "0". ac test input/output waveform 2.4 0.4 2.0 0.8 test points 2.0 0.8
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 30 5 . a bsolute m aximum ratings items rating temperature under bias 0 c to 70 c storage temperature - 65 c to 150 c input voltage - 0.3v to +6.0v output voltage - 0.3v to +6.0v operating frequency (2clk) dc to 20mhz
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 31 6 . electrical characteristics 6 .1 dc e lectrical characteristic ( ta= 0 c ~ 70 c, vdd= 5.0v 5%, vss= 0v ) symbol parameter condition min typ. max unit xtal: vdd to 3v two cycle with two clocks dc 8.0 mhz fxt xtal: vdd to 5v two cycle with t wo clocks dc 20.0 mhz erc erc: vdd to 5v r: 5.1k w , c: 100 pf f 30 % 950 f 30 % khz iil input leakage current for input pins vin = vdd, vss 1 m a vih1 input high voltage (vdd=5v) ports 5, 6 2.0 v vil1 input low voltage (vdd=5v) ports 5, 6 0.8 v vi ht1 input high threshold voltage (vdd=5v) /reset, tcc 2.0 v vilt1 input low threshold voltage (vdd=5v) /reset, tcc 0.8 v vihx1 clock input high voltage (vdd=5v) osci 3.5 v vilx1 clock input low voltage (vdd=5v) osci 1.5 v vih2 input high voltag e (vdd=3v) ports 5, 6 1.5 v vil2 input low voltage (vdd=3v) ports 5, 6 0.4 v viht2 input high threshold voltage (vdd=3v) /reset, tcc 1.5 v vilt2 input low threshold voltage (vdd=3v) /reset, tcc 0.4 v vihx2 clock input high voltage (vdd=3v) osci 2.1 v vilx2 clock input low voltage (vdd=3v) osci 0.9 v voh1 output high voltage (ports 5, 6, 7) ioh = - 10.0 ma 2.4 v vol1 output low voltage (ports 5, 6) iol = 9.0 ma 0.4 v vol2 output low voltage (port7) iol = 14.0 ma 0.4 v iph pull - high current pull - high active, input pin at vss - 50 - 100 - 240 m a isb1 power down current all input and i/o pins at vdd, output pin floating, wdt disabled 1 m a isb2 power down current all input and i/o pins at vdd, output pin floating, wdt enabled 7 m a ic c1 operating supply current (vdd=3v) at two cycles/four clocks /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt disabled 15 25 30 m a icc2 operating supply current (vdd=3v) at two cycles/four clocks /reset= 'high', fosc= 32khz (crystal type,clks="0"), output pin floating, wdt enabled 30 35 m a icc3 operating supply current (vdd=5v) at two cycles/two clocks /reset= 'high', fosc=4mhz (crystal type, clks="0"), output pin floating, wdt enabled 2.2 ma icc4 operating supply current (vdd=5v) at two cycles/four clocks /reset= 'high', fosc=10mhz (crystal type, clks="0"), output pin floating, wdt enabled 5.0 ma
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 32 6 .2 ac electrical characteristic (ta=0 c ~ 70 c, vdd=5v 5%, vss=0v) symbol parameter conditions min typ max unit dclk input clk duty cycle 45 50 55 % crystal type 100 dc ns tins instruction cycle time (clks="0") rc type 500 dc ns ttcc tcc input period (tins+20)/n* ns tdrh device reset hold time ta = 25 c 17.0 16.2 15.4 ms trst /reset pulse width ta = 25 c 2000 ns twdt watchdog timer period ta = 25 c 17.0 16.2 16 ms tset input pin setup time 0 ns thold input pin hold time 20 ns tdelay output pin delay time cload=20pf 50 ns * n= selected prescaler ratio.
em78p447s otp rom this specification is subject to change without prior notice. 2002/03/01 33 appendix package types: otp mcu pack age type pin count package size em78p447sap dip 28 600 mil em78p447sam sop 28 300 mil em78p447sas ssop 28 209 mil em78p447sbp dip 32 600 mil em78p447sbwm sop 32 450 mil

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