february 2002 4-73 stk16c68 8k x 8 autostoreplus ? nvsram quantumtrap ? cmos nonvolatile static ram features transparent data save on power down internal capacitor guarantees autostore ? regardless of power-down slew rate nonvolatile storage without battery problems directly replaces 8k x 8 static ram, battery- backed ram or eeprom 25ns, 35ns and 45ns access times store to eeprom initiated by software or autostoreplus ? on power down recall to sram initiated by software or power restore 10ma typical i cc at 200ns cycle time unlimited read, write and recall cycles 1,000,000 store cycles to eeprom 100-year data retention over full industrial temperature range no data loss from undershoot commercial and industrial temperatures 28-pin 600 mil pdip package description the stk16c68 is a fast sram with a nonvolatile eeprom element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in eeprom . data transfers from the sram to the eeprom (the store operation) can take place automatically on power down. an internal capacitor guarantees the store operation regardless of power- down slew rate. transfers from the eeprom to the sram (the recall operation) take place automatically on restoration of power. initiation of store and recall cycles can also be controlled by entering con- trol sequences on the sram inputs. the stk16c68 is pin-compatible with 8k x 8 sram s and battery-backed sram s, allowing direct substitution while enhancing performance. the stk12c68, which uses an external capacitor, and the stk15c68, which uses charge stored in system capacitance, are alternatives for sys- tems needing autostore ? operation. block diagram column i/o column dec static ram array 128 x 512 row decoder input buffers eeprom array 128 x 512 store/ recall control store recall power control a 5 a 6 a 9 a 11 a 12 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 software detect v cc a 0 - a 12 g e w a 8 a 7 a 10 a 3 a 2 a 0 a 1 a 4 internal capacitor pin names a 0 - a 12 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable v cc power (+ 5v) v ss ground pin configurations nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc nc a 8 a 9 a 11 g w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 28 - 600 pdip
stk16c68 february 2002 4-74 absolute maximum ratings a voltage on input relative to ground . . . . . . . . . . . . . .?0.5v to 7.0v voltage on input relative to v ss . . . . . . . . . . ?0.6v to (v cc + 0.5v) voltage on dq 0-7 . . . . . . . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . ?55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . . 15ma dc characteristics (v cc = 5.0v 10%) note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: i cc 2 and i cc 4 are the average currents required for the duration of the respective store cycles (t store ). note d: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. ac test conditions capacitance e (t a = 25 c, f = 1.0mhz) note e: these parameters are guaranteed but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 b average v cc current 90 75 65 90 75 65 ma ma ma t avav = 25ns t avav = 35ns t avav = 45ns i cc 2 c average v cc current during store 3 3 ma all inputs don?t care, v cc = max i cc 3 b average v cc current at t avav = 200ns 5v, 25c, typical 10 10 ma w (v cc ? 0.2v) all others cycling, cmos levels i sb 1 d average v cc current (standby, cycling ttl input levels) 27 23 20 28 24 21 ma ma ma t avav = 25ns, e v ih t avav = 35ns, e v ih t avav = 45ns, e v ih i sb 2 d v cc standby current (standby, stable cmos input levels) 1.5 1.5 ma e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 5 5 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 4ma v ol output logic ?0? voltage 0.4 0.4 v i out = 8ma t a operating temperature 0 70 ? 40 85 c input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 8pf ? v = 0 to 3v c out output capacitance 7pf ? v = 0 to 3v figure 1: ac output loading 480 ohms 30 pf 255 ohms 5.0v including o utput scope and fixture note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
stk16c68 february 2002 4-75 sram read cycles #1 & #2 (v cc = 5.0v 10%) note f: w must be high during sram read cycles and low during sram write cycles. note g: i/o state assumes e , g < v il and w > v ih ; device is continuously selected. note h: measured + 200mv from steady state output voltage. sram read cycle #1: address controlled f, g sram read cycle #2: e controlled f no. symbols parameter stk16c68-25 stk16c68-35 stk16c68-45 units #1, #2 alt. min max min max min max 1t elqv t acs chip enable access time 25 35 45 ns 2t avav f t rc read cycle time 25 35 45 ns 3t avqv g t aa address access time 25 35 45 ns 4t glqv t oe output enable to data valid 10 15 20 ns 5t axqx g t oh output hold after address change 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 ns 7t ehqz h t hz chip disable to output inactive 10 13 15 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz h t ohz output disable to output inactive 10 13 15 ns 10 t elicch e t pa chip enable to power active 0 0 0 ns 11 t ehiccl d, e t ps chip disable to power standby 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 8 t glqx 4 t glqv dq (data out) e address 2 t avav g i cc active 1 t elqv 10 t elicch 1 1 t ehiccl 7 t ehqz 9 t ghqz
stk16c68 february 2002 4-76 sram write cycles #1 & #2 (v cc = 5.0v 10%) note i: if w is low when e goes low, the outputs remain in the high-impedance state. note j: e or w must be v ih during address transitions. sram write cycle #1 : w controlled j sram write cycle #2 : e controlled j no. symbols parameter stk16c68-25 stk16c68-35 stk16c68-45 units #1 #2 alt. min max min max min max 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz h, i t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 5 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 1 9 t whax 13 t wlwh 18 t av wl 17 t av wh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data out e address 12 t avav w data in 13 t wleh 1 7 t aveh data valid high impedance 14 t eleh 18 t avel 19 t ehax 15 t dveh 16 t ehdx
stk16c68 february 2002 4-77 autostoreplus ?/power-up recall (v cc = 5.0v 10%) note k: t restore starts from the time v cc rises above v switch . autostoreplus ?/power-up recall no. symbols parameter stk16c68 units notes standard min max 22 t restore power-up recall duration 550 sk 23 t stg maximum v cc slew time to ground 500 ns f, h 24 v switch low voltage trigger level 4.0 4.5 v 25 v reset low voltage reset level 3.9 v e v cc v switch v reset p ower-up recall w dq (data out) autostore ? 5v 22 t restore 23 t stg 24 25 brown out autostoreplus ? no recall (v cc did not go below v reset ) brown out autostoreplus ? recall when v cc returns above v switch power-up recall brown out no store due to no sram writes no recall (v cc did not go below v reset )
stk16c68 february 2002 4-78 software store/recall mode selection note l: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. software store/recall cycle m, n (v cc = 5.0v 10%) note m: the software sequence is clocked with e controlled reads. note n: the six consecutive addresses must be in the order listed in the software store/recall mode selection table: (0000, 1555, 0aaa, 1fff, 10f0, 0f0f) for a store cycle or (0000, 1555, 0aaa, 1fff, 10f0, 0f0e) for a recall cycle. w must be high during all six consecutive cycles. software store/recall cycle: e controlled n e w g a 12 - a 0 (hex) mode i/o with g low i/o with g high notes lhx 0000 1555 0aaa 1fff 10f0 0f0f read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z output high z output high z output high z output high z output high z output high z l lhx 0000 1555 0aaa 1fff 10f0 0f0e read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z output high z output high z output high z output high z output high z output high z l no. symbols parameter stk16c68-20 stk16c68-25 stk16c68-35 stk16c68-45 units min max min max min max min max 26 t avav store / recall initiation cycle time 20 25 35 45 ns 27 t avel m address set-up time 0 0 0 0 ns 28 t eleh m clock pulse width 15 20 25 30 ns 29 t elax g, m address hold time 15 20 20 20 ns 30 t recall recall cycle duration 20 20 20 20 s 31 t store store cycle duration 10 10 10 10 ms high impedance address #6 address #1 data valid 26 t avav data valid d q (data out) e address 31 30 t store / t recall 26 t avav 27 t avel 28 t eleh 29 t elax
stk16c68 february 2002 4-79 the autostoreplus ? stk16c68 is a fast 8k x 8 sram that does not lose its data on power-down. the data is preserved in integral quantumtrap ? eeprom while power is unavailable. the nonvolatil- ity of the stk16c68 does not require any system intervention or support: autostoreplus ? on power- down and automatic recall on power-up guaran- tee data integrity without the use of batteries. noise considerations note that the stk16c68 is a high-speed memory and so must have a high-frequency bypass capaci- tor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, normal careful routing of power, ground and signals will help prevent noise problems. sram read the stk16c68 performs a read cycle whenever e and g are low and w is high. the address specified on pins a 0-12 determines which of the 8,192 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for tran- sitions on any control input pins, and will remain valid until another address change or until e or g is brought high or w is brought low. sram write a write cycle is performed whenever e and w are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 will be writ- ten into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostoreplus ? operation the stk16c68?s automatic store on power-down is completely transparent to the system. the autostore ? initiation takes less than 500ns when power is lost (v cc < v switch ) at which point the part depends only on its internal capacitor for store completion. this safe transfer of data from sram to eeprom takes place regardless of power supply slew rate. in order to prevent unneeded store operations, the automatic store will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software-initiated store cycles are performed regardless of whether or not a write operation has taken place. power-up recall during power up, or after any low-power condition (v cc < v reset ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t restore to complete. if the stk16c68 is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ? resistor should be connected either between w and system v cc or between e and system v cc . software nonvolatile store the stk16c68 software store cycle is initiated by executing sequential read cycles from six specific address locations. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. the program operation copies the sram data into nonvolatile memory. once a store cycle is initi- ated, further input and output are disabled until the cycle is completed. because a sequence of read s from specific addresses is used for store initiation, it is impor- tant that no other read or write accesses inter- vene in the sequence or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: device operation
stk16c68 february 2002 4-80 1. read address 0000 (hex) valid read 2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0f (hex) initiate store cycle the software sequence must be clocked with e controlled read s. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software nonvolatile recall a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of read operations must be performed: 1. read address 0000 (hex) valid read 2. read address 1555 (hex) valid read 3. read address 0aaa (hex) valid read 4. read address 1fff (hex) valid read 5. read address 10f0 (hex) valid read 6. read address 0f0e (hex) initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvola- tile information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. hardware protect the stk16c68 offers hardware protection against inadvertent store operation and sram write s during low-voltage conditions. when v cc < v switch , software store operations and sram write s are inhibited. low average active power the stk16c68 draws significantly less current when it is cycled at times longer than 50ns. figure 2 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for both cmos and ttl input levels (commercial tem- perature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 3 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by the stk16c68 depends on the following items: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read s to write s; 5) the operating temperature; 6) the v cc level; and 7) i/o loading. figure 2: i cc (max) reads 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) figure 3: i cc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma)
stk16c68 february 2002 4-81 ordering information temperature range blank = commercial (0 to 70c) i = industrial (?40 to 85c ) access time 25 = 25ns 35 = 35ns 45 = 45ns package w = plastic 28-pin 600 mil dip - w 25 i stk16c68
|
